testing a2onode
openpowerwtf
2 years ago
parent
2ab95aafc4
commit
bc0e3204b7
@ -1,331 +0,0 @@
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# a2o test tb
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# uses a2owb with sim mem interface
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import Timer
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from cocotb.triggers import FallingEdge
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from cocotb.handle import Force
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from cocotb.handle import Release
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import itertools
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from dotmap import DotMap
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from OPEnv import *
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from A2O import *
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from A2L2 import *
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# ------------------------------------------------------------------------------------------------
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# Tasks
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# get rid of z on anything that will be sampled here
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# is there a func to get all inputs?
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async def init(dut, sim):
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"""Initialize inputs. """
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dut.nclk.value = 0
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dut.scan_in.value = 0
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dut.an_ac_scan_type_dc.value = 0x0
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dut.an_ac_chipid_dc.value = 0x0
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dut.an_ac_coreid.value = 0x0
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dut.an_ac_scom_sat_id.value = 0x0
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dut.an_ac_lbist_ary_wrt_thru_dc.value = 0
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dut.an_ac_gsd_test_enable_dc.value = 0
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dut.an_ac_gsd_test_acmode_dc.value = 0
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dut.an_ac_ccflush_dc.value = 0
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dut.an_ac_ccenable_dc.value = 0
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dut.an_ac_lbist_en_dc.value = 0
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dut.an_ac_lbist_ip_dc.value = 0
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dut.an_ac_lbist_ac_mode_dc.value = 0
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dut.an_ac_scan_diag_dc.value = 0
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dut.an_ac_scan_dis_dc_b.value = 0
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dut.an_ac_rtim_sl_thold_8.value = 0
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dut.an_ac_func_sl_thold_8.value = 0
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dut.an_ac_func_nsl_thold_8.value = 0
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dut.an_ac_ary_nsl_thold_8.value = 0
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dut.an_ac_sg_8.value = 0
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dut.an_ac_fce_8.value = 0
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dut.an_ac_abst_scan_in.value = 0
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dut.an_ac_checkstop.value = 0
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dut.an_ac_reset_1_complete.value = 0
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dut.an_ac_reset_2_complete.value = 0
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dut.an_ac_reset_3_complete.value = 0
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dut.an_ac_reset_wd_complete.value = 0
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dut.an_ac_pm_fetch_halt.value = 0
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dut.an_ac_debug_stop.value = 0
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dut.an_ac_tb_update_enable.value = 1
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dut.an_ac_tb_update_pulse.value = 0 # tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock)
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# why is coco turning [0] into non-vector??? or is that gpi/vpi/icarus/???
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if sim.threads == 1:
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dut.an_ac_pm_thread_stop.value = 0x1
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dut.an_ac_external_mchk.value = 0
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dut.an_ac_sleep_en.value = 0
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dut.an_ac_ext_interrupt.value = 0
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dut.an_ac_crit_interrupt.value = 0
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dut.an_ac_perf_interrupt.value = 0
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dut.an_ac_hang_pulse.value = 0
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dut.an_ac_uncond_dbg_event.value = 0
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else:
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for i in range(sim.threads):
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dut.an_ac_pm_thread_stop[i].value = 0x1
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dut.an_ac_external_mchk[i].value = 0
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dut.an_ac_sleep_en[i].value = 0
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dut.an_ac_ext_interrupt[i].value = 0
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dut.an_ac_crit_interrupt[i].value = 0
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dut.an_ac_perf_interrupt[i].value = 0
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dut.an_ac_hang_pulse[i].value = 0
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dut.an_ac_uncond_dbg_event[i].value = 0
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await Timer(9, units='ns')
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async def config(dut, sim):
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"""Configure core, etc. """
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#wtf make A2 module to do core-specific stuff
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# A2L2 load/store credits
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creditsLd = dut.c0.lq0.lsq.arb.load_cred_cnt_d # 8 max
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creditsLdMax = dut.c0.lq0.lsq.arb.ld_cred_max # hdw check
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creditsSt = dut.c0.lq0.lsq.arb.store_cred_cnt_d # 32 max
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creditsStMax = dut.c0.lq0.lsq.arb.st_cred_max # hdw check
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creditsLdStSingle = dut.c0.lq0.lsq.arb.spr_xucr0_cred_d # 1 total credit
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#wtf this affects A2L2 - default=1
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# dut.c0.lq0.lsq.arb.spr_lsucr0_b2b_q # 0=crit first, every other 1=crit first, b2b **the a2l2 spec does not say crit must be first**
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lsucr0_d = dut.c0.lq0.ctl.spr.lq_spr_cspr.lsucr0_d
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lsucr0_q = dut.c0.lq0.ctl.spr.lq_spr_cspr.lsucr0_q
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cpcr2_d = dut.c0.iuq0.iuq_ifetch0.iuq_spr0.cpcr2_d
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cpcr2_q = dut.c0.iuq0.iuq_ifetch0.iuq_spr0.cpcr2_l2
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cpcr2_act = dut.c0.iuq0.iuq_ifetch0.iuq_spr0.cpcr2_wren
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cpcr4_d = dut.c0.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_d
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cpcr4_q = dut.c0.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_l2
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cpcr4_act = dut.c0.iuq0.iuq_ifetch0.iuq_spr0.cpcr4_wren
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await RisingEdge(dut.clk_1x)
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if sim.config.core.creditsLd is not None:
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creditsLd.value = Force(sim.config.core.creditsLd)
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creditsLdMax.value = Force(sim.config.core.creditsLd)
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sim.msg(f'A2L2: load credits changed from {creditsLd.value.integer} to {sim.config.core.creditsLd}.')
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await RisingEdge(dut.clk_1x)
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creditsLd.value = Release()
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if sim.config.core.creditsSt is not None:
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creditsSt.value = Force(sim.config.core.creditsSt)
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creditsStMax.value = Force(sim.config.core.creditsSt)
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sim.msg(f'A2L2: store credits changed from {creditsSt.value.integer} to {sim.config.core.creditsSt}.')
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await RisingEdge(dut.clk_1x)
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creditsSt.value = Release()
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if sim.config.core.creditsLdStSingle is not None:
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v = 1 if sim.config.core.creditsLdStSingle else 0
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creditsLdStSingle.value = Force(v)
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sim.msg(f'A2L2: only one load OR store allowed when credits=1/1.')
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await RisingEdge(dut.clk_1x)
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creditsLdStSingle.value = Release()
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#wtf make a function - needs mask,thread
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if sim.config.core.lsDataForward is not None:
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v = 1 if sim.config.core.lsDataForward else 0
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sim.msg(f'LSUCR0 = {hex(lsucr0_q.value), 8}')
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sim.msg(f'Setting LSUCR0[DFWD] = {v}.')
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v = v << 2
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v = (lsucr0_q.value.integer & ~0x4) | v
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lsucr0_d.value = Force(v)
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await RisingEdge(dut.clk_1x)
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lsucr0_d.value = Release()
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sim.msg(f'LSUCR0 = {hex(lsucr0_q.value), 8}')
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if sim.config.core.cpcr4_sq_cnt is not None:
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v = sim.config.core.cpcr4_sq_cnt
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sim.msg(f'CPCR4 = {hex(cpcr4_q[0], 8)}')
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sim.msg(f'Setting CPCR4[SQ_CNT] = {v}.')
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v = v << 0
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v = (cpcr4_q[0].value.integer & ~0x1F) | v
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await RisingEdge(dut.clk_1x) # need cuz of act?
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cpcr4_d[0].value = Force(v)
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cpcr4_act.value = Force(1)
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await RisingEdge(dut.clk_1x)
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await RisingEdge(dut.clk_1x) # need cuz of act?
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cpcr4_d[0].value = Release()
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cpcr4_act.value = Release()
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sim.msg(f'CPCR4 = {hex(cpcr4_q[0], 8)}')
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await RisingEdge(dut.clk_1x)
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# trilib/tri.vh:`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5xClk
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async def genReset(dut, sim):
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"""Generate reset. """
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first = True
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done = False
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while not done:
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await RisingEdge(dut.clk_1x)
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if sim.cycle < sim.resetCycle:
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if first:
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dut._log.info(f'[{sim.cycle:08d}] Resetting...')
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first = False
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dut.nclk[1].value = 1
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elif not done:
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dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
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dut.nclk[1].value = 0
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done = True
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sim.resetDone = True
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async def genClocks(dut, sim):
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"""Generate 1x, 2x, 4x clock pulses, depending on parms. """
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if sim.clk2x and sim.clk4x:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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sim.clk4x = Clock(dut.nclk[3], 2, 'ns')
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await cocotb.start(sim.clk4x.start())
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elif sim.clk2x:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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else:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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for cycle in range(sim.maxCycles):
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sim.cycle = cycle
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if cycle % sim.hbCycles == 0:
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dut._log.info(f'[{cycle:08d}] ...tick...')
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await RisingEdge(dut.clk_1x)
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dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')
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sim.ok = False
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sim.fail = 'Max cycle reached.'
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# ------------------------------------------------------------------------------------------------
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# Interfaces
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# SCOM
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async def scom(dut, sim):
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"""scom interface"""
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dut.an_ac_scom_dch.value = 0
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dut.an_ac_scom_cch.value = 0
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# ------------------------------------------------------------------------------------------------
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# Do something
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@cocotb.test()
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async def tb(dut):
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"""A Vulgar Display of OpenPower"""
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sim = Sim(dut)
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sim.mem = Memory(sim)
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sim.maxCycles = 9000
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# original fpga design needed 4 cred, no fwd (set in logic currently)
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#sim.config.core.creditsSt = 32
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#sim.config.core.lsDataForward = 0 # disable=1
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#sim.config.core.cpcr4_sq_cnt = 0 # default=6
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'''
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# rom
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sim.memFiles = ['../mem/boot.bin.hex'] #wtf cmdline parm
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
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sim.mem.loadFile(sim.memFiles[i])
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'''
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'''
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# rom+test; should end at 700
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sim.memFiles = [
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{
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'addr': 0x00000000,
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'file' : '../mem/test1/rom.init'
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},
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{
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'addr': 0x10000000,
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'file' : '../mem/test1/test.init'
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}
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]
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'''
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'''
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# rom+bios; should end at 7FC
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sim.memFiles = [
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{
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'addr': 0x00000000,
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'file' : '../mem/test2/rom.init'
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}
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]
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'''
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# rom+bios+arcitst
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sim.memFiles = [
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{
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'addr': 0x00000000,
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'file' : '../mem/test3/rom.init'
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}
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]
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for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
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sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
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if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
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sim.mem.write(sim.resetAddr, sim.resetOp)
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sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')
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# init stuff
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await init(dut, sim)
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# start clocks,reset
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await cocotb.start(genClocks(dut, sim))
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await cocotb.start(genReset(dut, sim))
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# start interfaces
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await cocotb.start(scom(dut, sim))
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sim.a2o = A2OCore(sim)
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sim.a2o.traceFacUpdates = True
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await cocotb.start(A2O.driver(dut, sim))
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await cocotb.start(A2O.checker(dut, sim))
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await cocotb.start(A2O.monitor(dut, sim))
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await cocotb.start(A2L2.driver(dut, sim))
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await cocotb.start(A2L2.checker(dut, sim))
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await cocotb.start(A2L2.monitor(dut, sim))
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await Timer((sim.resetCycle + 5)*8, units='ns')
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if dut.nclk[1].value != 0:
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sim.ok = False
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sim.fail = 'Reset active too long!'
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# config stuff
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await config(dut, sim)
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# monitor stuff
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#await cocotb.start(coreMonitor(dut, sim))
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# release thread(s)
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dut.an_ac_pm_thread_stop.value = 0
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await RisingEdge(dut.clk_1x)
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dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')
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# should await sim.done
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await Timer((sim.maxCycles+100)*8, units='ns')
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if sim.ok:
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dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
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else:
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dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
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dut._log.info(f'[{sim.cycle:08d}] {sim.fail}')
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assert False
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