test2
openpowerwtf
2 years ago
parent
63ebe271c8
commit
b79536e583
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../bin
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#include <stdint.h>
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#include "bios.h"
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int main(int tid) {
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int *p;
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int *fdata = _fdata;
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if (tid != 0) {
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return -1;
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}
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// r/w memory init
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// copy
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for (p = _fdata_rom; p < _edata_rom; p++){
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*(fdata++) = *p;
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}
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// zero
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for (p = _fbss; p < _ebss; p++) {
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*_fbss = 0;
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}
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// core init
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set_epcr(0x03000000); // icm=gicm=1
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set_dec(0);
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set_tbh(0);
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set_tbl(0);
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set_tsr(0xFE000000); // mask: clear enw,wis,wrs,dis,fis,udis
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set_xucr0(get_xucr0() & 0x00000200); // set tcs=0
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set_tsr(0);
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set_tcr(0); // disable all timers
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// thread enable
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// set_tens(0x3);
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return 0;
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}
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#ifndef BIOS_H
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#define BIOS_H
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extern int *_fdata_rom;
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extern int *_edata_rom;
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extern int *_fdata;
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extern int *_fbss;
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extern int *_ebss;
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inline void set_epcr(int v) __attribute__((always_inline));
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inline void set_dec(int v) __attribute__((always_inline));
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inline void set_tbh(int v) __attribute__((always_inline));
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inline void set_tbl(int v) __attribute__((always_inline));
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inline void set_tsr(int v) __attribute__((always_inline));
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inline void set_tcr(int v) __attribute__((always_inline));
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inline void set_tens(int v) __attribute__((always_inline));
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inline void set_xucr0(int v) __attribute__((always_inline));
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inline int get_xucr0(void) __attribute__((always_inline));
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inline void set_epcr(int v) {
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asm volatile(
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"lis 4,%0@h\n"
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"ori 4,4,%0@l\n"
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"mtspr 307,4\n" // epcr
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: // outputs
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: "r"(v) // inputs
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: "r4" // clobbers
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);
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}
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inline void set_dec(int v) {
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asm volatile(
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"lis 4,%0@h\n"
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"ori 4,4,%0@l\n"
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"mtspr 22,4\n" // dec
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: // outputs
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: "r"(v) // inputs
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: "r4" // clobbers
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);
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}
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inline void set_tbh(int v) {
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asm volatile(
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"lis 4,%0@h\n"
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"ori 4,4,%0@l\n"
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"mtspr 285,4\n" // tbh
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: // outputs
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: "r"(v) // inputs
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: "r4" // clobbers
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);
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}
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inline void set_tbl(int v) {
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asm volatile(
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"lis 4,%0@h\n"
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"ori 4,4,%0@l\n"
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"mtspr 284,4\n" // tbl
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: // outputs
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: "r"(v) // inputs
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: "r4" // clobbers
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);
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}
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inline void set_tsr(int v) {
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asm volatile(
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"lis 4,%0@h\n"
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"ori 4,4,%0@l\n"
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"mtspr 336,4\n" // tsr
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: // outputs
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: "r"(v) // inputs
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: "r4" // clobbers
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);
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}
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inline void set_tcr(int v) {
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asm volatile(
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"lis 4,%0@h\n"
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"ori 4,4,%0@l\n"
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"mtspr 340,4\n" // tcr
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: // outputs
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: "r"(v) // inputs
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: "r4" // clobbers
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);
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}
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inline int get_xucr0(void) {
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int v;
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asm volatile(
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"mfspr %0,1014\n" // xucr0
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: "=r"(v) // outputs
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: // inputs
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: // clobbers
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);
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return v;
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}
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inline void set_xucr0(int v) {
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asm volatile(
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"lis 4,%0@h\n"
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"ori 4,4,%0@l\n"
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"mtspr 1014,4\n" // xucr0
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: // outputs
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: "r"(v) // inputs
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: "r4" // clobbers
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);
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}
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inline void set_tens(int v) {
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asm volatile(
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"lis 4,%0@h\n"
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"ori 4,4,%0@l\n"
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"mtspr 438,4\n" // tens
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: // outputs
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: "r"(v) // inputs
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: "r4" // clobbers
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);
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}
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#endif
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Binary file not shown.
@ -0,0 +1,341 @@
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# © IBM Corp. 2022
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# Licensed under and subject to the terms of the CC-BY 4.0
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# license (https://creativecommons.org/licenses/by/4.0/legalcode).
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# Additional rights, including the right to physically implement a softcore
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# that is compliant with the required sections of the Power ISA
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# Specification, will be available at no cost via the OpenPOWER Foundation.
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# This README will be updated with additional information when OpenPOWER's
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# license is available.
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# boot kernel
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# resets to 32BE
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# set up translations for starting bios (inc. BE/LE)
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# copy modifiable rom data to ram - or do in bios?
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# set up msr for running bios (inc. 32/64)
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# jump to bios
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.include "defines.s"
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.macro load32 rx,v
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li \rx,0
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oris \rx,\rx,\v>>16
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ori \rx,\rx,\v&0x0000FFFF
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.endm
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.macro load16swiz rx,v
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li \rx,0
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ori \rx,\rx,(\v<<8)&0xFF00
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ori \rx,\rx,(\v>>8)&0x00FF
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.endm
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# constants from linker script, or defsym
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.ifdef BIOS_32
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# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
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.set BIOS_MSR,0x0002B000
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.else
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# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
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.set BIOS_MSR,0x8002B000
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.endif
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# erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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.ifdef BIOS_LE
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.set BIOS_ERATW2,0x000000BF
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.else
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.set BIOS_ERATW2,0x0000003F
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.endif
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# bios might be able to use one stack during thread startup if careful
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.ifndef BIOS_STACK_0
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.set BIOS_STACK_0,_stack_0
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.endif
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.ifndef BIOS_STACK_1
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.set BIOS_STACK_1,_stack_1
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.endif
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.ifndef BIOS_START
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.set BIOS_START,0x00010000
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.endif
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.section .text
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.global _start
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.org 0x000
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_start:
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int_000:
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b boot_start
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# critical input
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.org 0x020
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int_020:
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.ifndef INT_UNHANDLED
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b .
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.else
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b INT_UNHANDLED
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.endif
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# debug
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.org 0x040
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int_040:
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b .
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# dsi
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.org 0x060
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int_060:
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b .
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# isi
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.org 0x080
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int_080:
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b .
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# external
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.org 0x0A0
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int_0A0:
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b .
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# alignment
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.org 0x0C0
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int_0C0:
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b .
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# program
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.org 0x0E0
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int_0E0:
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b .
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# fp unavailable
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.org 0x100
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int_100:
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b .
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# sc
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.org 0x120
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int_120:
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b .
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# apu unavailable
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.org 0x140
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int_140:
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b .
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# decrementer
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.org 0x160
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int_160:
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b .
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# fit
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.org 0x180
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int_180:
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b .
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# watchdog
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.org 0x1A0
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int_1A0:
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b .
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# dtlb
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.org 0x1C0
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int_1C0:
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b .
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# itlb
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.org 0x1E0
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int_1E0:
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b .
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# vector unavailable
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.org 0x200
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int_200:
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b .
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#
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.org 0x220
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int_220:
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b .
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#
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.org 0x240
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int_240:
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b .
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#
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.org 0x260
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int_260:
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b .
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# doorbell
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.org 0x280
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int_280:
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b .
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# doorbell critical
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.org 0x2A0
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int_2A0:
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b .
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# doorbell guest
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.org 0x2C0
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int_2C0:
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b .
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# doorbell guest critical
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.org 0x2E0
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int_2E0:
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b .
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# hvsc
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.org 0x300
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int_300:
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b .
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# hvpriv
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.org 0x320
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int_320:
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b .
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# lrat
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.org 0x340
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int_340:
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b .
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# ------------------------------------------------------------------------------------------------------------------------------
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# initial translation
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# both erats:
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# 00000000 64K: (rom, BE)
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# 00010000 64K: (ram, BE or LE)
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#
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.org 0x400
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boot_start:
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mfspr r5,tir # who am i?
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cmpdi r5,0x00 # skip unless T0
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bne init_t123
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lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
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# derat 31 @00000000
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li r0,0x001F # entry #31
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li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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mtspr mmucr0,r3
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eratwe r2,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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# derat 30 @<BIOS_START>
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li r0,0x001E # entry #30
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load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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load32 r8,BIOS_START
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ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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eratwe r10,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
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# ierat 15 @00000000
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li r0,0x000F # entry #15
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li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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mtspr mmucr0,r3
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eratwe r2,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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# *** leave the init'd entry 14 for MT access to FFFFFFC0
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# ierat 13 @<BIOS_START>
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li r0,0x000D # entry #13
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load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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load32 r8,BIOS_START
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ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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eratwe r10,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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b init_t0
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# ------------------------------------------------------------------------------------------------------------------------------
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# init
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#
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# T0
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init_t0:
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# set up BIOS msr
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load32 r10,BIOS_MSR
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mtmsr r10
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isync
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# can't use load32 unless you can .set BIOS_STACK_0 to the linked value
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# load32 r1,BIOS_STACK_0 # @stack_0
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# this ignores def
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# lis r1,_stack_0@h
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# ori r1,r1,_stack_0@l
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# this requires data load
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lwz r1,stack_0(r0)
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b boot_complete
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# except T0
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init_t123:
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# set up BIOS msr
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load32 r10,BIOS_MSR
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mtmsr r10
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isync
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# check tir if more than 2 threads possible
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lwz r1,stack_1(r0)
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b boot_complete
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# ------------------------------------------------------------------------------------------------------------------------------
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boot_complete:
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# set up thread and hop to it
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lis r3,main@h
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ori r3,r3,main@l
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mtctr r3
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mfspr r3,tir # who am i?
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bctrl
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b kernel_return
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# ------------------------------------------------------------------------------------------------------------------------------
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.org 0x7FC
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kernel_return:
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b .
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# dec
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.org 0x800
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int_800:
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b .
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# perf
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.org 0x820
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int_820:
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b .
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.org 0x8F0
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.section .rodata
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stack_0: .long BIOS_STACK_0
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stack_1: .long BIOS_STACK_1
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@ -0,0 +1,84 @@
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#!/usr/bin/bash
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export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
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export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"
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# defines
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## define vars to init rom with csr's it uses...
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#
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#csr_base=`grep '#define CSR_BASE' generated/csr.h | cut -d ' ' -f 3 | cut -c 1-6`
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#uart_base=`grep 'CSR_UART_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
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#UART_ADDR="${csr_base}${uart_base}"
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#defsyms="-defsym $UART_ADDR"
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#
|
||||
#uart_base=`grep 'CSR_UART_1_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_1_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_1_ADDR"
|
||||
#fi
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_2_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_2_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_2_ADDR"
|
||||
#fi
|
||||
#
|
||||
#leds_base=`grep 'CSR_LEDS_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$leds_base" != "" ]] ; then
|
||||
# LEDS_ADDR="${csr_base}${leds_base}"
|
||||
# defsyms="$defsyms -defsym $LEDS_ADDR"
|
||||
#fi
|
||||
#
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_1_ADDR}"
|
||||
|
||||
# a2o nanokernel
|
||||
|
||||
echo -n "Compiling..."
|
||||
|
||||
echo -n "boot.s "
|
||||
#powerpc-linux-gnu-as -defsym UART_ADDR=$UART_ADDR -defsym LEDS_ADDR=$LEDS_ADDR -defsym UNHANDLED=1 -mbig-endian -mpower9 -I./asm asm/cmod7-boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
powerpc-linux-gnu-as -mbig-endian -ma2 -I. boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
echo -n "bios.c "
|
||||
powerpc-linux-gnu-gcc -c -I. $CFLAGS bios.c
|
||||
|
||||
echo ""
|
||||
echo "Linking..."
|
||||
powerpc-linux-gnu-ld -nostdlib -nodefaultlibs -T linker.ld crt0.o bios.o -o rom
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
powerpc-linux-gnu-objdump -d rom > rom.d #wtf: why not getting labels in asm code?
|
||||
powerpc-linux-gnu-objdump -s rom > rom.s
|
||||
#powerpc-linux-gnu-objcopy --change-section-lma .bios=0x10000 -O binary rom rom.bin
|
||||
powerpc-linux-gnu-objcopy -O binary rom rom.bin
|
||||
|
||||
#python3 -m litex.soc.software.memusage rom ./generated/regions.ld powerpc-linux-gnu
|
||||
|
||||
# make rom.bin.hex
|
||||
bin/bin2init rom.bin
|
||||
mv rom.bin.hex rom.init
|
||||
|
||||
echo "Built rom.d, rom.s, rom.init."
|
||||
|
||||
romsize=`grep rom regions.ld | cut -d " " -f 8 | cut -c 3-10`
|
||||
|
||||
echo "Hardware ROM Size $romsize"
|
||||
#echo ""
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_2_ADDR}"
|
||||
#
|
||||
|
||||
@ -0,0 +1,84 @@
|
||||
#!/usr/bin/bash
|
||||
|
||||
export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
|
||||
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"
|
||||
|
||||
# defines
|
||||
|
||||
## define vars to init rom with csr's it uses...
|
||||
|
||||
#
|
||||
#csr_base=`grep '#define CSR_BASE' generated/csr.h | cut -d ' ' -f 3 | cut -c 1-6`
|
||||
#uart_base=`grep 'CSR_UART_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#UART_ADDR="${csr_base}${uart_base}"
|
||||
#defsyms="-defsym $UART_ADDR"
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_1_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_1_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_1_ADDR"
|
||||
#fi
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_2_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_2_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_2_ADDR"
|
||||
#fi
|
||||
#
|
||||
#leds_base=`grep 'CSR_LEDS_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$leds_base" != "" ]] ; then
|
||||
# LEDS_ADDR="${csr_base}${leds_base}"
|
||||
# defsyms="$defsyms -defsym $LEDS_ADDR"
|
||||
#fi
|
||||
#
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_1_ADDR}"
|
||||
|
||||
# a2o nanokernel
|
||||
|
||||
echo -n "Compiling..."
|
||||
|
||||
echo -n "boot.s "
|
||||
#powerpc-linux-gnu-as -defsym UART_ADDR=$UART_ADDR -defsym LEDS_ADDR=$LEDS_ADDR -defsym UNHANDLED=1 -mbig-endian -mpower9 -I./asm asm/cmod7-boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
powerpc-linux-gnu-as -mbig-endian -ma2 -I. boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
echo -n "bios.c "
|
||||
powerpc-linux-gnu-gcc -c -I. $CFLAGS bios.c
|
||||
|
||||
echo ""
|
||||
echo "Linking..."
|
||||
powerpc-linux-gnu-ld -nostdlib -nodefaultlibs -T linker2.ld crt0.o bios.o -o rom
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
powerpc-linux-gnu-objdump -d rom > rom.d #wtf: why not getting labels in asm code?
|
||||
powerpc-linux-gnu-objdump -s rom > rom.s
|
||||
#powerpc-linux-gnu-objcopy --change-section-lma .bios=0x10000 -O binary rom rom.bin
|
||||
powerpc-linux-gnu-objcopy -O binary rom rom.bin
|
||||
|
||||
#python3 -m litex.soc.software.memusage rom ./generated/regions.ld powerpc-linux-gnu
|
||||
|
||||
# make rom.bin.hex
|
||||
bin/bin2init rom.bin
|
||||
mv rom.bin.hex rom.init
|
||||
|
||||
echo "Built rom.d, rom.s, rom.init."
|
||||
|
||||
romsize=`grep rom regions.ld | cut -d " " -f 8 | cut -c 3-10`
|
||||
|
||||
echo "Hardware ROM Size $romsize"
|
||||
#echo ""
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_2_ADDR}"
|
||||
#
|
||||
|
||||
@ -0,0 +1,619 @@
|
||||
1 # © IBM Corp. 2022
|
||||
2 # Licensed under and subject to the terms of the CC-BY 4.0
|
||||
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
4 # Additional rights, including the right to physically implement a softcore
|
||||
5 # that is compliant with the required sections of the Power ISA
|
||||
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
7 # This README will be updated with additional information when OpenPOWER's
|
||||
8 # license is available.
|
||||
9
|
||||
10 # boot kernel
|
||||
11 # resets to 32BE
|
||||
12 # set up translations for starting bios (inc. BE/LE)
|
||||
13 # copy modifiable rom data to ram - or do in bios?
|
||||
14 # set up msr for running bios (inc. 32/64)
|
||||
15 # jump to bios
|
||||
16
|
||||
17
|
||||
18 .include "defines.s"
|
||||
1 # © IBM Corp. 2020
|
||||
2 # Licensed under and subject to the terms of the CC-BY 4.0
|
||||
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
4 # Additional rights, including the right to physically implement a softcore
|
||||
5 # that is compliant with the required sections of the Power ISA
|
||||
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
7 # This README will be updated with additional information when OpenPOWER's
|
||||
8 # license is available.
|
||||
9
|
||||
10 #-----------------------------------------
|
||||
11 # Defines
|
||||
12 #-----------------------------------------
|
||||
13
|
||||
14 # Regs
|
||||
15
|
||||
16 .set r0, 0
|
||||
17 .set r1, 1
|
||||
18 .set r2, 2
|
||||
19 .set r3, 3
|
||||
20 .set r4, 4
|
||||
21 .set r5, 5
|
||||
22 .set r6, 6
|
||||
23 .set r7, 7
|
||||
24 .set r8, 8
|
||||
25 .set r9, 9
|
||||
26 .set r10,10
|
||||
27 .set r11,11
|
||||
28 .set r12,12
|
||||
29 .set r13,13
|
||||
30 .set r14,14
|
||||
31 .set r15,15
|
||||
32 .set r16,16
|
||||
33 .set r17,17
|
||||
34 .set r18,18
|
||||
35 .set r19,19
|
||||
36 .set r20,20
|
||||
37 .set r21,21
|
||||
38 .set r22,22
|
||||
39 .set r23,23
|
||||
40 .set r24,24
|
||||
41 .set r25,25
|
||||
42 .set r26,26
|
||||
43 .set r27,27
|
||||
44 .set r28,28
|
||||
45 .set r29,29
|
||||
46 .set r30,30
|
||||
47 .set r31,31
|
||||
48
|
||||
49 .set f0, 0
|
||||
50 .set f1, 1
|
||||
51 .set f2, 2
|
||||
52 .set f3, 3
|
||||
53 .set f4, 4
|
||||
54 .set f5, 5
|
||||
55 .set f6, 6
|
||||
56 .set f7, 7
|
||||
57 .set f8, 8
|
||||
58 .set f9, 9
|
||||
59 .set f10,10
|
||||
60 .set f11,11
|
||||
61 .set f12,12
|
||||
62 .set f13,13
|
||||
63 .set f14,14
|
||||
64 .set f15,15
|
||||
65 .set f16,16
|
||||
66 .set f17,17
|
||||
67 .set f18,18
|
||||
68 .set f19,19
|
||||
69 .set f20,20
|
||||
70 .set f21,21
|
||||
71 .set f22,22
|
||||
72 .set f23,23
|
||||
73 .set f24,24
|
||||
74 .set f25,25
|
||||
75 .set f26,26
|
||||
76 .set f27,27
|
||||
77 .set f28,28
|
||||
78 .set f29,29
|
||||
79 .set f30,30
|
||||
80 .set f31,31
|
||||
81
|
||||
82 .set cr0, 0
|
||||
83 .set cr1, 1
|
||||
84 .set cr2, 2
|
||||
85 .set cr3, 3
|
||||
86 .set cr4, 4
|
||||
87 .set cr5, 5
|
||||
88 .set cr6, 6
|
||||
89 .set cr7, 7
|
||||
90
|
||||
91 # SPR numbers
|
||||
92
|
||||
93 .set srr0, 26
|
||||
94 .set srr1, 27
|
||||
95 .set epcr, 307
|
||||
96 .set tar, 815
|
||||
97
|
||||
98 .set dbsr, 304
|
||||
99 .set dbcr0, 308
|
||||
100 .set dbcr1, 309
|
||||
101 .set dbcr2, 310
|
||||
102 .set dbcr3, 848
|
||||
103
|
||||
104 .set ivpr, 63
|
||||
105
|
||||
106 .set iucr0, 1011
|
||||
107 .set iucr1, 883
|
||||
108 .set iucr2, 884
|
||||
109
|
||||
110 .set iudbg0, 888
|
||||
111 .set iudbg1, 889
|
||||
112 .set iudbg2, 890
|
||||
113 .set iulfsr, 891
|
||||
114 .set iullcr, 892
|
||||
115
|
||||
116 .set mmucr0, 1020
|
||||
117 .set mmucr1, 1021
|
||||
118 .set mmucr2, 1022
|
||||
119 .set mmucr3, 1023
|
||||
120
|
||||
121 .set tb, 268
|
||||
122 .set tbl, 284
|
||||
123 .set tbh, 285
|
||||
124
|
||||
125 .set dec, 22
|
||||
126 .set udec, 550
|
||||
127 .set tsr, 336
|
||||
128 .set tcr, 340
|
||||
129
|
||||
130 .set xucr0, 1014
|
||||
131 .set xucr1, 851
|
||||
132 .set xucr2, 1016
|
||||
133 .set xucr3, 852
|
||||
134 .set xucr4, 853
|
||||
135
|
||||
136 .set tens, 438
|
||||
137 .set tenc, 439
|
||||
138 .set tensr, 437
|
||||
139
|
||||
140 .set pid, 48
|
||||
141 .set pir, 286
|
||||
142 .set pvr, 287
|
||||
143 .set tir, 446
|
||||
144
|
||||
19
|
||||
20 .macro load32 rx,v
|
||||
21 li \rx,0
|
||||
22 oris \rx,\rx,\v>>16
|
||||
23 ori \rx,\rx,\v&0x0000FFFF
|
||||
24 .endm
|
||||
25
|
||||
26 .macro load16swiz rx,v
|
||||
27 li \rx,0
|
||||
28 ori \rx,\rx,(\v<<8)&0xFF00
|
||||
29 ori \rx,\rx,(\v>>8)&0x00FF
|
||||
30 .endm
|
||||
31
|
||||
32 # constants from linker script, or defsym
|
||||
33
|
||||
34 .ifdef BIOS_32
|
||||
35 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
36 .set BIOS_MSR,0x0002B000
|
||||
37 .else
|
||||
38 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
39 .set BIOS_MSR,0x8002B000
|
||||
40 .endif
|
||||
41
|
||||
42 # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/s
|
||||
43 .ifdef BIOS_LE
|
||||
44 .set BIOS_ERATW2,0x000000BF
|
||||
45 .else
|
||||
46 .set BIOS_ERATW2,0x0000003F
|
||||
47 .endif
|
||||
48
|
||||
49 # bios might be able to use one stack during thread startup if careful
|
||||
50 .ifndef BIOS_STACK_0
|
||||
51 .set BIOS_STACK_0,_stack_0
|
||||
52 .endif
|
||||
53
|
||||
54 .ifndef BIOS_STACK_1
|
||||
55 .set BIOS_STACK_1,_stack_1
|
||||
56 .endif
|
||||
57
|
||||
58 .ifndef BIOS_START
|
||||
59 .set BIOS_START,0x00010000
|
||||
60 .endif
|
||||
61
|
||||
62 .section .text
|
||||
63
|
||||
64 .global _start
|
||||
65
|
||||
66 .org 0x000
|
||||
67 _start:
|
||||
68 int_000:
|
||||
69 0000 48000400 b boot_start
|
||||
70
|
||||
71 # critical input
|
||||
72 0004 00000000 .org 0x020
|
||||
72 00000000
|
||||
72 00000000
|
||||
72 00000000
|
||||
72 00000000
|
||||
73 int_020:
|
||||
74 .ifndef INT_UNHANDLED
|
||||
75 0020 48000000 b .
|
||||
76 .else
|
||||
77 b INT_UNHANDLED
|
||||
78 .endif
|
||||
79
|
||||
80 # debug
|
||||
81 0024 00000000 .org 0x040
|
||||
81 00000000
|
||||
81 00000000
|
||||
81 00000000
|
||||
81 00000000
|
||||
82 int_040:
|
||||
83 0040 48000000 b .
|
||||
84
|
||||
85 # dsi
|
||||
86 0044 00000000 .org 0x060
|
||||
86 00000000
|
||||
86 00000000
|
||||
86 00000000
|
||||
86 00000000
|
||||
87 int_060:
|
||||
88 0060 48000000 b .
|
||||
89
|
||||
90 # isi
|
||||
91 0064 00000000 .org 0x080
|
||||
91 00000000
|
||||
91 00000000
|
||||
91 00000000
|
||||
91 00000000
|
||||
92 int_080:
|
||||
93 0080 48000000 b .
|
||||
94
|
||||
95 # external
|
||||
96 0084 00000000 .org 0x0A0
|
||||
96 00000000
|
||||
96 00000000
|
||||
96 00000000
|
||||
96 00000000
|
||||
97 int_0A0:
|
||||
98 00a0 48000000 b .
|
||||
99
|
||||
100 # alignment
|
||||
101 00a4 00000000 .org 0x0C0
|
||||
101 00000000
|
||||
101 00000000
|
||||
101 00000000
|
||||
101 00000000
|
||||
102 int_0C0:
|
||||
103 00c0 48000000 b .
|
||||
104
|
||||
105 # program
|
||||
106 00c4 00000000 .org 0x0E0
|
||||
106 00000000
|
||||
106 00000000
|
||||
106 00000000
|
||||
106 00000000
|
||||
107 int_0E0:
|
||||
108 00e0 48000000 b .
|
||||
109
|
||||
110 # fp unavailable
|
||||
111 00e4 00000000 .org 0x100
|
||||
111 00000000
|
||||
111 00000000
|
||||
111 00000000
|
||||
111 00000000
|
||||
112 int_100:
|
||||
113 0100 48000000 b .
|
||||
114
|
||||
115 # sc
|
||||
116 0104 00000000 .org 0x120
|
||||
116 00000000
|
||||
116 00000000
|
||||
116 00000000
|
||||
116 00000000
|
||||
117 int_120:
|
||||
118 0120 48000000 b .
|
||||
119
|
||||
120 # apu unavailable
|
||||
121 0124 00000000 .org 0x140
|
||||
121 00000000
|
||||
121 00000000
|
||||
121 00000000
|
||||
121 00000000
|
||||
122 int_140:
|
||||
123 0140 48000000 b .
|
||||
124
|
||||
125 # decrementer
|
||||
126 0144 00000000 .org 0x160
|
||||
126 00000000
|
||||
126 00000000
|
||||
126 00000000
|
||||
126 00000000
|
||||
127 int_160:
|
||||
128 0160 48000000 b .
|
||||
129
|
||||
130 # fit
|
||||
131 0164 00000000 .org 0x180
|
||||
131 00000000
|
||||
131 00000000
|
||||
131 00000000
|
||||
131 00000000
|
||||
132 int_180:
|
||||
133 0180 48000000 b .
|
||||
134
|
||||
135 # watchdog
|
||||
136 0184 00000000 .org 0x1A0
|
||||
136 00000000
|
||||
136 00000000
|
||||
136 00000000
|
||||
136 00000000
|
||||
137 int_1A0:
|
||||
138 01a0 48000000 b .
|
||||
139
|
||||
140 # dtlb
|
||||
141 01a4 00000000 .org 0x1C0
|
||||
141 00000000
|
||||
141 00000000
|
||||
141 00000000
|
||||
141 00000000
|
||||
142 int_1C0:
|
||||
143 01c0 48000000 b .
|
||||
144
|
||||
145 # itlb
|
||||
146 01c4 00000000 .org 0x1E0
|
||||
146 00000000
|
||||
146 00000000
|
||||
146 00000000
|
||||
146 00000000
|
||||
147 int_1E0:
|
||||
148 01e0 48000000 b .
|
||||
149
|
||||
150 # vector unavailable
|
||||
151 01e4 00000000 .org 0x200
|
||||
151 00000000
|
||||
151 00000000
|
||||
151 00000000
|
||||
151 00000000
|
||||
152 int_200:
|
||||
153 0200 48000000 b .
|
||||
154
|
||||
155 #
|
||||
156 0204 00000000 .org 0x220
|
||||
156 00000000
|
||||
156 00000000
|
||||
156 00000000
|
||||
156 00000000
|
||||
157 int_220:
|
||||
158 0220 48000000 b .
|
||||
159
|
||||
160 #
|
||||
161 0224 00000000 .org 0x240
|
||||
161 00000000
|
||||
161 00000000
|
||||
161 00000000
|
||||
161 00000000
|
||||
162 int_240:
|
||||
163 0240 48000000 b .
|
||||
164
|
||||
165 #
|
||||
166 0244 00000000 .org 0x260
|
||||
166 00000000
|
||||
166 00000000
|
||||
166 00000000
|
||||
166 00000000
|
||||
167 int_260:
|
||||
168 0260 48000000 b .
|
||||
169
|
||||
170 # doorbell
|
||||
171 0264 00000000 .org 0x280
|
||||
171 00000000
|
||||
171 00000000
|
||||
171 00000000
|
||||
171 00000000
|
||||
172 int_280:
|
||||
173 0280 48000000 b .
|
||||
174
|
||||
175 # doorbell critical
|
||||
176 0284 00000000 .org 0x2A0
|
||||
176 00000000
|
||||
176 00000000
|
||||
176 00000000
|
||||
176 00000000
|
||||
177 int_2A0:
|
||||
178 02a0 48000000 b .
|
||||
179
|
||||
180 # doorbell guest
|
||||
181 02a4 00000000 .org 0x2C0
|
||||
181 00000000
|
||||
181 00000000
|
||||
181 00000000
|
||||
181 00000000
|
||||
182 int_2C0:
|
||||
183 02c0 48000000 b .
|
||||
184
|
||||
185 # doorbell guest critical
|
||||
186 02c4 00000000 .org 0x2E0
|
||||
186 00000000
|
||||
186 00000000
|
||||
186 00000000
|
||||
186 00000000
|
||||
187 int_2E0:
|
||||
188 02e0 48000000 b .
|
||||
189
|
||||
190 # hvsc
|
||||
191 02e4 00000000 .org 0x300
|
||||
191 00000000
|
||||
191 00000000
|
||||
191 00000000
|
||||
191 00000000
|
||||
192 int_300:
|
||||
193 0300 48000000 b .
|
||||
194
|
||||
195 # hvpriv
|
||||
196 0304 00000000 .org 0x320
|
||||
196 00000000
|
||||
196 00000000
|
||||
196 00000000
|
||||
196 00000000
|
||||
197 int_320:
|
||||
198 0320 48000000 b .
|
||||
199
|
||||
200 # lrat
|
||||
201 0324 00000000 .org 0x340
|
||||
201 00000000
|
||||
201 00000000
|
||||
201 00000000
|
||||
201 00000000
|
||||
202 int_340:
|
||||
203 0340 48000000 b .
|
||||
204
|
||||
205 # -------------------------------------------------------------------------------------------------
|
||||
206 # initial translation
|
||||
207 # both erats:
|
||||
208 # 00000000 64K: (rom, BE)
|
||||
209 # 00010000 64K: (ram, BE or LE)
|
||||
210 #
|
||||
211 0344 00000000 .org 0x400
|
||||
211 00000000
|
||||
211 00000000
|
||||
211 00000000
|
||||
211 00000000
|
||||
212 boot_start:
|
||||
213
|
||||
214 0400 7CBE6AA6 mfspr r5,tir # who am i?
|
||||
215 0404 2C250000 cmpdi r5,0x00 # skip unless T0
|
||||
216 0408 408200E0 bne init_t123
|
||||
217
|
||||
218 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
219
|
||||
220 # derat 31 @00000000
|
||||
221 0410 3800001F li r0,0x001F # entry #31
|
||||
222 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
|
||||
223 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
224 041c 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
225
|
||||
226 0420 7C7CFBA6 mtspr mmucr0,r3
|
||||
227 0424 7C4011A6 eratwe r2,r0,2
|
||||
228 0428 7C8009A6 eratwe r4,r0,1
|
||||
229 042c 7D0001A6 eratwe r8,r0,0
|
||||
230 0430 4C00012C isync
|
||||
231
|
||||
232 0434 39400000 load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
|
||||
232 654A0000
|
||||
232 614A003F
|
||||
233
|
||||
234 # derat 30 @<BIOS_START>
|
||||
235 0440 3800001E li r0,0x001E # entry #30
|
||||
236 0444 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
236 64840001
|
||||
236 60840000
|
||||
237 0450 39000000 load32 r8,BIOS_START
|
||||
237 65080001
|
||||
237 61080000
|
||||
238 045c 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
239
|
||||
240 0460 7D4011A6 eratwe r10,r0,2
|
||||
241 0464 7C8009A6 eratwe r4,r0,1
|
||||
242 0468 7D0001A6 eratwe r8,r0,0
|
||||
243 046c 4C00012C isync
|
||||
244
|
||||
245 0470 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
246
|
||||
247 # ierat 15 @00000000
|
||||
248 0474 3800000F li r0,0x000F # entry #15
|
||||
249 0478 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
|
||||
250 047c 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
251 0480 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
252
|
||||
253 0484 7C7CFBA6 mtspr mmucr0,r3
|
||||
254 0488 7C4011A6 eratwe r2,r0,2
|
||||
255 048c 7C8009A6 eratwe r4,r0,1
|
||||
256 0490 7D0001A6 eratwe r8,r0,0
|
||||
257 0494 4C00012C isync
|
||||
258
|
||||
259 # *** leave the init'd entry 14 for MT access to FFFFFFC0
|
||||
260 # ierat 13 @<BIOS_START>
|
||||
261 0498 3800000D li r0,0x000D # entry #13
|
||||
262 049c 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
262 64840001
|
||||
262 60840000
|
||||
263 04a8 39000000 load32 r8,BIOS_START
|
||||
263 65080001
|
||||
263 61080000
|
||||
264 04b4 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
265
|
||||
266 04b8 7D4011A6 eratwe r10,r0,2
|
||||
267 04bc 7C8009A6 eratwe r4,r0,1
|
||||
268 04c0 7D0001A6 eratwe r8,r0,0
|
||||
269 04c4 4C00012C isync
|
||||
270
|
||||
271 04c8 48000004 b init_t0
|
||||
272
|
||||
273 # -------------------------------------------------------------------------------------------------
|
||||
274 # init
|
||||
275 #
|
||||
276
|
||||
277 # T0
|
||||
278
|
||||
279 init_t0:
|
||||
280
|
||||
281 # set up BIOS msr
|
||||
282
|
||||
283 04cc 39400000 load32 r10,BIOS_MSR
|
||||
283 654A8002
|
||||
283 614AB000
|
||||
284 04d8 7D400124 mtmsr r10
|
||||
285 04dc 4C00012C isync
|
||||
286 # can't use load32 unless you can .set BIOS_STACK_0 to the linked value
|
||||
287 # load32 r1,BIOS_STACK_0 # @stack_0
|
||||
288 # this ignores def
|
||||
289 # lis r1,_stack_0@h
|
||||
290 # ori r1,r1,_stack_0@l
|
||||
291 # this requires data load
|
||||
292 04e0 80200000 lwz r1,stack_0(r0)
|
||||
293
|
||||
294 04e4 48000020 b boot_complete
|
||||
295
|
||||
296 # except T0
|
||||
297
|
||||
298 init_t123:
|
||||
299
|
||||
300 # set up BIOS msr
|
||||
301
|
||||
302 04e8 39400000 load32 r10,BIOS_MSR
|
||||
302 654A8002
|
||||
302 614AB000
|
||||
303 04f4 7D400124 mtmsr r10
|
||||
304 04f8 4C00012C isync
|
||||
305 # check tir if more than 2 threads possible
|
||||
306 04fc 80200000 lwz r1,stack_1(r0)
|
||||
307
|
||||
308 0500 48000004 b boot_complete
|
||||
309
|
||||
310 # -------------------------------------------------------------------------------------------------
|
||||
311 boot_complete:
|
||||
312
|
||||
313 # set up thread and hop to it
|
||||
314
|
||||
315 0504 3C600000 lis r3,main@h
|
||||
316 0508 60630000 ori r3,r3,main@l
|
||||
317 050c 7C6903A6 mtctr r3
|
||||
318 0510 7C7E6AA6 mfspr r3,tir # who am i?
|
||||
319 0514 4E800421 bctrl
|
||||
320 0518 480002E4 b kernel_return
|
||||
321
|
||||
322 # -------------------------------------------------------------------------------------------------
|
||||
323
|
||||
324 051c 00000000 .org 0x7FC
|
||||
324 00000000
|
||||
324 00000000
|
||||
324 00000000
|
||||
324 00000000
|
||||
325 kernel_return:
|
||||
326 07fc 48000000 b .
|
||||
327
|
||||
328 # dec
|
||||
329 .org 0x800
|
||||
330 int_800:
|
||||
331 0800 48000000 b .
|
||||
332
|
||||
333 # perf
|
||||
334 0804 00000000 .org 0x820
|
||||
334 00000000
|
||||
334 00000000
|
||||
334 00000000
|
||||
334 00000000
|
||||
335 int_820:
|
||||
336 0820 48000000 b .
|
||||
337
|
||||
338 0824 00000000 .org 0x8F0
|
||||
338 00000000
|
||||
338 00000000
|
||||
338 00000000
|
||||
338 00000000
|
||||
339 .section .rodata
|
||||
340 0000 00000000 stack_0: .long BIOS_STACK_0
|
||||
341 0004 00000000 stack_1: .long BIOS_STACK_1
|
||||
Binary file not shown.
@ -0,0 +1,144 @@
|
||||
# © IBM Corp. 2020
|
||||
# Licensed under and subject to the terms of the CC-BY 4.0
|
||||
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
# Additional rights, including the right to physically implement a softcore
|
||||
# that is compliant with the required sections of the Power ISA
|
||||
# Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
# This README will be updated with additional information when OpenPOWER's
|
||||
# license is available.
|
||||
|
||||
#-----------------------------------------
|
||||
# Defines
|
||||
#-----------------------------------------
|
||||
|
||||
# Regs
|
||||
|
||||
.set r0, 0
|
||||
.set r1, 1
|
||||
.set r2, 2
|
||||
.set r3, 3
|
||||
.set r4, 4
|
||||
.set r5, 5
|
||||
.set r6, 6
|
||||
.set r7, 7
|
||||
.set r8, 8
|
||||
.set r9, 9
|
||||
.set r10,10
|
||||
.set r11,11
|
||||
.set r12,12
|
||||
.set r13,13
|
||||
.set r14,14
|
||||
.set r15,15
|
||||
.set r16,16
|
||||
.set r17,17
|
||||
.set r18,18
|
||||
.set r19,19
|
||||
.set r20,20
|
||||
.set r21,21
|
||||
.set r22,22
|
||||
.set r23,23
|
||||
.set r24,24
|
||||
.set r25,25
|
||||
.set r26,26
|
||||
.set r27,27
|
||||
.set r28,28
|
||||
.set r29,29
|
||||
.set r30,30
|
||||
.set r31,31
|
||||
|
||||
.set f0, 0
|
||||
.set f1, 1
|
||||
.set f2, 2
|
||||
.set f3, 3
|
||||
.set f4, 4
|
||||
.set f5, 5
|
||||
.set f6, 6
|
||||
.set f7, 7
|
||||
.set f8, 8
|
||||
.set f9, 9
|
||||
.set f10,10
|
||||
.set f11,11
|
||||
.set f12,12
|
||||
.set f13,13
|
||||
.set f14,14
|
||||
.set f15,15
|
||||
.set f16,16
|
||||
.set f17,17
|
||||
.set f18,18
|
||||
.set f19,19
|
||||
.set f20,20
|
||||
.set f21,21
|
||||
.set f22,22
|
||||
.set f23,23
|
||||
.set f24,24
|
||||
.set f25,25
|
||||
.set f26,26
|
||||
.set f27,27
|
||||
.set f28,28
|
||||
.set f29,29
|
||||
.set f30,30
|
||||
.set f31,31
|
||||
|
||||
.set cr0, 0
|
||||
.set cr1, 1
|
||||
.set cr2, 2
|
||||
.set cr3, 3
|
||||
.set cr4, 4
|
||||
.set cr5, 5
|
||||
.set cr6, 6
|
||||
.set cr7, 7
|
||||
|
||||
# SPR numbers
|
||||
|
||||
.set srr0, 26
|
||||
.set srr1, 27
|
||||
.set epcr, 307
|
||||
.set tar, 815
|
||||
|
||||
.set dbsr, 304
|
||||
.set dbcr0, 308
|
||||
.set dbcr1, 309
|
||||
.set dbcr2, 310
|
||||
.set dbcr3, 848
|
||||
|
||||
.set ivpr, 63
|
||||
|
||||
.set iucr0, 1011
|
||||
.set iucr1, 883
|
||||
.set iucr2, 884
|
||||
|
||||
.set iudbg0, 888
|
||||
.set iudbg1, 889
|
||||
.set iudbg2, 890
|
||||
.set iulfsr, 891
|
||||
.set iullcr, 892
|
||||
|
||||
.set mmucr0, 1020
|
||||
.set mmucr1, 1021
|
||||
.set mmucr2, 1022
|
||||
.set mmucr3, 1023
|
||||
|
||||
.set tb, 268
|
||||
.set tbl, 284
|
||||
.set tbh, 285
|
||||
|
||||
.set dec, 22
|
||||
.set udec, 550
|
||||
.set tsr, 336
|
||||
.set tcr, 340
|
||||
|
||||
.set xucr0, 1014
|
||||
.set xucr1, 851
|
||||
.set xucr2, 1016
|
||||
.set xucr3, 852
|
||||
.set xucr4, 853
|
||||
|
||||
.set tens, 438
|
||||
.set tenc, 439
|
||||
.set tensr, 437
|
||||
|
||||
.set pid, 48
|
||||
.set pir, 286
|
||||
.set pvr, 287
|
||||
.set tir, 446
|
||||
|
||||
@ -0,0 +1,86 @@
|
||||
/* this version puts kernel at rom start and bios at ram start
|
||||
|
||||
/* define format
|
||||
INCLUDE output_format.ld */
|
||||
OUTPUT_FORMAT("elf32-powerpc")
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
/* define origin, len of rom, ram, csr */
|
||||
INCLUDE regions.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* kernel code */
|
||||
.kernel :
|
||||
{
|
||||
/*_fkernel = .; */
|
||||
*crt0*(.text)
|
||||
KEEP(*crt0*(.text))
|
||||
*(.gnu.linkonce.t.*)
|
||||
_ekernel = .;
|
||||
} > rom
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_frodata = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
*(.got2 .got2.*)
|
||||
*(.toc .toc.*)
|
||||
FILL(0);
|
||||
. = ALIGN(8);
|
||||
_erodata = .;
|
||||
} > rom
|
||||
|
||||
/* kernel data to be copied to ram by rom code...*/
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_fdata = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
FILL(0);
|
||||
. = ALIGN(8);
|
||||
_edata = .;
|
||||
} > ram AT > rom
|
||||
|
||||
/* bios code */
|
||||
.bios :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
bios.o (.text .text* .gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} > ram AT > ram
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_fbss = .;
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
} > ram
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.eh_frame)
|
||||
*(.comment)
|
||||
*(.gnu.attributes)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
PROVIDE(_stack_size = 0x00010000);
|
||||
PROVIDE(_stack_0 = ORIGIN(ram) + LENGTH(ram) - 8);
|
||||
PROVIDE(_stack_1 = _stack_0 - _stack_size);
|
||||
|
||||
PROVIDE(_fdata_rom = LOADADDR(.data));
|
||||
PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
|
||||
PROVIDE(_bios_start = LOADADDR(.bios));
|
||||
@ -0,0 +1,86 @@
|
||||
/* this version puts kernel and bios at rom start
|
||||
|
||||
/* define format
|
||||
INCLUDE output_format.ld */
|
||||
OUTPUT_FORMAT("elf32-powerpc")
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
/* define origin, len of rom, ram, csr */
|
||||
INCLUDE regions.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* kernel code */
|
||||
.kernel :
|
||||
{
|
||||
/*_fkernel = .; */
|
||||
*crt0*(.text)
|
||||
KEEP(*crt0*(.text))
|
||||
*(.gnu.linkonce.t.*)
|
||||
_ekernel = .;
|
||||
} > rom
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_frodata = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
*(.got2 .got2.*)
|
||||
*(.toc .toc.*)
|
||||
FILL(0);
|
||||
. = ALIGN(8);
|
||||
_erodata = .;
|
||||
} > rom
|
||||
|
||||
/* bios code */
|
||||
.bios :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
bios.o (.text .text* .gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} > rom
|
||||
|
||||
/* kernel data to be copied to ram by rom code...*/
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_fdata = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
FILL(0);
|
||||
. = ALIGN(8);
|
||||
_edata = .;
|
||||
} > ram AT > rom
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_fbss = .;
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
} > ram
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.eh_frame)
|
||||
*(.comment)
|
||||
*(.gnu.attributes)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
PROVIDE(_stack_size = 0x00010000);
|
||||
PROVIDE(_stack_0 = ORIGIN(ram) + LENGTH(ram) - 8);
|
||||
PROVIDE(_stack_1 = _stack_0 - _stack_size);
|
||||
|
||||
PROVIDE(_fdata_rom = LOADADDR(.data));
|
||||
PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
|
||||
PROVIDE(_bios_start = LOADADDR(.bios));
|
||||
@ -0,0 +1,21 @@
|
||||
# Updating build process - test1
|
||||
|
||||
* 32b crosscompile
|
||||
* partial original test kernel plus bios.c to complete boot
|
||||
* this version puts kernel at rom start and bios at ram start (different erat entries)
|
||||
|
||||
```
|
||||
build
|
||||
|
||||
# create mem file for coco sim
|
||||
cp rom.init test2
|
||||
```
|
||||
|
||||
* this version puts kernel and bios in rom
|
||||
|
||||
```
|
||||
build2
|
||||
|
||||
# create mem file for coco sim
|
||||
cp rom.init test2
|
||||
```
|
||||
@ -0,0 +1,5 @@
|
||||
MEMORY {
|
||||
rom : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
ram : ORIGIN = 0x00010000, LENGTH = 0x00010000
|
||||
csr : ORIGIN = 0xFFF00000, LENGTH = 0x00010000
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
@ -0,0 +1,319 @@
|
||||
|
||||
rom: file format elf32-powerpc
|
||||
|
||||
|
||||
Disassembly of section .kernel:
|
||||
|
||||
00000000 <_start>:
|
||||
0: 48 00 04 00 b 400 <boot_start>
|
||||
...
|
||||
|
||||
00000020 <int_020>:
|
||||
20: 48 00 00 00 b 20 <int_020>
|
||||
...
|
||||
|
||||
00000040 <int_040>:
|
||||
40: 48 00 00 00 b 40 <int_040>
|
||||
...
|
||||
|
||||
00000060 <int_060>:
|
||||
60: 48 00 00 00 b 60 <int_060>
|
||||
...
|
||||
|
||||
00000080 <int_080>:
|
||||
80: 48 00 00 00 b 80 <int_080>
|
||||
...
|
||||
|
||||
000000a0 <int_0A0>:
|
||||
a0: 48 00 00 00 b a0 <int_0A0>
|
||||
...
|
||||
|
||||
000000c0 <int_0C0>:
|
||||
c0: 48 00 00 00 b c0 <int_0C0>
|
||||
...
|
||||
|
||||
000000e0 <int_0E0>:
|
||||
e0: 48 00 00 00 b e0 <int_0E0>
|
||||
...
|
||||
|
||||
00000100 <int_100>:
|
||||
100: 48 00 00 00 b 100 <int_100>
|
||||
...
|
||||
|
||||
00000120 <int_120>:
|
||||
120: 48 00 00 00 b 120 <int_120>
|
||||
...
|
||||
|
||||
00000140 <int_140>:
|
||||
140: 48 00 00 00 b 140 <int_140>
|
||||
...
|
||||
|
||||
00000160 <int_160>:
|
||||
160: 48 00 00 00 b 160 <int_160>
|
||||
...
|
||||
|
||||
00000180 <int_180>:
|
||||
180: 48 00 00 00 b 180 <int_180>
|
||||
...
|
||||
|
||||
000001a0 <int_1A0>:
|
||||
1a0: 48 00 00 00 b 1a0 <int_1A0>
|
||||
...
|
||||
|
||||
000001c0 <int_1C0>:
|
||||
1c0: 48 00 00 00 b 1c0 <int_1C0>
|
||||
...
|
||||
|
||||
000001e0 <int_1E0>:
|
||||
1e0: 48 00 00 00 b 1e0 <int_1E0>
|
||||
...
|
||||
|
||||
00000200 <int_200>:
|
||||
200: 48 00 00 00 b 200 <int_200>
|
||||
...
|
||||
|
||||
00000220 <int_220>:
|
||||
220: 48 00 00 00 b 220 <int_220>
|
||||
...
|
||||
|
||||
00000240 <int_240>:
|
||||
240: 48 00 00 00 b 240 <int_240>
|
||||
...
|
||||
|
||||
00000260 <int_260>:
|
||||
260: 48 00 00 00 b 260 <int_260>
|
||||
...
|
||||
|
||||
00000280 <int_280>:
|
||||
280: 48 00 00 00 b 280 <int_280>
|
||||
...
|
||||
|
||||
000002a0 <int_2A0>:
|
||||
2a0: 48 00 00 00 b 2a0 <int_2A0>
|
||||
...
|
||||
|
||||
000002c0 <int_2C0>:
|
||||
2c0: 48 00 00 00 b 2c0 <int_2C0>
|
||||
...
|
||||
|
||||
000002e0 <int_2E0>:
|
||||
2e0: 48 00 00 00 b 2e0 <int_2E0>
|
||||
...
|
||||
|
||||
00000300 <int_300>:
|
||||
300: 48 00 00 00 b 300 <int_300>
|
||||
...
|
||||
|
||||
00000320 <int_320>:
|
||||
320: 48 00 00 00 b 320 <int_320>
|
||||
...
|
||||
|
||||
00000340 <int_340>:
|
||||
340: 48 00 00 00 b 340 <int_340>
|
||||
...
|
||||
|
||||
00000400 <boot_start>:
|
||||
400: 7c be 6a a6 mfspr r5,446
|
||||
404: 2c 25 00 00 cmpdi r5,0
|
||||
408: 40 82 00 e0 bne 4e8 <init_t123>
|
||||
40c: 3c 60 8c 00 lis r3,-29696
|
||||
410: 38 00 00 1f li r0,31
|
||||
414: 38 40 00 15 li r2,21
|
||||
418: 38 80 00 00 li r4,0
|
||||
41c: 39 00 02 3f li r8,575
|
||||
420: 7c 7c fb a6 mtspr 1020,r3
|
||||
424: 7c 40 11 a6 eratwe r2,r0,2
|
||||
428: 7c 80 09 a6 eratwe r4,r0,1
|
||||
42c: 7d 00 01 a6 mtfprwa f8,r0
|
||||
430: 4c 00 01 2c isync
|
||||
434: 39 40 00 00 li r10,0
|
||||
438: 65 4a 00 00 oris r10,r10,0
|
||||
43c: 61 4a 00 3f ori r10,r10,63
|
||||
440: 38 00 00 1e li r0,30
|
||||
444: 38 80 00 00 li r4,0
|
||||
448: 64 84 00 01 oris r4,r4,1
|
||||
44c: 60 84 00 00 ori r4,r4,0
|
||||
450: 39 00 00 00 li r8,0
|
||||
454: 65 08 00 01 oris r8,r8,1
|
||||
458: 61 08 00 00 ori r8,r8,0
|
||||
45c: 61 08 02 3f ori r8,r8,575
|
||||
460: 7d 40 11 a6 eratwe r10,r0,2
|
||||
464: 7c 80 09 a6 eratwe r4,r0,1
|
||||
468: 7d 00 01 a6 mtfprwa f8,r0
|
||||
46c: 4c 00 01 2c isync
|
||||
470: 3c 60 88 00 lis r3,-30720
|
||||
474: 38 00 00 0f li r0,15
|
||||
478: 38 40 00 3f li r2,63
|
||||
47c: 38 80 00 00 li r4,0
|
||||
480: 39 00 02 3f li r8,575
|
||||
484: 7c 7c fb a6 mtspr 1020,r3
|
||||
488: 7c 40 11 a6 eratwe r2,r0,2
|
||||
48c: 7c 80 09 a6 eratwe r4,r0,1
|
||||
490: 7d 00 01 a6 mtfprwa f8,r0
|
||||
494: 4c 00 01 2c isync
|
||||
498: 38 00 00 0d li r0,13
|
||||
49c: 38 80 00 00 li r4,0
|
||||
4a0: 64 84 00 01 oris r4,r4,1
|
||||
4a4: 60 84 00 00 ori r4,r4,0
|
||||
4a8: 39 00 00 00 li r8,0
|
||||
4ac: 65 08 00 01 oris r8,r8,1
|
||||
4b0: 61 08 00 00 ori r8,r8,0
|
||||
4b4: 61 08 02 3f ori r8,r8,575
|
||||
4b8: 7d 40 11 a6 eratwe r10,r0,2
|
||||
4bc: 7c 80 09 a6 eratwe r4,r0,1
|
||||
4c0: 7d 00 01 a6 mtfprwa f8,r0
|
||||
4c4: 4c 00 01 2c isync
|
||||
4c8: 48 00 00 04 b 4cc <init_t0>
|
||||
|
||||
000004cc <init_t0>:
|
||||
4cc: 39 40 00 00 li r10,0
|
||||
4d0: 65 4a 80 02 oris r10,r10,32770
|
||||
4d4: 61 4a b0 00 ori r10,r10,45056
|
||||
4d8: 7d 40 01 24 mtmsr r10
|
||||
4dc: 4c 00 01 2c isync
|
||||
4e0: 80 20 08 f0 lwz r1,2288(0)
|
||||
4e4: 48 00 00 20 b 504 <boot_complete>
|
||||
|
||||
000004e8 <init_t123>:
|
||||
4e8: 39 40 00 00 li r10,0
|
||||
4ec: 65 4a 80 02 oris r10,r10,32770
|
||||
4f0: 61 4a b0 00 ori r10,r10,45056
|
||||
4f4: 7d 40 01 24 mtmsr r10
|
||||
4f8: 4c 00 01 2c isync
|
||||
4fc: 80 20 08 f4 lwz r1,2292(0)
|
||||
500: 48 00 00 04 b 504 <boot_complete>
|
||||
|
||||
00000504 <boot_complete>:
|
||||
504: 3c 60 00 00 lis r3,0
|
||||
508: 60 63 09 00 ori r3,r3,2304
|
||||
50c: 7c 69 03 a6 mtctr r3
|
||||
510: 7c 7e 6a a6 mfspr r3,446
|
||||
514: 4e 80 04 21 bctrl
|
||||
518: 48 00 02 e4 b 7fc <kernel_return>
|
||||
...
|
||||
|
||||
000007fc <kernel_return>:
|
||||
7fc: 48 00 00 00 b 7fc <kernel_return>
|
||||
|
||||
00000800 <int_800>:
|
||||
800: 48 00 00 00 b 800 <int_800>
|
||||
...
|
||||
|
||||
00000820 <int_820>:
|
||||
820: 48 00 00 00 b 820 <int_820>
|
||||
...
|
||||
|
||||
Disassembly of section .bios:
|
||||
|
||||
000008f8 <main-0x8>:
|
||||
8f8: 60 00 00 00 nop
|
||||
8fc: 60 00 00 00 nop
|
||||
|
||||
00000900 <main>:
|
||||
900: 94 21 ff c0 stwu r1,-64(r1)
|
||||
904: 90 61 00 38 stw r3,56(r1)
|
||||
908: 3d 20 00 01 lis r9,1
|
||||
90c: 81 29 00 00 lwz r9,0(r9)
|
||||
910: 91 21 00 0c stw r9,12(r1)
|
||||
914: 81 21 00 38 lwz r9,56(r1)
|
||||
918: 2c 09 00 00 cmpwi r9,0
|
||||
91c: 41 82 00 0c beq 928 <main+0x28>
|
||||
920: 39 20 ff ff li r9,-1
|
||||
924: 48 00 01 7c b aa0 <main+0x1a0>
|
||||
928: 3d 20 00 00 lis r9,0
|
||||
92c: 81 29 0a ac lwz r9,2732(r9)
|
||||
930: 91 21 00 08 stw r9,8(r1)
|
||||
934: 48 00 00 28 b 95c <main+0x5c>
|
||||
938: 81 21 00 0c lwz r9,12(r1)
|
||||
93c: 39 49 00 04 addi r10,r9,4
|
||||
940: 91 41 00 0c stw r10,12(r1)
|
||||
944: 81 41 00 08 lwz r10,8(r1)
|
||||
948: 81 4a 00 00 lwz r10,0(r10)
|
||||
94c: 91 49 00 00 stw r10,0(r9)
|
||||
950: 81 21 00 08 lwz r9,8(r1)
|
||||
954: 39 29 00 04 addi r9,r9,4
|
||||
958: 91 21 00 08 stw r9,8(r1)
|
||||
95c: 3d 20 00 00 lis r9,0
|
||||
960: 81 29 0a ac lwz r9,2732(r9)
|
||||
964: 81 41 00 08 lwz r10,8(r1)
|
||||
968: 7c 0a 48 40 cmplw r10,r9
|
||||
96c: 41 80 ff cc blt 938 <main+0x38>
|
||||
970: 3d 20 00 01 lis r9,1
|
||||
974: 81 29 00 00 lwz r9,0(r9)
|
||||
978: 91 21 00 08 stw r9,8(r1)
|
||||
97c: 48 00 00 20 b 99c <main+0x9c>
|
||||
980: 3d 20 00 01 lis r9,1
|
||||
984: 81 29 00 00 lwz r9,0(r9)
|
||||
988: 39 40 00 00 li r10,0
|
||||
98c: 91 49 00 00 stw r10,0(r9)
|
||||
990: 81 21 00 08 lwz r9,8(r1)
|
||||
994: 39 29 00 04 addi r9,r9,4
|
||||
998: 91 21 00 08 stw r9,8(r1)
|
||||
99c: 3d 20 00 01 lis r9,1
|
||||
9a0: 81 29 00 00 lwz r9,0(r9)
|
||||
9a4: 81 41 00 08 lwz r10,8(r1)
|
||||
9a8: 7c 0a 48 40 cmplw r10,r9
|
||||
9ac: 41 80 ff d4 blt 980 <main+0x80>
|
||||
9b0: 3d 20 03 00 lis r9,768
|
||||
9b4: 91 21 00 30 stw r9,48(r1)
|
||||
9b8: 81 21 00 30 lwz r9,48(r1)
|
||||
9bc: 3c 80 00 00 lis r4,0
|
||||
9c0: 60 84 00 09 ori r4,r4,9
|
||||
9c4: 7c 93 4b a6 mtspr 307,r4
|
||||
9c8: 60 00 00 00 nop
|
||||
9cc: 39 20 00 00 li r9,0
|
||||
9d0: 91 21 00 2c stw r9,44(r1)
|
||||
9d4: 81 21 00 2c lwz r9,44(r1)
|
||||
9d8: 3c 80 00 00 lis r4,0
|
||||
9dc: 60 84 00 09 ori r4,r4,9
|
||||
9e0: 7c 96 03 a6 mtdec r4
|
||||
9e4: 60 00 00 00 nop
|
||||
9e8: 39 20 00 00 li r9,0
|
||||
9ec: 91 21 00 28 stw r9,40(r1)
|
||||
9f0: 81 21 00 28 lwz r9,40(r1)
|
||||
9f4: 3c 80 00 00 lis r4,0
|
||||
9f8: 60 84 00 09 ori r4,r4,9
|
||||
9fc: 7c 9d 43 a6 mttbu r4
|
||||
a00: 60 00 00 00 nop
|
||||
a04: 39 20 00 00 li r9,0
|
||||
a08: 91 21 00 24 stw r9,36(r1)
|
||||
a0c: 81 21 00 24 lwz r9,36(r1)
|
||||
a10: 3c 80 00 00 lis r4,0
|
||||
a14: 60 84 00 09 ori r4,r4,9
|
||||
a18: 7c 9c 43 a6 mttbl r4
|
||||
a1c: 60 00 00 00 nop
|
||||
a20: 3d 20 fe 00 lis r9,-512
|
||||
a24: 91 21 00 20 stw r9,32(r1)
|
||||
a28: 81 21 00 20 lwz r9,32(r1)
|
||||
a2c: 3c 80 00 00 lis r4,0
|
||||
a30: 60 84 00 09 ori r4,r4,9
|
||||
a34: 7c 90 53 a6 mtspr 336,r4
|
||||
a38: 60 00 00 00 nop
|
||||
a3c: 7d 36 fa a6 mfspr r9,1014
|
||||
a40: 91 21 00 1c stw r9,28(r1)
|
||||
a44: 81 21 00 1c lwz r9,28(r1)
|
||||
a48: 55 29 05 ac rlwinm r9,r9,0,22,22
|
||||
a4c: 91 21 00 18 stw r9,24(r1)
|
||||
a50: 81 21 00 18 lwz r9,24(r1)
|
||||
a54: 3c 80 00 00 lis r4,0
|
||||
a58: 60 84 00 09 ori r4,r4,9
|
||||
a5c: 7c 96 fb a6 mtspr 1014,r4
|
||||
a60: 60 00 00 00 nop
|
||||
a64: 39 20 00 00 li r9,0
|
||||
a68: 91 21 00 14 stw r9,20(r1)
|
||||
a6c: 81 21 00 14 lwz r9,20(r1)
|
||||
a70: 3c 80 00 00 lis r4,0
|
||||
a74: 60 84 00 09 ori r4,r4,9
|
||||
a78: 7c 90 53 a6 mtspr 336,r4
|
||||
a7c: 60 00 00 00 nop
|
||||
a80: 39 20 00 00 li r9,0
|
||||
a84: 91 21 00 10 stw r9,16(r1)
|
||||
a88: 81 21 00 10 lwz r9,16(r1)
|
||||
a8c: 3c 80 00 00 lis r4,0
|
||||
a90: 60 84 00 09 ori r4,r4,9
|
||||
a94: 7c 94 53 a6 mtspr 340,r4
|
||||
a98: 60 00 00 00 nop
|
||||
a9c: 39 20 00 00 li r9,0
|
||||
aa0: 7d 23 4b 78 mr r3,r9
|
||||
aa4: 38 21 00 40 addi r1,r1,64
|
||||
aa8: 4e 80 00 20 blr
|
||||
@ -0,0 +1,683 @@
|
||||
48000400
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00000000
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00000000
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00000000
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|
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|
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|
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|
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81210010
|
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|
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|
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|
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|
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38210040
|
||||
4E800020
|
||||
@ -0,0 +1,178 @@
|
||||
|
||||
rom: file format elf32-powerpc
|
||||
|
||||
Contents of section .kernel:
|
||||
0000 48000400 00000000 00000000 00000000 H...............
|
||||
0010 00000000 00000000 00000000 00000000 ................
|
||||
0020 48000000 00000000 00000000 00000000 H...............
|
||||
0030 00000000 00000000 00000000 00000000 ................
|
||||
0040 48000000 00000000 00000000 00000000 H...............
|
||||
0050 00000000 00000000 00000000 00000000 ................
|
||||
0060 48000000 00000000 00000000 00000000 H...............
|
||||
0070 00000000 00000000 00000000 00000000 ................
|
||||
0080 48000000 00000000 00000000 00000000 H...............
|
||||
0090 00000000 00000000 00000000 00000000 ................
|
||||
00a0 48000000 00000000 00000000 00000000 H...............
|
||||
00b0 00000000 00000000 00000000 00000000 ................
|
||||
00c0 48000000 00000000 00000000 00000000 H...............
|
||||
00d0 00000000 00000000 00000000 00000000 ................
|
||||
00e0 48000000 00000000 00000000 00000000 H...............
|
||||
00f0 00000000 00000000 00000000 00000000 ................
|
||||
0100 48000000 00000000 00000000 00000000 H...............
|
||||
0110 00000000 00000000 00000000 00000000 ................
|
||||
0120 48000000 00000000 00000000 00000000 H...............
|
||||
0130 00000000 00000000 00000000 00000000 ................
|
||||
0140 48000000 00000000 00000000 00000000 H...............
|
||||
0150 00000000 00000000 00000000 00000000 ................
|
||||
0160 48000000 00000000 00000000 00000000 H...............
|
||||
0170 00000000 00000000 00000000 00000000 ................
|
||||
0180 48000000 00000000 00000000 00000000 H...............
|
||||
0190 00000000 00000000 00000000 00000000 ................
|
||||
01a0 48000000 00000000 00000000 00000000 H...............
|
||||
01b0 00000000 00000000 00000000 00000000 ................
|
||||
01c0 48000000 00000000 00000000 00000000 H...............
|
||||
01d0 00000000 00000000 00000000 00000000 ................
|
||||
01e0 48000000 00000000 00000000 00000000 H...............
|
||||
01f0 00000000 00000000 00000000 00000000 ................
|
||||
0200 48000000 00000000 00000000 00000000 H...............
|
||||
0210 00000000 00000000 00000000 00000000 ................
|
||||
0220 48000000 00000000 00000000 00000000 H...............
|
||||
0230 00000000 00000000 00000000 00000000 ................
|
||||
0240 48000000 00000000 00000000 00000000 H...............
|
||||
0250 00000000 00000000 00000000 00000000 ................
|
||||
0260 48000000 00000000 00000000 00000000 H...............
|
||||
0270 00000000 00000000 00000000 00000000 ................
|
||||
0280 48000000 00000000 00000000 00000000 H...............
|
||||
0290 00000000 00000000 00000000 00000000 ................
|
||||
02a0 48000000 00000000 00000000 00000000 H...............
|
||||
02b0 00000000 00000000 00000000 00000000 ................
|
||||
02c0 48000000 00000000 00000000 00000000 H...............
|
||||
02d0 00000000 00000000 00000000 00000000 ................
|
||||
02e0 48000000 00000000 00000000 00000000 H...............
|
||||
02f0 00000000 00000000 00000000 00000000 ................
|
||||
0300 48000000 00000000 00000000 00000000 H...............
|
||||
0310 00000000 00000000 00000000 00000000 ................
|
||||
0320 48000000 00000000 00000000 00000000 H...............
|
||||
0330 00000000 00000000 00000000 00000000 ................
|
||||
0340 48000000 00000000 00000000 00000000 H...............
|
||||
0350 00000000 00000000 00000000 00000000 ................
|
||||
0360 00000000 00000000 00000000 00000000 ................
|
||||
0370 00000000 00000000 00000000 00000000 ................
|
||||
0380 00000000 00000000 00000000 00000000 ................
|
||||
0390 00000000 00000000 00000000 00000000 ................
|
||||
03a0 00000000 00000000 00000000 00000000 ................
|
||||
03b0 00000000 00000000 00000000 00000000 ................
|
||||
03c0 00000000 00000000 00000000 00000000 ................
|
||||
03d0 00000000 00000000 00000000 00000000 ................
|
||||
03e0 00000000 00000000 00000000 00000000 ................
|
||||
03f0 00000000 00000000 00000000 00000000 ................
|
||||
0400 7cbe6aa6 2c250000 408200e0 3c608c00 |.j.,%..@...<`..
|
||||
0410 3800001f 38400015 38800000 3900023f 8...8@..8...9..?
|
||||
0420 7c7cfba6 7c4011a6 7c8009a6 7d0001a6 ||..|@..|...}...
|
||||
0430 4c00012c 39400000 654a0000 614a003f L..,9@..eJ..aJ.?
|
||||
0440 3800001e 38800000 64840001 60840000 8...8...d...`...
|
||||
0450 39000000 65080001 61080000 6108023f 9...e...a...a..?
|
||||
0460 7d4011a6 7c8009a6 7d0001a6 4c00012c }@..|...}...L..,
|
||||
0470 3c608800 3800000f 3840003f 38800000 <`..8...8@.?8...
|
||||
0480 3900023f 7c7cfba6 7c4011a6 7c8009a6 9..?||..|@..|...
|
||||
0490 7d0001a6 4c00012c 3800000d 38800000 }...L..,8...8...
|
||||
04a0 64840001 60840000 39000000 65080001 d...`...9...e...
|
||||
04b0 61080000 6108023f 7d4011a6 7c8009a6 a...a..?}@..|...
|
||||
04c0 7d0001a6 4c00012c 48000004 39400000 }...L..,H...9@..
|
||||
04d0 654a8002 614ab000 7d400124 4c00012c eJ..aJ..}@.$L..,
|
||||
04e0 802008f0 48000020 39400000 654a8002 . ..H.. 9@..eJ..
|
||||
04f0 614ab000 7d400124 4c00012c 802008f4 aJ..}@.$L..,. ..
|
||||
0500 48000004 3c600000 60630900 7c6903a6 H...<`..`c..|i..
|
||||
0510 7c7e6aa6 4e800421 480002e4 00000000 |~j.N..!H.......
|
||||
0520 00000000 00000000 00000000 00000000 ................
|
||||
0530 00000000 00000000 00000000 00000000 ................
|
||||
0540 00000000 00000000 00000000 00000000 ................
|
||||
0550 00000000 00000000 00000000 00000000 ................
|
||||
0560 00000000 00000000 00000000 00000000 ................
|
||||
0570 00000000 00000000 00000000 00000000 ................
|
||||
0580 00000000 00000000 00000000 00000000 ................
|
||||
0590 00000000 00000000 00000000 00000000 ................
|
||||
05a0 00000000 00000000 00000000 00000000 ................
|
||||
05b0 00000000 00000000 00000000 00000000 ................
|
||||
05c0 00000000 00000000 00000000 00000000 ................
|
||||
05d0 00000000 00000000 00000000 00000000 ................
|
||||
05e0 00000000 00000000 00000000 00000000 ................
|
||||
05f0 00000000 00000000 00000000 00000000 ................
|
||||
0600 00000000 00000000 00000000 00000000 ................
|
||||
0610 00000000 00000000 00000000 00000000 ................
|
||||
0620 00000000 00000000 00000000 00000000 ................
|
||||
0630 00000000 00000000 00000000 00000000 ................
|
||||
0640 00000000 00000000 00000000 00000000 ................
|
||||
0650 00000000 00000000 00000000 00000000 ................
|
||||
0660 00000000 00000000 00000000 00000000 ................
|
||||
0670 00000000 00000000 00000000 00000000 ................
|
||||
0680 00000000 00000000 00000000 00000000 ................
|
||||
0690 00000000 00000000 00000000 00000000 ................
|
||||
06a0 00000000 00000000 00000000 00000000 ................
|
||||
06b0 00000000 00000000 00000000 00000000 ................
|
||||
06c0 00000000 00000000 00000000 00000000 ................
|
||||
06d0 00000000 00000000 00000000 00000000 ................
|
||||
06e0 00000000 00000000 00000000 00000000 ................
|
||||
06f0 00000000 00000000 00000000 00000000 ................
|
||||
0700 00000000 00000000 00000000 00000000 ................
|
||||
0710 00000000 00000000 00000000 00000000 ................
|
||||
0720 00000000 00000000 00000000 00000000 ................
|
||||
0730 00000000 00000000 00000000 00000000 ................
|
||||
0740 00000000 00000000 00000000 00000000 ................
|
||||
0750 00000000 00000000 00000000 00000000 ................
|
||||
0760 00000000 00000000 00000000 00000000 ................
|
||||
0770 00000000 00000000 00000000 00000000 ................
|
||||
0780 00000000 00000000 00000000 00000000 ................
|
||||
0790 00000000 00000000 00000000 00000000 ................
|
||||
07a0 00000000 00000000 00000000 00000000 ................
|
||||
07b0 00000000 00000000 00000000 00000000 ................
|
||||
07c0 00000000 00000000 00000000 00000000 ................
|
||||
07d0 00000000 00000000 00000000 00000000 ................
|
||||
07e0 00000000 00000000 00000000 00000000 ................
|
||||
07f0 00000000 00000000 00000000 48000000 ............H...
|
||||
0800 48000000 00000000 00000000 00000000 H...............
|
||||
0810 00000000 00000000 00000000 00000000 ................
|
||||
0820 48000000 00000000 00000000 00000000 H...............
|
||||
0830 00000000 00000000 00000000 00000000 ................
|
||||
0840 00000000 00000000 00000000 00000000 ................
|
||||
0850 00000000 00000000 00000000 00000000 ................
|
||||
0860 00000000 00000000 00000000 00000000 ................
|
||||
0870 00000000 00000000 00000000 00000000 ................
|
||||
0880 00000000 00000000 00000000 00000000 ................
|
||||
0890 00000000 00000000 00000000 00000000 ................
|
||||
08a0 00000000 00000000 00000000 00000000 ................
|
||||
08b0 00000000 00000000 00000000 00000000 ................
|
||||
08c0 00000000 00000000 00000000 00000000 ................
|
||||
08d0 00000000 00000000 00000000 00000000 ................
|
||||
08e0 00000000 00000000 00000000 00000000 ................
|
||||
Contents of section .rodata:
|
||||
08f0 0001fff8 0000fff8 ........
|
||||
Contents of section .bios:
|
||||
08f8 60000000 60000000 9421ffc0 90610038 `...`....!...a.8
|
||||
0908 3d200001 81290000 9121000c 81210038 = ...)...!...!.8
|
||||
0918 2c090000 4182000c 3920ffff 4800017c ,...A...9 ..H..|
|
||||
0928 3d200000 81290aac 91210008 48000028 = ...)...!..H..(
|
||||
0938 8121000c 39490004 9141000c 81410008 .!..9I...A...A..
|
||||
0948 814a0000 91490000 81210008 39290004 .J...I...!..9)..
|
||||
0958 91210008 3d200000 81290aac 81410008 .!..= ...)...A..
|
||||
0968 7c0a4840 4180ffcc 3d200001 81290000 |.H@A...= ...)..
|
||||
0978 91210008 48000020 3d200001 81290000 .!..H.. = ...)..
|
||||
0988 39400000 91490000 81210008 39290004 9@...I...!..9)..
|
||||
0998 91210008 3d200001 81290000 81410008 .!..= ...)...A..
|
||||
09a8 7c0a4840 4180ffd4 3d200300 91210030 |.H@A...= ...!.0
|
||||
09b8 81210030 3c800000 60840009 7c934ba6 .!.0<...`...|.K.
|
||||
09c8 60000000 39200000 9121002c 8121002c `...9 ...!.,.!.,
|
||||
09d8 3c800000 60840009 7c9603a6 60000000 <...`...|...`...
|
||||
09e8 39200000 91210028 81210028 3c800000 9 ...!.(.!.(<...
|
||||
09f8 60840009 7c9d43a6 60000000 39200000 `...|.C.`...9 ..
|
||||
0a08 91210024 81210024 3c800000 60840009 .!.$.!.$<...`...
|
||||
0a18 7c9c43a6 60000000 3d20fe00 91210020 |.C.`...= ...!.
|
||||
0a28 81210020 3c800000 60840009 7c9053a6 .!. <...`...|.S.
|
||||
0a38 60000000 7d36faa6 9121001c 8121001c `...}6...!...!..
|
||||
0a48 552905ac 91210018 81210018 3c800000 U)...!...!..<...
|
||||
0a58 60840009 7c96fba6 60000000 39200000 `...|...`...9 ..
|
||||
0a68 91210014 81210014 3c800000 60840009 .!...!..<...`...
|
||||
0a78 7c9053a6 60000000 39200000 91210010 |.S.`...9 ...!..
|
||||
0a88 81210010 3c800000 60840009 7c9453a6 .!..<...`...|.S.
|
||||
0a98 60000000 39200000 7d234b78 38210040 `...9 ..}#Kx8!.@
|
||||
0aa8 4e800020 N..
|
||||
@ -0,0 +1 @@
|
||||
../../sim/mem/test2
|
||||
Loading…
Reference in New Issue