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@ -25,29 +25,29 @@ async def init(dut, sim):
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dut.nclk.value = 0
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dut.nclk.value = 0
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dut.scan_in.value = 0
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dut.scan_in.value = 0
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dut.an_ac_scan_type_dc.value = 0x0
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#dut.an_ac_scan_type_dc.value = 0x0
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dut.an_ac_chipid_dc.value = 0x0
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#dut.an_ac_chipid_dc.value = 0x0
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dut.an_ac_coreid.value = 0x0
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#dut.an_ac_coreid.value = 0x0
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dut.an_ac_scom_sat_id.value = 0x0
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#dut.an_ac_scom_sat_id.value = 0x0
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dut.an_ac_lbist_ary_wrt_thru_dc.value = 0
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#dut.an_ac_lbist_ary_wrt_thru_dc.value = 0
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dut.an_ac_gsd_test_enable_dc.value = 0
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#dut.an_ac_gsd_test_enable_dc.value = 0
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dut.an_ac_gsd_test_acmode_dc.value = 0
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#dut.an_ac_gsd_test_acmode_dc.value = 0
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dut.an_ac_ccflush_dc.value = 0
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#dut.an_ac_ccflush_dc.value = 0
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dut.an_ac_ccenable_dc.value = 0
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#dut.an_ac_ccenable_dc.value = 0
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dut.an_ac_lbist_en_dc.value = 0
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#dut.an_ac_lbist_en_dc.value = 0
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dut.an_ac_lbist_ip_dc.value = 0
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#dut.an_ac_lbist_ip_dc.value = 0
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dut.an_ac_lbist_ac_mode_dc.value = 0
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#dut.an_ac_lbist_ac_mode_dc.value = 0
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dut.an_ac_scan_diag_dc.value = 0
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#dut.an_ac_scan_diag_dc.value = 0
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dut.an_ac_scan_dis_dc_b.value = 0
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#dut.an_ac_scan_dis_dc_b.value = 0
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dut.an_ac_rtim_sl_thold_8.value = 0
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#dut.an_ac_rtim_sl_thold_8.value = 0
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dut.an_ac_func_sl_thold_8.value = 0
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#dut.an_ac_func_sl_thold_8.value = 0
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dut.an_ac_func_nsl_thold_8.value = 0
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#dut.an_ac_func_nsl_thold_8.value = 0
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dut.an_ac_ary_nsl_thold_8.value = 0
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#dut.an_ac_ary_nsl_thold_8.value = 0
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dut.an_ac_sg_8.value = 0
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#dut.an_ac_sg_8.value = 0
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dut.an_ac_fce_8.value = 0
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#dut.an_ac_fce_8.value = 0
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dut.an_ac_abst_scan_in.value = 0
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#dut.an_ac_abst_scan_in.value = 0
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dut.an_ac_reset_1_complete.value = 0
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dut.an_ac_reset_1_complete.value = 0
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dut.an_ac_reset_2_complete.value = 0
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dut.an_ac_reset_2_complete.value = 0
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@ -166,7 +166,7 @@ async def memory(dut, sim):
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dut.mem_dat.value = 0
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dut.mem_dat.value = 0
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if dut.mem_wr_val.value:
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if dut.mem_wr_val.value:
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addr = dut.mem_adr.value.integer
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addr = dut.mem_adr.value.integer & 0xFFFFFF0
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dat = hex(dut.mem_wr_dat, 32)
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dat = hex(dut.mem_wr_dat, 32)
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be = f'{dut.mem_wr_be.value.integer:016b}'
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be = f'{dut.mem_wr_be.value.integer:016b}'
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for i in range(4):
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for i in range(4):
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@ -206,8 +206,9 @@ async def checker(dut, sim):
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async def scom(dut, sim):
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async def scom(dut, sim):
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"""scom interface"""
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"""scom interface"""
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dut.an_ac_scom_dch.value = 0
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#dut.an_ac_scom_dch.value = 0
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dut.an_ac_scom_cch.value = 0
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#dut.an_ac_scom_cch.value = 0
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pass
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# ------------------------------------------------------------------------------------------------
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# ------------------------------------------------------------------------------------------------
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@ -279,6 +280,7 @@ async def tb_node(dut):
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o = A2OCore(sim, dut.c0.c0)
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sim.a2o.traceFacUpdates = True
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sim.a2o.traceFacUpdates = True
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sim.a2o.stopOnHang = 200
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sim.a2o.stopOnLoop = 50
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sim.a2o.stopOnLoop = 50
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarPass = 0x7F0
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sim.a2o.iarFail = 0x7F4
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sim.a2o.iarFail = 0x7F4
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@ -296,12 +298,15 @@ async def tb_node(dut):
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sim.fail = 'Reset active too long!'
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sim.fail = 'Reset active too long!'
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# config stuff
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# config stuff
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# config for a2onode w/1 req buffer
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# a2node_verilotor defines have these set already
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#sim.a2o.config.creditsLd = 1
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#sim.a2o.config.creditsSt = 1
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#sim.a2o.config.creditsLdStSingle = True
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# original fpga design needed 4 cred, no fwd (set in logic currently)
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# original fpga design needed 4 cred, no fwd (set in logic currently)
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sim.a2o.config.creditsLd = 1
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sim.a2o.config.creditsSt = 1
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sim.a2o.config.creditsLdStSingle = True # need for node right now
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#sim.a2o.lsDataForward = 0 # disable=1
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#sim.a2o.lsDataForward = 0 # disable=1
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#sim.a2o.cpcr4_sq_cnt = 0 # default=6
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await A2O.config(dut, sim)
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await A2O.config(dut, sim)
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