ties for yosys

dev/verilog/work/fu.v

@@ -739,11 +739,6 @@ module fu(
    assign tidn = 1'b0;
    assign tiup = 1'b1;
 
-   assign vdd = 1'b1;
-   assign vcs = 1'b1;
-   assign gnd = 1'b0;
-
-
    // TEMP TEMP todo
    assign iu_fu_rf0_instr_match = tidn;
 

dev/verilog/work/iuq.v

@@ -1333,9 +1333,6 @@ module iuq(
    wire                           vdd;
    wire                           gnd;
 
-   assign vdd = 1'b1;
-   assign gnd = 1'b0;
-
    // Temp should be driven by external mode debug compare decodes
    assign mm_iu_reload_hit[0] = mm_iu_ierat_rel_val[0] & mm_iu_ierat_rel_val[4];
 `ifndef THREADS1

dev/verilog/work/iuq_ifetch.v

@@ -681,9 +681,6 @@ module iuq_ifetch(
    wire                              vdd;
    wire                              gnd;
 
-   assign vdd = 1'b1;
-   assign gnd = 1'b0;
-
    assign iu_lq_spr_iucr0_icbi_ack = spr_ic_icbi_ack_en;
    assign d_mode = 1'b0;
    assign mpw2_b = 1'b1;

dev/verilog/work/lq.v

@@ -1376,10 +1376,6 @@ wire							     gnd;
    assign mm_lq_mmucr0 = {mm_lq_mmucr0_t0, mm_lq_mmucr0_t1};
 `endif
 
-assign vdd = 1'b1;
-//assign vcs = 1'b1;
-assign gnd = 1'b0;
-
 // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
 // LQ CONTROL
 // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

dev/verilog/work/rv_perv.v

@@ -49,7 +49,7 @@ module rv_perv(		// 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
    input 		 an_ac_scan_diag_dc,
    input 		 an_ac_scan_dis_dc_b,
 
-   input                 d_mode,
+   input        d_mode,
 
    output 		 func_sl_thold_1,
    output 		 fce_1,
@@ -160,7 +160,7 @@ module rv_perv(		// 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
    (* analysis_not_referenced="TRUE" *)
    wire 		 unused;
 
-   wire func_sl_thold_0_b = 0;  // wtf: dangling test sig
+   wire func_sl_thold_0_b;  // wtf: dangling test sig
 
 
    //------------------------------------------------------------------------------------------------------------