verilator litex soc

pull/18/head
openpowerwtf 1 year ago
parent 81f5d8dca2
commit 7dc2afc522

@ -1,6 +1,7 @@
#!/usr/bin/python3

# A2O Test - build with core.py
# a2o.py --csr-csv csr.csv --no-compile-software
# a2o.py --csr-csv csr.csv --no-compile-software --build [--sys-clk-freq 50e6]
#

@ -11,6 +12,7 @@ from migen import *

# wtf - use local platform
from platforms import cmod7
from platforms import cmod7_kintex

# wtf - use local core (not built into litex)
# help python find package
@ -52,9 +54,7 @@ class _CRG(Module):
self.clock_domains.cd_idelay = ClockDomain()

self.submodules.pll = pll = S7MMCM(speedgrade=-1)
#wtf if you do this it crashes later..request() takes the pin off 'available' list i think; so can't put to csr reg
#no idea how to modify the reset signal later
#maybe have to change this class to take a signal you create first?
#wtf how do you add btn to reset sig?
#x = platform.request('user_btn',0)
self.comb += pll.reset.eq(self.rst)
#self.comb += pll.reset.eq(self.rst)
@ -77,28 +77,29 @@ class BaseSoC(SoCCore):
**kwargs):

coreUART = True
#romSize = 128*1024
#ramSize = 128*1024
romSize = 64 * 1024;
ramSize = 64 * 1024;
ddrSize = 16*1024*1024


# try build using different fpga's
#platform = cmod7.Platform()
#platform = cmod7.Platform(fpga='xc7a200t-SBG484-1') # arty-200
#platform = cmod7.Platform(fpga='xc7k325t-ffv676-1 ) #
platform = cmod7.Platform(fpga='xc7k410t-ffv676-1') #
#platform = cmod7_kintex.Platform(fpga='xc7k325t-ffv676-1 ) # kintex-325
platform = cmod7_kintex.Platform(fpga='xc7k410t-ffv676-1') # kintex-410

SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
with_uart=coreUART, integrated_sram_size=0, integrated_rom_size=0,
ident='A2O Test', ident_version=True, uart_baudrate=uart_baudrate,
#with_uart=coreUART, integrated_rom_size=romSize, integrated_sram_size=ramSize, don't set rom/ram if doing it below!!!!!
with_uart=coreUART, integrated_rom_size=0, integrated_sram_size=0,
ident='A2O', ident_version=True, uart_baudrate=uart_baudrate,
cpu_type='a2o')

print(f'Building variant={self.cpu.variant}.')

# no irq yet? should be able to connect
#self.add_constant('UART_POLLING')

#!!!!!!!!!!!!!!!!!!
# any hints here on using uarts (to get the gpio one working)?
# cult-soft.de/2920/05/24/litex-uart-hub
# played a little below but didnt try if it works
#!!!!!!!!!!!!!!!!!!
# no irq yet, but should be able to connect; need irq handler in crt0.s
self.add_constant('UART_POLLING')

# this appears to be how to set up fixed csr order but not sure it works this way. https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py
#SoCCore.csr_map
@ -114,12 +115,11 @@ class BaseSoC(SoCCore):
# 'uart': 0,
# 'timer0': 1,
#}}

self.mem_map = {
'csr': 0xFFF00000,
'main_ram': 0x00100000,
'rom': 0x00000000,
'ram': 0x00010000,
'main_ram': 0x01000000,
'csr': 0xFFF00000
}

# CRG --------------------------------------------------------------------------------------
@ -157,9 +157,12 @@ class BaseSoC(SoCCore):
outFile.close()
print('Wrote mem.init')

self.add_rom('rom', origin=self.mem_map['rom'], size=0x10000, contents=romdata) # name, origin, size, contents=[], mode='r'
self.add_rom('rom', origin=self.mem_map['rom'], size=romSize, contents=romdata) # name, origin, size, contents=[], mode='r'
# make this sram to match what linker expects
self.add_ram('sram', origin=self.mem_map['ram'], size=0x10000) # name, origin, size, contents=[], mode='rw'
self.add_ram('sram', origin=self.mem_map['ram'], size=ramSize) # name, origin, size, contents=[], mode='rw'

# External Mem -----------------------------------------------------------------------------
self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=ddrSize)

# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
@ -174,20 +177,17 @@ class BaseSoC(SoCCore):
)
self.add_csr('buttons')

# SRAM -------------------------------------------------------------------------------------
self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=0x100)

# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.cpu.dbus.stb,
self.cpu.dbus.cyc,
self.cpu.dbus.adr,
self.cpu.dbus.we,
self.cpu.dbus.ack,
self.cpu.dbus.sel,
self.cpu.dbus.dat_w,
self.cpu.dbus.dat_r,
self.cpu.wb_stb,
self.cpu.wb_cyc,
self.cpu.wb_adr,
self.cpu.wb_we,
self.cpu.wb_ack,
self.cpu.wb_sel,
self.cpu.wb_datw,
self.cpu.wb.datr,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,

@ -0,0 +1,50 @@
.section .text, "ax", @progbits
# called by bios boot commands to do the jump to code (r1,r2,r3 can be specified in terminal 'boot' command)

.include "defines.s"

.global boot_helper
# extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr);

.align 4
boot_helper:
lis r3,_fstack@h
ori r3,r3,_fstack@l # top o mem
mtctr r6
bctr # jump to callee

# play with stack. what could go wrong?
# r1 = new top
# orig lr 20(r1)
# ancient r1 16(r1)
# local1 12(r1)
# local2 8(r1)
# (next lr) 4(r1)
# orig r1 0(r1)
# doesnt help...getting a bad op, probably blr to wrong address off stack, within calls to do a putchar
stwu r1,-32(r1)
mflr r0
stw r0,36(r1)
stw r3,8(r1)
stw r4,12(r1)
stw r5,16(r1)
stw r6,20(r1)
li r3,'w'
slwi r3,r3,8
ori r3,r3,'t'
slwi r3,r3,8
ori r3,r3,'f'
slwi r3,r3,8
ori r3,r3,'!'
stw r3,24(r1)
stw r3,28(r1)
lwz r0,36(r1)
mtlr r6
addi r1,r1,32
blr

#addi r1,r1,32 # leave frame on stack
#mtctr r6
#bctrl # jump to callee

b .

@ -38,6 +38,8 @@ class A2O(CPU, AutoCSR):

@property
def mem_map(self):
return {}
# how do you make this be default but not overwrite any defines in soc.py?
return {
'rom': 0x00000000, # on-board
'sram': 0x00004000, # on-board
@ -78,8 +80,8 @@ class A2O(CPU, AutoCSR):
self.reset_address = 0x00000000

self.cpu_params = dict(
i_clk_1x = ClockSignal('sys'),
i_clk_2x = ClockSignal('sys2x'),
i_clk = ClockSignal('sys'),
#i_clk_2x = ClockSignal('sys2x'),
i_rst = ResetSignal() | self.reset,

# how do i connect these to csr?
@ -96,7 +98,9 @@ class A2O(CPU, AutoCSR):
#wtf i guess you get these names from the Inteface() def - but what about other sigs?
o_wb_cyc = dbus.cyc,
o_wb_stb = dbus.stb,
o_wb_adr = Cat(dbus.adr,Signal(2)),
#wtf litex is declaring wire [29:0] a2o_dbus_adr and connecting directly here but a2owb;wb_adr is [0:31]
# o_wb_adr = Cat(dbus.adr,Signal(2)),
o_wb_adr = Cat(Signal(2),dbus.adr), # wb adr [31:2] = a2o adr[0:29]
o_wb_we = dbus.we,
o_wb_sel = dbus.sel,
o_wb_datw = dbus.dat_w,

@ -0,0 +1,973 @@
# debug code for mem
#.set TEST_MEM,1

# boot code for rom integration with litex terminal code
# requires 64K ROM
# got rid of int handlers for now to shrink this code

# cmod7 - skip ddr stuff

# set for sim bypass version
#.set SIM,1 # this skips uart, ram check, etc.
#.set DELAY,0x00000005

# general delay (leds)
# should probs put this in a mem loc so it can be easily changed w/o compile
.set DELAY,0x01000000 # hardware (~1 secs)
#.set DELAY,0x00000100

# csr.csv
# need to set up CONFIG:
#csr_base,dna,0xfff00000,,
#csr_base,xadc,0xfff00800,,
#csr_base,leds,0xfff01000,,
#csr_base,buttons,0xfff01800,,
#csr_base,i2c,0xfff02000,,
#csr_base,motor_0,0xfff02800,,
#csr_base,ctrl,0xfff03000,,
#csr_base,identifier_mem,0xfff03800,,
#csr_base,timer0,0xfff04000,,
#csr_base,uart,0xfff04800,,

#
#memory_region,rom,0x00000000,65536,cached
#memory_region,ram,0x00010000,4096,cached
#memory_region,sram,0x80000000,4096,cached
#memory_region,csr,0xfff00000,65536,io

.include "defines.s"

#.section .hwinit # @00000000
# change to use litex linker.ld
.section .text

.global _start

# reset
_start:
b boot_start

.set REGSAVE,0x04
regsave:
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0


# ddr setup delay (intracommand)
.ifdef SIM
.set DDR_DELAY,0x00000010 # sim
.else
.set DDR_DELAY,0x00020000
.endif

.align 6
.set CONFIG,0x40

#.set SRAM_BASE, 0x00010000 # get from _fdata
#.set STACK, 0x0001FFF8 # first save of r0 is 4 past this! #get from _fstack

.set MAGIC, 0x08675309

rom_lo: .long 0
rom_hi: .long 0xFFFF
sram_lo: .long 0 # get from link syms; does chk for -1 to skip test
sram_hi: .long 0
ddr_lo: .long 0xFFFFFFFF # -1: no gots
ddr_hi: .long 0xF7FFFFFF

ctrl: .long 0xFFF03000
cpu: .long 0xFFFFFFFF # -1: no gots
uart: .long 0xFFF04800 # -1: no gots
leds: .long 0xFFF01000 # -1: no gots
switches: .long 0xFFFFFFFF # -1: no gots
buttons: .long 0xFFF01800 # -1: no gots
sdram: .long 0xFFFFFFFF
eob_data: .long MAGIC

# offsets for uart functions
.set UART_RXTX, 0x00
.set UART_TXFULL, 0x04
.set UART_RXEMPTY, 0x08
.set UART_EV_STATUS, 0x0C
.set UART_EV_PENDING, 0x10
.set UART_EV_ENABLE, 0x14
.set UART_TXEMPTY, 0x18
.set UART_RXFULL, 0x1C
.set UARTX_RXTX, 0x20
.set UARTX_TXFULL, 0x24
.set UARTX_RXEMPTY, 0x28
.set UARTX_EV_STATUS, 0x2C
.set UARTX_EV_PENDING, 0x30
.set UARTX_EV_ENABLE, 0x34
.set UARTX_TXEMPTY, 0x38
.set UARTX_RXFULL, 0x3C

.align 7
.set CONFIG_DDR,0x80

#wtf can litex be forced to put these at specific offsets from csr_base???
sdram_dfii: .long 0xFFF06000 # csr_register,sdram_dfii_control,0xfff05000,1,rw
ddr_cmd_delay: .long DDR_DELAY
ddr_chk_loops: .long 1 # 0=infinite
ddr_mrs0: .long 0 # wtf eventually set these up as config vals

# offsets from sdram_dfii base
.set DFII_CONTROL, 0x00
.set DFII_PI0_COMMAND, 0x04
.set DFII_PI0_COMMAND_ISSUE, 0x08
.set DFII_PI0_ADDRESS, 0x0C
.set DFII_PI0_BADDRESS, 0x10
.set DFII_PI0_WRDATA, 0x14
.set DFII_PI0_RDDATA, 0x18
.set DFII_PI1_COMMAND, 0x1C
.set DFII_PI1_COMMAND_ISSUE, 0x20
.set DFII_PI1_ADDRESS, 0x24
.set DFII_PI1_BADDRESS, 0x28
.set DFII_PI1_WRDATA, 0x2C
.set DFII_PI1_RDDATA, 0x30

# bits
.set CONTROL_SEL, 0x01
.set CONTROL_CKE, 0x02
.set CONTROL_ODT, 0x04 #wtf does this exist for ddr2??
.set CONTROL_RESET_N, 0x08
.set COMMAND_CS, 0x01
.set COMMAND_WE, 0x02
.set COMMAND_CAS, 0x04
.set COMMAND_RAS, 0x08
.set COMMAND_WRDATA, 0x10
.set COMMAND_RDDATA, 0x20
.set DDR_PARM_DELAY, 0x00020000

#
.align 8
int_100:
b .

# mck
.align 8
int_200:
b .

# dsi
.align 8
int_300:
b .

# dseg
.align 7
int_380:
b .

# isi
.align 8
int_400:
b .

# iseg
.align 7
int_480:
b .

# external
.align 8
int_500:
b .

# alignment
.align 8
int_600:
b .

# program
.align 8
int_700:
b .

# fp unavailable
.align 8
int_800:
b .

# dec
.align 8
int_900:
b .

# dec hyp
.align 7
int_980:
b .

# doorbell
.align 8# offsets from sdram_dfii base
.set DFII_CONTROL, 0x00
.set DFII_PI0_COMMAND, 0x04
.set DFII_PI0_COMMAND_ISSUE, 0x08
.set DFII_PI0_ADDRESS, 0x0C
.set DFII_PI0_BADDRESS, 0x10
.set DFII_PI0_WRDATA, 0x14
.set DFII_PI0_RDDATA, 0x18
.set DFII_PI1_COMMAND, 0x1C
.set DFII_PI1_COMMAND_ISSUE, 0x20
.set DFII_PI1_ADDRESS, 0x24
.set DFII_PI1_BADDRESS, 0x28
.set DFII_PI1_WRDATA, 0x2C
.set DFII_PI1_RDDATA, 0x30

# bits
.set CONTROL_SEL, 0x01
.set CONTROL_CKE, 0x02
.set CONTROL_ODT, 0x04 #wtf does this exist for ddr2??
.set CONTROL_RESET_N, 0x08
.set COMMAND_CS, 0x01
.set COMMAND_WE, 0x02
.set COMMAND_CAS, 0x04
.set COMMAND_RAS, 0x08
.set COMMAND_WRDATA, 0x10
.set COMMAND_RDDATA, 0x20
.set DDR_PARM_DELAY, 0x00020000
int_C00:
b .

# trace
.align 8
int_D00:
b .

# dsi hyp
.align 8
int_E00:
b .

# isi hyp
.align 5
int_E20:
b .

# emulation hyp
.align 5
int_E40:
b .

# maintenance hyp
.align 5
int_E60:
b .

# doorbell hyp
.align 5
int_E80:
b .

# virtualization hyp
.align 5
int_EA0:
b .

# reserved
.align 5
int_EC0:
b .

# reserved
.align 5
int_EE0:
b .

# perfmon
.align 5
int_F00:
b .

# vector unavailable
.align 5
int_F20:
b .

# vsx unavailable
.align 5
int_F40:
b .

# facility unavailable
.align 5
int_F60:
b .

# facility unavailable hyp
.align 5
int_F80:
b .

# ------------------------------------------------------------------------------------------------------------------------------
# init facilities and memories before blastoff
#

.macro load32 rx,v
li \rx,0
oris \rx,\rx,\v>>16
ori \rx,\rx,\v&0x0000FFFF
.endm

.macro load16swiz rx,v
li \rx,0
ori \rx,\rx,(\v<<8)&0xFF00
ori \rx,\rx,(\v>>8)&0x00FF
.endm

.macro delayr rx
mtctr \rx
bdnz .
.endm

.macro delay rx,v
li \rx,0
oris \rx,\rx,\v>>16
ori \rx,\rx,\v&0x0000FFFF
mtctr \rx
bdnz .
.endm

.org 0x1000
boot_start:

########################################################################################################################################
# sim only - go quickly to main() w/no console output

.ifdef SIM
li r3,0x01
bl set_leds_b0
bl uart_init
li r3,0x02
bl set_leds_b0
b jump2main
.endif

########################################################################################################################################
# clear and init core facilities

li r3,0x01
bl core_init
bl set_leds_b0 # 01; core init'd
delay r10,DELAY

########################################################################################################################################
# console

console:

li r3,0x02 # 02; console init
bl set_leds_b0
bl uart_init
delay r10,DELAY

li r3,0x03 # 03; console init done
bl set_leds_b0
delay r10,DELAY

li r3,DATA+MSG_HELLO
bl console_println

########################################################################################################################################
# check on-board sram

.ifdef TEST_MEM
b test_mem
.endif

sram_chk:
lwz r10,sram_lo(r0)
cmpwi r10,-1
beq ddr_chk
# use syms
lis r10,_fdata@h
ori r10,r10,_fdata@l
#lwz r11,sram_hi(r0)
# use stack top; else have to add sym to linker.ld
lis r11,_fstack@h
ori r11,r11,_fstack@l
addi r11,r11,3

subf r11,r10,r11
addi r11,r11,1
srwi r11,r11,4 # num word reads
mtctr r11

li r12,0
oris r12,r12,0x0867
ori r12,r12,0x5309 # data

sram_writes:
stw r12,0(r10)
addi r10,r10,4
bdnz sram_writes
# use syms
#lwz r10,sram_lo(r0)
lis r10,_fdata@h
ori r10,r10,_fdata@l
mtctr r11

sram_reads:
lwz r13,0(r10)
cmpw r13,r12
bne fail
addi r10,r10,4
bdnz sram_reads

li r3,0x07 # 07; sram checked
bl set_leds_b0
delay r10,DELAY

li r3,DATA+MSG_SRAM
bl console_println

# sram test someday
########################################################################################################################################
# check ddr, n loops

#wtf is there a way to disable/enable l2????

ddr_chk:
lwz r10,ddr_lo(r0)
cmpwi r10,-1
beq rominit

li r3,0x0F # 0F; dram checking
bl set_leds_b0
li r3,DATA+MSG_DDR_0
bl console_println

li r8,0 # loop counter
lwz r9,ddr_chk_loops(r0)

li r12,0 # data
oris r12,r12,0x6708
ori r12,r12,0x0953

ddr_start:
addi r8,r8,1
mr r3,r8
bl set_leds_b1 # running pass

lwz r10,ddr_lo(r0)
lwz r11,ddr_hi(r0)
addi r11,r11,1
subf r11,r10,r11
srwi r11,r11,2 # word r/w
mtctr r11

ddr_writes:
stw r12,0(r10)
addi r10,r10,4
bdnz ddr_writes

lwz r10,ddr_lo(r0)
mtctr r11

ddr_reads:
lwz r13,0(r10)
cmpw r13,r12
bne ddr_fail_save
addi r10,r10,4
bdnz ddr_reads

# loop done

addi r12,r12,7 # change pattern
cmpwi r9,0
beq ddr_start
cmpw r8,r9
bne ddr_start

li r3,0x0E # 0E; dram OK
bl set_leds_b0
li r3,0x00
bl set_leds_b1
li r3,DATA+MSG_DDR_1
bl console_println
delay r10,DELAY

########################################################################################################################################

rominit:

li r3,DATA+MSG_ROM_INIT
bl console_println

########################################################################################################################################
# VMA/LMA: copy .data, clear .bss

# get the linker script symbols needed...
#lis r1,(.TOC.-0)@h
#lis r1,.toc.@h
#lis r6,.got.@h
#lwz r1,_fdata_rom@got(r6)

lis r1,_fdata_rom@h
ori r1,r1,_fdata_rom@l
lis r2,_fdata@h
ori r2,r2,_fdata@l
lis r3,_edata_rom@h
ori r3,r3,_edata_rom@l
lis r4,_fbss@h
ori r4,r4,_fbss@l
lis r5,_ebss@h
ori r5,r5,_ebss@l

subf r9,r1,r3
srwi. r9,r9,2
beq romcopy_done
mtctr r9
addi r1,r1,-4
addi r2,r2,-4

romcopy:
lwzu r9,4(r1)
stwu r9,4(r2)
bdnz romcopy

romcopy_done:
subf r9,r4,r5
srwi. r9,r9,2
beq romclear_done

mtctr r9
addi r4,r4,-4
li r9,0

romclear:
stwu r9,4(r4)
bdnz romclear

romclear_done:

########################################################################################################################################

########################################################################################################################################

process_start:

li r3,DATA+MSG_BANNER
bl console_println

jump2main:
lis r1,_fstack@h
ori r1,r1,_fstack@l
li r3, 0 # parm 1
b main

########################################################################################################################################

.ifdef TEST_MEM

.macro asciib rt,rs
andi. \rt,\rs,0x0F
cmpwi \rt,10
blt +8
addi \rt,\rt,0x11-10
addi \rt,\rt,0x30
.endm

.macro println_reg rt
rotlwi \rt,\rt,4
asciib r3,\rt
bl uart_write
rotlwi \rt,\rt,4
asciib r3,\rt
bl uart_write
rotlwi \rt,\rt,4
asciib r3,\rt
bl uart_write
rotlwi \rt,\rt,4
asciib r3,\rt
bl uart_write
rotlwi \rt,\rt,4
asciib r3,\rt
bl uart_write
rotlwi \rt,\rt,4
asciib r3,\rt
bl uart_write
rotlwi \rt,\rt,4
asciib r3,\rt
bl uart_write
rotlwi \rt,\rt,4
asciib r3,\rt
bl uart_write
li r3,0x0D
bl uart_write
li r3,0x0A
bl uart_write
.endm

# running out of space
print_r6:
mflr r0
println_reg r6
mtlr r0
blr

test_mem:
lis r5,1 # start@-
ori r10,r5,0x40 # end@

load32 r6,0x0a0b0c0d
li r3,'W'
bl uart_write
bl print_r6

#stw r6,0(r5)
#load32 r6,0
#stw r6,4(r5)
#stw r6,8(r5)
#stw r6,12(r5)
stb r6,0(r5)
srwi r6,r6,8
stb r6,5(r5)
srwi r6,r6,8
stb r6,10(r5)
srwi r6,r6,8
stb r6,15(r5)
lbz r6,0(r5)
bl print_r6
lbz r6,1(r5)
bl print_r6
lbz r6,2(r5)
bl print_r6
lbz r6,3(r5)
bl print_r6
lbz r6,4(r5)
bl print_r6
nop
nop
nop
nop
test_mem_read:
lwz r7,0(r5)
li r3,'R'
bl uart_write
println_reg r7
addi r5,r5,4
cmpw r5,r10
blt test_mem_read
#b .
b sram_chk

.endif

########################################################################################################################################
# rom: just check high address - could be a crc check

test_rom:
lwz r20,rom_hi(r0)
li r21,-4
and r21,r20,r21
lwz r21,0(r21)
lwz r22,eob_data(r0)
cmpw r21,r22
li r3,1
bne fail
bl set_leds

b pass

# put data in sram so it can be read from uart
ddr_fail_save:

lis r1,_fdata@h
ori r1,r1,_fdata@l

stw r0,0(1)
#stw r1,4(1)
stw r2,8(1)
stw r3,12(1) # loops
stw r4,16(1)
stw r5,20(1)
stw r6,24(1)
stw r7,28(1)
stw r8,32(1)
stw r9,36(1)
stw r10,40(1) # addr
stw r11,44(1)
stw r12,48(1) # exp
stw r13,52(1) # act
stw r14,56(1)
stw r15,60(1)
stw r16,64(1)
stw r17,68(1)
stw r18,72(1)
stw r19,76(1)
stw r20,80(1)
stw r21,84(1)
stw r22,88(1)
stw r23,92(1)
stw r24,96(1)
stw r25,100(1)
stw r26,104(1)
stw r27,108(1)
stw r28,112(1)
stw r29,116(1)
stw r30,120(1)
stw r31,124(1)

mfcr r31
stw r31,128(1) # cr
mfctr r31
stw r31,132(1) # ctr
mflr r31
stw r31,136(1) # lr
mfspr r31,tar
stw r31,140(1) # tar
li r31,-1
stw r31,144(1) # error code

b fail

console_echo:

mflr r0

lwz r5,sram_lo(r0) # buffer start
mr r6,r5 # buffer ptr

console_echo_1:
bl uart_read_nonblock # this could just be uart_read() unless want to do something else while waiting
cmpwi r3, 0
beq console_echo_1
bl uart_read

cmpwi r3,0x0A # lf
beq console_echo_2
cmpwi r3,0x0D # cr
beq console_echo_2
stb r3,0(6)
addi r6,r6,1
bl uart_write
b console_echo_1

console_echo_2:
# print back the whole line surrounded by <>
subf r3,r5,r6
mtctr r3
li r3,0x0D # cr
bl uart_write
li r3,0x0A # lf
bl uart_write
li r3,0x3C # <
bl uart_write
mr r6,r5 # start of buffer

console_echo_3:
lbz r3,0(6)
bl uart_write
addi r6,r6,1
bdnz console_echo_3

li r3,0x3E # >
bl uart_write
li r3,0x0D # cr
bl uart_write
li r3,0x0A # lf
bl uart_write
mr r6,r5 # start of buffer
b console_echo_1

mtlr r0
blr

console_print:

mflr r0
mr r5,r3 # buffer ptr

console_print_1:
lbz r3,0(5)
cmpwi r3,0
beq console_print_2
bl uart_write
addi r5,r5,1
bdnz console_print_1

console_print_2:
mtlr r0
blr

console_println:
mflr r0
mr r5,r3 # buffer ptr

console_println_1:
lbz r3,0(5)
cmpwi r3,0
beq console_println_2
bl uart_write
addi r5,r5,1
bdnz console_println_1

console_println_2:
li r3,0x0D # cr
bl uart_write
li r3,0x0A # lf
bl uart_write

mtlr r0
blr

.org 0x1800

pass:
mflr r0
li r3,0x01C0
bl set_leds
b .

.align 6
# fail w/generic code, or specify
fail:
li r3,0x6666
fail_rc:
mflr r0
bl set_leds
fail_no_rc:
b .

.align 6
# set up everything that isn't reset; not really needed for fpga
core_init:
blr

# leds 15:0
get_leds:
lwz r1,leds(r0)
lhz r3,0(1)
blr

set_leds:
lwz r1,leds(r0)
sth r3,0(1)
blr

# litex csr don't obey sel!?!?!
set_leds_b0:
lwz r1,leds(r0)
#stb r3,0(1)
lhz r2,0(1) # 0011
andi. r2,r2,0x00FF
slwi r3,r3,8
or r2,r2,r3
sth r2,0(1) # 0011
blr

set_leds_b1:
lwz r1,leds(r0)
lhz r2,0(1) # 0011
andi. r2,r2,0xFF00
andi. r3,r3,0x00FF
or r2,r2,r3
sth r2,0(1) # 0011
blr

.align 6

.set UART_EV_TX, 0x1
.set UART_EV_RX, 0x2

uart_init:
lwz r2, uart(r0)
lbz r1, UART_EV_PENDING(r2)
stb r1, UART_EV_PENDING(r2)
li r1, UART_EV_TX | UART_EV_RX
stb r1, UART_EV_ENABLE(r2)
blr


uart_read:
lwz r2, uart(r0)
lbz r1, UART_RXEMPTY(r2)
cmpwi r1,0
bne uart_read
lbz r3, UART_RXTX(r2)
li r1, UART_EV_RX
stb r1, UART_EV_PENDING(r2)
blr

uart_read_nonblock:
lwz r2, uart(r0)
li r3,0
lbz r1, UART_RXEMPTY(r2)
cmpw r1,r3
bne uart_read_nonblock_1
li r3,1
uart_read_nonblock_1:
blr

uart_write:
lwz r2, uart(r0)
lbz r1, UART_TXFULL(r2)
cmpwi r1,0
bne uart_write
stb r3, UART_RXTX(r2)
li r1, UART_EV_TX
stb r1, UART_EV_PENDING(r2)
blr

uart_sync:
lwz r2, uart(r0)
lbz r1, UART_TXFULL(r2)
cmpwi r1,0
bne uart_sync
blr

.org 0x1C00
.set DATA, 0x1C00

msg_hello:
.byte 0x0D
.byte 0x0A
.ascii "A2P POWAflight"
.byte 0x0D
.byte 0x0A
.asciz ""

.align 5
msg_sram:
.ascii "SRAM OK."
.asciz ""


.align 5
msg_ddr_0:
.ascii "SDRAM TEST..."
.asciz ""

.align 5
.msg_ddr_1:
.ascii "SDRAM OK "
.ascii "@10000000:"
.asciz "17FFFFFF"

.align 5
.msg_rom:
.ascii "Copying"
.ascii " ROM to"
.asciz " RAM..."

.align 5
.msg_banner:
#.include "banner.s"
.ascii "Jumping to"
.asciz " main()..."

.set MSG_HELLO, 0
.set MSG_SRAM, MSG_HELLO+32
.set MSG_DDR_0, MSG_SRAM+32
.set MSG_DDR_1, MSG_DDR_0+32
.set MSG_ROM_INIT, MSG_DDR_1+32
.set MSG_BANNER, MSG_ROM_INIT+32

@ -0,0 +1,146 @@
# © IBM Corp. 2020
# Licensed under and subject to the terms of the CC-BY 4.0
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
# Additional rights, including the right to physically implement a softcore
# that is compliant with the required sections of the Power ISA
# Specification, will be available at no cost via the OpenPOWER Foundation.
# This README will be updated with additional information when OpenPOWER's
# license is available.

#-----------------------------------------
# Defines
#-----------------------------------------

# Regs

.set r0, 0
.set r1, 1
.set r2, 2
.set r3, 3
.set r4, 4
.set r5, 5
.set r6, 6
.set r7, 7
.set r8, 8
.set r9, 9
.set r10,10
.set r11,11
.set r12,12
.set r13,13
.set r14,14
.set r15,15
.set r16,16
.set r17,17
.set r18,18
.set r19,19
.set r20,20
.set r21,21
.set r22,22
.set r23,23
.set r24,24
.set r25,25
.set r26,26
.set r27,27
.set r28,28
.set r29,29
.set r30,30
.set r31,31

.set f0, 0
.set f1, 1
.set f2, 2
.set f3, 3
.set f4, 4
.set f5, 5
.set f6, 6
.set f7, 7
.set f8, 8
.set f9, 9
.set f10,10
.set f11,11
.set f12,12
.set f13,13
.set f14,14
.set f15,15
.set f16,16
.set f17,17
.set f18,18
.set f19,19
.set f20,20
.set f21,21
.set f22,22
.set f23,23
.set f24,24
.set f25,25
.set f26,26
.set f27,27
.set f28,28
.set f29,29
.set f30,30
.set f31,31

.set cr0, 0
.set cr1, 1
.set cr2, 2
.set cr3, 3
.set cr4, 4
.set cr5, 5
.set cr6, 6
.set cr7, 7

# SPR numbers

.set srr0, 26
.set srr1, 27
.set epcr, 307
.set tar, 815
.set dsisr, 18
.set dar, 19

.set dbsr, 304
.set dbcr0, 308
.set dbcr1, 309
.set dbcr2, 310
.set dbcr3, 848

.set ivpr, 63

.set iucr0, 1011
.set iucr1, 883
.set iucr2, 884

.set iudbg0, 888
.set iudbg1, 889
.set iudbg2, 890
.set iulfsr, 891
.set iullcr, 892

.set mmucr0, 1020
.set mmucr1, 1021
.set mmucr2, 1022
.set mmucr3, 1023

.set tb, 268
.set tbl, 284
.set tbh, 285

.set dec, 22
.set udec, 550
.set tsr, 336
.set tcr, 340

.set xucr0, 1014
.set xucr1, 851
.set xucr2, 1016
.set xucr3, 852
.set xucr4, 853

.set tens, 438
.set tenc, 439
.set tensr, 437

.set pid, 48
.set pir, 286
.set pvr, 287
.set tir, 446

@ -0,0 +1,18 @@
#ifndef __IRQ_H
#define __IRQ_H

static inline void irq_setmask(unsigned int mask) {
}

static inline unsigned int irq_getmask(void) {
return 0;
}

static inline unsigned int irq_pending(void) {
return 0;
}

static inline void irq_setie(unsigned int mask) {
}

#endif

@ -0,0 +1,61 @@
// a2p

#ifndef __SYSTEM_H
#define __SYSTEM_H

#include <stdint.h>

/*
void flush_l2_cache(void) {
}
*/
static void flush_cpu_icache(void);
static void flush_cpu_dcache(void);

static void flush_cpu_icache(void) {
}
static void flush_cpu_dcache(void) {
}

#define CSR_ACCESSORS_DEFINED

#ifdef __ASSEMBLER__
#define MMPTR(x) x
#else /* ! __ASSEMBLER__ */

/* CSRs are stored in subregister slices of CONFIG_CSR_DATA_WIDTH (native
* endianness), with the least significant slice at the lowest aligned
* (base) address. */

#include <generated/soc.h>
#if !defined(CONFIG_CSR_DATA_WIDTH)
#error CSR_DATA_WIDTH MUST be set before including this file!
#endif

/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside uint32_t
* aligned locations: */
#define MMPTR(a) (*((volatile uint32_t *)(a)))

static inline unsigned long swizzle(unsigned long v);

static inline unsigned long swizzle(unsigned long v) {
return ((v & 0x000000FF) << 24) | ((v & 0x0000FF00) << 8) | ((v & 0x00FF0000) >> 8) | ((v & 0xFF000000) >> 24);
//return v;
}

static inline void csr_write_simple(unsigned long v, unsigned long a)
{
//MMPTR(a) = v;
MMPTR(a) = swizzle(v);
}

static inline unsigned long csr_read_simple(unsigned long a)
{
//return MMPTR(a);
return swizzle(MMPTR(a));
}

#endif /* ! __ASSEMBLER__ */

#endif /* __SYSTEM_H */

@ -1,3 +1,3 @@
# Autogenerated by LiteX / git: 6932fc51
# Autogenerated by LiteX / git: 33ae301d
set -e
vivado -mode batch -source cmod7_kintex.tcl

@ -8,8 +8,8 @@
//
// Filename : cmod7_kintex.v
// Device : xc7k410t-ffv676-1
// LiteX sha1 : 6932fc51
// Date : 2022-08-04 09:13:14
// LiteX sha1 : 33ae301d
// Date : 2022-08-15 13:16:22
//------------------------------------------------------------------------------


@ -284,17 +284,6 @@ wire [13:0] sram0_adr;
wire [31:0] sram0_dat_r;
reg [3:0] sram0_we = 4'd0;
wire [31:0] sram0_dat_w;
reg [1:0] leds_storage = 2'd0;
reg leds_re = 1'd0;
reg [1:0] leds_chaser = 2'd0;
reg leds_mode = 1'd0;
wire leds_wait;
wire leds_done;
reg [24:0] leds_count = 25'd25000000;
reg [1:0] leds_leds = 2'd0;
wire [1:0] buttons_status;
wire buttons_we;
reg buttons_re = 1'd0;
wire [29:0] interface1_ram_bus_adr;
wire [31:0] interface1_ram_bus_dat_w;
wire [31:0] interface1_ram_bus_dat_r;
@ -307,10 +296,21 @@ wire [2:0] interface1_ram_bus_cti;
wire [1:0] interface1_ram_bus_bte;
reg interface1_ram_bus_err = 1'd0;
reg sram1_adr_burst = 1'd0;
wire [5:0] sram1_adr;
wire [21:0] sram1_adr;
wire [31:0] sram1_dat_r;
reg [3:0] sram1_we = 4'd0;
wire [31:0] sram1_dat_w;
reg [1:0] leds_storage = 2'd0;
reg leds_re = 1'd0;
reg [1:0] leds_chaser = 2'd0;
reg leds_mode = 1'd0;
wire leds_wait;
wire leds_done;
reg [24:0] leds_count = 25'd25000000;
reg [1:0] leds_leds = 2'd0;
wire [1:0] buttons_status;
wire buttons_we;
reg buttons_re = 1'd0;
reg [13:0] basesoc_adr = 14'd0;
reg basesoc_we = 1'd0;
reg [31:0] basesoc_dat_w = 32'd0;
@ -527,7 +527,6 @@ always @(*) begin
end
assign bus_errors_status = bus_errors;
always @(*) begin
serial_tx_rs232phytx_next_value1 <= 1'd0;
serial_tx_rs232phytx_next_value_ce1 <= 1'd0;
tx_enable <= 1'd0;
tx_data_rs232phytx_next_value2 <= 8'd0;
@ -536,6 +535,7 @@ always @(*) begin
basesoc_rs232phytx_next_state <= 1'd0;
tx_count_rs232phytx_next_value0 <= 4'd0;
tx_count_rs232phytx_next_value_ce0 <= 1'd0;
serial_tx_rs232phytx_next_value1 <= 1'd0;
basesoc_rs232phytx_next_state <= basesoc_rs232phytx_state;
case (basesoc_rs232phytx_state)
1'd1: begin
@ -739,6 +739,16 @@ end
assign sram0_adr = interface0_ram_bus_adr[13:0];
assign interface0_ram_bus_dat_r = sram0_dat_r;
assign sram0_dat_w = interface0_ram_bus_dat_w;
always @(*) begin
sram1_we <= 4'd0;
sram1_we[0] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[0]);
sram1_we[1] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[1]);
sram1_we[2] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[2]);
sram1_we[3] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[3]);
end
assign sram1_adr = interface1_ram_bus_adr[21:0];
assign interface1_ram_bus_dat_r = sram1_dat_r;
assign sram1_dat_w = interface1_ram_bus_dat_w;
assign leds_wait = (~leds_done);
always @(*) begin
leds_leds <= 2'd0;
@ -750,21 +760,11 @@ always @(*) begin
end
assign {user_led1, user_led0} = (leds_leds ^ 1'd0);
assign leds_done = (leds_count == 1'd0);
always @(*) begin
sram1_we <= 4'd0;
sram1_we[0] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[0]);
sram1_we[1] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[1]);
sram1_we[2] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[2]);
sram1_we[3] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[3]);
end
assign sram1_adr = interface1_ram_bus_adr[5:0];
assign interface1_ram_bus_dat_r = sram1_dat_r;
assign sram1_dat_w = interface1_ram_bus_dat_w;
always @(*) begin
basesoc_wishbone_ack <= 1'd0;
basesoc_dat_w <= 32'd0;
basesoc_next_state <= 1'd0;
basesoc_wishbone_dat_r <= 32'd0;
basesoc_next_state <= 1'd0;
basesoc_adr <= 14'd0;
basesoc_we <= 1'd0;
basesoc_next_state <= basesoc_state;
@ -801,7 +801,7 @@ always @(*) begin
slave_sel <= 4'd0;
slave_sel[0] <= (shared_adr[29:14] == 1'd0);
slave_sel[1] <= (shared_adr[29:14] == 1'd1);
slave_sel[2] <= (shared_adr[29:6] == 13'd4096);
slave_sel[2] <= (shared_adr[29:22] == 1'd1);
slave_sel[3] <= (shared_adr[29:14] == 16'd65520);
end
assign ram_bus_adr = shared_adr;
@ -839,9 +839,9 @@ assign basesoc_wishbone_cyc = (shared_cyc & slave_sel[3]);
assign shared_err = (((ram_bus_err | interface0_ram_bus_err) | interface1_ram_bus_err) | basesoc_wishbone_err);
assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
always @(*) begin
shared_ack <= 1'd0;
error <= 1'd0;
shared_dat_r <= 32'd0;
shared_ack <= 1'd0;
shared_ack <= (((ram_bus_ack | interface0_ram_bus_ack) | interface1_ram_bus_ack) | basesoc_wishbone_ack);
shared_dat_r <= (((({32{slave_sel_r[0]}} & ram_bus_dat_r) | ({32{slave_sel_r[1]}} & interface0_ram_bus_dat_r)) | ({32{slave_sel_r[2]}} & interface1_ram_bus_dat_r)) | ({32{slave_sel_r[3]}} & basesoc_wishbone_dat_r));
if (done) begin
@ -942,8 +942,8 @@ always @(*) begin
end
assign csr_bankarray_csrbank3_en0_r = csr_bankarray_interface3_bank_bus_dat_w[0];
always @(*) begin
csr_bankarray_csrbank3_en0_re <= 1'd0;
csr_bankarray_csrbank3_en0_we <= 1'd0;
csr_bankarray_csrbank3_en0_re <= 1'd0;
if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd2))) begin
csr_bankarray_csrbank3_en0_re <= csr_bankarray_interface3_bank_bus_we;
csr_bankarray_csrbank3_en0_we <= (~csr_bankarray_interface3_bank_bus_we);
@ -969,8 +969,8 @@ always @(*) begin
end
assign csr_bankarray_csrbank3_ev_status_r = csr_bankarray_interface3_bank_bus_dat_w[0];
always @(*) begin
csr_bankarray_csrbank3_ev_status_re <= 1'd0;
csr_bankarray_csrbank3_ev_status_we <= 1'd0;
csr_bankarray_csrbank3_ev_status_re <= 1'd0;
if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd5))) begin
csr_bankarray_csrbank3_ev_status_re <= csr_bankarray_interface3_bank_bus_we;
csr_bankarray_csrbank3_ev_status_we <= (~csr_bankarray_interface3_bank_bus_we);
@ -1011,8 +1011,8 @@ assign csr_bankarray_csrbank3_ev_enable0_w = timer_enable_storage;
assign csr_bankarray_csrbank4_sel = (csr_bankarray_interface4_bank_bus_adr[13:9] == 4'd8);
assign uart_rxtx_r = csr_bankarray_interface4_bank_bus_dat_w[7:0];
always @(*) begin
uart_rxtx_we <= 1'd0;
uart_rxtx_re <= 1'd0;
uart_rxtx_we <= 1'd0;
if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin
uart_rxtx_re <= csr_bankarray_interface4_bank_bus_we;
uart_rxtx_we <= (~csr_bankarray_interface4_bank_bus_we);
@ -1056,8 +1056,8 @@ always @(*) begin
end
assign csr_bankarray_csrbank4_ev_enable0_r = csr_bankarray_interface4_bank_bus_dat_w[1:0];
always @(*) begin
csr_bankarray_csrbank4_ev_enable0_re <= 1'd0;
csr_bankarray_csrbank4_ev_enable0_we <= 1'd0;
csr_bankarray_csrbank4_ev_enable0_re <= 1'd0;
if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd5))) begin
csr_bankarray_csrbank4_ev_enable0_re <= csr_bankarray_interface4_bank_bus_we;
csr_bankarray_csrbank4_ev_enable0_we <= (~csr_bankarray_interface4_bank_bus_we);
@ -1334,6 +1334,10 @@ always @(posedge sys_clk) begin
if (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & ((~interface0_ram_bus_ack) | sram0_adr_burst))) begin
interface0_ram_bus_ack <= 1'd1;
end
interface1_ram_bus_ack <= 1'd0;
if (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & ((~interface1_ram_bus_ack) | sram1_adr_burst))) begin
interface1_ram_bus_ack <= 1'd1;
end
if (leds_done) begin
leds_chaser <= {leds_chaser, (~leds_chaser[1])};
end
@ -1347,10 +1351,6 @@ always @(posedge sys_clk) begin
end else begin
leds_count <= 25'd25000000;
end
interface1_ram_bus_ack <= 1'd0;
if (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & ((~interface1_ram_bus_ack) | sram1_adr_burst))) begin
interface1_ram_bus_ack <= 1'd1;
end
basesoc_state <= basesoc_next_state;
slave_sel_r <= slave_sel;
if (wait_1) begin
@ -1554,13 +1554,13 @@ always @(posedge sys_clk) begin
timer_value <= 32'd0;
ram_bus_ack <= 1'd0;
interface0_ram_bus_ack <= 1'd0;
interface1_ram_bus_ack <= 1'd0;
leds_storage <= 2'd0;
leds_re <= 1'd0;
leds_chaser <= 2'd0;
leds_mode <= 1'd0;
leds_count <= 25'd25000000;
buttons_re <= 1'd0;
interface1_ram_bus_ack <= 1'd0;
slave_sel_r <= 4'd0;
count <= 20'd1000000;
csr_bankarray_sel_r <= 1'd0;
@ -1580,10 +1580,10 @@ end
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Memory mem: 29-words x 8-bit
// Memory mem: 24-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: ---- |
reg [7:0] mem[0:28];
reg [7:0] mem[0:23];
initial begin
$readmemh("cmod7_kintex_mem.init", mem);
end
@ -1695,14 +1695,14 @@ assign sram0_dat_r = sram[sram_adr0];


//------------------------------------------------------------------------------
// Memory main_ram: 64-words x 32-bit
// Memory main_ram: 4194304-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8
reg [31:0] main_ram[0:63];
reg [31:0] main_ram[0:4194303];
initial begin
$readmemh("cmod7_kintex_main_ram.init", main_ram);
end
reg [5:0] main_ram_adr0;
reg [21:0] main_ram_adr0;
always @(posedge sys_clk) begin
if (sram1_we[0])
main_ram[sram1_adr][7:0] <= sram1_dat_w[7:0];
@ -1719,8 +1719,7 @@ assign sram1_dat_r = main_ram[main_ram_adr0];

a2owb a2owb(
.cfg_wr(1'd0),
.clk_1x(sys_clk),
.clk_2x(sys2x_clk),
.clk(sys_clk),
.externalInterrupt(a2o_interrupt[0]),
.externalInterruptS(a2o_interruptS),
.rst((sys_rst | a2o_reset)),
@ -1728,7 +1727,7 @@ a2owb a2owb(
.timerInterrupt(a2o_interrupt[1]),
.wb_ack(a2o_dbus_ack),
.wb_datr(a2o_dbus_dat_r),
.wb_adr({a2o, a2o_dbus_adr}),
.wb_adr({a2o_dbus_adr, a2o}),
.wb_cyc(a2o_dbus_cyc),
.wb_datw(a2o_dbus_dat_w),
.wb_sel(a2o_dbus_sel),
@ -1887,5 +1886,5 @@ MMCME2_ADV #(
endmodule

// -----------------------------------------------------------------------------
// Auto-Generated by LiteX on 2022-08-04 09:13:14.
// Auto-Generated by LiteX on 2022-08-15 13:16:22.
//------------------------------------------------------------------------------

@ -2,11 +2,6 @@
32
4f
20
54
65
73
74
20
32
30
32
@ -15,15 +10,15 @@
30
38
2d
30
34
31
35
20
30
39
3a
31
33
3a
31
34
36
3a
32
32
00

@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
// Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H

@ -1,8 +1,8 @@
//--------------------------------------------------------------------------------
// Auto-generated by LiteX (6932fc51) on 2022-08-04 09:13:14
// Auto-generated by LiteX (33ae301d) on 2022-08-15 13:16:22
//--------------------------------------------------------------------------------
#ifndef __GENERATED_GIT_H
#define __GENERATED_GIT_H

#define LITEX_GIT_SHA1 "6932fc51"
#define LITEX_GIT_SHA1 "33ae301d"
#endif

@ -1,5 +1,5 @@
//--------------------------------------------------------------------------------
<