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974 lines
22 KiB
ArmAsm
974 lines
22 KiB
ArmAsm
# debug code for mem
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#.set TEST_MEM,1
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# boot code for rom integration with litex terminal code
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# requires 64K ROM
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# got rid of int handlers for now to shrink this code
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# cmod7 - skip ddr stuff
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# set for sim bypass version
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#.set SIM,1 # this skips uart, ram check, etc.
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#.set DELAY,0x00000005
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# general delay (leds)
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# should probs put this in a mem loc so it can be easily changed w/o compile
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.set DELAY,0x01000000 # hardware (~1 secs)
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#.set DELAY,0x00000100
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# csr.csv
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# need to set up CONFIG:
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#csr_base,dna,0xfff00000,,
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#csr_base,xadc,0xfff00800,,
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#csr_base,leds,0xfff01000,,
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#csr_base,buttons,0xfff01800,,
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#csr_base,i2c,0xfff02000,,
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#csr_base,motor_0,0xfff02800,,
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#csr_base,ctrl,0xfff03000,,
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#csr_base,identifier_mem,0xfff03800,,
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#csr_base,timer0,0xfff04000,,
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#csr_base,uart,0xfff04800,,
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#
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#memory_region,rom,0x00000000,65536,cached
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#memory_region,ram,0x00010000,4096,cached
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#memory_region,sram,0x80000000,4096,cached
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#memory_region,csr,0xfff00000,65536,io
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.include "defines.s"
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#.section .hwinit # @00000000
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# change to use litex linker.ld
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.section .text
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.global _start
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# reset
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_start:
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b boot_start
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.set REGSAVE,0x04
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regsave:
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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.long 0
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# ddr setup delay (intracommand)
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.ifdef SIM
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.set DDR_DELAY,0x00000010 # sim
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.else
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.set DDR_DELAY,0x00020000
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.endif
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.align 6
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.set CONFIG,0x40
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#.set SRAM_BASE, 0x00010000 # get from _fdata
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#.set STACK, 0x0001FFF8 # first save of r0 is 4 past this! #get from _fstack
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.set MAGIC, 0x08675309
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rom_lo: .long 0
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rom_hi: .long 0xFFFF
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sram_lo: .long 0 # get from link syms; does chk for -1 to skip test
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sram_hi: .long 0
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ddr_lo: .long 0xFFFFFFFF # -1: no gots
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ddr_hi: .long 0xF7FFFFFF
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ctrl: .long 0xFFF03000
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cpu: .long 0xFFFFFFFF # -1: no gots
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uart: .long 0xFFF04800 # -1: no gots
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leds: .long 0xFFF01000 # -1: no gots
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switches: .long 0xFFFFFFFF # -1: no gots
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buttons: .long 0xFFF01800 # -1: no gots
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sdram: .long 0xFFFFFFFF
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eob_data: .long MAGIC
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# offsets for uart functions
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.set UART_RXTX, 0x00
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.set UART_TXFULL, 0x04
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.set UART_RXEMPTY, 0x08
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.set UART_EV_STATUS, 0x0C
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.set UART_EV_PENDING, 0x10
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.set UART_EV_ENABLE, 0x14
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.set UART_TXEMPTY, 0x18
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.set UART_RXFULL, 0x1C
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.set UARTX_RXTX, 0x20
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.set UARTX_TXFULL, 0x24
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.set UARTX_RXEMPTY, 0x28
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.set UARTX_EV_STATUS, 0x2C
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.set UARTX_EV_PENDING, 0x30
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.set UARTX_EV_ENABLE, 0x34
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.set UARTX_TXEMPTY, 0x38
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.set UARTX_RXFULL, 0x3C
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.align 7
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.set CONFIG_DDR,0x80
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#wtf can litex be forced to put these at specific offsets from csr_base???
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sdram_dfii: .long 0xFFF06000 # csr_register,sdram_dfii_control,0xfff05000,1,rw
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ddr_cmd_delay: .long DDR_DELAY
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ddr_chk_loops: .long 1 # 0=infinite
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ddr_mrs0: .long 0 # wtf eventually set these up as config vals
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# offsets from sdram_dfii base
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.set DFII_CONTROL, 0x00
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.set DFII_PI0_COMMAND, 0x04
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.set DFII_PI0_COMMAND_ISSUE, 0x08
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.set DFII_PI0_ADDRESS, 0x0C
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.set DFII_PI0_BADDRESS, 0x10
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.set DFII_PI0_WRDATA, 0x14
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.set DFII_PI0_RDDATA, 0x18
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.set DFII_PI1_COMMAND, 0x1C
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.set DFII_PI1_COMMAND_ISSUE, 0x20
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.set DFII_PI1_ADDRESS, 0x24
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.set DFII_PI1_BADDRESS, 0x28
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.set DFII_PI1_WRDATA, 0x2C
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.set DFII_PI1_RDDATA, 0x30
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# bits
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.set CONTROL_SEL, 0x01
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.set CONTROL_CKE, 0x02
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.set CONTROL_ODT, 0x04 #wtf does this exist for ddr2??
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.set CONTROL_RESET_N, 0x08
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.set COMMAND_CS, 0x01
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.set COMMAND_WE, 0x02
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.set COMMAND_CAS, 0x04
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.set COMMAND_RAS, 0x08
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.set COMMAND_WRDATA, 0x10
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.set COMMAND_RDDATA, 0x20
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.set DDR_PARM_DELAY, 0x00020000
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#
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.align 8
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int_100:
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b .
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# mck
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.align 8
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int_200:
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b .
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# dsi
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.align 8
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int_300:
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b .
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# dseg
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.align 7
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int_380:
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b .
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# isi
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.align 8
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int_400:
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b .
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# iseg
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.align 7
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int_480:
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b .
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# external
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.align 8
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int_500:
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b .
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# alignment
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.align 8
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int_600:
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b .
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# program
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.align 8
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int_700:
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b .
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# fp unavailable
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.align 8
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int_800:
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b .
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# dec
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.align 8
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int_900:
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b .
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# dec hyp
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.align 7
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int_980:
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b .
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# doorbell
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.align 8# offsets from sdram_dfii base
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.set DFII_CONTROL, 0x00
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.set DFII_PI0_COMMAND, 0x04
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.set DFII_PI0_COMMAND_ISSUE, 0x08
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.set DFII_PI0_ADDRESS, 0x0C
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.set DFII_PI0_BADDRESS, 0x10
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.set DFII_PI0_WRDATA, 0x14
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.set DFII_PI0_RDDATA, 0x18
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.set DFII_PI1_COMMAND, 0x1C
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.set DFII_PI1_COMMAND_ISSUE, 0x20
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.set DFII_PI1_ADDRESS, 0x24
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.set DFII_PI1_BADDRESS, 0x28
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.set DFII_PI1_WRDATA, 0x2C
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.set DFII_PI1_RDDATA, 0x30
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# bits
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.set CONTROL_SEL, 0x01
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.set CONTROL_CKE, 0x02
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.set CONTROL_ODT, 0x04 #wtf does this exist for ddr2??
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.set CONTROL_RESET_N, 0x08
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.set COMMAND_CS, 0x01
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.set COMMAND_WE, 0x02
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.set COMMAND_CAS, 0x04
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.set COMMAND_RAS, 0x08
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.set COMMAND_WRDATA, 0x10
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.set COMMAND_RDDATA, 0x20
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.set DDR_PARM_DELAY, 0x00020000
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int_C00:
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b .
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# trace
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.align 8
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int_D00:
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b .
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# dsi hyp
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.align 8
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int_E00:
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b .
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# isi hyp
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.align 5
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int_E20:
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b .
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# emulation hyp
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.align 5
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int_E40:
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b .
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# maintenance hyp
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.align 5
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int_E60:
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b .
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# doorbell hyp
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.align 5
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int_E80:
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b .
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# virtualization hyp
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.align 5
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int_EA0:
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b .
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# reserved
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.align 5
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int_EC0:
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b .
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# reserved
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.align 5
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int_EE0:
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b .
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# perfmon
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.align 5
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int_F00:
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b .
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# vector unavailable
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.align 5
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int_F20:
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b .
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# vsx unavailable
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.align 5
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int_F40:
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b .
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# facility unavailable
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.align 5
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int_F60:
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b .
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# facility unavailable hyp
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.align 5
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int_F80:
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b .
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# ------------------------------------------------------------------------------------------------------------------------------
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# init facilities and memories before blastoff
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#
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.macro load32 rx,v
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li \rx,0
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oris \rx,\rx,\v>>16
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ori \rx,\rx,\v&0x0000FFFF
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.endm
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.macro load16swiz rx,v
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li \rx,0
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ori \rx,\rx,(\v<<8)&0xFF00
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ori \rx,\rx,(\v>>8)&0x00FF
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.endm
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.macro delayr rx
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mtctr \rx
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bdnz .
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.endm
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.macro delay rx,v
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li \rx,0
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oris \rx,\rx,\v>>16
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ori \rx,\rx,\v&0x0000FFFF
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mtctr \rx
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bdnz .
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.endm
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.org 0x1000
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boot_start:
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########################################################################################################################################
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# sim only - go quickly to main() w/no console output
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.ifdef SIM
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li r3,0x01
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bl set_leds_b0
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bl uart_init
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li r3,0x02
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bl set_leds_b0
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b jump2main
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.endif
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########################################################################################################################################
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# clear and init core facilities
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li r3,0x01
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bl core_init
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bl set_leds_b0 # 01; core init'd
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delay r10,DELAY
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########################################################################################################################################
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# console
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console:
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li r3,0x02 # 02; console init
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bl set_leds_b0
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bl uart_init
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delay r10,DELAY
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li r3,0x03 # 03; console init done
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bl set_leds_b0
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delay r10,DELAY
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li r3,DATA+MSG_HELLO
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bl console_println
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########################################################################################################################################
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# check on-board sram
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.ifdef TEST_MEM
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b test_mem
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.endif
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sram_chk:
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lwz r10,sram_lo(r0)
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cmpwi r10,-1
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beq ddr_chk
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# use syms
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lis r10,_fdata@h
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ori r10,r10,_fdata@l
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#lwz r11,sram_hi(r0)
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# use stack top; else have to add sym to linker.ld
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lis r11,_fstack@h
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ori r11,r11,_fstack@l
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addi r11,r11,3
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subf r11,r10,r11
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addi r11,r11,1
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srwi r11,r11,4 # num word reads
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mtctr r11
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li r12,0
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oris r12,r12,0x0867
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ori r12,r12,0x5309 # data
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sram_writes:
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stw r12,0(r10)
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addi r10,r10,4
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bdnz sram_writes
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# use syms
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#lwz r10,sram_lo(r0)
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lis r10,_fdata@h
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ori r10,r10,_fdata@l
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mtctr r11
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sram_reads:
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lwz r13,0(r10)
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cmpw r13,r12
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bne fail
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addi r10,r10,4
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bdnz sram_reads
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li r3,0x07 # 07; sram checked
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bl set_leds_b0
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delay r10,DELAY
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li r3,DATA+MSG_SRAM
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bl console_println
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# sram test someday
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########################################################################################################################################
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# check ddr, n loops
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#wtf is there a way to disable/enable l2????
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ddr_chk:
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lwz r10,ddr_lo(r0)
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cmpwi r10,-1
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beq rominit
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li r3,0x0F # 0F; dram checking
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bl set_leds_b0
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li r3,DATA+MSG_DDR_0
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bl console_println
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li r8,0 # loop counter
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lwz r9,ddr_chk_loops(r0)
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li r12,0 # data
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oris r12,r12,0x6708
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ori r12,r12,0x0953
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ddr_start:
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addi r8,r8,1
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mr r3,r8
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bl set_leds_b1 # running pass
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lwz r10,ddr_lo(r0)
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lwz r11,ddr_hi(r0)
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addi r11,r11,1
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subf r11,r10,r11
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srwi r11,r11,2 # word r/w
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mtctr r11
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ddr_writes:
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stw r12,0(r10)
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addi r10,r10,4
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bdnz ddr_writes
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lwz r10,ddr_lo(r0)
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mtctr r11
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ddr_reads:
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lwz r13,0(r10)
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cmpw r13,r12
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bne ddr_fail_save
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addi r10,r10,4
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bdnz ddr_reads
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# loop done
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addi r12,r12,7 # change pattern
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cmpwi r9,0
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beq ddr_start
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cmpw r8,r9
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bne ddr_start
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li r3,0x0E # 0E; dram OK
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bl set_leds_b0
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li r3,0x00
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bl set_leds_b1
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li r3,DATA+MSG_DDR_1
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bl console_println
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delay r10,DELAY
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########################################################################################################################################
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rominit:
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li r3,DATA+MSG_ROM_INIT
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bl console_println
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########################################################################################################################################
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# VMA/LMA: copy .data, clear .bss
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# get the linker script symbols needed...
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#lis r1,(.TOC.-0)@h
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#lis r1,.toc.@h
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#lis r6,.got.@h
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#lwz r1,_fdata_rom@got(r6)
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lis r1,_fdata_rom@h
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ori r1,r1,_fdata_rom@l
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lis r2,_fdata@h
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ori r2,r2,_fdata@l
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lis r3,_edata_rom@h
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ori r3,r3,_edata_rom@l
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lis r4,_fbss@h
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ori r4,r4,_fbss@l
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lis r5,_ebss@h
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ori r5,r5,_ebss@l
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subf r9,r1,r3
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srwi. r9,r9,2
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beq romcopy_done
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mtctr r9
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addi r1,r1,-4
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addi r2,r2,-4
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romcopy:
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lwzu r9,4(r1)
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stwu r9,4(r2)
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bdnz romcopy
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romcopy_done:
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subf r9,r4,r5
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srwi. r9,r9,2
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beq romclear_done
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mtctr r9
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addi r4,r4,-4
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li r9,0
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romclear:
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stwu r9,4(r4)
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bdnz romclear
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romclear_done:
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########################################################################################################################################
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########################################################################################################################################
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process_start:
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li r3,DATA+MSG_BANNER
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bl console_println
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jump2main:
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lis r1,_fstack@h
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ori r1,r1,_fstack@l
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li r3, 0 # parm 1
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b main
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########################################################################################################################################
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.ifdef TEST_MEM
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|
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.macro asciib rt,rs
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andi. \rt,\rs,0x0F
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cmpwi \rt,10
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blt +8
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addi \rt,\rt,0x11-10
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addi \rt,\rt,0x30
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|
.endm
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|
.macro println_reg rt
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|
rotlwi \rt,\rt,4
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|
asciib r3,\rt
|
|
bl uart_write
|
|
rotlwi \rt,\rt,4
|
|
asciib r3,\rt
|
|
bl uart_write
|
|
rotlwi \rt,\rt,4
|
|
asciib r3,\rt
|
|
bl uart_write
|
|
rotlwi \rt,\rt,4
|
|
asciib r3,\rt
|
|
bl uart_write
|
|
rotlwi \rt,\rt,4
|
|
asciib r3,\rt
|
|
bl uart_write
|
|
rotlwi \rt,\rt,4
|
|
asciib r3,\rt
|
|
bl uart_write
|
|
rotlwi \rt,\rt,4
|
|
asciib r3,\rt
|
|
bl uart_write
|
|
rotlwi \rt,\rt,4
|
|
asciib r3,\rt
|
|
bl uart_write
|
|
li r3,0x0D
|
|
bl uart_write
|
|
li r3,0x0A
|
|
bl uart_write
|
|
.endm
|
|
|
|
# running out of space
|
|
print_r6:
|
|
mflr r0
|
|
println_reg r6
|
|
mtlr r0
|
|
blr
|
|
|
|
test_mem:
|
|
lis r5,1 # start@-
|
|
ori r10,r5,0x40 # end@
|
|
|
|
load32 r6,0x0a0b0c0d
|
|
li r3,'W'
|
|
bl uart_write
|
|
bl print_r6
|
|
|
|
#stw r6,0(r5)
|
|
#load32 r6,0
|
|
#stw r6,4(r5)
|
|
#stw r6,8(r5)
|
|
#stw r6,12(r5)
|
|
stb r6,0(r5)
|
|
srwi r6,r6,8
|
|
stb r6,5(r5)
|
|
srwi r6,r6,8
|
|
stb r6,10(r5)
|
|
srwi r6,r6,8
|
|
stb r6,15(r5)
|
|
lbz r6,0(r5)
|
|
bl print_r6
|
|
lbz r6,1(r5)
|
|
bl print_r6
|
|
lbz r6,2(r5)
|
|
bl print_r6
|
|
lbz r6,3(r5)
|
|
bl print_r6
|
|
lbz r6,4(r5)
|
|
bl print_r6
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
test_mem_read:
|
|
lwz r7,0(r5)
|
|
li r3,'R'
|
|
bl uart_write
|
|
println_reg r7
|
|
addi r5,r5,4
|
|
cmpw r5,r10
|
|
blt test_mem_read
|
|
#b .
|
|
b sram_chk
|
|
|
|
.endif
|
|
|
|
########################################################################################################################################
|
|
# rom: just check high address - could be a crc check
|
|
|
|
test_rom:
|
|
lwz r20,rom_hi(r0)
|
|
li r21,-4
|
|
and r21,r20,r21
|
|
lwz r21,0(r21)
|
|
lwz r22,eob_data(r0)
|
|
cmpw r21,r22
|
|
li r3,1
|
|
bne fail
|
|
bl set_leds
|
|
|
|
b pass
|
|
|
|
# put data in sram so it can be read from uart
|
|
ddr_fail_save:
|
|
|
|
lis r1,_fdata@h
|
|
ori r1,r1,_fdata@l
|
|
|
|
stw r0,0(1)
|
|
#stw r1,4(1)
|
|
stw r2,8(1)
|
|
stw r3,12(1) # loops
|
|
stw r4,16(1)
|
|
stw r5,20(1)
|
|
stw r6,24(1)
|
|
stw r7,28(1)
|
|
stw r8,32(1)
|
|
stw r9,36(1)
|
|
stw r10,40(1) # addr
|
|
stw r11,44(1)
|
|
stw r12,48(1) # exp
|
|
stw r13,52(1) # act
|
|
stw r14,56(1)
|
|
stw r15,60(1)
|
|
stw r16,64(1)
|
|
stw r17,68(1)
|
|
stw r18,72(1)
|
|
stw r19,76(1)
|
|
stw r20,80(1)
|
|
stw r21,84(1)
|
|
stw r22,88(1)
|
|
stw r23,92(1)
|
|
stw r24,96(1)
|
|
stw r25,100(1)
|
|
stw r26,104(1)
|
|
stw r27,108(1)
|
|
stw r28,112(1)
|
|
stw r29,116(1)
|
|
stw r30,120(1)
|
|
stw r31,124(1)
|
|
|
|
mfcr r31
|
|
stw r31,128(1) # cr
|
|
mfctr r31
|
|
stw r31,132(1) # ctr
|
|
mflr r31
|
|
stw r31,136(1) # lr
|
|
mfspr r31,tar
|
|
stw r31,140(1) # tar
|
|
li r31,-1
|
|
stw r31,144(1) # error code
|
|
|
|
b fail
|
|
|
|
console_echo:
|
|
|
|
mflr r0
|
|
|
|
lwz r5,sram_lo(r0) # buffer start
|
|
mr r6,r5 # buffer ptr
|
|
|
|
console_echo_1:
|
|
bl uart_read_nonblock # this could just be uart_read() unless want to do something else while waiting
|
|
cmpwi r3, 0
|
|
beq console_echo_1
|
|
bl uart_read
|
|
|
|
cmpwi r3,0x0A # lf
|
|
beq console_echo_2
|
|
cmpwi r3,0x0D # cr
|
|
beq console_echo_2
|
|
stb r3,0(6)
|
|
addi r6,r6,1
|
|
bl uart_write
|
|
b console_echo_1
|
|
|
|
console_echo_2:
|
|
# print back the whole line surrounded by <>
|
|
subf r3,r5,r6
|
|
mtctr r3
|
|
li r3,0x0D # cr
|
|
bl uart_write
|
|
li r3,0x0A # lf
|
|
bl uart_write
|
|
li r3,0x3C # <
|
|
bl uart_write
|
|
mr r6,r5 # start of buffer
|
|
|
|
console_echo_3:
|
|
lbz r3,0(6)
|
|
bl uart_write
|
|
addi r6,r6,1
|
|
bdnz console_echo_3
|
|
|
|
li r3,0x3E # >
|
|
bl uart_write
|
|
li r3,0x0D # cr
|
|
bl uart_write
|
|
li r3,0x0A # lf
|
|
bl uart_write
|
|
mr r6,r5 # start of buffer
|
|
b console_echo_1
|
|
|
|
mtlr r0
|
|
blr
|
|
|
|
console_print:
|
|
|
|
mflr r0
|
|
mr r5,r3 # buffer ptr
|
|
|
|
console_print_1:
|
|
lbz r3,0(5)
|
|
cmpwi r3,0
|
|
beq console_print_2
|
|
bl uart_write
|
|
addi r5,r5,1
|
|
bdnz console_print_1
|
|
|
|
console_print_2:
|
|
mtlr r0
|
|
blr
|
|
|
|
console_println:
|
|
mflr r0
|
|
mr r5,r3 # buffer ptr
|
|
|
|
console_println_1:
|
|
lbz r3,0(5)
|
|
cmpwi r3,0
|
|
beq console_println_2
|
|
bl uart_write
|
|
addi r5,r5,1
|
|
bdnz console_println_1
|
|
|
|
console_println_2:
|
|
li r3,0x0D # cr
|
|
bl uart_write
|
|
li r3,0x0A # lf
|
|
bl uart_write
|
|
|
|
mtlr r0
|
|
blr
|
|
|
|
.org 0x1800
|
|
|
|
pass:
|
|
mflr r0
|
|
li r3,0x01C0
|
|
bl set_leds
|
|
b .
|
|
|
|
.align 6
|
|
# fail w/generic code, or specify
|
|
fail:
|
|
li r3,0x6666
|
|
fail_rc:
|
|
mflr r0
|
|
bl set_leds
|
|
fail_no_rc:
|
|
b .
|
|
|
|
.align 6
|
|
# set up everything that isn't reset; not really needed for fpga
|
|
core_init:
|
|
blr
|
|
|
|
# leds 15:0
|
|
get_leds:
|
|
lwz r1,leds(r0)
|
|
lhz r3,0(1)
|
|
blr
|
|
|
|
set_leds:
|
|
lwz r1,leds(r0)
|
|
sth r3,0(1)
|
|
blr
|
|
|
|
# litex csr don't obey sel!?!?!
|
|
set_leds_b0:
|
|
lwz r1,leds(r0)
|
|
#stb r3,0(1)
|
|
lhz r2,0(1) # 0011
|
|
andi. r2,r2,0x00FF
|
|
slwi r3,r3,8
|
|
or r2,r2,r3
|
|
sth r2,0(1) # 0011
|
|
blr
|
|
|
|
set_leds_b1:
|
|
lwz r1,leds(r0)
|
|
lhz r2,0(1) # 0011
|
|
andi. r2,r2,0xFF00
|
|
andi. r3,r3,0x00FF
|
|
or r2,r2,r3
|
|
sth r2,0(1) # 0011
|
|
blr
|
|
|
|
.align 6
|
|
|
|
.set UART_EV_TX, 0x1
|
|
.set UART_EV_RX, 0x2
|
|
|
|
uart_init:
|
|
lwz r2, uart(r0)
|
|
lbz r1, UART_EV_PENDING(r2)
|
|
stb r1, UART_EV_PENDING(r2)
|
|
li r1, UART_EV_TX | UART_EV_RX
|
|
stb r1, UART_EV_ENABLE(r2)
|
|
blr
|
|
|
|
|
|
uart_read:
|
|
lwz r2, uart(r0)
|
|
lbz r1, UART_RXEMPTY(r2)
|
|
cmpwi r1,0
|
|
bne uart_read
|
|
lbz r3, UART_RXTX(r2)
|
|
li r1, UART_EV_RX
|
|
stb r1, UART_EV_PENDING(r2)
|
|
blr
|
|
|
|
uart_read_nonblock:
|
|
lwz r2, uart(r0)
|
|
li r3,0
|
|
lbz r1, UART_RXEMPTY(r2)
|
|
cmpw r1,r3
|
|
bne uart_read_nonblock_1
|
|
li r3,1
|
|
uart_read_nonblock_1:
|
|
blr
|
|
|
|
uart_write:
|
|
lwz r2, uart(r0)
|
|
lbz r1, UART_TXFULL(r2)
|
|
cmpwi r1,0
|
|
bne uart_write
|
|
stb r3, UART_RXTX(r2)
|
|
li r1, UART_EV_TX
|
|
stb r1, UART_EV_PENDING(r2)
|
|
blr
|
|
|
|
uart_sync:
|
|
lwz r2, uart(r0)
|
|
lbz r1, UART_TXFULL(r2)
|
|
cmpwi r1,0
|
|
bne uart_sync
|
|
blr
|
|
|
|
.org 0x1C00
|
|
.set DATA, 0x1C00
|
|
|
|
msg_hello:
|
|
.byte 0x0D
|
|
.byte 0x0A
|
|
.ascii "A2P POWAflight"
|
|
.byte 0x0D
|
|
.byte 0x0A
|
|
.asciz ""
|
|
|
|
.align 5
|
|
msg_sram:
|
|
.ascii "SRAM OK."
|
|
.asciz ""
|
|
|
|
|
|
.align 5
|
|
msg_ddr_0:
|
|
.ascii "SDRAM TEST..."
|
|
.asciz ""
|
|
|
|
.align 5
|
|
.msg_ddr_1:
|
|
.ascii "SDRAM OK "
|
|
.ascii "@10000000:"
|
|
.asciz "17FFFFFF"
|
|
|
|
.align 5
|
|
.msg_rom:
|
|
.ascii "Copying"
|
|
.ascii " ROM to"
|
|
.asciz " RAM..."
|
|
|
|
.align 5
|
|
.msg_banner:
|
|
#.include "banner.s"
|
|
.ascii "Jumping to"
|
|
.asciz " main()..."
|
|
|
|
.set MSG_HELLO, 0
|
|
.set MSG_SRAM, MSG_HELLO+32
|
|
.set MSG_DDR_0, MSG_SRAM+32
|
|
.set MSG_DDR_1, MSG_DDR_0+32
|
|
.set MSG_ROM_INIT, MSG_DDR_1+32
|
|
.set MSG_BANNER, MSG_ROM_INIT+32
|
|
|