test3 - cpl hang in results save
openpowerwtf
2 years ago
parent
b79536e583
commit
7d5b53f672
@ -1,5 +1,15 @@
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# Kernel updates/build process
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* test1 - minimal updates to kernel; add linker script and build kernel and test separately
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### test1
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* 32b crosscompile
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* minimal updates to kernel; add linker script and build kernel and test separately
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* passed coco sim
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### test2
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* 32b crosscompile
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* update kernel for minimal setup and branch to bios C code; add linker script and build kernel and test separately
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* passed coco sim
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### test3
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* 32b crosscompile
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* add bios code to execute and check a .tst; link test.s
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@ -0,0 +1,297 @@
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# asmtst.tpl
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# powerpc-linux-gnu-as -c arcitst.s
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.include "defines.s"
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# -------------------------------------------------------------------------------------------------
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# c-accessible
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.global init_tst
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.global tst_start
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.global tst_end
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.global tst_inits
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.global tst_results
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.global tst_expects
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# -------------------------------------------------------------------------------------------------
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tst_misc:
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tst_info: .asciz "info text"
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tst_header: .asciz "header text"
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.set SAVESPR,sprg3
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.set MAGIC,0x8675309
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# -------------------------------------------------------------------------------------------------
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.align 5
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tst_inits:
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init_r0: .int 0x5EA9536C
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init_r1: .int 0x07EC9BA7
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init_r2: .int 0xFFFFFFFF
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init_r3: .int 0x18FAD811
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init_r4: .int 0xFFFFFFFF
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init_r5: .int 0xFFFFFFFF
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init_r6: .int 0xFFFFFFFF
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init_r7: .int 0xFFFFFFFF
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init_r8: .int 0xFFFFFFFF
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init_r9: .int 0xFFFFFFFF
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init_r10: .int 0xB186394A
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init_r11: .int 0x07EC9BA7
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init_r12: .int 0xFFFFFFFF
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init_r13: .int 0xFC9D07CE
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init_r14: .int 0x7305868F
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init_r15: .int 0xFFFFFFFF
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init_r16: .int 0xFFFFFFFF
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init_r17: .int 0x6E078D56
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init_r18: .int 0xFFFFFFFF
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init_r19: .int 0xFFFFFFFF
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init_r20: .int 0x0F8F2BB1
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init_r21: .int 0xFFFFFFFF
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init_r22: .int 0xFFFFFFFF
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init_r23: .int 0x9E47F6C0
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init_r24: .int 0x46B0FC81
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init_r25: .int 0xFFFFFFFF
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init_r26: .int 0xFFFFFFFF
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init_r27: .int 0x48026438
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init_r28: .int 0xEFB046E4
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init_r29: .int 0x4B5CBE25
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init_r30: .int 0xFFFFFFFF
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init_r31: .int 0xFFFFFFFF
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init_cr: .int 0xB0215BC8
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init_xer: .int 0xBFC0004B
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init_ctr: .int 0xF7DA2C8A
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init_lr: .int 0x8BC7C22B
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init_tar: .int 0xFFFFFFFF
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init_msr: .int 0x00001081
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init_iar: .int 0x00010000
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save_r1: .int 0
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codelen: .int 13
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ops: .int 0x36E86A7F,0x10748A7F,0x71AE9D7E,0x1C865B55,0xF45EAA7D,0x2000154D,0x50E01B7C,0x4933037B,0x00082B7D,0x36B8317C,0x00000060,0x00000060,0x00000060
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iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x0001001C,0x00010020,0x00010024,0x00010028,0x0001002C,0x00010030
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# -------------------------------------------------------------------------------------------------
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# r3=@tst_inits
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.align 5
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init_tst:
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# save c stuff
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stw r1,(save_r1-tst_inits)(r3)
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# copy ops
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opcopy:
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lwz r1,(codelen-tst_inits)(r3)
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mtctr r1
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opcopy_loop:
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la r1,(cops-tst_inits)(r3)
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la r2,(iars-tst_inits)(r3)
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stw r1,0(r2)
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addi r2,r2,4
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bdnz opcopy_loop
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# init test regs
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init_regs:
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lwz r1,(init_cr-tst_inits)(r3)
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mtcr r1
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lwz r1,(init_xer-tst_inits)(r3)
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mtxer r1
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lwz r1,(init_ctr-tst_inits)(r3)
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mtctr r1
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lwz r1,(init_lr-tst_inits)(r3)
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mtlr r1
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lwz r1,(init_tar-tst_inits)(r3)
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mtspr tar,r1
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lwz r0,(init_r0-tst_inits)(r3)
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lwz r1,(init_r1-tst_inits)(r3)
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lwz r2,(init_r2-tst_inits)(r3)
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lwz r4,(init_r4-tst_inits)(r3)
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lwz r5,(init_r5-tst_inits)(r3)
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lwz r6,(init_r6-tst_inits)(r3)
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lwz r7,(init_r7-tst_inits)(r3)
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lwz r8,(init_r8-tst_inits)(r3)
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lwz r9,(init_r9-tst_inits)(r3)
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lwz r10,(init_r10-tst_inits)(r3)
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lwz r11,(init_r11-tst_inits)(r3)
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lwz r12,(init_r12-tst_inits)(r3)
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lwz r13,(init_r13-tst_inits)(r3)
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lwz r14,(init_r14-tst_inits)(r3)
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lwz r15,(init_r15-tst_inits)(r3)
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lwz r16,(init_r16-tst_inits)(r3)
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lwz r17,(init_r17-tst_inits)(r3)
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lwz r18,(init_r18-tst_inits)(r3)
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lwz r19,(init_r19-tst_inits)(r3)
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lwz r20,(init_r20-tst_inits)(r3)
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lwz r21,(init_r21-tst_inits)(r3)
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lwz r22,(init_r22-tst_inits)(r3)
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lwz r23,(init_r23-tst_inits)(r3)
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lwz r24,(init_r24-tst_inits)(r3)
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lwz r25,(init_r25-tst_inits)(r3)
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lwz r26,(init_r26-tst_inits)(r3)
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lwz r27,(init_r27-tst_inits)(r3)
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lwz r28,(init_r28-tst_inits)(r3)
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lwz r29,(init_r29-tst_inits)(r3)
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lwz r30,(init_r30-tst_inits)(r3)
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lwz r31,(init_r31-tst_inits)(r3)
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lwz r3,(init_r3-tst_inits)(r3)
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jmp2tst: rfi
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# needs to be inserted into epilogue of tst!
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#tst_end:
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# b save_results
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# -------------------------------------------------------------------------------------------------
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.align 5
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save_results:
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# use a designated spr to save (sprgx, ...)
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mtspr SAVESPR,r1
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lis r1,tst_results@h
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ori r1,r1,tst_results@l
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stw r0,(rslt_r0-tst_results)(r1)
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stw r2,(rslt_r2-tst_results)(r1)
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stw r3,(rslt_r3-tst_results)(r1)
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stw r4,(rslt_r4-tst_results)(r1)
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stw r5,(rslt_r5-tst_results)(r1)
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stw r6,(rslt_r6-tst_results)(r1)
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stw r7,(rslt_r7-tst_results)(r1)
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stw r8,(rslt_r8-tst_results)(r1)
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stw r9,(rslt_r9-tst_results)(r1)
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stw r10,(rslt_r10-tst_results)(r1)
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stw r11,(rslt_r11-tst_results)(r1)
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stw r12,(rslt_r12-tst_results)(r1)
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stw r13,(rslt_r13-tst_results)(r1)
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stw r14,(rslt_r14-tst_results)(r1)
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stw r15,(rslt_r15-tst_results)(r1)
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stw r16,(rslt_r16-tst_results)(r1)
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stw r17,(rslt_r17-tst_results)(r1)
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stw r18,(rslt_r18-tst_results)(r1)
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stw r19,(rslt_r19-tst_results)(r1)
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stw r20,(rslt_r20-tst_results)(r1)
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stw r21,(rslt_r21-tst_results)(r1)
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stw r22,(rslt_r22-tst_results)(r1)
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stw r23,(rslt_r23-tst_results)(r1)
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stw r24,(rslt_r24-tst_results)(r1)
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stw r25,(rslt_r25-tst_results)(r1)
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stw r26,(rslt_r26-tst_results)(r1)
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stw r27,(rslt_r27-tst_results)(r1)
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stw r28,(rslt_r28-tst_results)(r1)
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stw r29,(rslt_r29-tst_results)(r1)
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stw r30,(rslt_r30-tst_results)(r1)
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stw r31,(rslt_r31-tst_results)(r1)
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mfspr r2,SAVESPR
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stw r2,(rslt_r1-tst_results)(r1)
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mfcr r2
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stw r2,(rslt_cr-tst_results)(r1)
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mfxer r2
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stw r2,(rslt_xer-tst_results)(r1)
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mfctr r2
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stw r2,(rslt_ctr-tst_results)(r1)
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mflr r2
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stw r2,(rslt_lr-tst_results)(r1)
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mfspr r2,tar
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stw r2,(rslt_tar-tst_results)(r1)
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tst_cleanup:
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# restore c stuff
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lis r3,tst_inits@h
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ori r3,r3,tst_inits@l
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lwz r1,(save_r1-tst_inits)(r3)
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lis r3,MAGIC@h
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ori r3,r3,MAGIC@l
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b tst_done
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# -------------------------------------------------------------------------------------------------
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.align 5
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tst_results:
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rslt_r0: .int 0xFFFFFFFF
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rslt_r1: .int 0xFFFFFFFF
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rslt_r2: .int 0xFFFFFFFF
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rslt_r3: .int 0xFFFFFFFF
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rslt_r4: .int 0xFFFFFFFF
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rslt_r5: .int 0xFFFFFFFF
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rslt_r6: .int 0xFFFFFFFF
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rslt_r7: .int 0xFFFFFFFF
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rslt_r8: .int 0xFFFFFFFF
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rslt_r9: .int 0xFFFFFFFF
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rslt_r10: .int 0xFFFFFFFF
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rslt_r11: .int 0xFFFFFFFF
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rslt_r12: .int 0xFFFFFFFF
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rslt_r13: .int 0xFFFFFFFF
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rslt_r14: .int 0xFFFFFFFF
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rslt_r15: .int 0xFFFFFFFF
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rslt_r16: .int 0xFFFFFFFF
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rslt_r17: .int 0xFFFFFFFF
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rslt_r18: .int 0xFFFFFFFF
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rslt_r19: .int 0xFFFFFFFF
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rslt_r20: .int 0xFFFFFFFF
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rslt_r21: .int 0xFFFFFFFF
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rslt_r22: .int 0xFFFFFFFF
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rslt_r23: .int 0xFFFFFFFF
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rslt_r24: .int 0xFFFFFFFF
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rslt_r25: .int 0xFFFFFFFF
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rslt_r26: .int 0xFFFFFFFF
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rslt_r27: .int 0xFFFFFFFF
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rslt_r28: .int 0xFFFFFFFF
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rslt_r29: .int 0xFFFFFFFF
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rslt_r30: .int 0xFFFFFFFF
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rslt_r31: .int 0xFFFFFFFF
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rslt_cr: .int 0xFFFFFFFF
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rslt_xer: .int 0xFFFFFFFF
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rslt_ctr: .int 0xFFFFFFFF
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rslt_lr: .int 0xFFFFFFFF
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rslt_tar: .int 0xFFFFFFFF
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# -------------------------------------------------------------------------------------------------
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.align 5
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tst_expects:
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expt_r0: .int 0x7305868F
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expt_r1: .int 0x07EC9BA7
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expt_r2: .int 0xFFFFFFFF
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expt_r3: .int 0xAC3F2040
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expt_r4: .int 0xFFFFFFFF
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expt_r5: .int 0xFFFFFFFF
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expt_r6: .int 0xFFFFFFFF
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expt_r7: .int 0xFFFFFFFF
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expt_r8: .int 0xFFFFFFFF
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expt_r9: .int 0xFFFFFFFF
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expt_r10: .int 0xE83E7000
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expt_r11: .int 0x07EC9BA7
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expt_r12: .int 0xFFFFFFFF
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expt_r13: .int 0xFC9D07CE
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expt_r14: .int 0x7305868F
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expt_r15: .int 0xFFFFFFFF
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expt_r16: .int 0xFFFFFFFF
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expt_r17: .int 0x00000000
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expt_r18: .int 0xFFFFFFFF
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expt_r19: .int 0xFFFFFFFF
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expt_r20: .int 0x0F8F2BB1
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expt_r21: .int 0xFFFFFFFF
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expt_r22: .int 0xFFFFFFFF
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expt_r23: .int 0x9E47F6C0
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expt_r24: .int 0x46B0FC81
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expt_r25: .int 0xFFFFFFFF
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expt_r26: .int 0xFFFFFFFF
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expt_r27: .int 0x00000000
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expt_r28: .int 0x7305868F
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expt_r29: .int 0x0000007C
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expt_r30: .int 0xFFFFFFFF
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expt_r31: .int 0xFFFFFFFF
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expt_cr: .int 0x90315BC8
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expt_xer: .int 0x82C0004B
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expt_ctr: .int 0xF7DA2C89
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expt_lr: .int 0x8BC7C22B
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expt_tar: .int 0xFFFFFFFF
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expt_msr: .int 0x00001081
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expt_iar: .int 0x00010038
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@ -0,0 +1,492 @@
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1 # asmtst.tpl
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2
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3 .include "defines.s"
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1 # © IBM Corp. 2020
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2 # Licensed under and subject to the terms of the CC-BY 4.0
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3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
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4 # Additional rights, including the right to physically implement a softcore
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5 # that is compliant with the required sections of the Power ISA
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6 # Specification, will be available at no cost via the OpenPOWER Foundation.
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7 # This README will be updated with additional information when OpenPOWER's
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8 # license is available.
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9
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10 #-----------------------------------------
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11 # Defines
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12 #-----------------------------------------
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13
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14 # Regs
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15
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16 .set r0, 0
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17 .set r1, 1
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18 .set r2, 2
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19 .set r3, 3
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20 .set r4, 4
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21 .set r5, 5
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22 .set r6, 6
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23 .set r7, 7
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24 .set r8, 8
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25 .set r9, 9
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26 .set r10,10
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27 .set r11,11
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28 .set r12,12
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29 .set r13,13
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30 .set r14,14
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31 .set r15,15
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32 .set r16,16
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33 .set r17,17
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34 .set r18,18
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35 .set r19,19
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36 .set r20,20
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37 .set r21,21
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38 .set r22,22
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39 .set r23,23
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40 .set r24,24
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41 .set r25,25
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42 .set r26,26
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43 .set r27,27
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44 .set r28,28
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45 .set r29,29
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46 .set r30,30
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47 .set r31,31
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48
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49 .set f0, 0
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50 .set f1, 1
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51 .set f2, 2
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52 .set f3, 3
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53 .set f4, 4
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54 .set f5, 5
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55 .set f6, 6
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56 .set f7, 7
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57 .set f8, 8
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58 .set f9, 9
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59 .set f10,10
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60 .set f11,11
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61 .set f12,12
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62 .set f13,13
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63 .set f14,14
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64 .set f15,15
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65 .set f16,16
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66 .set f17,17
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67 .set f18,18
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68 .set f19,19
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69 .set f20,20
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70 .set f21,21
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71 .set f22,22
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72 .set f23,23
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73 .set f24,24
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74 .set f25,25
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75 .set f26,26
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76 .set f27,27
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77 .set f28,28
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78 .set f29,29
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79 .set f30,30
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80 .set f31,31
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81
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82 .set cr0, 0
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83 .set cr1, 1
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84 .set cr2, 2
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85 .set cr3, 3
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86 .set cr4, 4
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87 .set cr5, 5
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88 .set cr6, 6
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89 .set cr7, 7
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90
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91 # SPR numbers
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92
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93 .set srr0, 26
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94 .set srr1, 27
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95 .set dar, 19
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96 .set dsisr, 18
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97 .set epcr, 307
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98 .set tar, 815
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99
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100 .set dbsr, 304
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101 .set dbcr0, 308
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102 .set dbcr1, 309
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103 .set dbcr2, 310
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104 .set dbcr3, 848
|
||||
105
|
||||
106 .set ivpr, 63
|
||||
107
|
||||
108 .set iucr0, 1011
|
||||
109 .set iucr1, 883
|
||||
110 .set iucr2, 884
|
||||
111
|
||||
112 .set iudbg0, 888
|
||||
113 .set iudbg1, 889
|
||||
114 .set iudbg2, 890
|
||||
115 .set iulfsr, 891
|
||||
116 .set iullcr, 892
|
||||
117
|
||||
118 .set mmucr0, 1020
|
||||
119 .set mmucr1, 1021
|
||||
120 .set mmucr2, 1022
|
||||
121 .set mmucr3, 1023
|
||||
122
|
||||
123 .set tb, 268
|
||||
124 .set tbl, 284
|
||||
125 .set tbh, 285
|
||||
126
|
||||
127 .set dec, 22
|
||||
128 .set udec, 550
|
||||
129 .set tsr, 336
|
||||
130 .set tcr, 340
|
||||
131
|
||||
132 .set xucr0, 1014
|
||||
133 .set xucr1, 851
|
||||
134 .set xucr2, 1016
|
||||
135 .set xucr3, 852
|
||||
136 .set xucr4, 853
|
||||
137
|
||||
138 .set tens, 438
|
||||
139 .set tenc, 439
|
||||
140 .set tensr, 437
|
||||
141
|
||||
142 .set pid, 48
|
||||
143 .set pir, 286
|
||||
144 .set pvr, 287
|
||||
145 .set tir, 446
|
||||
146
|
||||
147 #.set sprg0,
|
||||
148 #.set sprg1,
|
||||
149 #.set sprg2,
|
||||
150 .set sprg3, 259
|
||||
4
|
||||
5 # -------------------------------------------------------------------------------------------------
|
||||
6 # c-accessible
|
||||
7
|
||||
8 .global init_tst
|
||||
9 .global tst_start
|
||||
10 .global tst_end
|
||||
11 .global tst_inits
|
||||
12 .global tst_results
|
||||
13 .global tst_expects
|
||||
14
|
||||
15 # -------------------------------------------------------------------------------------------------
|
||||
16 tst_misc:
|
||||
17
|
||||
18 0000 696E666F tst_info: .asciz "info text"
|
||||
18 20746578
|
||||
18 7400
|
||||
19 000a 68656164 tst_header: .asciz "header text"
|
||||
19 65722074
|
||||
19 65787400
|
||||
20
|
||||
21 .set SAVESPR,tar
|
||||
22 .set MAGIC,0x8675309
|
||||
23
|
||||
24 # -------------------------------------------------------------------------------------------------
|
||||
25 0016 00000000 .align 5
|
||||
25 00000000
|
||||
25 0000
|
||||
26 tst_inits:
|
||||
27
|
||||
28 0020 00000000 init_r0: .int 0x00000000
|
||||
29 0024 5822C905 init_r1: .int 0x5822C905
|
||||
30 0028 FFFFFFFF init_r2: .int 0xFFFFFFFF
|
||||
31 002c 91B6D1A3 init_r3: .int 0x91B6D1A3
|
||||
32 0030 FFFFFFFF init_r4: .int 0xFFFFFFFF
|
||||
33 0034 FFFFFFFF init_r5: .int 0xFFFFFFFF
|
||||
34 0038 FFFFFFFF init_r6: .int 0xFFFFFFFF
|
||||
35 003c FFFFFFFF init_r7: .int 0xFFFFFFFF
|
||||
36 0040 FFFFFFFF init_r8: .int 0xFFFFFFFF
|
||||
37 0044 7E11EE88 init_r9: .int 0x7E11EE88
|
||||
38 0048 FFFFFFFF init_r10: .int 0xFFFFFFFF
|
||||
39 004c 7FFFFFFF init_r11: .int 0x7FFFFFFF
|
||||
40 0050 FFFFFFFF init_r12: .int 0xFFFFFFFF
|
||||
41 0054 FFFFFFFF init_r13: .int 0xFFFFFFFF
|
||||
42 0058 8C20BDE6 init_r14: .int 0x8C20BDE6
|
||||
43 005c FFFFFFFF init_r15: .int 0xFFFFFFFF
|
||||
44 0060 76D0DADF init_r16: .int 0x76D0DADF
|
||||
45 0064 15111F42 init_r17: .int 0x15111F42
|
||||
46 0068 FFFFFFFF init_r18: .int 0xFFFFFFFF
|
||||
47 006c 36108E50 init_r19: .int 0x36108E50
|
||||
48 0070 FFFFFFFF init_r20: .int 0xFFFFFFFF
|
||||
49 0074 FFFFFFFF init_r21: .int 0xFFFFFFFF
|
||||
50 0078 328A0CED init_r22: .int 0x328A0CED
|
||||
51 007c FFFFFFFF init_r23: .int 0xFFFFFFFF
|
||||
52 0080 FFFFFFFF init_r24: .int 0xFFFFFFFF
|
||||
53 0084 AF224C19 init_r25: .int 0xAF224C19
|
||||
54 0088 FFFFFFFF init_r26: .int 0xFFFFFFFF
|
||||
55 008c FFFFFFFF init_r27: .int 0xFFFFFFFF
|
||||
56 0090 D624B27A init_r28: .int 0xD624B27A
|
||||
57 0094 FFFFFFFF init_r29: .int 0xFFFFFFFF
|
||||
58 0098 FFFFFFFF init_r30: .int 0xFFFFFFFF
|
||||
59 009c FFFFFFFF init_r31: .int 0xFFFFFFFF
|
||||
60
|
||||
61 00a0 DBFD3628 init_cr: .int 0xDBFD3628
|
||||
62 00a4 89F0006E init_xer: .int 0x89F0006E
|
||||
63 00a8 FFFFFFFF init_ctr: .int 0xFFFFFFFF
|
||||
64 00ac FFFFFFFF init_lr: .int 0xFFFFFFFF
|
||||
65 00b0 FFFFFFFF init_tar: .int 0xFFFFFFFF
|
||||
66 00b4 00001104 init_msr: .int 0x00001104
|
||||
67
|
||||
68 00b8 00010000 init_iar: .int 0x00010000
|
||||
69
|
||||
70 00bc 00000000 save_r1: .int 0
|
||||
71
|
||||
72 00c0 0000000D codelen: .int 13
|
||||
73 00c4 7C61CC14 ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x
|
||||
73 7D230595
|
||||
73 7AC37392
|
||||
73 7E094C11
|
||||
73 7E1CB115
|
||||
74 00f8 00010000 iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x
|
||||
74 00010004
|
||||
74 00010008
|
||||
74 0001000C
|
||||
74 00010010
|
||||
75
|
||||
76 # -------------------------------------------------------------------------------------------------
|
||||
77 # r3=@tst_inits
|
||||
78 012c 48000014 .align 5
|
||||
78 60000000
|
||||
78 60000000
|
||||
78 60000000
|
||||
78 60000000
|
||||
79 init_tst:
|
||||
80
|
||||
81 # save c stuff
|
||||
82 0140 9023009C stw r1,(save_r1-tst_inits)(r3)
|
||||
83
|
||||
84 # copy ops
|
||||
85 opcopy:
|
||||
86 0144 802300A0 lwz r1,(codelen-tst_inits)(r3)
|
||||
87 0148 7C2903A6 mtctr r1
|
||||
88 014c 382300A4 la r1,(ops-tst_inits)(r3) # @ ops list
|
||||
89 0150 384300D8 la r2,(iars-tst_inits)(r3) # @ iars list
|
||||
90 opcopy_loop:
|
||||
91 0154 80810000 lwz r4,0(r1) # next op
|
||||
92 0158 80A20000 lwz r5,0(r2) # next iar
|
||||
93 015c 90850000 stw r4,0(r5) # store it
|
||||
94 0160 38210004 addi r1,r1,4 # inc to next
|
||||
95 0164 38420004 addi r2,r2,4
|
||||
96 0168 4200FFEC bdnz opcopy_loop
|
||||
97
|
||||
98 # add end of test op - could be done here or by builder
|
||||
99 # ways to end:
|
||||
100 # ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
|
||||
101 # trap,sc,scv - branch to tst_end in handler
|
||||
102 # attn, priv op, etc. - "
|
||||
103 # overwrite the last epilogue op to avoid any crossing
|
||||
104 opcopy_eot:
|
||||
105 016c 3C804800 lis r4,0x4800
|
||||
106 0170 60840006 ori r4,r4,0x0006 # ba 0x0004
|
||||
107 0174 90850000 stw r4,0(r5)
|
||||
108
|
||||
109 # get tst start
|
||||
110 0178 80200000 lwz r1,init_msr(r0)
|
||||
111 017c 7C3B03A6 mtsrr1 r1
|
||||
112 0180 80200000 lwz r1,iars(r0)
|
||||
113 0184 7C3A03A6 mtsrr0 r1
|
||||
114
|
||||
115 # init test regs
|
||||
116 init_regs:
|
||||
117 0188 80230080 lwz r1,(init_cr-tst_inits)(r3)
|
||||
118 018c 7C2FF120 mtcr r1
|
||||
119 0190 80230084 lwz r1,(init_xer-tst_inits)(r3)
|
||||
120 0194 7C2103A6 mtxer r1
|
||||
121 0198 80230088 lwz r1,(init_ctr-tst_inits)(r3)
|
||||
122 019c 7C2903A6 mtctr r1
|
||||
123 01a0 8023008C lwz r1,(init_lr-tst_inits)(r3)
|
||||
124 01a4 7C2803A6 mtlr r1
|
||||
125 01a8 80230090 lwz r1,(init_tar-tst_inits)(r3)
|
||||
126 01ac 7C2FCBA6 mtspr tar,r1
|
||||
127
|
||||
128 01b0 80030000 lwz r0,(init_r0-tst_inits)(r3)
|
||||
129 01b4 80230004 lwz r1,(init_r1-tst_inits)(r3)
|
||||
130 01b8 80430008 lwz r2,(init_r2-tst_inits)(r3)
|
||||
131 01bc 80830010 lwz r4,(init_r4-tst_inits)(r3)
|
||||
132 01c0 80A30014 lwz r5,(init_r5-tst_inits)(r3)
|
||||
133 01c4 80C30018 lwz r6,(init_r6-tst_inits)(r3)
|
||||
134 01c8 80E3001C lwz r7,(init_r7-tst_inits)(r3)
|
||||
135 01cc 81030020 lwz r8,(init_r8-tst_inits)(r3)
|
||||
136 01d0 81230024 lwz r9,(init_r9-tst_inits)(r3)
|
||||
137 01d4 81430028 lwz r10,(init_r10-tst_inits)(r3)
|
||||
138 01d8 8163002C lwz r11,(init_r11-tst_inits)(r3)
|
||||
139 01dc 81830030 lwz r12,(init_r12-tst_inits)(r3)
|
||||
140 01e0 81A30034 lwz r13,(init_r13-tst_inits)(r3)
|
||||
141 01e4 81C30038 lwz r14,(init_r14-tst_inits)(r3)
|
||||
142 01e8 81E3003C lwz r15,(init_r15-tst_inits)(r3)
|
||||
143 01ec 82030040 lwz r16,(init_r16-tst_inits)(r3)
|
||||
144 01f0 82230044 lwz r17,(init_r17-tst_inits)(r3)
|
||||
145 01f4 82430048 lwz r18,(init_r18-tst_inits)(r3)
|
||||
146 01f8 8263004C lwz r19,(init_r19-tst_inits)(r3)
|
||||
147 01fc 82830050 lwz r20,(init_r20-tst_inits)(r3)
|
||||
148 0200 82A30054 lwz r21,(init_r21-tst_inits)(r3)
|
||||
149 0204 82C30058 lwz r22,(init_r22-tst_inits)(r3)
|
||||
150 0208 82E3005C lwz r23,(init_r23-tst_inits)(r3)
|
||||
151 020c 83030060 lwz r24,(init_r24-tst_inits)(r3)
|
||||
152 0210 83230064 lwz r25,(init_r25-tst_inits)(r3)
|
||||
153 0214 83430068 lwz r26,(init_r26-tst_inits)(r3)
|
||||
154 0218 8363006C lwz r27,(init_r27-tst_inits)(r3)
|
||||
155 021c 83830070 lwz r28,(init_r28-tst_inits)(r3)
|
||||
156 0220 83A30074 lwz r29,(init_r29-tst_inits)(r3)
|
||||
157 0224 83C30078 lwz r30,(init_r30-tst_inits)(r3)
|
||||
158 0228 83E3007C lwz r31,(init_r31-tst_inits)(r3)
|
||||
159 022c 8063000C lwz r3,(init_r3-tst_inits)(r3)
|
||||
160
|
||||
161 jmp2tst:
|
||||
162 #rfi
|
||||
163 #rfid
|
||||
164 0230 48010002 ba 0x10000
|
||||
165
|
||||
166 tst_end:
|
||||
167 0234 4800000C b save_results
|
||||
168
|
||||
169 # -------------------------------------------------------------------------------------------------
|
||||
170 0238 60000000 .align 5
|
||||
170 60000000
|
||||
171 save_results:
|
||||
172 # use a designated spr to save (sprgx, ...)
|
||||
173 0240 7C2FCBA6 mtspr SAVESPR,r1
|
||||
174 0244 3C200000 lis r1,tst_results@h
|
||||
175 0248 60210000 ori r1,r1,tst_results@l
|
||||
176 024c 90010000 stw r0,(rslt_r0-tst_results)(r1)
|
||||
177 0250 90410008 stw r2,(rslt_r2-tst_results)(r1)
|
||||
178 0254 9061000C stw r3,(rslt_r3-tst_results)(r1)
|
||||
179 0258 90810010 stw r4,(rslt_r4-tst_results)(r1)
|
||||
180 025c 90A10014 stw r5,(rslt_r5-tst_results)(r1)
|
||||
181 0260 90C10018 stw r6,(rslt_r6-tst_results)(r1)
|
||||
182 0264 90E1001C stw r7,(rslt_r7-tst_results)(r1)
|
||||
183 0268 91010020 stw r8,(rslt_r8-tst_results)(r1)
|
||||
184 026c 91210024 stw r9,(rslt_r9-tst_results)(r1)
|
||||
185 0270 91410028 stw r10,(rslt_r10-tst_results)(r1)
|
||||
186 0274 9161002C stw r11,(rslt_r11-tst_results)(r1)
|
||||
187 0278 91810030 stw r12,(rslt_r12-tst_results)(r1)
|
||||
188 027c 91A10034 stw r13,(rslt_r13-tst_results)(r1)
|
||||
189 0280 91C10038 stw r14,(rslt_r14-tst_results)(r1)
|
||||
190 0284 91E1003C stw r15,(rslt_r15-tst_results)(r1)
|
||||
191 0288 92010040 stw r16,(rslt_r16-tst_results)(r1)
|
||||
192 028c 92210044 stw r17,(rslt_r17-tst_results)(r1)
|
||||
193 0290 92410048 stw r18,(rslt_r18-tst_results)(r1)
|
||||
194 0294 9261004C stw r19,(rslt_r19-tst_results)(r1)
|
||||
195 0298 92810050 stw r20,(rslt_r20-tst_results)(r1)
|
||||
196 029c 92A10054 stw r21,(rslt_r21-tst_results)(r1)
|
||||
197 02a0 92C10058 stw r22,(rslt_r22-tst_results)(r1)
|
||||
198 02a4 92E1005C stw r23,(rslt_r23-tst_results)(r1)
|
||||
199 02a8 93010060 stw r24,(rslt_r24-tst_results)(r1)
|
||||
200 02ac 93210064 stw r25,(rslt_r25-tst_results)(r1)
|
||||
201 02b0 93410068 stw r26,(rslt_r26-tst_results)(r1)
|
||||
202 02b4 9361006C stw r27,(rslt_r27-tst_results)(r1)
|
||||
203 02b8 93810070 stw r28,(rslt_r28-tst_results)(r1)
|
||||
204 02bc 93A10074 stw r29,(rslt_r29-tst_results)(r1)
|
||||
205 02c0 93C10078 stw r30,(rslt_r30-tst_results)(r1)
|
||||
206 02c4 93E1007C stw r31,(rslt_r31-tst_results)(r1)
|
||||
207 02c8 7C4FCAA6 mfspr r2,SAVESPR
|
||||
208 02cc 90410004 stw r2,(rslt_r1-tst_results)(r1)
|
||||
209 02d0 7C400026 mfcr r2
|
||||
210 02d4 90410080 stw r2,(rslt_cr-tst_results)(r1)
|
||||
211 02d8 7C4102A6 mfxer r2
|
||||
212 02dc 90410084 stw r2,(rslt_xer-tst_results)(r1)
|
||||
213 02e0 7C4902A6 mfctr r2
|
||||
214 02e4 90410088 stw r2,(rslt_ctr-tst_results)(r1)
|
||||
215 02e8 7C4802A6 mflr r2
|
||||
216 02ec 9041008C stw r2,(rslt_lr-tst_results)(r1)
|
||||
217 02f0 7C4FCAA6 mfspr r2,tar
|
||||
218 02f4 90410090 stw r2,(rslt_tar-tst_results)(r1)
|
||||
219
|
||||
220 tst_cleanup:
|
||||
221 # restore c stuff
|
||||
222 02f8 3C600000 lis r3,tst_inits@h
|
||||
223 02fc 60630000 ori r3,r3,tst_inits@l
|
||||
224 0300 8023009C lwz r1,(save_r1-tst_inits)(r3)
|
||||
225 0304 3C600867 lis r3,MAGIC@h
|
||||
226 0308 60635309 ori r3,r3,MAGIC@l
|
||||
227
|
||||
228 030c 48000000 b tst_done
|
||||
229
|
||||
230 # -------------------------------------------------------------------------------------------------
|
||||
231 0310 60000000 .align 5
|
||||
231 60000000
|
||||
231 60000000
|
||||
231 60000000
|
||||
232 tst_results:
|
||||
233
|
||||
234 0320 FFFFFFFF rslt_r0: .int 0xFFFFFFFF
|
||||
235 0324 FFFFFFFF rslt_r1: .int 0xFFFFFFFF
|
||||
236 0328 FFFFFFFF rslt_r2: .int 0xFFFFFFFF
|
||||
237 032c FFFFFFFF rslt_r3: .int 0xFFFFFFFF
|
||||
238 0330 FFFFFFFF rslt_r4: .int 0xFFFFFFFF
|
||||
239 0334 FFFFFFFF rslt_r5: .int 0xFFFFFFFF
|
||||
240 0338 FFFFFFFF rslt_r6: .int 0xFFFFFFFF
|
||||
241 033c FFFFFFFF rslt_r7: .int 0xFFFFFFFF
|
||||
242 0340 FFFFFFFF rslt_r8: .int 0xFFFFFFFF
|
||||
243 0344 FFFFFFFF rslt_r9: .int 0xFFFFFFFF
|
||||
244 0348 FFFFFFFF rslt_r10: .int 0xFFFFFFFF
|
||||
245 034c FFFFFFFF rslt_r11: .int 0xFFFFFFFF
|
||||
246 0350 FFFFFFFF rslt_r12: .int 0xFFFFFFFF
|
||||
247 0354 FFFFFFFF rslt_r13: .int 0xFFFFFFFF
|
||||
248 0358 FFFFFFFF rslt_r14: .int 0xFFFFFFFF
|
||||
249 035c FFFFFFFF rslt_r15: .int 0xFFFFFFFF
|
||||
250 0360 FFFFFFFF rslt_r16: .int 0xFFFFFFFF
|
||||
251 0364 FFFFFFFF rslt_r17: .int 0xFFFFFFFF
|
||||
252 0368 FFFFFFFF rslt_r18: .int 0xFFFFFFFF
|
||||
253 036c FFFFFFFF rslt_r19: .int 0xFFFFFFFF
|
||||
254 0370 FFFFFFFF rslt_r20: .int 0xFFFFFFFF
|
||||
255 0374 FFFFFFFF rslt_r21: .int 0xFFFFFFFF
|
||||
256 0378 FFFFFFFF rslt_r22: .int 0xFFFFFFFF
|
||||
257 037c FFFFFFFF rslt_r23: .int 0xFFFFFFFF
|
||||
258 0380 FFFFFFFF rslt_r24: .int 0xFFFFFFFF
|
||||
259 0384 FFFFFFFF rslt_r25: .int 0xFFFFFFFF
|
||||
260 0388 FFFFFFFF rslt_r26: .int 0xFFFFFFFF
|
||||
261 038c FFFFFFFF rslt_r27: .int 0xFFFFFFFF
|
||||
262 0390 FFFFFFFF rslt_r28: .int 0xFFFFFFFF
|
||||
263 0394 FFFFFFFF rslt_r29: .int 0xFFFFFFFF
|
||||
264 0398 FFFFFFFF rslt_r30: .int 0xFFFFFFFF
|
||||
265 039c FFFFFFFF rslt_r31: .int 0xFFFFFFFF
|
||||
266
|
||||
267 03a0 FFFFFFFF rslt_cr: .int 0xFFFFFFFF
|
||||
268 03a4 FFFFFFFF rslt_xer: .int 0xFFFFFFFF
|
||||
269 03a8 FFFFFFFF rslt_ctr: .int 0xFFFFFFFF
|
||||
270 03ac FFFFFFFF rslt_lr: .int 0xFFFFFFFF
|
||||
271 03b0 FFFFFFFF rslt_tar: .int 0xFFFFFFFF
|
||||
272
|
||||
273 # -------------------------------------------------------------------------------------------------
|
||||
274 03b4 60000000 .align 5
|
||||
274 60000000
|
||||
274 60000000
|
||||
275 tst_expects:
|
||||
276
|
||||
277 03c0 00000000 expt_r0: .int 0x00000000
|
||||
278 03c4 CD75F313 expt_r1: .int 0xCD75F313
|
||||
279 03c8 FFFFFFFF expt_r2: .int 0xFFFFFFFF
|
||||
280 03cc 00000000 expt_r3: .int 0x00000000
|
||||
281 03d0 FFFFFFFF expt_r4: .int 0xFFFFFFFF
|
||||
282 03d4 FFFFFFFF expt_r5: .int 0xFFFFFFFF
|
||||
283 03d8 FFFFFFFF expt_r6: .int 0xFFFFFFFF
|
||||
284 03dc FFFFFFFF expt_r7: .int 0xFFFFFFFF
|
||||
285 03e0 FFFFFFFF expt_r8: .int 0xFFFFFFFF
|
||||
286 03e4 008A0C68 expt_r9: .int 0x008A0C68
|
||||
287 03e8 FFFFFFFF expt_r10: .int 0xFFFFFFFF
|
||||
288 03ec 7FFFFFFF expt_r11: .int 0x7FFFFFFF
|
||||
289 03f0 FFFFFFFF expt_r12: .int 0xFFFFFFFF
|
||||
290 03f4 FFFFFFFF expt_r13: .int 0xFFFFFFFF
|
||||
291 03f8 8C20BDE6 expt_r14: .int 0x8C20BDE6
|
||||
292 03fc FFFFFFFF expt_r15: .int 0xFFFFFFFF
|
||||
293 0400 08AEBF68 expt_r16: .int 0x08AEBF68
|
||||
294 0404 80000001 expt_r17: .int 0x80000001
|
||||
295 0408 FFFFFFFF expt_r18: .int 0xFFFFFFFF
|
||||
296 040c 00000000 expt_r19: .int 0x00000000
|
||||
297 0410 FFFFFFFF expt_r20: .int 0xFFFFFFFF
|
||||
298 0414 FFFFFFFF expt_r21: .int 0xFFFFFFFF
|
||||
299 0418 328A0CED expt_r22: .int 0x328A0CED
|
||||
300 041c FFFFFFFF expt_r23: .int 0xFFFFFFFF
|
||||
301 0420 FFFFFFFF expt_r24: .int 0xFFFFFFFF
|
||||
302 0424 AF224C19 expt_r25: .int 0xAF224C19
|
||||
303 0428 FFFFFFFF expt_r26: .int 0xFFFFFFFF
|
||||
304 042c FFFFFFFF expt_r27: .int 0xFFFFFFFF
|
||||
305 0430 D624B27A expt_r28: .int 0xD624B27A
|
||||
306 0434 FFFFFFFF expt_r29: .int 0xFFFFFFFF
|
||||
307 0438 FFFFFFFF expt_r30: .int 0xFFFFFFFF
|
||||
308 043c FFFFFFFF expt_r31: .int 0xFFFFFFFF
|
||||
309
|
||||
310 0440 9BFD3628 expt_cr: .int 0x9BFD3628
|
||||
311 0444 98F0006E expt_xer: .int 0x98F0006E
|
||||
312 0448 FFFFFFFF expt_ctr: .int 0xFFFFFFFF
|
||||
313 044c FFFFFFFF expt_lr: .int 0xFFFFFFFF
|
||||
314 0450 FFFFFFFF expt_tar: .int 0xFFFFFFFF
|
||||
315 0454 00001104 expt_msr: .int 0x00001104
|
||||
316
|
||||
317 0458 00010038 expt_iar: .int 0x00010038
|
||||
318
|
||||
Binary file not shown.
@ -0,0 +1,318 @@
|
||||
# asmtst.tpl
|
||||
|
||||
.include "defines.s"
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
# c-accessible
|
||||
|
||||
.global init_tst
|
||||
.global tst_start
|
||||
.global tst_end
|
||||
.global tst_inits
|
||||
.global tst_results
|
||||
.global tst_expects
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
tst_misc:
|
||||
|
||||
tst_info: .asciz "info text"
|
||||
tst_header: .asciz "header text"
|
||||
|
||||
.set SAVESPR,tar
|
||||
.set MAGIC,0x8675309
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_inits:
|
||||
|
||||
init_r0: .int 0x00000000
|
||||
init_r1: .int 0x5822C905
|
||||
init_r2: .int 0xFFFFFFFF
|
||||
init_r3: .int 0x91B6D1A3
|
||||
init_r4: .int 0xFFFFFFFF
|
||||
init_r5: .int 0xFFFFFFFF
|
||||
init_r6: .int 0xFFFFFFFF
|
||||
init_r7: .int 0xFFFFFFFF
|
||||
init_r8: .int 0xFFFFFFFF
|
||||
init_r9: .int 0x7E11EE88
|
||||
init_r10: .int 0xFFFFFFFF
|
||||
init_r11: .int 0x7FFFFFFF
|
||||
init_r12: .int 0xFFFFFFFF
|
||||
init_r13: .int 0xFFFFFFFF
|
||||
init_r14: .int 0x8C20BDE6
|
||||
init_r15: .int 0xFFFFFFFF
|
||||
init_r16: .int 0x76D0DADF
|
||||
init_r17: .int 0x15111F42
|
||||
init_r18: .int 0xFFFFFFFF
|
||||
init_r19: .int 0x36108E50
|
||||
init_r20: .int 0xFFFFFFFF
|
||||
init_r21: .int 0xFFFFFFFF
|
||||
init_r22: .int 0x328A0CED
|
||||
init_r23: .int 0xFFFFFFFF
|
||||
init_r24: .int 0xFFFFFFFF
|
||||
init_r25: .int 0xAF224C19
|
||||
init_r26: .int 0xFFFFFFFF
|
||||
init_r27: .int 0xFFFFFFFF
|
||||
init_r28: .int 0xD624B27A
|
||||
init_r29: .int 0xFFFFFFFF
|
||||
init_r30: .int 0xFFFFFFFF
|
||||
init_r31: .int 0xFFFFFFFF
|
||||
|
||||
init_cr: .int 0xDBFD3628
|
||||
init_xer: .int 0x89F0006E
|
||||
init_ctr: .int 0xFFFFFFFF
|
||||
init_lr: .int 0xFFFFFFFF
|
||||
init_tar: .int 0xFFFFFFFF
|
||||
init_msr: .int 0x00001104
|
||||
|
||||
init_iar: .int 0x00010000
|
||||
|
||||
save_r1: .int 0
|
||||
|
||||
codelen: .int 13
|
||||
ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x7E09B038,0x7C360591,0x7E2B00D1,0x60000000,0x60000000,0x60000000
|
||||
iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x0001001C,0x00010020,0x00010024,0x00010028,0x0001002C,0x00010030
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
# r3=@tst_inits
|
||||
.align 5
|
||||
init_tst:
|
||||
|
||||
# save c stuff
|
||||
stw r1,(save_r1-tst_inits)(r3)
|
||||
|
||||
# copy ops
|
||||
opcopy:
|
||||
lwz r1,(codelen-tst_inits)(r3)
|
||||
mtctr r1
|
||||
la r1,(ops-tst_inits)(r3) # @ ops list
|
||||
la r2,(iars-tst_inits)(r3) # @ iars list
|
||||
opcopy_loop:
|
||||
lwz r4,0(r1) # next op
|
||||
lwz r5,0(r2) # next iar
|
||||
stw r4,0(r5) # store it
|
||||
addi r1,r1,4 # inc to next
|
||||
addi r2,r2,4
|
||||
bdnz opcopy_loop
|
||||
|
||||
# add end of test op - could be done here or by builder
|
||||
# ways to end:
|
||||
# ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
|
||||
# trap,sc,scv - branch to tst_end in handler
|
||||
# attn, priv op, etc. - "
|
||||
# overwrite the last epilogue op to avoid any crossing
|
||||
opcopy_eot:
|
||||
lis r4,0x4800
|
||||
ori r4,r4,0x0006 # ba 0x0004
|
||||
stw r4,0(r5)
|
||||
|
||||
# get tst start
|
||||
lwz r1,init_msr(r0)
|
||||
mtsrr1 r1
|
||||
lwz r1,iars(r0)
|
||||
mtsrr0 r1
|
||||
|
||||
# init test regs
|
||||
init_regs:
|
||||
lwz r1,(init_cr-tst_inits)(r3)
|
||||
mtcr r1
|
||||
lwz r1,(init_xer-tst_inits)(r3)
|
||||
mtxer r1
|
||||
lwz r1,(init_ctr-tst_inits)(r3)
|
||||
mtctr r1
|
||||
lwz r1,(init_lr-tst_inits)(r3)
|
||||
mtlr r1
|
||||
lwz r1,(init_tar-tst_inits)(r3)
|
||||
mtspr tar,r1
|
||||
|
||||
lwz r0,(init_r0-tst_inits)(r3)
|
||||
lwz r1,(init_r1-tst_inits)(r3)
|
||||
lwz r2,(init_r2-tst_inits)(r3)
|
||||
lwz r4,(init_r4-tst_inits)(r3)
|
||||
lwz r5,(init_r5-tst_inits)(r3)
|
||||
lwz r6,(init_r6-tst_inits)(r3)
|
||||
lwz r7,(init_r7-tst_inits)(r3)
|
||||
lwz r8,(init_r8-tst_inits)(r3)
|
||||
lwz r9,(init_r9-tst_inits)(r3)
|
||||
lwz r10,(init_r10-tst_inits)(r3)
|
||||
lwz r11,(init_r11-tst_inits)(r3)
|
||||
lwz r12,(init_r12-tst_inits)(r3)
|
||||
lwz r13,(init_r13-tst_inits)(r3)
|
||||
lwz r14,(init_r14-tst_inits)(r3)
|
||||
lwz r15,(init_r15-tst_inits)(r3)
|
||||
lwz r16,(init_r16-tst_inits)(r3)
|
||||
lwz r17,(init_r17-tst_inits)(r3)
|
||||
lwz r18,(init_r18-tst_inits)(r3)
|
||||
lwz r19,(init_r19-tst_inits)(r3)
|
||||
lwz r20,(init_r20-tst_inits)(r3)
|
||||
lwz r21,(init_r21-tst_inits)(r3)
|
||||
lwz r22,(init_r22-tst_inits)(r3)
|
||||
lwz r23,(init_r23-tst_inits)(r3)
|
||||
lwz r24,(init_r24-tst_inits)(r3)
|
||||
lwz r25,(init_r25-tst_inits)(r3)
|
||||
lwz r26,(init_r26-tst_inits)(r3)
|
||||
lwz r27,(init_r27-tst_inits)(r3)
|
||||
lwz r28,(init_r28-tst_inits)(r3)
|
||||
lwz r29,(init_r29-tst_inits)(r3)
|
||||
lwz r30,(init_r30-tst_inits)(r3)
|
||||
lwz r31,(init_r31-tst_inits)(r3)
|
||||
lwz r3,(init_r3-tst_inits)(r3)
|
||||
|
||||
jmp2tst:
|
||||
#rfi
|
||||
#rfid
|
||||
ba 0x10000
|
||||
|
||||
tst_end:
|
||||
b save_results
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
save_results:
|
||||
# use a designated spr to save (sprgx, ...)
|
||||
mtspr SAVESPR,r1
|
||||
lis r1,tst_results@h
|
||||
ori r1,r1,tst_results@l
|
||||
stw r0,(rslt_r0-tst_results)(r1)
|
||||
stw r2,(rslt_r2-tst_results)(r1)
|
||||
stw r3,(rslt_r3-tst_results)(r1)
|
||||
stw r4,(rslt_r4-tst_results)(r1)
|
||||
stw r5,(rslt_r5-tst_results)(r1)
|
||||
stw r6,(rslt_r6-tst_results)(r1)
|
||||
stw r7,(rslt_r7-tst_results)(r1)
|
||||
stw r8,(rslt_r8-tst_results)(r1)
|
||||
stw r9,(rslt_r9-tst_results)(r1)
|
||||
stw r10,(rslt_r10-tst_results)(r1)
|
||||
stw r11,(rslt_r11-tst_results)(r1)
|
||||
stw r12,(rslt_r12-tst_results)(r1)
|
||||
stw r13,(rslt_r13-tst_results)(r1)
|
||||
stw r14,(rslt_r14-tst_results)(r1)
|
||||
stw r15,(rslt_r15-tst_results)(r1)
|
||||
stw r16,(rslt_r16-tst_results)(r1)
|
||||
stw r17,(rslt_r17-tst_results)(r1)
|
||||
stw r18,(rslt_r18-tst_results)(r1)
|
||||
stw r19,(rslt_r19-tst_results)(r1)
|
||||
stw r20,(rslt_r20-tst_results)(r1)
|
||||
stw r21,(rslt_r21-tst_results)(r1)
|
||||
stw r22,(rslt_r22-tst_results)(r1)
|
||||
stw r23,(rslt_r23-tst_results)(r1)
|
||||
stw r24,(rslt_r24-tst_results)(r1)
|
||||
stw r25,(rslt_r25-tst_results)(r1)
|
||||
stw r26,(rslt_r26-tst_results)(r1)
|
||||
stw r27,(rslt_r27-tst_results)(r1)
|
||||
stw r28,(rslt_r28-tst_results)(r1)
|
||||
stw r29,(rslt_r29-tst_results)(r1)
|
||||
stw r30,(rslt_r30-tst_results)(r1)
|
||||
stw r31,(rslt_r31-tst_results)(r1)
|
||||
mfspr r2,SAVESPR
|
||||
stw r2,(rslt_r1-tst_results)(r1)
|
||||
mfcr r2
|
||||
stw r2,(rslt_cr-tst_results)(r1)
|
||||
mfxer r2
|
||||
stw r2,(rslt_xer-tst_results)(r1)
|
||||
mfctr r2
|
||||
stw r2,(rslt_ctr-tst_results)(r1)
|
||||
mflr r2
|
||||
stw r2,(rslt_lr-tst_results)(r1)
|
||||
mfspr r2,tar
|
||||
stw r2,(rslt_tar-tst_results)(r1)
|
||||
|
||||
tst_cleanup:
|
||||
# restore c stuff
|
||||
lis r3,tst_inits@h
|
||||
ori r3,r3,tst_inits@l
|
||||
lwz r1,(save_r1-tst_inits)(r3)
|
||||
lis r3,MAGIC@h
|
||||
ori r3,r3,MAGIC@l
|
||||
|
||||
b tst_done
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_results:
|
||||
|
||||
rslt_r0: .int 0xFFFFFFFF
|
||||
rslt_r1: .int 0xFFFFFFFF
|
||||
rslt_r2: .int 0xFFFFFFFF
|
||||
rslt_r3: .int 0xFFFFFFFF
|
||||
rslt_r4: .int 0xFFFFFFFF
|
||||
rslt_r5: .int 0xFFFFFFFF
|
||||
rslt_r6: .int 0xFFFFFFFF
|
||||
rslt_r7: .int 0xFFFFFFFF
|
||||
rslt_r8: .int 0xFFFFFFFF
|
||||
rslt_r9: .int 0xFFFFFFFF
|
||||
rslt_r10: .int 0xFFFFFFFF
|
||||
rslt_r11: .int 0xFFFFFFFF
|
||||
rslt_r12: .int 0xFFFFFFFF
|
||||
rslt_r13: .int 0xFFFFFFFF
|
||||
rslt_r14: .int 0xFFFFFFFF
|
||||
rslt_r15: .int 0xFFFFFFFF
|
||||
rslt_r16: .int 0xFFFFFFFF
|
||||
rslt_r17: .int 0xFFFFFFFF
|
||||
rslt_r18: .int 0xFFFFFFFF
|
||||
rslt_r19: .int 0xFFFFFFFF
|
||||
rslt_r20: .int 0xFFFFFFFF
|
||||
rslt_r21: .int 0xFFFFFFFF
|
||||
rslt_r22: .int 0xFFFFFFFF
|
||||
rslt_r23: .int 0xFFFFFFFF
|
||||
rslt_r24: .int 0xFFFFFFFF
|
||||
rslt_r25: .int 0xFFFFFFFF
|
||||
rslt_r26: .int 0xFFFFFFFF
|
||||
rslt_r27: .int 0xFFFFFFFF
|
||||
rslt_r28: .int 0xFFFFFFFF
|
||||
rslt_r29: .int 0xFFFFFFFF
|
||||
rslt_r30: .int 0xFFFFFFFF
|
||||
rslt_r31: .int 0xFFFFFFFF
|
||||
|
||||
rslt_cr: .int 0xFFFFFFFF
|
||||
rslt_xer: .int 0xFFFFFFFF
|
||||
rslt_ctr: .int 0xFFFFFFFF
|
||||
rslt_lr: .int 0xFFFFFFFF
|
||||
rslt_tar: .int 0xFFFFFFFF
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_expects:
|
||||
|
||||
expt_r0: .int 0x00000000
|
||||
expt_r1: .int 0xCD75F313
|
||||
expt_r2: .int 0xFFFFFFFF
|
||||
expt_r3: .int 0x00000000
|
||||
expt_r4: .int 0xFFFFFFFF
|
||||
expt_r5: .int 0xFFFFFFFF
|
||||
expt_r6: .int 0xFFFFFFFF
|
||||
expt_r7: .int 0xFFFFFFFF
|
||||
expt_r8: .int 0xFFFFFFFF
|
||||
expt_r9: .int 0x008A0C68
|
||||
expt_r10: .int 0xFFFFFFFF
|
||||
expt_r11: .int 0x7FFFFFFF
|
||||
expt_r12: .int 0xFFFFFFFF
|
||||
expt_r13: .int 0xFFFFFFFF
|
||||
expt_r14: .int 0x8C20BDE6
|
||||
expt_r15: .int 0xFFFFFFFF
|
||||
expt_r16: .int 0x08AEBF68
|
||||
expt_r17: .int 0x80000001
|
||||
expt_r18: .int 0xFFFFFFFF
|
||||
expt_r19: .int 0x00000000
|
||||
expt_r20: .int 0xFFFFFFFF
|
||||
expt_r21: .int 0xFFFFFFFF
|
||||
expt_r22: .int 0x328A0CED
|
||||
expt_r23: .int 0xFFFFFFFF
|
||||
expt_r24: .int 0xFFFFFFFF
|
||||
expt_r25: .int 0xAF224C19
|
||||
expt_r26: .int 0xFFFFFFFF
|
||||
expt_r27: .int 0xFFFFFFFF
|
||||
expt_r28: .int 0xD624B27A
|
||||
expt_r29: .int 0xFFFFFFFF
|
||||
expt_r30: .int 0xFFFFFFFF
|
||||
expt_r31: .int 0xFFFFFFFF
|
||||
|
||||
expt_cr: .int 0x9BFD3628
|
||||
expt_xer: .int 0x98F0006E
|
||||
expt_ctr: .int 0xFFFFFFFF
|
||||
expt_lr: .int 0xFFFFFFFF
|
||||
expt_tar: .int 0xFFFFFFFF
|
||||
expt_msr: .int 0x00001104
|
||||
|
||||
expt_iar: .int 0x00010038
|
||||
|
||||
@ -0,0 +1 @@
|
||||
../bin
|
||||
@ -0,0 +1,121 @@
|
||||
#include <stdint.h>
|
||||
|
||||
#include "bios.h"
|
||||
|
||||
// arci stuff1
|
||||
void tst_done(unsigned int rc);
|
||||
unsigned int checkResult(unsigned int r, char* name);
|
||||
// shouldn't need any of these if i use the .o from bios build???
|
||||
//#include "generated/soc.h"
|
||||
extern unsigned int tst_start;
|
||||
extern unsigned int tst_end;
|
||||
extern unsigned int tst_inits;
|
||||
extern unsigned int tst_results;
|
||||
extern unsigned int tst_expects;
|
||||
|
||||
|
||||
int main(int tid) {
|
||||
int *p;
|
||||
int *fdata = _fdata;
|
||||
unsigned int *inits = &tst_inits;
|
||||
|
||||
if (tid != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// r/w memory init
|
||||
|
||||
// copy
|
||||
for (p = _fdata_rom; p < _edata_rom; p++){
|
||||
*(fdata++) = *p;
|
||||
}
|
||||
// zero
|
||||
for (p = _fbss; p < _ebss; p++) {
|
||||
*_fbss = 0;
|
||||
}
|
||||
|
||||
// core init
|
||||
set_epcr(0x03000000); // icm=gicm=1
|
||||
set_dec(0);
|
||||
set_tbh(0);
|
||||
set_tbl(0);
|
||||
set_tsr(0xFE000000); // mask: clear enw,wis,wrs,dis,fis,udis
|
||||
set_xucr0(get_xucr0() & 0x00000200); // set tcs=0
|
||||
set_tsr(0);
|
||||
set_tcr(0); // disable all timers
|
||||
|
||||
// thread enable
|
||||
// set_tens(0x3);
|
||||
|
||||
// run a .tst
|
||||
// danger! once r1 is whacked, any c code like bad int handler, etc. needs
|
||||
// to make sure it has a safe stack for calls
|
||||
asm (
|
||||
"mr 3,%0\n"
|
||||
//"lis 4,init_tst@h\n"
|
||||
//"ori 4,4,init_tst@l\n"
|
||||
//"mtctr 4\n"
|
||||
//"bcctr\n"
|
||||
"b init_tst\n"
|
||||
: // outputs
|
||||
: "r"(inits) // inputs
|
||||
: "r3" // clobbers
|
||||
);
|
||||
|
||||
while(1) {}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define MAGIC 0x08675309
|
||||
|
||||
//void __attribute__((noreturn)) tst_done(unsigned int rc) {
|
||||
void tst_done(unsigned int rc) {
|
||||
unsigned int i, ok = 1, done = 0;
|
||||
/*
|
||||
char c;
|
||||
char name[10];
|
||||
unsigned int r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;
|
||||
unsigned int cr, xer, ctr, lr, tar;
|
||||
unsigned int op, *cia;
|
||||
*/
|
||||
|
||||
if (rc != MAGIC) {
|
||||
ok = 0;
|
||||
}
|
||||
|
||||
// ops
|
||||
|
||||
// cr, xer, ctr, lr, tar
|
||||
ok = ok && checkResult(32, "CR");
|
||||
ok = ok && checkResult(33, "XER");
|
||||
ok = ok && checkResult(34, "CTR");
|
||||
ok = ok && checkResult(35, "LR");
|
||||
ok = ok && checkResult(36, "TAR");
|
||||
}
|
||||
|
||||
unsigned int checkResult(unsigned int r, char* name) {
|
||||
unsigned int init, act, exp, ok = 1;
|
||||
|
||||
init = *(&tst_inits + r);
|
||||
act = *(&tst_results + r);
|
||||
exp = *(&tst_expects + r);
|
||||
|
||||
ok = act != exp;
|
||||
|
||||
return ok;
|
||||
}
|
||||
|
||||
// these are branched to!
|
||||
void int_sc(int code, int srr0) {
|
||||
asm (
|
||||
"b tst_end\n"
|
||||
: // outputs
|
||||
: // inputs
|
||||
: // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
void int_unhandled(void) {
|
||||
while(1) {}
|
||||
}
|
||||
@ -0,0 +1,123 @@
|
||||
#ifndef BIOS_H
|
||||
|
||||
#define BIOS_H
|
||||
|
||||
extern int *_fdata_rom;
|
||||
extern int *_edata_rom;
|
||||
extern int *_fdata;
|
||||
extern int *_fbss;
|
||||
extern int *_ebss;
|
||||
|
||||
void int_sc(int code, int srr0);
|
||||
void int_unhandled(void);
|
||||
|
||||
inline void set_epcr(int v) __attribute__((always_inline));
|
||||
inline void set_dec(int v) __attribute__((always_inline));
|
||||
inline void set_tbh(int v) __attribute__((always_inline));
|
||||
inline void set_tbl(int v) __attribute__((always_inline));
|
||||
inline void set_tsr(int v) __attribute__((always_inline));
|
||||
inline void set_tcr(int v) __attribute__((always_inline));
|
||||
inline void set_tens(int v) __attribute__((always_inline));
|
||||
inline void set_xucr0(int v) __attribute__((always_inline));
|
||||
inline int get_xucr0(void) __attribute__((always_inline));
|
||||
|
||||
inline void set_epcr(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 307,4\n" // epcr
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_dec(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 22,4\n" // dec
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tbh(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 285,4\n" // tbh
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tbl(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 284,4\n" // tbl
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tsr(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 336,4\n" // tsr
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tcr(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 340,4\n" // tcr
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline int get_xucr0(void) {
|
||||
int v;
|
||||
asm volatile(
|
||||
"mfspr %0,1014\n" // xucr0
|
||||
: "=r"(v) // outputs
|
||||
: // inputs
|
||||
: // clobbers
|
||||
);
|
||||
return v;
|
||||
}
|
||||
|
||||
inline void set_xucr0(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 1014,4\n" // xucr0
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tens(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 438,4\n" // tens
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
#endif
|
||||
Binary file not shown.
@ -0,0 +1,356 @@
|
||||
# © IBM Corp. 2022
|
||||
# Licensed under and subject to the terms of the CC-BY 4.0
|
||||
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
# Additional rights, including the right to physically implement a softcore
|
||||
# that is compliant with the required sections of the Power ISA
|
||||
# Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
# This README will be updated with additional information when OpenPOWER's
|
||||
# license is available.
|
||||
|
||||
# boot kernel
|
||||
# resets to 32BE
|
||||
# set up translations for starting bios (inc. BE/LE)
|
||||
# copy modifiable rom data to ram - or do in bios?
|
||||
# set up msr for running bios (inc. 32/64)
|
||||
# jump to bios
|
||||
|
||||
|
||||
.include "defines.s"
|
||||
|
||||
.macro load32 rx,v
|
||||
li \rx,0
|
||||
oris \rx,\rx,\v>>16
|
||||
ori \rx,\rx,\v&0x0000FFFF
|
||||
.endm
|
||||
|
||||
.macro load16swiz rx,v
|
||||
li \rx,0
|
||||
ori \rx,\rx,(\v<<8)&0xFF00
|
||||
ori \rx,\rx,(\v>>8)&0x00FF
|
||||
.endm
|
||||
|
||||
# constants from linker script, or defsym
|
||||
|
||||
.ifdef BIOS_32
|
||||
# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.set BIOS_MSR,0x0002B000
|
||||
.else
|
||||
# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.set BIOS_MSR,0x8002B000
|
||||
.endif
|
||||
|
||||
# erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
.ifdef BIOS_LE
|
||||
.set BIOS_ERATW2,0x000000BF
|
||||
.else
|
||||
.set BIOS_ERATW2,0x0000003F
|
||||
.endif
|
||||
|
||||
# bios might be able to use one stack during thread startup if careful
|
||||
.ifndef BIOS_STACK_0
|
||||
.set BIOS_STACK_0,_stack_0
|
||||
.endif
|
||||
|
||||
.ifndef BIOS_STACK_1
|
||||
.set BIOS_STACK_1,_stack_1
|
||||
.endif
|
||||
|
||||
.ifndef BIOS_START
|
||||
.set BIOS_START,0x00010000
|
||||
.endif
|
||||
|
||||
.section .text
|
||||
|
||||
.global _start
|
||||
|
||||
.org 0x000
|
||||
_start:
|
||||
int_000:
|
||||
b boot_start
|
||||
|
||||
.ifdef TST_END
|
||||
b tst_end
|
||||
.endif
|
||||
|
||||
# critical input
|
||||
.org 0x020
|
||||
int_020:
|
||||
.ifdef INT_UNHANDLED
|
||||
b int_unhandled
|
||||
.else
|
||||
b .
|
||||
.endif
|
||||
|
||||
# debug
|
||||
.org 0x040
|
||||
int_040:
|
||||
b .
|
||||
|
||||
# dsi
|
||||
.org 0x060
|
||||
int_060:
|
||||
b .
|
||||
|
||||
# isi
|
||||
.org 0x080
|
||||
int_080:
|
||||
b .
|
||||
|
||||
# external
|
||||
.org 0x0A0
|
||||
int_0A0:
|
||||
b .
|
||||
|
||||
# alignment
|
||||
.org 0x0C0
|
||||
int_0C0:
|
||||
b .
|
||||
|
||||
# program
|
||||
.org 0x0E0
|
||||
int_0E0:
|
||||
b .
|
||||
|
||||
# fp unavailable
|
||||
.org 0x100
|
||||
int_100:
|
||||
b .
|
||||
|
||||
# sc
|
||||
.org 0x120
|
||||
int_120:
|
||||
.ifdef INT_SC
|
||||
# lev is in 20:26, but supposed to use scv now
|
||||
li r3,0
|
||||
mfsrr0 r4
|
||||
b int_sc
|
||||
.else
|
||||
.ifdef INT_UNHANDLED
|
||||
b int_unhandled
|
||||
.else
|
||||
b .
|
||||
.endif
|
||||
.endif
|
||||
|
||||
# apu unavailable
|
||||
.org 0x140
|
||||
int_140:
|
||||
b .
|
||||
|
||||
# decrementer
|
||||
.org 0x160
|
||||
int_160:
|
||||
b .
|
||||
|
||||
# fit
|
||||
.org 0x180
|
||||
int_180:
|
||||
b .
|
||||
|
||||
# watchdog
|
||||
.org 0x1A0
|
||||
int_1A0:
|
||||
b .
|
||||
|
||||
# dtlb
|
||||
.org 0x1C0
|
||||
int_1C0:
|
||||
b .
|
||||
|
||||
# itlb
|
||||
.org 0x1E0
|
||||
int_1E0:
|
||||
b .
|
||||
|
||||
# vector unavailable
|
||||
.org 0x200
|
||||
int_200:
|
||||
b .
|
||||
|
||||
#
|
||||
.org 0x220
|
||||
int_220:
|
||||
b .
|
||||
|
||||
#
|
||||
.org 0x240
|
||||
int_240:
|
||||
b .
|
||||
|
||||
#
|
||||
.org 0x260
|
||||
int_260:
|
||||
b .
|
||||
|
||||
# doorbell
|
||||
.org 0x280
|
||||
int_280:
|
||||
b .
|
||||
|
||||
# doorbell critical
|
||||
.org 0x2A0
|
||||
int_2A0:
|
||||
b .
|
||||
|
||||
# doorbell guest
|
||||
.org 0x2C0
|
||||
int_2C0:
|
||||
b .
|
||||
|
||||
# doorbell guest critical
|
||||
.org 0x2E0
|
||||
int_2E0:
|
||||
b .
|
||||
|
||||
# hvsc
|
||||
.org 0x300
|
||||
int_300:
|
||||
b .
|
||||
|
||||
# hvpriv
|
||||
.org 0x320
|
||||
int_320:
|
||||
b .
|
||||
|
||||
# lrat
|
||||
.org 0x340
|
||||
int_340:
|
||||
b .
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# initial translation
|
||||
# both erats:
|
||||
# 00000000 64K: (rom, BE)
|
||||
# 00010000 64K: (ram, BE or LE)
|
||||
#
|
||||
.org 0x400
|
||||
boot_start:
|
||||
|
||||
mfspr r5,tir # who am i?
|
||||
cmpdi r5,0x00 # skip unless T0
|
||||
bne init_t123
|
||||
|
||||
lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
|
||||
# derat 31 @00000000
|
||||
li r0,0x001F # entry #31
|
||||
li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
mtspr mmucr0,r3
|
||||
eratwe r2,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
|
||||
# derat 30 @<BIOS_START>
|
||||
li r0,0x001E # entry #30
|
||||
load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
load32 r8,BIOS_START
|
||||
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
eratwe r10,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
|
||||
# ierat 15 @00000000
|
||||
li r0,0x000F # entry #15
|
||||
li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
mtspr mmucr0,r3
|
||||
eratwe r2,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
# *** leave the init'd entry 14 for MT access to FFFFFFC0
|
||||
# ierat 13 @<BIOS_START>
|
||||
li r0,0x000D # entry #13
|
||||
load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
load32 r8,BIOS_START
|
||||
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
eratwe r10,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
b init_t0
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# init
|
||||
#
|
||||
|
||||
# T0
|
||||
|
||||
init_t0:
|
||||
|
||||
# set up BIOS msr
|
||||
|
||||
load32 r10,BIOS_MSR
|
||||
mtmsr r10
|
||||
isync
|
||||
# can't use load32 unless you can .set BIOS_STACK_0 to the linked value
|
||||
# load32 r1,BIOS_STACK_0 # @stack_0
|
||||
# this ignores def
|
||||
# lis r1,_stack_0@h
|
||||
# ori r1,r1,_stack_0@l
|
||||
# this requires data load
|
||||
lwz r1,stack_0(r0)
|
||||
|
||||
b boot_complete
|
||||
|
||||
# except T0
|
||||
|
||||
init_t123:
|
||||
|
||||
# set up BIOS msr
|
||||
|
||||
load32 r10,BIOS_MSR
|
||||
mtmsr r10
|
||||
isync
|
||||
# check tir if more than 2 threads possible
|
||||
lwz r1,stack_1(r0)
|
||||
|
||||
b boot_complete
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
boot_complete:
|
||||
|
||||
# set up thread and hop to it
|
||||
|
||||
lis r3,main@h
|
||||
ori r3,r3,main@l
|
||||
mtctr r3
|
||||
mfspr r3,tir # who am i?
|
||||
bctrl
|
||||
b kernel_return
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
.org 0x7FC
|
||||
kernel_return:
|
||||
b .
|
||||
|
||||
# dec
|
||||
.org 0x800
|
||||
int_800:
|
||||
b .
|
||||
|
||||
# perf
|
||||
.org 0x820
|
||||
int_820:
|
||||
b .
|
||||
|
||||
.org 0x8F0
|
||||
.section .rodata
|
||||
stack_0: .long BIOS_STACK_0
|
||||
stack_1: .long BIOS_STACK_1
|
||||
@ -0,0 +1,93 @@
|
||||
#!/usr/bin/bash
|
||||
|
||||
export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
|
||||
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"
|
||||
|
||||
# defines
|
||||
|
||||
## define vars to init rom with csr's it uses...
|
||||
|
||||
#
|
||||
#csr_base=`grep '#define CSR_BASE' generated/csr.h | cut -d ' ' -f 3 | cut -c 1-6`
|
||||
#uart_base=`grep 'CSR_UART_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#UART_ADDR="${csr_base}${uart_base}"
|
||||
#defsyms="-defsym $UART_ADDR"
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_1_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_1_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_1_ADDR"
|
||||
#fi
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_2_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_2_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_2_ADDR"
|
||||
#fi
|
||||
#
|
||||
#leds_base=`grep 'CSR_LEDS_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$leds_base" != "" ]] ; then
|
||||
# LEDS_ADDR="${csr_base}${leds_base}"
|
||||
# defsyms="$defsyms -defsym $LEDS_ADDR"
|
||||
#fi
|
||||
#
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_1_ADDR}"
|
||||
|
||||
# a2o nanokernel
|
||||
|
||||
echo -n "Compiling..."
|
||||
|
||||
echo -n "boot.s "
|
||||
#powerpc-linux-gnu-as -mbig-endian -ma2 -defsym INT_SC=1 -defsym INT_UNHANDLED=1 -I. boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
powerpc-linux-gnu-as -mbig-endian -ma2 -defsym TST_END=1 -defsym INT_UNHANDLED=1 -I. boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
echo -n "arcitst.s "
|
||||
#powerpc-linux-gnu-as -defsym UART_ADDR=$UART_ADDR -defsym LEDS_ADDR=$LEDS_ADDR -defsym UNHANDLED=1 -mbig-endian -mpower9 -I./asm asm/cmod7-boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
powerpc-linux-gnu-as -mbig-endian -ma2 -I. arcitst.s -ahlnd -o arcitst.o > arcitst.lst
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
echo ""
|
||||
echo -n "bios.c "
|
||||
powerpc-linux-gnu-gcc -c -I. $CFLAGS bios.c
|
||||
|
||||
echo ""
|
||||
echo "Linking..."
|
||||
powerpc-linux-gnu-ld -nostdlib -nodefaultlibs -T linker.ld crt0.o bios.o arcitst.o -o rom
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
powerpc-linux-gnu-objdump -d rom > rom.d #wtf: why not getting labels in asm code?
|
||||
powerpc-linux-gnu-objdump -s rom > rom.s
|
||||
#powerpc-linux-gnu-objcopy --change-section-lma .bios=0x10000 -O binary rom rom.bin
|
||||
powerpc-linux-gnu-objcopy -O binary rom rom.bin
|
||||
|
||||
#python3 -m litex.soc.software.memusage rom ./generated/regions.ld powerpc-linux-gnu
|
||||
|
||||
# make rom.bin.hex
|
||||
bin/bin2init rom.bin
|
||||
mv rom.bin.hex rom.init
|
||||
|
||||
echo "Built rom.d, rom.s, rom.init."
|
||||
|
||||
romsize=`grep rom regions.ld | cut -d " " -f 8 | cut -c 3-10`
|
||||
|
||||
echo "Hardware ROM Size $romsize"
|
||||
#echo ""
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_2_ADDR}"
|
||||
#
|
||||
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 2.7 MiB |
@ -0,0 +1,640 @@
|
||||
1 # © IBM Corp. 2022
|
||||
2 # Licensed under and subject to the terms of the CC-BY 4.0
|
||||
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
4 # Additional rights, including the right to physically implement a softcore
|
||||
5 # that is compliant with the required sections of the Power ISA
|
||||
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
7 # This README will be updated with additional information when OpenPOWER's
|
||||
8 # license is available.
|
||||
9
|
||||
10 # boot kernel
|
||||
11 # resets to 32BE
|
||||
12 # set up translations for starting bios (inc. BE/LE)
|
||||
13 # copy modifiable rom data to ram - or do in bios?
|
||||
14 # set up msr for running bios (inc. 32/64)
|
||||
15 # jump to bios
|
||||
16
|
||||
17
|
||||
18 .include "defines.s"
|
||||
1 # © IBM Corp. 2020
|
||||
2 # Licensed under and subject to the terms of the CC-BY 4.0
|
||||
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
4 # Additional rights, including the right to physically implement a softcore
|
||||
5 # that is compliant with the required sections of the Power ISA
|
||||
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
7 # This README will be updated with additional information when OpenPOWER's
|
||||
8 # license is available.
|
||||
9
|
||||
10 #-----------------------------------------
|
||||
11 # Defines
|
||||
12 #-----------------------------------------
|
||||
13
|
||||
14 # Regs
|
||||
15
|
||||
16 .set r0, 0
|
||||
17 .set r1, 1
|
||||
18 .set r2, 2
|
||||
19 .set r3, 3
|
||||
20 .set r4, 4
|
||||
21 .set r5, 5
|
||||
22 .set r6, 6
|
||||
23 .set r7, 7
|
||||
24 .set r8, 8
|
||||
25 .set r9, 9
|
||||
26 .set r10,10
|
||||
27 .set r11,11
|
||||
28 .set r12,12
|
||||
29 .set r13,13
|
||||
30 .set r14,14
|
||||
31 .set r15,15
|
||||
32 .set r16,16
|
||||
33 .set r17,17
|
||||
34 .set r18,18
|
||||
35 .set r19,19
|
||||
36 .set r20,20
|
||||
37 .set r21,21
|
||||
38 .set r22,22
|
||||
39 .set r23,23
|
||||
40 .set r24,24
|
||||
41 .set r25,25
|
||||
42 .set r26,26
|
||||
43 .set r27,27
|
||||
44 .set r28,28
|
||||
45 .set r29,29
|
||||
46 .set r30,30
|
||||
47 .set r31,31
|
||||
48
|
||||
49 .set f0, 0
|
||||
50 .set f1, 1
|
||||
51 .set f2, 2
|
||||
52 .set f3, 3
|
||||
53 .set f4, 4
|
||||
54 .set f5, 5
|
||||
55 .set f6, 6
|
||||
56 .set f7, 7
|
||||
57 .set f8, 8
|
||||
58 .set f9, 9
|
||||
59 .set f10,10
|
||||
60 .set f11,11
|
||||
61 .set f12,12
|
||||
62 .set f13,13
|
||||
63 .set f14,14
|
||||
64 .set f15,15
|
||||
65 .set f16,16
|
||||
66 .set f17,17
|
||||
67 .set f18,18
|
||||
68 .set f19,19
|
||||
69 .set f20,20
|
||||
70 .set f21,21
|
||||
71 .set f22,22
|
||||
72 .set f23,23
|
||||
73 .set f24,24
|
||||
74 .set f25,25
|
||||
75 .set f26,26
|
||||
76 .set f27,27
|
||||
77 .set f28,28
|
||||
78 .set f29,29
|
||||
79 .set f30,30
|
||||
80 .set f31,31
|
||||
81
|
||||
82 .set cr0, 0
|
||||
83 .set cr1, 1
|
||||
84 .set cr2, 2
|
||||
85 .set cr3, 3
|
||||
86 .set cr4, 4
|
||||
87 .set cr5, 5
|
||||
88 .set cr6, 6
|
||||
89 .set cr7, 7
|
||||
90
|
||||
91 # SPR numbers
|
||||
92
|
||||
93 .set srr0, 26
|
||||
94 .set srr1, 27
|
||||
95 .set dar, 19
|
||||
96 .set dsisr, 18
|
||||
97 .set epcr, 307
|
||||
98 .set tar, 815
|
||||
99
|
||||
100 .set dbsr, 304
|
||||
101 .set dbcr0, 308
|
||||
102 .set dbcr1, 309
|
||||
103 .set dbcr2, 310
|
||||
104 .set dbcr3, 848
|
||||
105
|
||||
106 .set ivpr, 63
|
||||
107
|
||||
108 .set iucr0, 1011
|
||||
109 .set iucr1, 883
|
||||
110 .set iucr2, 884
|
||||
111
|
||||
112 .set iudbg0, 888
|
||||
113 .set iudbg1, 889
|
||||
114 .set iudbg2, 890
|
||||
115 .set iulfsr, 891
|
||||
116 .set iullcr, 892
|
||||
117
|
||||
118 .set mmucr0, 1020
|
||||
119 .set mmucr1, 1021
|
||||
120 .set mmucr2, 1022
|
||||
121 .set mmucr3, 1023
|
||||
122
|
||||
123 .set tb, 268
|
||||
124 .set tbl, 284
|
||||
125 .set tbh, 285
|
||||
126
|
||||
127 .set dec, 22
|
||||
128 .set udec, 550
|
||||
129 .set tsr, 336
|
||||
130 .set tcr, 340
|
||||
131
|
||||
132 .set xucr0, 1014
|
||||
133 .set xucr1, 851
|
||||
134 .set xucr2, 1016
|
||||
135 .set xucr3, 852
|
||||
136 .set xucr4, 853
|
||||
137
|
||||
138 .set tens, 438
|
||||
139 .set tenc, 439
|
||||
140 .set tensr, 437
|
||||
141
|
||||
142 .set pid, 48
|
||||
143 .set pir, 286
|
||||
144 .set pvr, 287
|
||||
145 .set tir, 446
|
||||
146
|
||||
147 #.set sprg0,
|
||||
148 #.set sprg1,
|
||||
149 #.set sprg2,
|
||||
150 .set sprg3, 259
|
||||
19
|
||||
20 .macro load32 rx,v
|
||||
21 li \rx,0
|
||||
22 oris \rx,\rx,\v>>16
|
||||
23 ori \rx,\rx,\v&0x0000FFFF
|
||||
24 .endm
|
||||
25
|
||||
26 .macro load16swiz rx,v
|
||||
27 li \rx,0
|
||||
28 ori \rx,\rx,(\v<<8)&0xFF00
|
||||
29 ori \rx,\rx,(\v>>8)&0x00FF
|
||||
30 .endm
|
||||
31
|
||||
32 # constants from linker script, or defsym
|
||||
33
|
||||
34 .ifdef BIOS_32
|
||||
35 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
36 .set BIOS_MSR,0x0002B000
|
||||
37 .else
|
||||
38 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
39 .set BIOS_MSR,0x8002B000
|
||||
40 .endif
|
||||
41
|
||||
42 # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/s
|
||||
43 .ifdef BIOS_LE
|
||||
44 .set BIOS_ERATW2,0x000000BF
|
||||
45 .else
|
||||
46 .set BIOS_ERATW2,0x0000003F
|
||||
47 .endif
|
||||
48
|
||||
49 # bios might be able to use one stack during thread startup if careful
|
||||
50 .ifndef BIOS_STACK_0
|
||||
51 .set BIOS_STACK_0,_stack_0
|
||||
52 .endif
|
||||
53
|
||||
54 .ifndef BIOS_STACK_1
|
||||
55 .set BIOS_STACK_1,_stack_1
|
||||
56 .endif
|
||||
57
|
||||
58 .ifndef BIOS_START
|
||||
59 .set BIOS_START,0x00010000
|
||||
60 .endif
|
||||
61
|
||||
62 .section .text
|
||||
63
|
||||
64 .global _start
|
||||
65
|
||||
66 .org 0x000
|
||||
67 _start:
|
||||
68 int_000:
|
||||
69 0000 48000400 b boot_start
|
||||
70
|
||||
71 .ifdef TST_END
|
||||
72 0004 48000000 b tst_end
|
||||
73 .endif
|
||||
74
|
||||
75 # critical input
|
||||
76 0008 00000000 .org 0x020
|
||||
76 00000000
|
||||
76 00000000
|
||||
76 00000000
|
||||
76 00000000
|
||||
77 int_020:
|
||||
78 .ifdef INT_UNHANDLED
|
||||
79 0020 48000000 b int_unhandled
|
||||
80 .else
|
||||
81 b .
|
||||
82 .endif
|
||||
83
|
||||
84 # debug
|
||||
85 0024 00000000 .org 0x040
|
||||
85 00000000
|
||||
85 00000000
|
||||
85 00000000
|
||||
85 00000000
|
||||
86 int_040:
|
||||
87 0040 48000000 b .
|
||||
88
|
||||
89 # dsi
|
||||
90 0044 00000000 .org 0x060
|
||||
90 00000000
|
||||
90 00000000
|
||||
90 00000000
|
||||
90 00000000
|
||||
91 int_060:
|
||||
92 0060 48000000 b .
|
||||
93
|
||||
94 # isi
|
||||
95 0064 00000000 .org 0x080
|
||||
95 00000000
|
||||
95 00000000
|
||||
95 00000000
|
||||
95 00000000
|
||||
96 int_080:
|
||||
97 0080 48000000 b .
|
||||
98
|
||||
99 # external
|
||||
100 0084 00000000 .org 0x0A0
|
||||
100 00000000
|
||||
100 00000000
|
||||
100 00000000
|
||||
100 00000000
|
||||
101 int_0A0:
|
||||
102 00a0 48000000 b .
|
||||
103
|
||||
104 # alignment
|
||||
105 00a4 00000000 .org 0x0C0
|
||||
105 00000000
|
||||
105 00000000
|
||||
105 00000000
|
||||
105 00000000
|
||||
106 int_0C0:
|
||||
107 00c0 48000000 b .
|
||||
108
|
||||
109 # program
|
||||
110 00c4 00000000 .org 0x0E0
|
||||
110 00000000
|
||||
110 00000000
|
||||
110 00000000
|
||||
110 00000000
|
||||
111 int_0E0:
|
||||
112 00e0 48000000 b .
|
||||
113
|
||||
114 # fp unavailable
|
||||
115 00e4 00000000 .org 0x100
|
||||
115 00000000
|
||||
115 00000000
|
||||
115 00000000
|
||||
115 00000000
|
||||
116 int_100:
|
||||
117 0100 48000000 b .
|
||||
118
|
||||
119 # sc
|
||||
120 0104 00000000 .org 0x120
|
||||
120 00000000
|
||||
120 00000000
|
||||
120 00000000
|
||||
120 00000000
|
||||
121 int_120:
|
||||
122 .ifdef INT_SC
|
||||
123 # lev is in 20:26, but supposed to use scv now
|
||||
124 li r3,0
|
||||
125 mfsrr0 r4
|
||||
126 b int_sc
|
||||
127 .else
|
||||
128 .ifdef INT_UNHANDLED
|
||||
129 0120 48000000 b int_unhandled
|
||||
130 .else
|
||||
131 b .
|
||||
132 .endif
|
||||
133 .endif
|
||||
134
|
||||
135 # apu unavailable
|
||||
136 0124 00000000 .org 0x140
|
||||
136 00000000
|
||||
136 00000000
|
||||
136 00000000
|
||||
136 00000000
|
||||
137 int_140:
|
||||
138 0140 48000000 b .
|
||||
139
|
||||
140 # decrementer
|
||||
141 0144 00000000 .org 0x160
|
||||
141 00000000
|
||||
141 00000000
|
||||
141 00000000
|
||||
141 00000000
|
||||
142 int_160:
|
||||
143 0160 48000000 b .
|
||||
144
|
||||
145 # fit
|
||||
146 0164 00000000 .org 0x180
|
||||
146 00000000
|
||||
146 00000000
|
||||
146 00000000
|
||||
146 00000000
|
||||
147 int_180:
|
||||
148 0180 48000000 b .
|
||||
149
|
||||
150 # watchdog
|
||||
151 0184 00000000 .org 0x1A0
|
||||
151 00000000
|
||||
151 00000000
|
||||
151 00000000
|
||||
151 00000000
|
||||
152 int_1A0:
|
||||
153 01a0 48000000 b .
|
||||
154
|
||||
155 # dtlb
|
||||
156 01a4 00000000 .org 0x1C0
|
||||
156 00000000
|
||||
156 00000000
|
||||
156 00000000
|
||||
156 00000000
|
||||
157 int_1C0:
|
||||
158 01c0 48000000 b .
|
||||
159
|
||||
160 # itlb
|
||||
161 01c4 00000000 .org 0x1E0
|
||||
161 00000000
|
||||
161 00000000
|
||||
161 00000000
|
||||
161 00000000
|
||||
162 int_1E0:
|
||||
163 01e0 48000000 b .
|
||||
164
|
||||
165 # vector unavailable
|
||||
166 01e4 00000000 .org 0x200
|
||||
166 00000000
|
||||
166 00000000
|
||||
166 00000000
|
||||
166 00000000
|
||||
167 int_200:
|
||||
168 0200 48000000 b .
|
||||
169
|
||||
170 #
|
||||
171 0204 00000000 .org 0x220
|
||||
171 00000000
|
||||
171 00000000
|
||||
171 00000000
|
||||
171 00000000
|
||||
172 int_220:
|
||||
173 0220 48000000 b .
|
||||
174
|
||||
175 #
|
||||
176 0224 00000000 .org 0x240
|
||||
176 00000000
|
||||
176 00000000
|
||||
176 00000000
|
||||
176 00000000
|
||||
177 int_240:
|
||||
178 0240 48000000 b .
|
||||
179
|
||||
180 #
|
||||
181 0244 00000000 .org 0x260
|
||||
181 00000000
|
||||
181 00000000
|
||||
181 00000000
|
||||
181 00000000
|
||||
182 int_260:
|
||||
183 0260 48000000 b .
|
||||
184
|
||||
185 # doorbell
|
||||
186 0264 00000000 .org 0x280
|
||||
186 00000000
|
||||
186 00000000
|
||||
186 00000000
|
||||
186 00000000
|
||||
187 int_280:
|
||||
188 0280 48000000 b .
|
||||
189
|
||||
190 # doorbell critical
|
||||
191 0284 00000000 .org 0x2A0
|
||||
191 00000000
|
||||
191 00000000
|
||||
191 00000000
|
||||
191 00000000
|
||||
192 int_2A0:
|
||||
193 02a0 48000000 b .
|
||||
194
|
||||
195 # doorbell guest
|
||||
196 02a4 00000000 .org 0x2C0
|
||||
196 00000000
|
||||
196 00000000
|
||||
196 00000000
|
||||
196 00000000
|
||||
197 int_2C0:
|
||||
198 02c0 48000000 b .
|
||||
199
|
||||
200 # doorbell guest critical
|
||||
201 02c4 00000000 .org 0x2E0
|
||||
201 00000000
|
||||
201 00000000
|
||||
201 00000000
|
||||
201 00000000
|
||||
202 int_2E0:
|
||||
203 02e0 48000000 b .
|
||||
204
|
||||
205 # hvsc
|
||||
206 02e4 00000000 .org 0x300
|
||||
206 00000000
|
||||
206 00000000
|
||||
206 00000000
|
||||
206 00000000
|
||||
207 int_300:
|
||||
208 0300 48000000 b .
|
||||
209
|
||||
210 # hvpriv
|
||||
211 0304 00000000 .org 0x320
|
||||
211 00000000
|
||||
211 00000000
|
||||
211 00000000
|
||||
211 00000000
|
||||
212 int_320:
|
||||
213 0320 48000000 b .
|
||||
214
|
||||
215 # lrat
|
||||
216 0324 00000000 .org 0x340
|
||||
216 00000000
|
||||
216 00000000
|
||||
216 00000000
|
||||
216 00000000
|
||||
217 int_340:
|
||||
218 0340 48000000 b .
|
||||
219
|
||||
220 # -------------------------------------------------------------------------------------------------
|
||||
221 # initial translation
|
||||
222 # both erats:
|
||||
223 # 00000000 64K: (rom, BE)
|
||||
224 # 00010000 64K: (ram, BE or LE)
|
||||
225 #
|
||||
226 0344 00000000 .org 0x400
|
||||
226 00000000
|
||||
226 00000000
|
||||
226 00000000
|
||||
226 00000000
|
||||
227 boot_start:
|
||||
228
|
||||
229 0400 7CBE6AA6 mfspr r5,tir # who am i?
|
||||
230 0404 2C250000 cmpdi r5,0x00 # skip unless T0
|
||||
231 0408 408200E0 bne init_t123
|
||||
232
|
||||
233 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
234
|
||||
235 # derat 31 @00000000
|
||||
236 0410 3800001F li r0,0x001F # entry #31
|
||||
237 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
|
||||
238 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
239 041c 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
240
|
||||
241 0420 7C7CFBA6 mtspr mmucr0,r3
|
||||
242 0424 7C4011A6 eratwe r2,r0,2
|
||||
243 0428 7C8009A6 eratwe r4,r0,1
|
||||
244 042c 7D0001A6 eratwe r8,r0,0
|
||||
245 0430 4C00012C isync
|
||||
246
|
||||
247 0434 39400000 load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
|
||||
247 654A0000
|
||||
247 614A003F
|
||||
248
|
||||
249 # derat 30 @<BIOS_START>
|
||||
250 0440 3800001E li r0,0x001E # entry #30
|
||||
251 0444 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
251 64840001
|
||||
251 60840000
|
||||
252 0450 39000000 load32 r8,BIOS_START
|
||||
252 65080001
|
||||
252 61080000
|
||||
253 045c 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
254
|
||||
255 0460 7D4011A6 eratwe r10,r0,2
|
||||
256 0464 7C8009A6 eratwe r4,r0,1
|
||||
257 0468 7D0001A6 eratwe r8,r0,0
|
||||
258 046c 4C00012C isync
|
||||
259
|
||||
260 0470 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
261
|
||||
262 # ierat 15 @00000000
|
||||
263 0474 3800000F li r0,0x000F # entry #15
|
||||
264 0478 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
|
||||
265 047c 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
266 0480 3900023F li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
267
|
||||
268 0484 7C7CFBA6 mtspr mmucr0,r3
|
||||
269 0488 7C4011A6 eratwe r2,r0,2
|
||||
270 048c 7C8009A6 eratwe r4,r0,1
|
||||
271 0490 7D0001A6 eratwe r8,r0,0
|
||||
272 0494 4C00012C isync
|
||||
273
|
||||
274 # *** leave the init'd entry 14 for MT access to FFFFFFC0
|
||||
275 # ierat 13 @<BIOS_START>
|
||||
276 0498 3800000D li r0,0x000D # entry #13
|
||||
277 049c 38800000 load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
277 64840001
|
||||
277 60840000
|
||||
278 04a8 39000000 load32 r8,BIOS_START
|
||||
278 65080001
|
||||
278 61080000
|
||||
279 04b4 6108023F ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
280
|
||||
281 04b8 7D4011A6 eratwe r10,r0,2
|
||||
282 04bc 7C8009A6 eratwe r4,r0,1
|
||||
283 04c0 7D0001A6 eratwe r8,r0,0
|
||||
284 04c4 4C00012C isync
|
||||
285
|
||||
286 04c8 48000004 b init_t0
|
||||
287
|
||||
288 # -------------------------------------------------------------------------------------------------
|
||||
289 # init
|
||||
290 #
|
||||
291
|
||||
292 # T0
|
||||
293
|
||||
294 init_t0:
|
||||
295
|
||||
296 # set up BIOS msr
|
||||
297
|
||||
298 04cc 39400000 load32 r10,BIOS_MSR
|
||||
298 654A8002
|
||||
298 614AB000
|
||||
299 04d8 7D400124 mtmsr r10
|
||||
300 04dc 4C00012C isync
|
||||
301 # can't use load32 unless you can .set BIOS_STACK_0 to the linked value
|
||||
302 # load32 r1,BIOS_STACK_0 # @stack_0
|
||||
303 # this ignores def
|
||||
304 # lis r1,_stack_0@h
|
||||
305 # ori r1,r1,_stack_0@l
|
||||
306 # this requires data load
|
||||
307 04e0 80200000 lwz r1,stack_0(r0)
|
||||
308
|
||||
309 04e4 48000020 b boot_complete
|
||||
310
|
||||
311 # except T0
|
||||
312
|
||||
313 init_t123:
|
||||
314
|
||||
315 # set up BIOS msr
|
||||
316
|
||||
317 04e8 39400000 load32 r10,BIOS_MSR
|
||||
317 654A8002
|
||||
317 614AB000
|
||||
318 04f4 7D400124 mtmsr r10
|
||||
319 04f8 4C00012C isync
|
||||
320 # check tir if more than 2 threads possible
|
||||
321 04fc 80200000 lwz r1,stack_1(r0)
|
||||
322
|
||||
323 0500 48000004 b boot_complete
|
||||
324
|
||||
325 # -------------------------------------------------------------------------------------------------
|
||||
326 boot_complete:
|
||||
327
|
||||
328 # set up thread and hop to it
|
||||
329
|
||||
330 0504 3C600000 lis r3,main@h
|
||||
331 0508 60630000 ori r3,r3,main@l
|
||||
332 050c 7C6903A6 mtctr r3
|
||||
333 0510 7C7E6AA6 mfspr r3,tir # who am i?
|
||||
334 0514 4E800421 bctrl
|
||||
335 0518 480002E4 b kernel_return
|
||||
336
|
||||
337 # -------------------------------------------------------------------------------------------------
|
||||
338
|
||||
339 051c 00000000 .org 0x7FC
|
||||
339 00000000
|
||||
339 00000000
|
||||
339 00000000
|
||||
339 00000000
|
||||
340 kernel_return:
|
||||
341 07fc 48000000 b .
|
||||
342
|
||||
343 # dec
|
||||
344 .org 0x800
|
||||
345 int_800:
|
||||
346 0800 48000000 b .
|
||||
347
|
||||
348 # perf
|
||||
349 0804 00000000 .org 0x820
|
||||
349 00000000
|
||||
349 00000000
|
||||
349 00000000
|
||||
349 00000000
|
||||
350 int_820:
|
||||
351 0820 48000000 b .
|
||||
352
|
||||
353 0824 00000000 .org 0x8F0
|
||||
353 00000000
|
||||
353 00000000
|
||||
353 00000000
|
||||
353 00000000
|
||||
354 .section .rodata
|
||||
355 0000 00000000 stack_0: .long BIOS_STACK_0
|
||||
356 0004 00000000 stack_1: .long BIOS_STACK_1
|
||||
Binary file not shown.
@ -0,0 +1,150 @@
|
||||
# © IBM Corp. 2020
|
||||
# Licensed under and subject to the terms of the CC-BY 4.0
|
||||
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
# Additional rights, including the right to physically implement a softcore
|
||||
# that is compliant with the required sections of the Power ISA
|
||||
# Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
# This README will be updated with additional information when OpenPOWER's
|
||||
# license is available.
|
||||
|
||||
#-----------------------------------------
|
||||
# Defines
|
||||
#-----------------------------------------
|
||||
|
||||
# Regs
|
||||
|
||||
.set r0, 0
|
||||
.set r1, 1
|
||||
.set r2, 2
|
||||
.set r3, 3
|
||||
.set r4, 4
|
||||
.set r5, 5
|
||||
.set r6, 6
|
||||
.set r7, 7
|
||||
.set r8, 8
|
||||
.set r9, 9
|
||||
.set r10,10
|
||||
.set r11,11
|
||||
.set r12,12
|
||||
.set r13,13
|
||||
.set r14,14
|
||||
.set r15,15
|
||||
.set r16,16
|
||||
.set r17,17
|
||||
.set r18,18
|
||||
.set r19,19
|
||||
.set r20,20
|
||||
.set r21,21
|
||||
.set r22,22
|
||||
.set r23,23
|
||||
.set r24,24
|
||||
.set r25,25
|
||||
.set r26,26
|
||||
.set r27,27
|
||||
.set r28,28
|
||||
.set r29,29
|
||||
.set r30,30
|
||||
.set r31,31
|
||||
|
||||
.set f0, 0
|
||||
.set f1, 1
|
||||
.set f2, 2
|
||||
.set f3, 3
|
||||
.set f4, 4
|
||||
.set f5, 5
|
||||
.set f6, 6
|
||||
.set f7, 7
|
||||
.set f8, 8
|
||||
.set f9, 9
|
||||
.set f10,10
|
||||
.set f11,11
|
||||
.set f12,12
|
||||
.set f13,13
|
||||
.set f14,14
|
||||
.set f15,15
|
||||
.set f16,16
|
||||
.set f17,17
|
||||
.set f18,18
|
||||
.set f19,19
|
||||
.set f20,20
|
||||
.set f21,21
|
||||
.set f22,22
|
||||
.set f23,23
|
||||
.set f24,24
|
||||
.set f25,25
|
||||
.set f26,26
|
||||
.set f27,27
|
||||
.set f28,28
|
||||
.set f29,29
|
||||
.set f30,30
|
||||
.set f31,31
|
||||
|
||||
.set cr0, 0
|
||||
.set cr1, 1
|
||||
.set cr2, 2
|
||||
.set cr3, 3
|
||||
.set cr4, 4
|
||||
.set cr5, 5
|
||||
.set cr6, 6
|
||||
.set cr7, 7
|
||||
|
||||
# SPR numbers
|
||||
|
||||
.set srr0, 26
|
||||
.set srr1, 27
|
||||
.set dar, 19
|
||||
.set dsisr, 18
|
||||
.set epcr, 307
|
||||
.set tar, 815
|
||||
|
||||
.set dbsr, 304
|
||||
.set dbcr0, 308
|
||||
.set dbcr1, 309
|
||||
.set dbcr2, 310
|
||||
.set dbcr3, 848
|
||||
|
||||
.set ivpr, 63
|
||||
|
||||
.set iucr0, 1011
|
||||
.set iucr1, 883
|
||||
.set iucr2, 884
|
||||
|
||||
.set iudbg0, 888
|
||||
.set iudbg1, 889
|
||||
.set iudbg2, 890
|
||||
.set iulfsr, 891
|
||||
.set iullcr, 892
|
||||
|
||||
.set mmucr0, 1020
|
||||
.set mmucr1, 1021
|
||||
.set mmucr2, 1022
|
||||
.set mmucr3, 1023
|
||||
|
||||
.set tb, 268
|
||||
.set tbl, 284
|
||||
.set tbh, 285
|
||||
|
||||
.set dec, 22
|
||||
.set udec, 550
|
||||
.set tsr, 336
|
||||
.set tcr, 340
|
||||
|
||||
.set xucr0, 1014
|
||||
.set xucr1, 851
|
||||
.set xucr2, 1016
|
||||
.set xucr3, 852
|
||||
.set xucr4, 853
|
||||
|
||||
.set tens, 438
|
||||
.set tenc, 439
|
||||
.set tensr, 437
|
||||
|
||||
.set pid, 48
|
||||
.set pir, 286
|
||||
.set pvr, 287
|
||||
.set tir, 446
|
||||
|
||||
#.set sprg0,
|
||||
#.set sprg1,
|
||||
#.set sprg2,
|
||||
.set sprg3, 259
|
||||
@ -0,0 +1,319 @@
|
||||
* OPV
|
||||
* Testname: fx_alucmpbr.tst
|
||||
|
||||
* --------------------------------------------------------------------------------
|
||||
TEST 1001
|
||||
INITIALIZATIONS: DATA MEMORY
|
||||
D 0000000008F00850 0001FFFFFF000007D400000068877812 * PTE Match EPN=0x000000000001 VPN=0x0001FFFFFF000001 RPN=0x000000006887 WIMG=0x2 I TA=0
|
||||
D 0000000053E6FD70 2000000008F10B02 * Root Table Descriptor , Partition Table Primary Entry for LPID = 0xFD7: HTABORG = 0x0800_0000_023C, HTABSIZE = 0x02, PS = 0x0, Entry Address = 0x0000_0000_53E6_FD70 WIMG=0x2
|
||||
D 0000000053E6FD78 000618E1E5836C87 * Segmentation On HPT, Process Table Descriptor, Partition Table Secondary Entry for LPID = 0xFD7: PRTB = 0x00_030C_70F2, PTS = 0x07, NUT = 0x0, PTPS = 0x4 WIMG=0x2
|
||||
D 00000000F0D2D3F0 400AC1CD9CEF56376DF7C045D17603CB * Guest Root Table Descriptor, Process Table Entry for LPID = 0x000 STABORGU = 0x000A_C1CD_9CEF_5637 STABORGL = 0x6 STABSIZE = 0xC B = 0x1 STPS = 0x5
|
||||
INITIALIZATIONS: INSTRUCTION MEMORY
|
||||
LEVEL 4 CHIP 0
|
||||
LEVEL 3 CORE 0
|
||||
INITIALIZATIONS: REGISTERS
|
||||
LEVEL 2 PARTITION 0
|
||||
INITIALIZATIONS: REGISTERS
|
||||
LEVEL 1 THREAD 0
|
||||
INITIALIZATIONS: REGISTERS
|
||||
R CR DBFD3628 * LT:1 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
|
||||
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
|
||||
* CR7:8
|
||||
R DAR 96A22826D573F45F
|
||||
R DSISR 48068CFB * TS:0 PF:1 ATT:0 Rsrv35:0 Prot:1 CI:0
|
||||
* Store:0 Rsrv39_40:0 DAWR:0 VPCK:0
|
||||
* SMF:0 RADIX:0 RC:1 Guest_Tbl:1
|
||||
* Rsrv47_61:233E CIX:1 EAO:1
|
||||
R DEC 0000000005792645
|
||||
R XER 00002E2289F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
|
||||
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:0
|
||||
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
|
||||
R G0 CC7B4BBA00000000
|
||||
R G1 F99E00E65822C905
|
||||
R G3 48577A9C91B6D1A3
|
||||
R G9 6872DEB47E11EE88
|
||||
R G11 415D35187FFFFFFF
|
||||
R G14 BCF163168C20BDE6
|
||||
R G16 CE83BAA576D0DADF
|
||||
R G17 06C01CAE15111F42
|
||||
R G19 4283519E36108E50
|
||||
R G22 4FA8B87B328A0CED
|
||||
R G25 9138C732AF224C19
|
||||
R G28 2F4816B9D624B27A
|
||||
R IAR 0000000000010000
|
||||
R MSR 0000000000001104 * SF:0 TA:0 Rsrv2_old_ISF:0 HV:0
|
||||
* Rsrv4:0 SLE:0 Rsrv6_28:000000 TS:0
|
||||
* TM:0 Rsrv32_37:00 VMX:0 Rsrv39:0
|
||||
* VSX:0 S:0 Rsrv42_47:00 EE:0 PR:0 FP:0
|
||||
* ME:1 FE0:0 SE:0 BE:0 FE1:1 US:0
|
||||
* Rsrv57_old_IP:0 IR:0 DR:0
|
||||
* Rsrv60_old_SO:0 PMM:1 RI:0 LE:0
|
||||
|
||||
PHASE 0 INSTRUCTIONS
|
||||
I 0000000068870000 7C61CC14 * EA=0000000000010000 WIMG=2 addco G3,G1,G25 INum:1 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G1 F99E00E65822C905
|
||||
R G25 9138C732AF224C19
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 0000000000000000 M 0000000000000000 * PTE
|
||||
TRACE WRITES
|
||||
R G3 8AD6C8190745151E
|
||||
R XER 00002E22A9F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
|
||||
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:1
|
||||
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
|
||||
R IAR 0000000000010004
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
I 0000000068870004 7D230595 * EA=0000000000010004 WIMG=2 addzeo. G9,G3 INum:2 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G3 8AD6C8190745151E
|
||||
R XER 00002E22A9F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
|
||||
* OC:0 LT:1 GT:0 EQ:0 IC:1 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:1
|
||||
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G9 8AD6C8190745151F
|
||||
R XER 00002E2284F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
|
||||
* OC:0 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:0
|
||||
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
|
||||
R CR 5BFD3628 * LT:0 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
|
||||
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
|
||||
* CR7:8
|
||||
R IAR 0000000000010008
|
||||
I 0000000068870008 7AC37392 * EA=0000000000010008 WIMG=2 rldcr G3,G22,G14,0x0E INum:3 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G14 BCF163168C20BDE6
|
||||
R G22 4FA8B87B328A0CED
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G3 A282000000000000
|
||||
R IAR 000000000001000C
|
||||
I 000000006887000C 7E094C11 * EA=000000000001000C WIMG=2 subfco. G16,G9,G9 INum:4 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G9 8AD6C8190745151F
|
||||
R XER 00002E2284F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
|
||||
* OC:0 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:0
|
||||
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G16 0000000000000000
|
||||
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
|
||||
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:1
|
||||
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
|
||||
R CR 3BFD3628 * LT:0 GT:0 EQ:1 SO:1 FX:1 FEX:0 VX:1
|
||||
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
|
||||
* CR7:8
|
||||
R IAR 0000000000010010
|
||||
I 0000000068870010 7E1CB115 * EA=0000000000010010 WIMG=2 adde. G16,G28,G22 INum:5 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G28 2F4816B9D624B27A
|
||||
R G22 4FA8B87B328A0CED
|
||||
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
|
||||
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:1
|
||||
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G16 7EF0CF3508AEBF68
|
||||
R XER 00002E22B4F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
|
||||
* OC:1 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:1
|
||||
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
|
||||
R CR 5BFD3628 * LT:0 GT:1 EQ:0 SO:1 FX:1 FEX:0 VX:1
|
||||
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
|
||||
* CR7:8
|
||||
R IAR 0000000000010014
|
||||
I 0000000068870014 7A338886 * EA=0000000000010014 WIMG=2 rldicr G19,G17,0x31,0x02 INum:6 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G17 06C01CAE15111F42
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G19 2000000000000000
|
||||
R IAR 0000000000010018
|
||||
I 0000000068870018 7C6004D1 * EA=0000000000010018 WIMG=2 nego. G3,G0 INum:7 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G0 CC7B4BBA00000000
|
||||
R XER 00002E22B4F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
|
||||
* OC:1 LT:0 GT:1 EQ:0 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:1
|
||||
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G3 3384B44600000000
|
||||
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
|
||||
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:1
|
||||
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
|
||||
R CR 3BFD3628 * LT:0 GT:0 EQ:1 SO:1 FX:1 FEX:0 VX:1
|
||||
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
|
||||
* CR7:8
|
||||
R IAR 000000000001001C
|
||||
I 000000006887001C 7E09B038 * EA=000000000001001C WIMG=2 and G9,G16,G22 INum:8 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G16 7EF0CF3508AEBF68
|
||||
R G22 4FA8B87B328A0CED
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G9 4EA08831008A0C68
|
||||
R IAR 0000000000010020
|
||||
I 0000000068870020 7C360591 * EA=0000000000010020 WIMG=2 subfzeo. G1,G22 INum:9 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G22 4FA8B87B328A0CED
|
||||
R XER 00002E22B2F4006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:1
|
||||
* OC:1 LT:0 GT:0 EQ:1 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:1
|
||||
* Rsrv46_56:000 Rsrv44_56:0800 len:6E
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G1 B0574784CD75F313
|
||||
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
|
||||
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:0
|
||||
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
|
||||
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
|
||||
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
|
||||
* CR7:8
|
||||
R IAR 0000000000010024
|
||||
I 0000000068870024 7E2B00D1 * EA=0000000000010024 WIMG=2 neg. G17,G11 INum:10 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
R G11 415D35187FFFFFFF
|
||||
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
|
||||
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:0
|
||||
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R G17 BEA2CAE780000001
|
||||
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
|
||||
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:0
|
||||
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
|
||||
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
|
||||
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
|
||||
* CR7:8
|
||||
* FALSE PHASE 0.0 INSTRUCTIONS
|
||||
R IAR 0000000000010028
|
||||
|
||||
EPILOGUE
|
||||
* Begin macro Epilogue_Sequence
|
||||
* TRUE
|
||||
* TRUE
|
||||
I 0000000068870028 60000000 * EA=0000000000010028 WIMG=2 nop INum:11 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R IAR 000000000001002C
|
||||
I 000000006887002C 60000000 * EA=000000000001002C WIMG=2 nop_Epilogue INum:12 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R IAR 0000000000010030
|
||||
I 0000000068870030 60000000 * EA=0000000000010030 WIMG=2 nop_Epilogue INum:13 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
|
||||
TRACE READS
|
||||
D 0000000053E6FD70 2000000008F10B02 * RADIX
|
||||
D 0000000053E6FD78 000618E1E5836C87 * RADIX
|
||||
D 0000000008F00850 0001FFFFFF000007 * PTE
|
||||
D 0000000008F00858 D400000068877912 * PTE
|
||||
TRACE WRITES
|
||||
R IAR 0000000000010034
|
||||
I 0000000068870034 24000000 * EA=0000000000010034 WIMG=2 notrace INum:14 PartId:0 ThreadId:0 Phase:0 CoreId:0
|
||||
* End of macro Epilogue_Sequence
|
||||
RESULTS: REGISTERS
|
||||
R CR 9BFD3628 * LT:1 GT:0 EQ:0 SO:1 FX:1 FEX:0 VX:1
|
||||
* OX:1 CR2:F CR3:D CR4:3 CR5:6 CR6:2
|
||||
* CR7:8
|
||||
R DAR 96A22826D573F45F
|
||||
R DSISR 48068CFB * TS:0 PF:1 ATT:0 Rsrv35:0 Prot:1 CI:0
|
||||
* Store:0 Rsrv39_40:0 DAWR:0 VPCK:0
|
||||
* SMF:0 RADIX:0 RC:1 Guest_Tbl:1
|
||||
* Rsrv47_61:233E CIX:1 EAO:1
|
||||
R DEC 0000000005792645
|
||||
R XER 00002E2298F0006E * Rsrv0_15:0000 DC:2E22 SO:1 OV:0 CA:0
|
||||
* OC:1 LT:1 GT:0 EQ:0 IC:0 DS:1 TAG0:1
|
||||
* TAG1:1 TAG:1 OV32:0 CA32:0
|
||||
* Rsrv46_56:000 Rsrv44_56:0000 len:6E
|
||||
R G0 CC7B4BBA00000000
|
||||
R G1 B0574784CD75F313
|
||||
R G3 3384B44600000000
|
||||
R G9 4EA08831008A0C68
|
||||
R G11 415D35187FFFFFFF
|
||||
R G14 BCF163168C20BDE6
|
||||
R G16 7EF0CF3508AEBF68
|
||||
R G17 BEA2CAE780000001
|
||||
R G19 2000000000000000
|
||||
R G22 4FA8B87B328A0CED
|
||||
R G25 9138C732AF224C19
|
||||
R G28 2F4816B9D624B27A
|
||||
R IAR 0000000000010038
|
||||
R MSR 0000000000001104 * SF:0 TA:0 Rsrv2_old_ISF:0 HV:0
|
||||
* Rsrv4:0 SLE:0 Rsrv6_28:000000 TS:0
|
||||
* TM:0 Rsrv32_37:00 VMX:0 Rsrv39:0
|
||||
* VSX:0 S:0 Rsrv42_47:00 EE:0 PR:0 FP:0
|
||||
* ME:1 FE0:0 SE:0 BE:0 FE1:1 US:0
|
||||
* Rsrv57_old_IP:0 IR:0 DR:0
|
||||
* Rsrv60_old_SO:0 PMM:1 RI:0 LE:0
|
||||
END_OF_LEVEL 1 THREAD 0
|
||||
RESULTS: REGISTERS
|
||||
END_OF_LEVEL 2 PARTITION 0
|
||||
RESULTS: REGISTERS
|
||||
END_OF_LEVEL 3 CORE 0
|
||||
END_OF_LEVEL 4 CHIP 0
|
||||
RESULTS: DATA MEMORY
|
||||
D 0000000008F00850 0001FFFFFF000007D400000068877912 * PTE
|
||||
D 0000000053E6FD70 2000000008F10B02
|
||||
D 0000000053E6FD78 000618E1E5836C87
|
||||
D 00000000F0D2D3F0 400AC1CD9CEF56376DF7C045D17603CB
|
||||
END_OF_TEST
|
||||
@ -0,0 +1,94 @@
|
||||
/* this version puts kernel and bios at rom start
|
||||
|
||||
/* define format
|
||||
INCLUDE output_format.ld */
|
||||
OUTPUT_FORMAT("elf32-powerpc")
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
/* define origin, len of rom, ram, csr */
|
||||
INCLUDE regions.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* kernel code */
|
||||
.kernel :
|
||||
{
|
||||
/*_fkernel = .; */
|
||||
*crt0*(.text)
|
||||
KEEP(*crt0*(.text))
|
||||
*(.gnu.linkonce.t.*)
|
||||
_ekernel = .;
|
||||
} > rom
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_frodata = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
*(.got2 .got2.*)
|
||||
*(.toc .toc.*)
|
||||
FILL(0);
|
||||
. = ALIGN(8);
|
||||
_erodata = .;
|
||||
} > rom
|
||||
|
||||
/* bios code */
|
||||
.bios :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
bios.o (.text .text* .gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} > rom
|
||||
|
||||
/* kernel data to be copied to ram by rom code...*/
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_fdata = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
FILL(0);
|
||||
. = ALIGN(8);
|
||||
_edata = .;
|
||||
} > ram AT > rom
|
||||
|
||||
/* tst */
|
||||
.arcitst :
|
||||
{
|
||||
. = ALIGN(32);
|
||||
arcitst.o (.text .text* .gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} > rom
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_fbss = .;
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
} > ram
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.eh_frame)
|
||||
*(.comment)
|
||||
*(.gnu.attributes)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
PROVIDE(_stack_size = 0x00010000);
|
||||
PROVIDE(_stack_0 = ORIGIN(ram) + LENGTH(ram) - 8);
|
||||
PROVIDE(_stack_1 = _stack_0 - _stack_size);
|
||||
|
||||
PROVIDE(_fdata_rom = LOADADDR(.data));
|
||||
PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
|
||||
PROVIDE(_bios_start = LOADADDR(.bios));
|
||||
@ -0,0 +1,14 @@
|
||||
# test3 - kernel+bios+arci
|
||||
|
||||
* gen, convert, and link random tst (fx_alucmpbr.tst), and try to run
|
||||
|
||||
```
|
||||
build
|
||||
|
||||
# create mem file for coco sim
|
||||
cp rom.init test3
|
||||
```
|
||||
|
||||
* hanging during results save; itags not executed in cpl queue
|
||||
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
MEMORY {
|
||||
rom : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
ram : ORIGIN = 0x00010000, LENGTH = 0x00010000
|
||||
csr : ORIGIN = 0xFFF00000, LENGTH = 0x00010000
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,285 @@
|
||||
|
||||
rom: file format elf32-powerpc
|
||||
|
||||
Contents of section .kernel:
|
||||
0000 48000400 48000f30 00000000 00000000 H...H..0........
|
||||
0010 00000000 00000000 00000000 00000000 ................
|
||||
0020 48000cdc 00000000 00000000 00000000 H...............
|
||||
0030 00000000 00000000 00000000 00000000 ................
|
||||
0040 48000000 00000000 00000000 00000000 H...............
|
||||
0050 00000000 00000000 00000000 00000000 ................
|
||||
0060 48000000 00000000 00000000 00000000 H...............
|
||||
0070 00000000 00000000 00000000 00000000 ................
|
||||
0080 48000000 00000000 00000000 00000000 H...............
|
||||
0090 00000000 00000000 00000000 00000000 ................
|
||||
00a0 48000000 00000000 00000000 00000000 H...............
|
||||
00b0 00000000 00000000 00000000 00000000 ................
|
||||
00c0 48000000 00000000 00000000 00000000 H...............
|
||||
00d0 00000000 00000000 00000000 00000000 ................
|
||||
00e0 48000000 00000000 00000000 00000000 H...............
|
||||
00f0 00000000 00000000 00000000 00000000 ................
|
||||
0100 48000000 00000000 00000000 00000000 H...............
|
||||
0110 00000000 00000000 00000000 00000000 ................
|
||||
0120 48000bdc 00000000 00000000 00000000 H...............
|
||||
0130 00000000 00000000 00000000 00000000 ................
|
||||
0140 48000000 00000000 00000000 00000000 H...............
|
||||
0150 00000000 00000000 00000000 00000000 ................
|
||||
0160 48000000 00000000 00000000 00000000 H...............
|
||||
0170 00000000 00000000 00000000 00000000 ................
|
||||
0180 48000000 00000000 00000000 00000000 H...............
|
||||
0190 00000000 00000000 00000000 00000000 ................
|
||||
01a0 48000000 00000000 00000000 00000000 H...............
|
||||
01b0 00000000 00000000 00000000 00000000 ................
|
||||
01c0 48000000 00000000 00000000 00000000 H...............
|
||||
01d0 00000000 00000000 00000000 00000000 ................
|
||||
01e0 48000000 00000000 00000000 00000000 H...............
|
||||
01f0 00000000 00000000 00000000 00000000 ................
|
||||
0200 48000000 00000000 00000000 00000000 H...............
|
||||
0210 00000000 00000000 00000000 00000000 ................
|
||||
0220 48000000 00000000 00000000 00000000 H...............
|
||||
0230 00000000 00000000 00000000 00000000 ................
|
||||
0240 48000000 00000000 00000000 00000000 H...............
|
||||
0250 00000000 00000000 00000000 00000000 ................
|
||||
0260 48000000 00000000 00000000 00000000 H...............
|
||||
0270 00000000 00000000 00000000 00000000 ................
|
||||
0280 48000000 00000000 00000000 00000000 H...............
|
||||
0290 00000000 00000000 00000000 00000000 ................
|
||||
02a0 48000000 00000000 00000000 00000000 H...............
|
||||
02b0 00000000 00000000 00000000 00000000 ................
|
||||
02c0 48000000 00000000 00000000 00000000 H...............
|
||||
02d0 00000000 00000000 00000000 00000000 ................
|
||||
02e0 48000000 00000000 00000000 00000000 H...............
|
||||
02f0 00000000 00000000 00000000 00000000 ................
|
||||
0300 48000000 00000000 00000000 00000000 H...............
|
||||
0310 00000000 00000000 00000000 00000000 ................
|
||||
0320 48000000 00000000 00000000 00000000 H...............
|
||||
0330 00000000 00000000 00000000 00000000 ................
|
||||
0340 48000000 00000000 00000000 00000000 H...............
|
||||
0350 00000000 00000000 00000000 00000000 ................
|
||||
0360 00000000 00000000 00000000 00000000 ................
|
||||
0370 00000000 00000000 00000000 00000000 ................
|
||||
0380 00000000 00000000 00000000 00000000 ................
|
||||
0390 00000000 00000000 00000000 00000000 ................
|
||||
03a0 00000000 00000000 00000000 00000000 ................
|
||||
03b0 00000000 00000000 00000000 00000000 ................
|
||||
03c0 00000000 00000000 00000000 00000000 ................
|
||||
03d0 00000000 00000000 00000000 00000000 ................
|
||||
03e0 00000000 00000000 00000000 00000000 ................
|
||||
03f0 00000000 00000000 00000000 00000000 ................
|
||||
0400 7cbe6aa6 2c250000 408200e0 3c608c00 |.j.,%..@...<`..
|
||||
0410 3800001f 38400015 38800000 3900023f 8...8@..8...9..?
|
||||
0420 7c7cfba6 7c4011a6 7c8009a6 7d0001a6 ||..|@..|...}...
|
||||
0430 4c00012c 39400000 654a0000 614a003f L..,9@..eJ..aJ.?
|
||||
0440 3800001e 38800000 64840001 60840000 8...8...d...`...
|
||||
0450 39000000 65080001 61080000 6108023f 9...e...a...a..?
|
||||
0460 7d4011a6 7c8009a6 7d0001a6 4c00012c }@..|...}...L..,
|
||||
0470 3c608800 3800000f 3840003f 38800000 <`..8...8@.?8...
|
||||
0480 3900023f 7c7cfba6 7c4011a6 7c8009a6 9..?||..|@..|...
|
||||
0490 7d0001a6 4c00012c 3800000d 38800000 }...L..,8...8...
|
||||
04a0 64840001 60840000 39000000 65080001 d...`...9...e...
|
||||
04b0 61080000 6108023f 7d4011a6 7c8009a6 a...a..?}@..|...
|
||||
04c0 7d0001a6 4c00012c 48000004 39400000 }...L..,H...9@..
|
||||
04d0 654a8002 614ab000 7d400124 4c00012c eJ..aJ..}@.$L..,
|
||||
04e0 80200904 48000020 39400000 654a8002 . ..H.. 9@..eJ..
|
||||
04f0 614ab000 7d400124 4c00012c 80200908 aJ..}@.$L..,. ..
|
||||
0500 48000004 3c600000 60630920 7c6903a6 H...<`..`c. |i..
|
||||
0510 7c7e6aa6 4e800421 480002e4 00000000 |~j.N..!H.......
|
||||
0520 00000000 00000000 00000000 00000000 ................
|
||||
0530 00000000 00000000 00000000 00000000 ................
|
||||
0540 00000000 00000000 00000000 00000000 ................
|
||||
0550 00000000 00000000 00000000 00000000 ................
|
||||
0560 00000000 00000000 00000000 00000000 ................
|
||||
0570 00000000 00000000 00000000 00000000 ................
|
||||
0580 00000000 00000000 00000000 00000000 ................
|
||||
0590 00000000 00000000 00000000 00000000 ................
|
||||
05a0 00000000 00000000 00000000 00000000 ................
|
||||
05b0 00000000 00000000 00000000 00000000 ................
|
||||
05c0 00000000 00000000 00000000 00000000 ................
|
||||
05d0 00000000 00000000 00000000 00000000 ................
|
||||
05e0 00000000 00000000 00000000 00000000 ................
|
||||
05f0 00000000 00000000 00000000 00000000 ................
|
||||
0600 00000000 00000000 00000000 00000000 ................
|
||||
0610 00000000 00000000 00000000 00000000 ................
|
||||
0620 00000000 00000000 00000000 00000000 ................
|
||||
0630 00000000 00000000 00000000 00000000 ................
|
||||
0640 00000000 00000000 00000000 00000000 ................
|
||||
0650 00000000 00000000 00000000 00000000 ................
|
||||
0660 00000000 00000000 00000000 00000000 ................
|
||||
0670 00000000 00000000 00000000 00000000 ................
|
||||
0680 00000000 00000000 00000000 00000000 ................
|
||||
0690 00000000 00000000 00000000 00000000 ................
|
||||
06a0 00000000 00000000 00000000 00000000 ................
|
||||
06b0 00000000 00000000 00000000 00000000 ................
|
||||
06c0 00000000 00000000 00000000 00000000 ................
|
||||
06d0 00000000 00000000 00000000 00000000 ................
|
||||
06e0 00000000 00000000 00000000 00000000 ................
|
||||
06f0 00000000 00000000 00000000 00000000 ................
|
||||
0700 00000000 00000000 00000000 00000000 ................
|
||||
0710 00000000 00000000 00000000 00000000 ................
|
||||
0720 00000000 00000000 00000000 00000000 ................
|
||||
0730 00000000 00000000 00000000 00000000 ................
|
||||
0740 00000000 00000000 00000000 00000000 ................
|
||||
0750 00000000 00000000 00000000 00000000 ................
|
||||
0760 00000000 00000000 00000000 00000000 ................
|
||||
0770 00000000 00000000 00000000 00000000 ................
|
||||
0780 00000000 00000000 00000000 00000000 ................
|
||||
0790 00000000 00000000 00000000 00000000 ................
|
||||
07a0 00000000 00000000 00000000 00000000 ................
|
||||
07b0 00000000 00000000 00000000 00000000 ................
|
||||
07c0 00000000 00000000 00000000 00000000 ................
|
||||
07d0 00000000 00000000 00000000 00000000 ................
|
||||
07e0 00000000 00000000 00000000 00000000 ................
|
||||
07f0 00000000 00000000 00000000 48000000 ............H...
|
||||
0800 48000000 00000000 00000000 00000000 H...............
|
||||
0810 00000000 00000000 00000000 00000000 ................
|
||||
0820 48000000 00000000 00000000 00000000 H...............
|
||||
0830 00000000 00000000 00000000 00000000 ................
|
||||
0840 00000000 00000000 00000000 00000000 ................
|
||||
0850 00000000 00000000 00000000 00000000 ................
|
||||
0860 00000000 00000000 00000000 00000000 ................
|
||||
0870 00000000 00000000 00000000 00000000 ................
|
||||
0880 00000000 00000000 00000000 00000000 ................
|
||||
0890 00000000 00000000 00000000 00000000 ................
|
||||
08a0 00000000 00000000 00000000 00000000 ................
|
||||
08b0 00000000 00000000 00000000 00000000 ................
|
||||
08c0 00000000 00000000 00000000 00000000 ................
|
||||
08d0 00000000 00000000 00000000 00000000 ................
|
||||
08e0 00000000 00000000 00000000 00000000 ................
|
||||
Contents of section .rodata:
|
||||
08f0 43520000 58455200 43545200 4c520000 CR..XER.CTR.LR..
|
||||
0900 54415200 0001fff8 0000fff8 00000000 TAR.............
|
||||
Contents of section .bios:
|
||||
0910 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0920 9421ffc0 90610038 3d200001 81290000 .!...a.8= ...)..
|
||||
0930 9121000c 3d200000 39290d20 91210010 .!..= ..9). .!..
|
||||
0940 81210038 2c090000 4182000c 3920ffff .!.8,...A...9 ..
|
||||
0950 48000188 3d200000 81290d00 91210008 H...= ...)...!..
|
||||
0960 48000028 8121000c 39490004 9141000c H..(.!..9I...A..
|
||||
0970 81410008 814a0000 91490000 81210008 .A...J...I...!..
|
||||
0980 39290004 91210008 3d200000 81290d00 9)...!..= ...)..
|
||||
0990 81410008 7c0a4840 4180ffcc 3d200001 .A..|.H@A...= ..
|
||||
09a0 81290000 91210008 48000020 3d200001 .)...!..H.. = ..
|
||||
09b0 81290000 39400000 91490000 81210008 .)..9@...I...!..
|
||||
09c0 39290004 91210008 3d200001 81290000 9)...!..= ...)..
|
||||
09d0 81410008 7c0a4840 4180ffd4 3d200300 .A..|.H@A...= ..
|
||||
09e0 91210034 81210034 3c800000 60840009 .!.4.!.4<...`...
|
||||
09f0 7c934ba6 60000000 39200000 91210030 |.K.`...9 ...!.0
|
||||
0a00 81210030 3c800000 60840009 7c9603a6 .!.0<...`...|...
|
||||
0a10 60000000 39200000 9121002c 8121002c `...9 ...!.,.!.,
|
||||
0a20 3c800000 60840009 7c9d43a6 60000000 <...`...|.C.`...
|
||||
0a30 39200000 91210028 81210028 3c800000 9 ...!.(.!.(<...
|
||||
0a40 60840009 7c9c43a6 60000000 3d20fe00 `...|.C.`...= ..
|
||||
0a50 91210024 81210024 3c800000 60840009 .!.$.!.$<...`...
|
||||
0a60 7c9053a6 60000000 7d36faa6 91210020 |.S.`...}6...!.
|
||||
0a70 81210020 552905ac 9121001c 8121001c .!. U)...!...!..
|
||||
0a80 3c800000 60840009 7c96fba6 60000000 <...`...|...`...
|
||||
0a90 39200000 91210018 81210018 3c800000 9 ...!...!..<...
|
||||
0aa0 60840009 7c9053a6 60000000 39200000 `...|.S.`...9 ..
|
||||
0ab0 91210014 81210014 3c800000 60840009 .!...!..<...`...
|
||||
0ac0 7c9453a6 60000000 81210010 7d234b78 |.S.`....!..}#Kx
|
||||
0ad0 48000370 48000000 7d234b78 38210040 H..pH...}#Kx8!.@
|
||||
0ae0 4e800020 9421ffe0 7c0802a6 90010024 N.. .!..|......$
|
||||
0af0 90610018 39200001 91210008 39200000 .a..9 ...!..9 ..
|
||||
0b00 9121000c 81410018 3d200867 61295309 .!...A..= .ga)S.
|
||||
0b10 7c0a4800 4182000c 39200000 91210008 |.H.A...9 ...!..
|
||||
0b20 81210008 2c090000 41820028 3d200000 .!..,...A..(= ..
|
||||
0b30 388908f0 38600020 48000115 7c691b78 8...8`. H...|i.x
|
||||
0b40 2c090000 4182000c 39200001 48000008 ,...A...9 ..H...
|
||||
0b50 39200000 91210008 81210008 2c090000 9 ...!...!..,...
|
||||
0b60 41820028 3d200000 388908f4 38600021 A..(= ..8...8`.!
|
||||
0b70 480000dd 7c691b78 2c090000 4182000c H...|i.x,...A...
|
||||
0b80 39200001 48000008 39200000 91210008 9 ..H...9 ...!..
|
||||
0b90 81210008 2c090000 41820028 3d200000 .!..,...A..(= ..
|
||||
0ba0 388908f8 38600022 480000a5 7c691b78 8...8`."H...|i.x
|
||||
0bb0 2c090000 4182000c 39200001 48000008 ,...A...9 ..H...
|
||||
0bc0 39200000 91210008 81210008 2c090000 9 ...!...!..,...
|
||||
0bd0 41820028 3d200000 388908fc 38600023 A..(= ..8...8`.#
|
||||
0be0 4800006d 7c691b78 2c090000 4182000c H..m|i.x,...A...
|
||||
0bf0 39200001 48000008 39200000 91210008 9 ..H...9 ...!..
|
||||
0c00 81210008 2c090000 41820028 3d200000 .!..,...A..(= ..
|
||||
0c10 38890900 38600024 48000035 7c691b78 8...8`.$H..5|i.x
|
||||
0c20 2c090000 4182000c 39200001 48000008 ,...A...9 ..H...
|
||||
0c30 39200000 91210008 60000000 80010024 9 ...!..`......$
|
||||
0c40 7c0803a6 38210020 4e800020 9421ffe0 |...8!. N.. .!..
|
||||
0c50 90610018 9081001c 39200001 91210008 .a......9 ...!..
|
||||
0c60 81210018 552a103a 3d200000 39290d20 .!..U*.:= ..9).
|
||||
0c70 7d2a4a14 81290000 9121000c 81210018 }*J..)...!...!..
|
||||
0c80 552a103a 3d200000 39291020 7d2a4a14 U*.:= ..9). }*J.
|
||||
0c90 81290000 91210010 81210018 552a103a .)...!...!..U*.:
|
||||
0ca0 3d200000 392910c0 7d2a4a14 81290000 = ..9)..}*J..)..
|
||||
0cb0 91210014 81410010 81210014 7d494a78 .!...A...!..}IJx
|
||||
0cc0 3149ffff 7d2a4910 5529063e 91210008 1I..}*I.U).>.!..
|
||||
0cd0 81210008 7d234b78 38210020 4e800020 .!..}#Kx8!. N..
|
||||
0ce0 9421fff0 90610008 9081000c 48000248 .!...a......H..H
|
||||
0cf0 60000000 38210010 4e800020 48000000 `...8!..N.. H...
|
||||
Contents of section .arcitst:
|
||||
0d00 696e666f 20746578 74006865 61646572 info text.header
|
||||
0d10 20746578 74000000 00000000 00000000 text...........
|
||||
0d20 00000000 5822c905 ffffffff 91b6d1a3 ....X"..........
|
||||
0d30 ffffffff ffffffff ffffffff ffffffff ................
|
||||
0d40 ffffffff 7e11ee88 ffffffff 7fffffff ....~...........
|
||||
0d50 ffffffff ffffffff 8c20bde6 ffffffff ......... ......
|
||||
0d60 76d0dadf 15111f42 ffffffff 36108e50 v......B....6..P
|
||||
0d70 ffffffff ffffffff 328a0ced ffffffff ........2.......
|
||||
0d80 ffffffff af224c19 ffffffff ffffffff ....."L.........
|
||||
0d90 d624b27a ffffffff ffffffff ffffffff .$.z............
|
||||
0da0 dbfd3628 89f0006e ffffffff ffffffff ..6(...n........
|
||||
0db0 ffffffff 00001104 00010000 00000000 ................
|
||||
0dc0 0000000d 7c61cc14 7d230595 7ac37392 ....|a..}#..z.s.
|
||||
0dd0 7e094c11 7e1cb115 7a338886 7c6004d1 ~.L.~...z3..|`..
|
||||
0de0 7e09b038 7c360591 7e2b00d1 60000000 ~..8|6..~+..`...
|
||||
0df0 60000000 60000000 00010000 00010004 `...`...........
|
||||
0e00 00010008 0001000c 00010010 00010014 ................
|
||||
0e10 00010018 0001001c 00010020 00010024 ........... ...$
|
||||
0e20 00010028 0001002c 00010030 48000014 ...(...,...0H...
|
||||
0e30 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0e40 9023009c 802300a0 7c2903a6 382300a4 .#...#..|)..8#..
|
||||
0e50 384300d8 80810000 80a20000 90850000 8C..............
|
||||
0e60 38210004 38420004 4200ffec 3c804800 8!..8B..B...<.H.
|
||||
0e70 60840006 90850000 80200db4 7c3b03a6 `........ ..|;..
|
||||
0e80 80200df8 7c3a03a6 80230080 7c2ff120 . ..|:...#..|/.
|
||||
0e90 80230084 7c2103a6 80230088 7c2903a6 .#..|!...#..|)..
|
||||
0ea0 8023008c 7c2803a6 80230090 7c2fcba6 .#..|(...#..|/..
|
||||
0eb0 80030000 80230004 80430008 80830010 .....#...C......
|
||||
0ec0 80a30014 80c30018 80e3001c 81030020 ...............
|
||||
0ed0 81230024 81430028 8163002c 81830030 .#.$.C.(.c.,...0
|
||||
0ee0 81a30034 81c30038 81e3003c 82030040 ...4...8...<...@
|
||||
0ef0 82230044 82430048 8263004c 82830050 .#.D.C.H.c.L...P
|
||||
0f00 82a30054 82c30058 82e3005c 83030060 ...T...X...\...`
|
||||
0f10 83230064 83430068 8363006c 83830070 .#.d.C.h.c.l...p
|
||||
0f20 83a30074 83c30078 83e3007c 8063000c ...t...x...|.c..
|
||||
0f30 48010002 4800000c 60000000 60000000 H...H...`...`...
|
||||
0f40 7c2fcba6 3c200000 60211020 90010000 |/..< ..`!. ....
|
||||
0f50 90410008 9061000c 90810010 90a10014 .A...a..........
|
||||
0f60 90c10018 90e1001c 91010020 91210024 ........... .!.$
|
||||
0f70 91410028 9161002c 91810030 91a10034 .A.(.a.,...0...4
|
||||
0f80 91c10038 91e1003c 92010040 92210044 ...8...<...@.!.D
|
||||
0f90 92410048 9261004c 92810050 92a10054 .A.H.a.L...P...T
|
||||
0fa0 92c10058 92e1005c 93010060 93210064 ...X...\...`.!.d
|
||||
0fb0 93410068 9361006c 93810070 93a10074 .A.h.a.l...p...t
|
||||
0fc0 93c10078 93e1007c 7c4fcaa6 90410004 ...x...||O...A..
|
||||
0fd0 7c400026 90410080 7c4102a6 90410084 |@.&.A..|A...A..
|
||||
0fe0 7c4902a6 90410088 7c4802a6 9041008c |I...A..|H...A..
|
||||
0ff0 7c4fcaa6 90410090 3c600000 60630d20 |O...A..<`..`c.
|
||||
1000 8023009c 3c600867 60635309 4bfffad8 .#..<`.g`cS.K...
|
||||
1010 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
1020 ffffffff ffffffff ffffffff ffffffff ................
|
||||
1030 ffffffff ffffffff ffffffff ffffffff ................
|
||||
1040 ffffffff ffffffff ffffffff ffffffff ................
|
||||
1050 ffffffff ffffffff ffffffff ffffffff ................
|
||||
1060 ffffffff ffffffff ffffffff ffffffff ................
|
||||
1070 ffffffff ffffffff ffffffff ffffffff ................
|
||||
1080 ffffffff ffffffff ffffffff ffffffff ................
|
||||
1090 ffffffff ffffffff ffffffff ffffffff ................
|
||||
10a0 ffffffff ffffffff ffffffff ffffffff ................
|
||||
10b0 ffffffff 60000000 60000000 60000000 ....`...`...`...
|
||||
10c0 00000000 cd75f313 ffffffff 00000000 .....u..........
|
||||
10d0 ffffffff ffffffff ffffffff ffffffff ................
|
||||
10e0 ffffffff 008a0c68 ffffffff 7fffffff .......h........
|
||||
10f0 ffffffff ffffffff 8c20bde6 ffffffff ......... ......
|
||||
1100 08aebf68 80000001 ffffffff 00000000 ...h............
|
||||
1110 ffffffff ffffffff 328a0ced ffffffff ........2.......
|
||||
1120 ffffffff af224c19 ffffffff ffffffff ....."L.........
|
||||
1130 d624b27a ffffffff ffffffff ffffffff .$.z............
|
||||
1140 9bfd3628 98f0006e ffffffff ffffffff ..6(...n........
|
||||
1150 ffffffff 00001104 00010038 ...........8
|
||||
@ -0,0 +1 @@
|
||||
../../sim/mem/test3
|
||||
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Reference in New Issue