test3 - cpl hang in results save
openpowerwtf
1 year ago
parent
b79536e583
commit
7d5b53f672
@ -1,5 +1,15 @@
|
||||
# Kernel updates/build process
|
||||
|
||||
* test1 - minimal updates to kernel; add linker script and build kernel and test separately
|
||||
* passed coco sim
|
||||
### test1
|
||||
* 32b crosscompile
|
||||
* minimal updates to kernel; add linker script and build kernel and test separately
|
||||
* passed coco sim
|
||||
|
||||
### test2
|
||||
* 32b crosscompile
|
||||
* update kernel for minimal setup and branch to bios C code; add linker script and build kernel and test separately
|
||||
* passed coco sim
|
||||
|
||||
### test3
|
||||
* 32b crosscompile
|
||||
* add bios code to execute and check a .tst; link test.s
|
||||
|
||||
@ -0,0 +1,297 @@
|
||||
# asmtst.tpl
|
||||
# powerpc-linux-gnu-as -c arcitst.s
|
||||
|
||||
.include "defines.s"
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
# c-accessible
|
||||
|
||||
.global init_tst
|
||||
.global tst_start
|
||||
.global tst_end
|
||||
.global tst_inits
|
||||
.global tst_results
|
||||
.global tst_expects
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
tst_misc:
|
||||
|
||||
tst_info: .asciz "info text"
|
||||
tst_header: .asciz "header text"
|
||||
|
||||
.set SAVESPR,sprg3
|
||||
.set MAGIC,0x8675309
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_inits:
|
||||
|
||||
init_r0: .int 0x5EA9536C
|
||||
init_r1: .int 0x07EC9BA7
|
||||
init_r2: .int 0xFFFFFFFF
|
||||
init_r3: .int 0x18FAD811
|
||||
init_r4: .int 0xFFFFFFFF
|
||||
init_r5: .int 0xFFFFFFFF
|
||||
init_r6: .int 0xFFFFFFFF
|
||||
init_r7: .int 0xFFFFFFFF
|
||||
init_r8: .int 0xFFFFFFFF
|
||||
init_r9: .int 0xFFFFFFFF
|
||||
init_r10: .int 0xB186394A
|
||||
init_r11: .int 0x07EC9BA7
|
||||
init_r12: .int 0xFFFFFFFF
|
||||
init_r13: .int 0xFC9D07CE
|
||||
init_r14: .int 0x7305868F
|
||||
init_r15: .int 0xFFFFFFFF
|
||||
init_r16: .int 0xFFFFFFFF
|
||||
init_r17: .int 0x6E078D56
|
||||
init_r18: .int 0xFFFFFFFF
|
||||
init_r19: .int 0xFFFFFFFF
|
||||
init_r20: .int 0x0F8F2BB1
|
||||
init_r21: .int 0xFFFFFFFF
|
||||
init_r22: .int 0xFFFFFFFF
|
||||
init_r23: .int 0x9E47F6C0
|
||||
init_r24: .int 0x46B0FC81
|
||||
init_r25: .int 0xFFFFFFFF
|
||||
init_r26: .int 0xFFFFFFFF
|
||||
init_r27: .int 0x48026438
|
||||
init_r28: .int 0xEFB046E4
|
||||
init_r29: .int 0x4B5CBE25
|
||||
init_r30: .int 0xFFFFFFFF
|
||||
init_r31: .int 0xFFFFFFFF
|
||||
|
||||
init_cr: .int 0xB0215BC8
|
||||
init_xer: .int 0xBFC0004B
|
||||
init_ctr: .int 0xF7DA2C8A
|
||||
init_lr: .int 0x8BC7C22B
|
||||
init_tar: .int 0xFFFFFFFF
|
||||
init_msr: .int 0x00001081
|
||||
|
||||
init_iar: .int 0x00010000
|
||||
|
||||
save_r1: .int 0
|
||||
|
||||
codelen: .int 13
|
||||
ops: .int 0x36E86A7F,0x10748A7F,0x71AE9D7E,0x1C865B55,0xF45EAA7D,0x2000154D,0x50E01B7C,0x4933037B,0x00082B7D,0x36B8317C,0x00000060,0x00000060,0x00000060
|
||||
iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x0001001C,0x00010020,0x00010024,0x00010028,0x0001002C,0x00010030
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
# r3=@tst_inits
|
||||
.align 5
|
||||
init_tst:
|
||||
|
||||
# save c stuff
|
||||
stw r1,(save_r1-tst_inits)(r3)
|
||||
|
||||
# copy ops
|
||||
opcopy:
|
||||
lwz r1,(codelen-tst_inits)(r3)
|
||||
mtctr r1
|
||||
opcopy_loop:
|
||||
la r1,(cops-tst_inits)(r3)
|
||||
la r2,(iars-tst_inits)(r3)
|
||||
stw r1,0(r2)
|
||||
addi r2,r2,4
|
||||
bdnz opcopy_loop
|
||||
|
||||
# init test regs
|
||||
init_regs:
|
||||
lwz r1,(init_cr-tst_inits)(r3)
|
||||
mtcr r1
|
||||
lwz r1,(init_xer-tst_inits)(r3)
|
||||
mtxer r1
|
||||
lwz r1,(init_ctr-tst_inits)(r3)
|
||||
mtctr r1
|
||||
lwz r1,(init_lr-tst_inits)(r3)
|
||||
mtlr r1
|
||||
lwz r1,(init_tar-tst_inits)(r3)
|
||||
mtspr tar,r1
|
||||
|
||||
lwz r0,(init_r0-tst_inits)(r3)
|
||||
lwz r1,(init_r1-tst_inits)(r3)
|
||||
lwz r2,(init_r2-tst_inits)(r3)
|
||||
lwz r4,(init_r4-tst_inits)(r3)
|
||||
lwz r5,(init_r5-tst_inits)(r3)
|
||||
lwz r6,(init_r6-tst_inits)(r3)
|
||||
lwz r7,(init_r7-tst_inits)(r3)
|
||||
lwz r8,(init_r8-tst_inits)(r3)
|
||||
lwz r9,(init_r9-tst_inits)(r3)
|
||||
lwz r10,(init_r10-tst_inits)(r3)
|
||||
lwz r11,(init_r11-tst_inits)(r3)
|
||||
lwz r12,(init_r12-tst_inits)(r3)
|
||||
lwz r13,(init_r13-tst_inits)(r3)
|
||||
lwz r14,(init_r14-tst_inits)(r3)
|
||||
lwz r15,(init_r15-tst_inits)(r3)
|
||||
lwz r16,(init_r16-tst_inits)(r3)
|
||||
lwz r17,(init_r17-tst_inits)(r3)
|
||||
lwz r18,(init_r18-tst_inits)(r3)
|
||||
lwz r19,(init_r19-tst_inits)(r3)
|
||||
lwz r20,(init_r20-tst_inits)(r3)
|
||||
lwz r21,(init_r21-tst_inits)(r3)
|
||||
lwz r22,(init_r22-tst_inits)(r3)
|
||||
lwz r23,(init_r23-tst_inits)(r3)
|
||||
lwz r24,(init_r24-tst_inits)(r3)
|
||||
lwz r25,(init_r25-tst_inits)(r3)
|
||||
lwz r26,(init_r26-tst_inits)(r3)
|
||||
lwz r27,(init_r27-tst_inits)(r3)
|
||||
lwz r28,(init_r28-tst_inits)(r3)
|
||||
lwz r29,(init_r29-tst_inits)(r3)
|
||||
lwz r30,(init_r30-tst_inits)(r3)
|
||||
lwz r31,(init_r31-tst_inits)(r3)
|
||||
lwz r3,(init_r3-tst_inits)(r3)
|
||||
|
||||
jmp2tst: rfi
|
||||
|
||||
# needs to be inserted into epilogue of tst!
|
||||
#tst_end:
|
||||
# b save_results
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
save_results:
|
||||
# use a designated spr to save (sprgx, ...)
|
||||
mtspr SAVESPR,r1
|
||||
lis r1,tst_results@h
|
||||
ori r1,r1,tst_results@l
|
||||
stw r0,(rslt_r0-tst_results)(r1)
|
||||
stw r2,(rslt_r2-tst_results)(r1)
|
||||
stw r3,(rslt_r3-tst_results)(r1)
|
||||
stw r4,(rslt_r4-tst_results)(r1)
|
||||
stw r5,(rslt_r5-tst_results)(r1)
|
||||
stw r6,(rslt_r6-tst_results)(r1)
|
||||
stw r7,(rslt_r7-tst_results)(r1)
|
||||
stw r8,(rslt_r8-tst_results)(r1)
|
||||
stw r9,(rslt_r9-tst_results)(r1)
|
||||
stw r10,(rslt_r10-tst_results)(r1)
|
||||
stw r11,(rslt_r11-tst_results)(r1)
|
||||
stw r12,(rslt_r12-tst_results)(r1)
|
||||
stw r13,(rslt_r13-tst_results)(r1)
|
||||
stw r14,(rslt_r14-tst_results)(r1)
|
||||
stw r15,(rslt_r15-tst_results)(r1)
|
||||
stw r16,(rslt_r16-tst_results)(r1)
|
||||
stw r17,(rslt_r17-tst_results)(r1)
|
||||
stw r18,(rslt_r18-tst_results)(r1)
|
||||
stw r19,(rslt_r19-tst_results)(r1)
|
||||
stw r20,(rslt_r20-tst_results)(r1)
|
||||
stw r21,(rslt_r21-tst_results)(r1)
|
||||
stw r22,(rslt_r22-tst_results)(r1)
|
||||
stw r23,(rslt_r23-tst_results)(r1)
|
||||
stw r24,(rslt_r24-tst_results)(r1)
|
||||
stw r25,(rslt_r25-tst_results)(r1)
|
||||
stw r26,(rslt_r26-tst_results)(r1)
|
||||
stw r27,(rslt_r27-tst_results)(r1)
|
||||
stw r28,(rslt_r28-tst_results)(r1)
|
||||
stw r29,(rslt_r29-tst_results)(r1)
|
||||
stw r30,(rslt_r30-tst_results)(r1)
|
||||
stw r31,(rslt_r31-tst_results)(r1)
|
||||
mfspr r2,SAVESPR
|
||||
stw r2,(rslt_r1-tst_results)(r1)
|
||||
mfcr r2
|
||||
stw r2,(rslt_cr-tst_results)(r1)
|
||||
mfxer r2
|
||||
stw r2,(rslt_xer-tst_results)(r1)
|
||||
mfctr r2
|
||||
stw r2,(rslt_ctr-tst_results)(r1)
|
||||
mflr r2
|
||||
stw r2,(rslt_lr-tst_results)(r1)
|
||||
mfspr r2,tar
|
||||
stw r2,(rslt_tar-tst_results)(r1)
|
||||
|
||||
tst_cleanup:
|
||||
# restore c stuff
|
||||
lis r3,tst_inits@h
|
||||
ori r3,r3,tst_inits@l
|
||||
lwz r1,(save_r1-tst_inits)(r3)
|
||||
lis r3,MAGIC@h
|
||||
ori r3,r3,MAGIC@l
|
||||
|
||||
b tst_done
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_results:
|
||||
|
||||
rslt_r0: .int 0xFFFFFFFF
|
||||
rslt_r1: .int 0xFFFFFFFF
|
||||
rslt_r2: .int 0xFFFFFFFF
|
||||
rslt_r3: .int 0xFFFFFFFF
|
||||
rslt_r4: .int 0xFFFFFFFF
|
||||
rslt_r5: .int 0xFFFFFFFF
|
||||
rslt_r6: .int 0xFFFFFFFF
|
||||
rslt_r7: .int 0xFFFFFFFF
|
||||
rslt_r8: .int 0xFFFFFFFF
|
||||
rslt_r9: .int 0xFFFFFFFF
|
||||
rslt_r10: .int 0xFFFFFFFF
|
||||
rslt_r11: .int 0xFFFFFFFF
|
||||
rslt_r12: .int 0xFFFFFFFF
|
||||
rslt_r13: .int 0xFFFFFFFF
|
||||
rslt_r14: .int 0xFFFFFFFF
|
||||
rslt_r15: .int 0xFFFFFFFF
|
||||
rslt_r16: .int 0xFFFFFFFF
|
||||
rslt_r17: .int 0xFFFFFFFF
|
||||
rslt_r18: .int 0xFFFFFFFF
|
||||
rslt_r19: .int 0xFFFFFFFF
|
||||
rslt_r20: .int 0xFFFFFFFF
|
||||
rslt_r21: .int 0xFFFFFFFF
|
||||
rslt_r22: .int 0xFFFFFFFF
|
||||
rslt_r23: .int 0xFFFFFFFF
|
||||
rslt_r24: .int 0xFFFFFFFF
|
||||
rslt_r25: .int 0xFFFFFFFF
|
||||
rslt_r26: .int 0xFFFFFFFF
|
||||
rslt_r27: .int 0xFFFFFFFF
|
||||
rslt_r28: .int 0xFFFFFFFF
|
||||
rslt_r29: .int 0xFFFFFFFF
|
||||
rslt_r30: .int 0xFFFFFFFF
|
||||
rslt_r31: .int 0xFFFFFFFF
|
||||
|
||||
rslt_cr: .int 0xFFFFFFFF
|
||||
rslt_xer: .int 0xFFFFFFFF
|
||||
rslt_ctr: .int 0xFFFFFFFF
|
||||
rslt_lr: .int 0xFFFFFFFF
|
||||
rslt_tar: .int 0xFFFFFFFF
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_expects:
|
||||
|
||||
expt_r0: .int 0x7305868F
|
||||
expt_r1: .int 0x07EC9BA7
|
||||
expt_r2: .int 0xFFFFFFFF
|
||||
expt_r3: .int 0xAC3F2040
|
||||
expt_r4: .int 0xFFFFFFFF
|
||||
expt_r5: .int 0xFFFFFFFF
|
||||
expt_r6: .int 0xFFFFFFFF
|
||||
expt_r7: .int 0xFFFFFFFF
|
||||
expt_r8: .int 0xFFFFFFFF
|
||||
expt_r9: .int 0xFFFFFFFF
|
||||
expt_r10: .int 0xE83E7000
|
||||
expt_r11: .int 0x07EC9BA7
|
||||
expt_r12: .int 0xFFFFFFFF
|
||||
expt_r13: .int 0xFC9D07CE
|
||||
expt_r14: .int 0x7305868F
|
||||
expt_r15: .int 0xFFFFFFFF
|
||||
expt_r16: .int 0xFFFFFFFF
|
||||
expt_r17: .int 0x00000000
|
||||
expt_r18: .int 0xFFFFFFFF
|
||||
expt_r19: .int 0xFFFFFFFF
|
||||
expt_r20: .int 0x0F8F2BB1
|
||||
expt_r21: .int 0xFFFFFFFF
|
||||
expt_r22: .int 0xFFFFFFFF
|
||||
expt_r23: .int 0x9E47F6C0
|
||||
expt_r24: .int 0x46B0FC81
|
||||
expt_r25: .int 0xFFFFFFFF
|
||||
expt_r26: .int 0xFFFFFFFF
|
||||
expt_r27: .int 0x00000000
|
||||
expt_r28: .int 0x7305868F
|
||||
expt_r29: .int 0x0000007C
|
||||
expt_r30: .int 0xFFFFFFFF
|
||||
expt_r31: .int 0xFFFFFFFF
|
||||
|
||||
expt_cr: .int 0x90315BC8
|
||||
expt_xer: .int 0x82C0004B
|
||||
expt_ctr: .int 0xF7DA2C89
|
||||
expt_lr: .int 0x8BC7C22B
|
||||
expt_tar: .int 0xFFFFFFFF
|
||||
expt_msr: .int 0x00001081
|
||||
|
||||
expt_iar: .int 0x00010038
|
||||
|
||||
@ -0,0 +1,492 @@
|
||||
1 # asmtst.tpl
|
||||
2
|
||||
3 .include "defines.s"
|
||||
1 # © IBM Corp. 2020
|
||||
2 # Licensed under and subject to the terms of the CC-BY 4.0
|
||||
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
4 # Additional rights, including the right to physically implement a softcore
|
||||
5 # that is compliant with the required sections of the Power ISA
|
||||
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
7 # This README will be updated with additional information when OpenPOWER's
|
||||
8 # license is available.
|
||||
9
|
||||
10 #-----------------------------------------
|
||||
11 # Defines
|
||||
12 #-----------------------------------------
|
||||
13
|
||||
14 # Regs
|
||||
15
|
||||
16 .set r0, 0
|
||||
17 .set r1, 1
|
||||
18 .set r2, 2
|
||||
19 .set r3, 3
|
||||
20 .set r4, 4
|
||||
21 .set r5, 5
|
||||
22 .set r6, 6
|
||||
23 .set r7, 7
|
||||
24 .set r8, 8
|
||||
25 .set r9, 9
|
||||
26 .set r10,10
|
||||
27 .set r11,11
|
||||
28 .set r12,12
|
||||
29 .set r13,13
|
||||
30 .set r14,14
|
||||
31 .set r15,15
|
||||
32 .set r16,16
|
||||
33 .set r17,17
|
||||
34 .set r18,18
|
||||
35 .set r19,19
|
||||
36 .set r20,20
|
||||
37 .set r21,21
|
||||
38 .set r22,22
|
||||
39 .set r23,23
|
||||
40 .set r24,24
|
||||
41 .set r25,25
|
||||
42 .set r26,26
|
||||
43 .set r27,27
|
||||
44 .set r28,28
|
||||
45 .set r29,29
|
||||
46 .set r30,30
|
||||
47 .set r31,31
|
||||
48
|
||||
49 .set f0, 0
|
||||
50 .set f1, 1
|
||||
51 .set f2, 2
|
||||
52 .set f3, 3
|
||||
53 .set f4, 4
|
||||
54 .set f5, 5
|
||||
55 .set f6, 6
|
||||
56 .set f7, 7
|
||||
57 .set f8, 8
|
||||
58 .set f9, 9
|
||||
59 .set f10,10
|
||||
60 .set f11,11
|
||||
61 .set f12,12
|
||||
62 .set f13,13
|
||||
63 .set f14,14
|
||||
64 .set f15,15
|
||||
65 .set f16,16
|
||||
66 .set f17,17
|
||||
67 .set f18,18
|
||||
68 .set f19,19
|
||||
69 .set f20,20
|
||||
70 .set f21,21
|
||||
71 .set f22,22
|
||||
72 .set f23,23
|
||||
73 .set f24,24
|
||||
74 .set f25,25
|
||||
75 .set f26,26
|
||||
76 .set f27,27
|
||||
77 .set f28,28
|
||||
78 .set f29,29
|
||||
79 .set f30,30
|
||||
80 .set f31,31
|
||||
81
|
||||
82 .set cr0, 0
|
||||
83 .set cr1, 1
|
||||
84 .set cr2, 2
|
||||
85 .set cr3, 3
|
||||
86 .set cr4, 4
|
||||
87 .set cr5, 5
|
||||
88 .set cr6, 6
|
||||
89 .set cr7, 7
|
||||
90
|
||||
91 # SPR numbers
|
||||
92
|
||||
93 .set srr0, 26
|
||||
94 .set srr1, 27
|
||||
95 .set dar, 19
|
||||
96 .set dsisr, 18
|
||||
97 .set epcr, 307
|
||||
98 .set tar, 815
|
||||
99
|
||||
100 .set dbsr, 304
|
||||
101 .set dbcr0, 308
|
||||
102 .set dbcr1, 309
|
||||
103 .set dbcr2, 310
|
||||
104 .set dbcr3, 848
|
||||
105
|
||||
106 .set ivpr, 63
|
||||
107
|
||||
108 .set iucr0, 1011
|
||||
109 .set iucr1, 883
|
||||
110 .set iucr2, 884
|
||||
111
|
||||
112 .set iudbg0, 888
|
||||
113 .set iudbg1, 889
|
||||
114 .set iudbg2, 890
|
||||
115 .set iulfsr, 891
|
||||
116 .set iullcr, 892
|
||||
117
|
||||
118 .set mmucr0, 1020
|
||||
119 .set mmucr1, 1021
|
||||
120 .set mmucr2, 1022
|
||||
121 .set mmucr3, 1023
|
||||
122
|
||||
123 .set tb, 268
|
||||
124 .set tbl, 284
|
||||
125 .set tbh, 285
|
||||
126
|
||||
127 .set dec, 22
|
||||
128 .set udec, 550
|
||||
129 .set tsr, 336
|
||||
130 .set tcr, 340
|
||||
131
|
||||
132 .set xucr0, 1014
|
||||
133 .set xucr1, 851
|
||||
134 .set xucr2, 1016
|
||||
135 .set xucr3, 852
|
||||
136 .set xucr4, 853
|
||||
137
|
||||
138 .set tens, 438
|
||||
139 .set tenc, 439
|
||||
140 .set tensr, 437
|
||||
141
|
||||
142 .set pid, 48
|
||||
143 .set pir, 286
|
||||
144 .set pvr, 287
|
||||
145 .set tir, 446
|
||||
146
|
||||
147 #.set sprg0,
|
||||
148 #.set sprg1,
|
||||
149 #.set sprg2,
|
||||
150 .set sprg3, 259
|
||||
4
|
||||
5 # -------------------------------------------------------------------------------------------------
|
||||
6 # c-accessible
|
||||
7
|
||||
8 .global init_tst
|
||||
9 .global tst_start
|
||||
10 .global tst_end
|
||||
11 .global tst_inits
|
||||
12 .global tst_results
|
||||
13 .global tst_expects
|
||||
14
|
||||
15 # -------------------------------------------------------------------------------------------------
|
||||
16 tst_misc:
|
||||
17
|
||||
18 0000 696E666F tst_info: .asciz "info text"
|
||||
18 20746578
|
||||
18 7400
|
||||
19 000a 68656164 tst_header: .asciz "header text"
|
||||
19 65722074
|
||||
19 65787400
|
||||
20
|
||||
21 .set SAVESPR,tar
|
||||
22 .set MAGIC,0x8675309
|
||||
23
|
||||
24 # -------------------------------------------------------------------------------------------------
|
||||
25 0016 00000000 .align 5
|
||||
25 00000000
|
||||
25 0000
|
||||
26 tst_inits:
|
||||
27
|
||||
28 0020 00000000 init_r0: .int 0x00000000
|
||||
29 0024 5822C905 init_r1: .int 0x5822C905
|
||||
30 0028 FFFFFFFF init_r2: .int 0xFFFFFFFF
|
||||
31 002c 91B6D1A3 init_r3: .int 0x91B6D1A3
|
||||
32 0030 FFFFFFFF init_r4: .int 0xFFFFFFFF
|
||||
33 0034 FFFFFFFF init_r5: .int 0xFFFFFFFF
|
||||
34 0038 FFFFFFFF init_r6: .int 0xFFFFFFFF
|
||||
35 003c FFFFFFFF init_r7: .int 0xFFFFFFFF
|
||||
36 0040 FFFFFFFF init_r8: .int 0xFFFFFFFF
|
||||
37 0044 7E11EE88 init_r9: .int 0x7E11EE88
|
||||
38 0048 FFFFFFFF init_r10: .int 0xFFFFFFFF
|
||||
39 004c 7FFFFFFF init_r11: .int 0x7FFFFFFF
|
||||
40 0050 FFFFFFFF init_r12: .int 0xFFFFFFFF
|
||||
41 0054 FFFFFFFF init_r13: .int 0xFFFFFFFF
|
||||
42 0058 8C20BDE6 init_r14: .int 0x8C20BDE6
|
||||
43 005c FFFFFFFF init_r15: .int 0xFFFFFFFF
|
||||
44 0060 76D0DADF init_r16: .int 0x76D0DADF
|
||||
45 0064 15111F42 init_r17: .int 0x15111F42
|
||||
46 0068 FFFFFFFF init_r18: .int 0xFFFFFFFF
|
||||
47 006c 36108E50 init_r19: .int 0x36108E50
|
||||
48 0070 FFFFFFFF init_r20: .int 0xFFFFFFFF
|
||||
49 0074 FFFFFFFF init_r21: .int 0xFFFFFFFF
|
||||
50 0078 328A0CED init_r22: .int 0x328A0CED
|
||||
51 007c FFFFFFFF init_r23: .int 0xFFFFFFFF
|
||||
52 0080 FFFFFFFF init_r24: .int 0xFFFFFFFF
|
||||
53 0084 AF224C19 init_r25: .int 0xAF224C19
|
||||
54 0088 FFFFFFFF init_r26: .int 0xFFFFFFFF
|
||||
55 008c FFFFFFFF init_r27: .int 0xFFFFFFFF
|
||||
56 0090 D624B27A init_r28: .int 0xD624B27A
|
||||
57 0094 FFFFFFFF init_r29: .int 0xFFFFFFFF
|
||||
58 0098 FFFFFFFF init_r30: .int 0xFFFFFFFF
|
||||
59 009c FFFFFFFF init_r31: .int 0xFFFFFFFF
|
||||
60
|
||||
61 00a0 DBFD3628 init_cr: .int 0xDBFD3628
|
||||
62 00a4 89F0006E init_xer: .int 0x89F0006E
|
||||
63 00a8 FFFFFFFF init_ctr: .int 0xFFFFFFFF
|
||||
64 00ac FFFFFFFF init_lr: .int 0xFFFFFFFF
|
||||
65 00b0 FFFFFFFF init_tar: .int 0xFFFFFFFF
|
||||
66 00b4 00001104 init_msr: .int 0x00001104
|
||||
67
|
||||
68 00b8 00010000 init_iar: .int 0x00010000
|
||||
69
|
||||
70 00bc 00000000 save_r1: .int 0
|
||||
71
|
||||
72 00c0 0000000D codelen: .int 13
|
||||
73 00c4 7C61CC14 ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x
|
||||
73 7D230595
|
||||
73 7AC37392
|
||||
73 7E094C11
|
||||
73 7E1CB115
|
||||
74 00f8 00010000 iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x
|
||||
74 00010004
|
||||
74 00010008
|
||||
74 0001000C
|
||||
74 00010010
|
||||
75
|
||||
76 # -------------------------------------------------------------------------------------------------
|
||||
77 # r3=@tst_inits
|
||||
78 012c 48000014 .align 5
|
||||
78 60000000
|
||||
78 60000000
|
||||
78 60000000
|
||||
78 60000000
|
||||
79 init_tst:
|
||||
80
|
||||
81 # save c stuff
|
||||
82 0140 9023009C stw r1,(save_r1-tst_inits)(r3)
|
||||
83
|
||||
84 # copy ops
|
||||
85 opcopy:
|
||||
86 0144 802300A0 lwz r1,(codelen-tst_inits)(r3)
|
||||
87 0148 7C2903A6 mtctr r1
|
||||
88 014c 382300A4 la r1,(ops-tst_inits)(r3) # @ ops list
|
||||
89 0150 384300D8 la r2,(iars-tst_inits)(r3) # @ iars list
|
||||
90 opcopy_loop:
|
||||
91 0154 80810000 lwz r4,0(r1) # next op
|
||||
92 0158 80A20000 lwz r5,0(r2) # next iar
|
||||
93 015c 90850000 stw r4,0(r5) # store it
|
||||
94 0160 38210004 addi r1,r1,4 # inc to next
|
||||
95 0164 38420004 addi r2,r2,4
|
||||
96 0168 4200FFEC bdnz opcopy_loop
|
||||
97
|
||||
98 # add end of test op - could be done here or by builder
|
||||
99 # ways to end:
|
||||
100 # ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
|
||||
101 # trap,sc,scv - branch to tst_end in handler
|
||||
102 # attn, priv op, etc. - "
|
||||
103 # overwrite the last epilogue op to avoid any crossing
|
||||
104 opcopy_eot:
|
||||
105 016c 3C804800 lis r4,0x4800
|
||||
106 0170 60840006 ori r4,r4,0x0006 # ba 0x0004
|
||||
107 0174 90850000 stw r4,0(r5)
|
||||
108
|
||||
109 # get tst start
|
||||
110 0178 80200000 lwz r1,init_msr(r0)
|
||||
111 017c 7C3B03A6 mtsrr1 r1
|
||||
112 0180 80200000 lwz r1,iars(r0)
|
||||
113 0184 7C3A03A6 mtsrr0 r1
|
||||
114
|
||||
115 # init test regs
|
||||
116 init_regs:
|
||||
117 0188 80230080 lwz r1,(init_cr-tst_inits)(r3)
|
||||
118 018c 7C2FF120 mtcr r1
|
||||
119 0190 80230084 lwz r1,(init_xer-tst_inits)(r3)
|
||||
120 0194 7C2103A6 mtxer r1
|
||||
121 0198 80230088 lwz r1,(init_ctr-tst_inits)(r3)
|
||||
122 019c 7C2903A6 mtctr r1
|
||||
123 01a0 8023008C lwz r1,(init_lr-tst_inits)(r3)
|
||||
124 01a4 7C2803A6 mtlr r1
|
||||
125 01a8 80230090 lwz r1,(init_tar-tst_inits)(r3)
|
||||
126 01ac 7C2FCBA6 mtspr tar,r1
|
||||
127
|
||||
128 01b0 80030000 lwz r0,(init_r0-tst_inits)(r3)
|
||||
129 01b4 80230004 lwz r1,(init_r1-tst_inits)(r3)
|
||||
130 01b8 80430008 lwz r2,(init_r2-tst_inits)(r3)
|
||||
131 01bc 80830010 lwz r4,(init_r4-tst_inits)(r3)
|
||||
132 01c0 80A30014 lwz r5,(init_r5-tst_inits)(r3)
|
||||
133 01c4 80C30018 lwz r6,(init_r6-tst_inits)(r3)
|
||||
134 01c8 80E3001C lwz r7,(init_r7-tst_inits)(r3)
|
||||
135 01cc 81030020 lwz r8,(init_r8-tst_inits)(r3)
|
||||
136 01d0 81230024 lwz r9,(init_r9-tst_inits)(r3)
|
||||
137 01d4 81430028 lwz r10,(init_r10-tst_inits)(r3)
|
||||
138 01d8 8163002C lwz r11,(init_r11-tst_inits)(r3)
|
||||
139 01dc 81830030 lwz r12,(init_r12-tst_inits)(r3)
|
||||
140 01e0 81A30034 lwz r13,(init_r13-tst_inits)(r3)
|
||||
141 01e4 81C30038 lwz r14,(init_r14-tst_inits)(r3)
|
||||
142 01e8 81E3003C lwz r15,(init_r15-tst_inits)(r3)
|
||||
143 01ec 82030040 lwz r16,(init_r16-tst_inits)(r3)
|
||||
144 01f0 82230044 lwz r17,(init_r17-tst_inits)(r3)
|
||||
145 01f4 82430048 lwz r18,(init_r18-tst_inits)(r3)
|
||||
146 01f8 8263004C lwz r19,(init_r19-tst_inits)(r3)
|
||||
147 01fc 82830050 lwz r20,(init_r20-tst_inits)(r3)
|
||||
148 0200 82A30054 lwz r21,(init_r21-tst_inits)(r3)
|
||||
149 0204 82C30058 lwz r22,(init_r22-tst_inits)(r3)
|
||||
150 0208 82E3005C lwz r23,(init_r23-tst_inits)(r3)
|
||||
151 020c 83030060 lwz r24,(init_r24-tst_inits)(r3)
|
||||
152 0210 83230064 lwz r25,(init_r25-tst_inits)(r3)
|
||||
153 0214 83430068 lwz r26,(init_r26-tst_inits)(r3)
|
||||
154 0218 8363006C lwz r27,(init_r27-tst_inits)(r3)
|
||||
155 021c 83830070 lwz r28,(init_r28-tst_inits)(r3)
|
||||
156 0220 83A30074 lwz r29,(init_r29-tst_inits)(r3)
|
||||
157 0224 83C30078 lwz r30,(init_r30-tst_inits)(r3)
|
||||
158 0228 83E3007C lwz r31,(init_r31-tst_inits)(r3)
|
||||
159 022c 8063000C lwz r3,(init_r3-tst_inits)(r3)
|
||||
160
|
||||
161 jmp2tst:
|
||||
162 #rfi
|
||||
163 #rfid
|
||||
164 0230 48010002 ba 0x10000
|
||||
165
|
||||
166 tst_end:
|
||||
167 0234 4800000C b save_results
|
||||
168
|
||||
169 # -------------------------------------------------------------------------------------------------
|
||||
170 0238 60000000 .align 5
|
||||
170 60000000
|
||||
171 save_results:
|
||||
172 # use a designated spr to save (sprgx, ...)
|
||||
173 0240 7C2FCBA6 mtspr SAVESPR,r1
|
||||
174 0244 3C200000 lis r1,tst_results@h
|
||||
175 0248 60210000 ori r1,r1,tst_results@l
|
||||
176 024c 90010000 stw r0,(rslt_r0-tst_results)(r1)
|
||||
177 0250 90410008 stw r2,(rslt_r2-tst_results)(r1)
|
||||
178 0254 9061000C stw r3,(rslt_r3-tst_results)(r1)
|
||||
179 0258 90810010 stw r4,(rslt_r4-tst_results)(r1)
|
||||
180 025c 90A10014 stw r5,(rslt_r5-tst_results)(r1)
|
||||
181 0260 90C10018 stw r6,(rslt_r6-tst_results)(r1)
|
||||
182 0264 90E1001C stw r7,(rslt_r7-tst_results)(r1)
|
||||
183 0268 91010020 stw r8,(rslt_r8-tst_results)(r1)
|
||||
184 026c 91210024 stw r9,(rslt_r9-tst_results)(r1)
|
||||
185 0270 91410028 stw r10,(rslt_r10-tst_results)(r1)
|
||||
186 0274 9161002C stw r11,(rslt_r11-tst_results)(r1)
|
||||
187 0278 91810030 stw r12,(rslt_r12-tst_results)(r1)
|
||||
188 027c 91A10034 stw r13,(rslt_r13-tst_results)(r1)
|
||||
189 0280 91C10038 stw r14,(rslt_r14-tst_results)(r1)
|
||||
190 0284 91E1003C stw r15,(rslt_r15-tst_results)(r1)
|
||||
191 0288 92010040 stw r16,(rslt_r16-tst_results)(r1)
|
||||
192 028c 92210044 stw r17,(rslt_r17-tst_results)(r1)
|
||||
193 0290 92410048 stw r18,(rslt_r18-tst_results)(r1)
|
||||
194 0294 9261004C stw r19,(rslt_r19-tst_results)(r1)
|
||||
195 0298 92810050 stw r20,(rslt_r20-tst_results)(r1)
|
||||
196 029c 92A10054 stw r21,(rslt_r21-tst_results)(r1)
|
||||
197 02a0 92C10058 stw r22,(rslt_r22-tst_results)(r1)
|
||||
198 02a4 92E1005C stw r23,(rslt_r23-tst_results)(r1)
|
||||
199 02a8 93010060 stw r24,(rslt_r24-tst_results)(r1)
|
||||
200 02ac 93210064 stw r25,(rslt_r25-tst_results)(r1)
|
||||
201 02b0 93410068 stw r26,(rslt_r26-tst_results)(r1)
|
||||
202 02b4 9361006C stw r27,(rslt_r27-tst_results)(r1)
|
||||
203 02b8 93810070 stw r28,(rslt_r28-tst_results)(r1)
|
||||
204 02bc 93A10074 stw r29,(rslt_r29-tst_results)(r1)
|
||||
205 02c0 93C10078 stw r30,(rslt_r30-tst_results)(r1)
|
||||
206 02c4 93E1007C stw r31,(rslt_r31-tst_results)(r1)
|
||||
207 02c8 7C4FCAA6 mfspr r2,SAVESPR
|
||||
208 02cc 90410004 stw r2,(rslt_r1-tst_results)(r1)
|
||||
209 02d0 7C400026 mfcr r2
|
||||
210 02d4 90410080 stw r2,(rslt_cr-tst_results)(r1)
|
||||
211 02d8 7C4102A6 mfxer r2
|
||||
212 02dc 90410084 stw r2,(rslt_xer-tst_results)(r1)
|
||||
213 02e0 7C4902A6 mfctr r2
|
||||
214 02e4 90410088 stw r2,(rslt_ctr-tst_results)(r1)
|
||||
215 02e8 7C4802A6 mflr r2
|
||||
216 02ec 9041008C stw r2,(rslt_lr-tst_results)(r1)
|
||||
217 02f0 7C4FCAA6 mfspr r2,tar
|
||||
218 02f4 90410090 stw r2,(rslt_tar-tst_results)(r1)
|
||||
219
|
||||
220 tst_cleanup:
|
||||
221 # restore c stuff
|
||||
222 02f8 3C600000 lis r3,tst_inits@h
|
||||
223 02fc 60630000 ori r3,r3,tst_inits@l
|
||||
224 0300 8023009C lwz r1,(save_r1-tst_inits)(r3)
|
||||
225 0304 3C600867 lis r3,MAGIC@h
|
||||
226 0308 60635309 ori r3,r3,MAGIC@l
|
||||
227
|
||||
228 030c 48000000 b tst_done
|
||||
229
|
||||
230 # -------------------------------------------------------------------------------------------------
|
||||
231 0310 60000000 .align 5
|
||||
231 60000000
|
||||
231 60000000
|
||||
231 60000000
|
||||
232 tst_results:
|
||||
233
|
||||
234 0320 FFFFFFFF rslt_r0: .int 0xFFFFFFFF
|
||||
235 0324 FFFFFFFF rslt_r1: .int 0xFFFFFFFF
|
||||
236 0328 FFFFFFFF rslt_r2: .int 0xFFFFFFFF
|
||||
237 032c FFFFFFFF rslt_r3: .int 0xFFFFFFFF
|
||||
238 0330 FFFFFFFF rslt_r4: .int 0xFFFFFFFF
|
||||
239 0334 FFFFFFFF rslt_r5: .int 0xFFFFFFFF
|
||||
240 0338 FFFFFFFF rslt_r6: .int 0xFFFFFFFF
|
||||
241 033c FFFFFFFF rslt_r7: .int 0xFFFFFFFF
|
||||
242 0340 FFFFFFFF rslt_r8: .int 0xFFFFFFFF
|
||||
243 0344 FFFFFFFF rslt_r9: .int 0xFFFFFFFF
|
||||
244 0348 FFFFFFFF rslt_r10: .int 0xFFFFFFFF
|
||||
245 034c FFFFFFFF rslt_r11: .int 0xFFFFFFFF
|
||||
246 0350 FFFFFFFF rslt_r12: .int 0xFFFFFFFF
|
||||
247 0354 FFFFFFFF rslt_r13: .int 0xFFFFFFFF
|
||||
248 0358 FFFFFFFF rslt_r14: .int 0xFFFFFFFF
|
||||
249 035c FFFFFFFF rslt_r15: .int 0xFFFFFFFF
|
||||
250 0360 FFFFFFFF rslt_r16: .int 0xFFFFFFFF
|
||||
251 0364 FFFFFFFF rslt_r17: .int 0xFFFFFFFF
|
||||
252 0368 FFFFFFFF rslt_r18: .int 0xFFFFFFFF
|
||||
253 036c FFFFFFFF rslt_r19: .int 0xFFFFFFFF
|
||||
254 0370 FFFFFFFF rslt_r20: .int 0xFFFFFFFF
|
||||
255 0374 FFFFFFFF rslt_r21: .int 0xFFFFFFFF
|
||||
256 0378 FFFFFFFF rslt_r22: .int 0xFFFFFFFF
|
||||
257 037c FFFFFFFF rslt_r23: .int 0xFFFFFFFF
|
||||
258 0380 FFFFFFFF rslt_r24: .int 0xFFFFFFFF
|
||||
259 0384 FFFFFFFF rslt_r25: .int 0xFFFFFFFF
|
||||
260 0388 FFFFFFFF rslt_r26: .int 0xFFFFFFFF
|
||||
261 038c FFFFFFFF rslt_r27: .int 0xFFFFFFFF
|
||||
262 0390 FFFFFFFF rslt_r28: .int 0xFFFFFFFF
|
||||
263 0394 FFFFFFFF rslt_r29: .int 0xFFFFFFFF
|
||||
264 0398 FFFFFFFF rslt_r30: .int 0xFFFFFFFF
|
||||
265 039c FFFFFFFF rslt_r31: .int 0xFFFFFFFF
|
||||
266
|
||||
267 03a0 FFFFFFFF rslt_cr: .int 0xFFFFFFFF
|
||||
268 03a4 FFFFFFFF rslt_xer: .int 0xFFFFFFFF
|
||||
269 03a8 FFFFFFFF rslt_ctr: .int 0xFFFFFFFF
|
||||
270 03ac FFFFFFFF rslt_lr: .int 0xFFFFFFFF
|
||||
271 03b0 FFFFFFFF rslt_tar: .int 0xFFFFFFFF
|
||||
272
|
||||
273 # -------------------------------------------------------------------------------------------------
|
||||
274 03b4 60000000 .align 5
|
||||
274 60000000
|
||||
274 60000000
|
||||
275 tst_expects:
|
||||
276
|
||||
277 03c0 00000000 expt_r0: .int 0x00000000
|
||||
278 03c4 CD75F313 expt_r1: .int 0xCD75F313
|
||||
279 03c8 FFFFFFFF expt_r2: .int 0xFFFFFFFF
|
||||
280 03cc 00000000 expt_r3: .int 0x00000000
|
||||
281 03d0 FFFFFFFF expt_r4: .int 0xFFFFFFFF
|
||||
282 03d4 FFFFFFFF expt_r5: .int 0xFFFFFFFF
|
||||
283 03d8 FFFFFFFF expt_r6: .int 0xFFFFFFFF
|
||||
284 03dc FFFFFFFF expt_r7: .int 0xFFFFFFFF
|
||||
285 03e0 FFFFFFFF expt_r8: .int 0xFFFFFFFF
|
||||
286 03e4 008A0C68 expt_r9: .int 0x008A0C68
|
||||
287 03e8 FFFFFFFF expt_r10: .int 0xFFFFFFFF
|
||||
288 03ec 7FFFFFFF expt_r11: .int 0x7FFFFFFF
|
||||
289 03f0 FFFFFFFF expt_r12: .int 0xFFFFFFFF
|
||||
290 03f4 FFFFFFFF expt_r13: .int 0xFFFFFFFF
|
||||
291 03f8 8C20BDE6 expt_r14: .int 0x8C20BDE6
|
||||
292 03fc FFFFFFFF expt_r15: .int 0xFFFFFFFF
|
||||
293 0400 08AEBF68 expt_r16: .int 0x08AEBF68
|
||||
294 0404 80000001 expt_r17: .int 0x80000001
|
||||
295 0408 FFFFFFFF expt_r18: .int 0xFFFFFFFF
|
||||
296 040c 00000000 expt_r19: .int 0x00000000
|
||||
297 0410 FFFFFFFF expt_r20: .int 0xFFFFFFFF
|
||||
298 0414 FFFFFFFF expt_r21: .int 0xFFFFFFFF
|
||||
299 0418 328A0CED expt_r22: .int 0x328A0CED
|
||||
300 041c FFFFFFFF expt_r23: .int 0xFFFFFFFF
|
||||
301 0420 FFFFFFFF expt_r24: .int 0xFFFFFFFF
|
||||
302 0424 AF224C19 expt_r25: .int 0xAF224C19
|
||||
303 0428 FFFFFFFF expt_r26: .int 0xFFFFFFFF
|
||||
304 042c FFFFFFFF expt_r27: .int 0xFFFFFFFF
|
||||
305 0430 D624B27A expt_r28: .int 0xD624B27A
|
||||
306 0434 FFFFFFFF expt_r29: .int 0xFFFFFFFF
|
||||
307 0438 FFFFFFFF expt_r30: .int 0xFFFFFFFF
|
||||
308 043c FFFFFFFF expt_r31: .int 0xFFFFFFFF
|
||||
309
|
||||
310 0440 9BFD3628 expt_cr: .int 0x9BFD3628
|
||||
311 0444 98F0006E expt_xer: .int 0x98F0006E
|
||||
312 0448 FFFFFFFF expt_ctr: .int 0xFFFFFFFF
|
||||
313 044c FFFFFFFF expt_lr: .int 0xFFFFFFFF
|
||||
314 0450 FFFFFFFF expt_tar: .int 0xFFFFFFFF
|
||||
315 0454 00001104 expt_msr: .int 0x00001104
|
||||
316
|
||||
317 0458 00010038 expt_iar: .int 0x00010038
|
||||
318
|
||||
Binary file not shown.
@ -0,0 +1,318 @@
|
||||
# asmtst.tpl
|
||||
|
||||
.include "defines.s"
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
# c-accessible
|
||||
|
||||
.global init_tst
|
||||
.global tst_start
|
||||
.global tst_end
|
||||
.global tst_inits
|
||||
.global tst_results
|
||||
.global tst_expects
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
tst_misc:
|
||||
|
||||
tst_info: .asciz "info text"
|
||||
tst_header: .asciz "header text"
|
||||
|
||||
.set SAVESPR,tar
|
||||
.set MAGIC,0x8675309
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_inits:
|
||||
|
||||
init_r0: .int 0x00000000
|
||||
init_r1: .int 0x5822C905
|
||||
init_r2: .int 0xFFFFFFFF
|
||||
init_r3: .int 0x91B6D1A3
|
||||
init_r4: .int 0xFFFFFFFF
|
||||
init_r5: .int 0xFFFFFFFF
|
||||
init_r6: .int 0xFFFFFFFF
|
||||
init_r7: .int 0xFFFFFFFF
|
||||
init_r8: .int 0xFFFFFFFF
|
||||
init_r9: .int 0x7E11EE88
|
||||
init_r10: .int 0xFFFFFFFF
|
||||
init_r11: .int 0x7FFFFFFF
|
||||
init_r12: .int 0xFFFFFFFF
|
||||
init_r13: .int 0xFFFFFFFF
|
||||
init_r14: .int 0x8C20BDE6
|
||||
init_r15: .int 0xFFFFFFFF
|
||||
init_r16: .int 0x76D0DADF
|
||||
init_r17: .int 0x15111F42
|
||||
init_r18: .int 0xFFFFFFFF
|
||||
init_r19: .int 0x36108E50
|
||||
init_r20: .int 0xFFFFFFFF
|
||||
init_r21: .int 0xFFFFFFFF
|
||||
init_r22: .int 0x328A0CED
|
||||
init_r23: .int 0xFFFFFFFF
|
||||
init_r24: .int 0xFFFFFFFF
|
||||
init_r25: .int 0xAF224C19
|
||||
init_r26: .int 0xFFFFFFFF
|
||||
init_r27: .int 0xFFFFFFFF
|
||||
init_r28: .int 0xD624B27A
|
||||
init_r29: .int 0xFFFFFFFF
|
||||
init_r30: .int 0xFFFFFFFF
|
||||
init_r31: .int 0xFFFFFFFF
|
||||
|
||||
init_cr: .int 0xDBFD3628
|
||||
init_xer: .int 0x89F0006E
|
||||
init_ctr: .int 0xFFFFFFFF
|
||||
init_lr: .int 0xFFFFFFFF
|
||||
init_tar: .int 0xFFFFFFFF
|
||||
init_msr: .int 0x00001104
|
||||
|
||||
init_iar: .int 0x00010000
|
||||
|
||||
save_r1: .int 0
|
||||
|
||||
codelen: .int 13
|
||||
ops: .int 0x7C61CC14,0x7D230595,0x7AC37392,0x7E094C11,0x7E1CB115,0x7A338886,0x7C6004D1,0x7E09B038,0x7C360591,0x7E2B00D1,0x60000000,0x60000000,0x60000000
|
||||
iars: .int 0x00010000,0x00010004,0x00010008,0x0001000C,0x00010010,0x00010014,0x00010018,0x0001001C,0x00010020,0x00010024,0x00010028,0x0001002C,0x00010030
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
# r3=@tst_inits
|
||||
.align 5
|
||||
init_tst:
|
||||
|
||||
# save c stuff
|
||||
stw r1,(save_r1-tst_inits)(r3)
|
||||
|
||||
# copy ops
|
||||
opcopy:
|
||||
lwz r1,(codelen-tst_inits)(r3)
|
||||
mtctr r1
|
||||
la r1,(ops-tst_inits)(r3) # @ ops list
|
||||
la r2,(iars-tst_inits)(r3) # @ iars list
|
||||
opcopy_loop:
|
||||
lwz r4,0(r1) # next op
|
||||
lwz r5,0(r2) # next iar
|
||||
stw r4,0(r5) # store it
|
||||
addi r1,r1,4 # inc to next
|
||||
addi r2,r2,4
|
||||
bdnz opcopy_loop
|
||||
|
||||
# add end of test op - could be done here or by builder
|
||||
# ways to end:
|
||||
# ba <fixed_loc> - avoid reloc, target op can then branch to tst_end
|
||||
# trap,sc,scv - branch to tst_end in handler
|
||||
# attn, priv op, etc. - "
|
||||
# overwrite the last epilogue op to avoid any crossing
|
||||
opcopy_eot:
|
||||
lis r4,0x4800
|
||||
ori r4,r4,0x0006 # ba 0x0004
|
||||
stw r4,0(r5)
|
||||
|
||||
# get tst start
|
||||
lwz r1,init_msr(r0)
|
||||
mtsrr1 r1
|
||||
lwz r1,iars(r0)
|
||||
mtsrr0 r1
|
||||
|
||||
# init test regs
|
||||
init_regs:
|
||||
lwz r1,(init_cr-tst_inits)(r3)
|
||||
mtcr r1
|
||||
lwz r1,(init_xer-tst_inits)(r3)
|
||||
mtxer r1
|
||||
lwz r1,(init_ctr-tst_inits)(r3)
|
||||
mtctr r1
|
||||
lwz r1,(init_lr-tst_inits)(r3)
|
||||
mtlr r1
|
||||
lwz r1,(init_tar-tst_inits)(r3)
|
||||
mtspr tar,r1
|
||||
|
||||
lwz r0,(init_r0-tst_inits)(r3)
|
||||
lwz r1,(init_r1-tst_inits)(r3)
|
||||
lwz r2,(init_r2-tst_inits)(r3)
|
||||
lwz r4,(init_r4-tst_inits)(r3)
|
||||
lwz r5,(init_r5-tst_inits)(r3)
|
||||
lwz r6,(init_r6-tst_inits)(r3)
|
||||
lwz r7,(init_r7-tst_inits)(r3)
|
||||
lwz r8,(init_r8-tst_inits)(r3)
|
||||
lwz r9,(init_r9-tst_inits)(r3)
|
||||
lwz r10,(init_r10-tst_inits)(r3)
|
||||
lwz r11,(init_r11-tst_inits)(r3)
|
||||
lwz r12,(init_r12-tst_inits)(r3)
|
||||
lwz r13,(init_r13-tst_inits)(r3)
|
||||
lwz r14,(init_r14-tst_inits)(r3)
|
||||
lwz r15,(init_r15-tst_inits)(r3)
|
||||
lwz r16,(init_r16-tst_inits)(r3)
|
||||
lwz r17,(init_r17-tst_inits)(r3)
|
||||
lwz r18,(init_r18-tst_inits)(r3)
|
||||
lwz r19,(init_r19-tst_inits)(r3)
|
||||
lwz r20,(init_r20-tst_inits)(r3)
|
||||
lwz r21,(init_r21-tst_inits)(r3)
|
||||
lwz r22,(init_r22-tst_inits)(r3)
|
||||
lwz r23,(init_r23-tst_inits)(r3)
|
||||
lwz r24,(init_r24-tst_inits)(r3)
|
||||
lwz r25,(init_r25-tst_inits)(r3)
|
||||
lwz r26,(init_r26-tst_inits)(r3)
|
||||
lwz r27,(init_r27-tst_inits)(r3)
|
||||
lwz r28,(init_r28-tst_inits)(r3)
|
||||
lwz r29,(init_r29-tst_inits)(r3)
|
||||
lwz r30,(init_r30-tst_inits)(r3)
|
||||
lwz r31,(init_r31-tst_inits)(r3)
|
||||
lwz r3,(init_r3-tst_inits)(r3)
|
||||
|
||||
jmp2tst:
|
||||
#rfi
|
||||
#rfid
|
||||
ba 0x10000
|
||||
|
||||
tst_end:
|
||||
b save_results
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
save_results:
|
||||
# use a designated spr to save (sprgx, ...)
|
||||
mtspr SAVESPR,r1
|
||||
lis r1,tst_results@h
|
||||
ori r1,r1,tst_results@l
|
||||
stw r0,(rslt_r0-tst_results)(r1)
|
||||
stw r2,(rslt_r2-tst_results)(r1)
|
||||
stw r3,(rslt_r3-tst_results)(r1)
|
||||
stw r4,(rslt_r4-tst_results)(r1)
|
||||
stw r5,(rslt_r5-tst_results)(r1)
|
||||
stw r6,(rslt_r6-tst_results)(r1)
|
||||
stw r7,(rslt_r7-tst_results)(r1)
|
||||
stw r8,(rslt_r8-tst_results)(r1)
|
||||
stw r9,(rslt_r9-tst_results)(r1)
|
||||
stw r10,(rslt_r10-tst_results)(r1)
|
||||
stw r11,(rslt_r11-tst_results)(r1)
|
||||
stw r12,(rslt_r12-tst_results)(r1)
|
||||
stw r13,(rslt_r13-tst_results)(r1)
|
||||
stw r14,(rslt_r14-tst_results)(r1)
|
||||
stw r15,(rslt_r15-tst_results)(r1)
|
||||
stw r16,(rslt_r16-tst_results)(r1)
|
||||
stw r17,(rslt_r17-tst_results)(r1)
|
||||
stw r18,(rslt_r18-tst_results)(r1)
|
||||
stw r19,(rslt_r19-tst_results)(r1)
|
||||
stw r20,(rslt_r20-tst_results)(r1)
|
||||
stw r21,(rslt_r21-tst_results)(r1)
|
||||
stw r22,(rslt_r22-tst_results)(r1)
|
||||
stw r23,(rslt_r23-tst_results)(r1)
|
||||
stw r24,(rslt_r24-tst_results)(r1)
|
||||
stw r25,(rslt_r25-tst_results)(r1)
|
||||
stw r26,(rslt_r26-tst_results)(r1)
|
||||
stw r27,(rslt_r27-tst_results)(r1)
|
||||
stw r28,(rslt_r28-tst_results)(r1)
|
||||
stw r29,(rslt_r29-tst_results)(r1)
|
||||
stw r30,(rslt_r30-tst_results)(r1)
|
||||
stw r31,(rslt_r31-tst_results)(r1)
|
||||
mfspr r2,SAVESPR
|
||||
stw r2,(rslt_r1-tst_results)(r1)
|
||||
mfcr r2
|
||||
stw r2,(rslt_cr-tst_results)(r1)
|
||||
mfxer r2
|
||||
stw r2,(rslt_xer-tst_results)(r1)
|
||||
mfctr r2
|
||||
stw r2,(rslt_ctr-tst_results)(r1)
|
||||
mflr r2
|
||||
stw r2,(rslt_lr-tst_results)(r1)
|
||||
mfspr r2,tar
|
||||
stw r2,(rslt_tar-tst_results)(r1)
|
||||
|
||||
tst_cleanup:
|
||||
# restore c stuff
|
||||
lis r3,tst_inits@h
|
||||
ori r3,r3,tst_inits@l
|
||||
lwz r1,(save_r1-tst_inits)(r3)
|
||||
lis r3,MAGIC@h
|
||||
ori r3,r3,MAGIC@l
|
||||
|
||||
b tst_done
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_results:
|
||||
|
||||
rslt_r0: .int 0xFFFFFFFF
|
||||
rslt_r1: .int 0xFFFFFFFF
|
||||
rslt_r2: .int 0xFFFFFFFF
|
||||
rslt_r3: .int 0xFFFFFFFF
|
||||
rslt_r4: .int 0xFFFFFFFF
|
||||
rslt_r5: .int 0xFFFFFFFF
|
||||
rslt_r6: .int 0xFFFFFFFF
|
||||
rslt_r7: .int 0xFFFFFFFF
|
||||
rslt_r8: .int 0xFFFFFFFF
|
||||
rslt_r9: .int 0xFFFFFFFF
|
||||
rslt_r10: .int 0xFFFFFFFF
|
||||
rslt_r11: .int 0xFFFFFFFF
|
||||
rslt_r12: .int 0xFFFFFFFF
|
||||
rslt_r13: .int 0xFFFFFFFF
|
||||
rslt_r14: .int 0xFFFFFFFF
|
||||
rslt_r15: .int 0xFFFFFFFF
|
||||
rslt_r16: .int 0xFFFFFFFF
|
||||
rslt_r17: .int 0xFFFFFFFF
|
||||
rslt_r18: .int 0xFFFFFFFF
|
||||
rslt_r19: .int 0xFFFFFFFF
|
||||
rslt_r20: .int 0xFFFFFFFF
|
||||
rslt_r21: .int 0xFFFFFFFF
|
||||
rslt_r22: .int 0xFFFFFFFF
|
||||
rslt_r23: .int 0xFFFFFFFF
|
||||
rslt_r24: .int 0xFFFFFFFF
|
||||
rslt_r25: .int 0xFFFFFFFF
|
||||
rslt_r26: .int 0xFFFFFFFF
|
||||
rslt_r27: .int 0xFFFFFFFF
|
||||
rslt_r28: .int 0xFFFFFFFF
|
||||
rslt_r29: .int 0xFFFFFFFF
|
||||
rslt_r30: .int 0xFFFFFFFF
|
||||
rslt_r31: .int 0xFFFFFFFF
|
||||
|
||||
rslt_cr: .int 0xFFFFFFFF
|
||||
rslt_xer: .int 0xFFFFFFFF
|
||||
rslt_ctr: .int 0xFFFFFFFF
|
||||
rslt_lr: .int 0xFFFFFFFF
|
||||
rslt_tar: .int 0xFFFFFFFF
|
||||
|
||||
# -------------------------------------------------------------------------------------------------
|
||||
.align 5
|
||||
tst_expects:
|
||||
|
||||
expt_r0: .int 0x00000000
|
||||
expt_r1: .int 0xCD75F313
|
||||
expt_r2: .int 0xFFFFFFFF
|
||||
expt_r3: .int 0x00000000
|
||||
expt_r4: .int 0xFFFFFFFF
|
||||
expt_r5: .int 0xFFFFFFFF
|
||||
expt_r6: .int 0xFFFFFFFF
|
||||
expt_r7: .int 0xFFFFFFFF
|
||||
expt_r8: .int 0xFFFFFFFF
|
||||
expt_r9: .int 0x008A0C68
|
||||
expt_r10: .int 0xFFFFFFFF
|
||||
expt_r11: .int 0x7FFFFFFF
|
||||
expt_r12: .int 0xFFFFFFFF
|
||||
expt_r13: .int 0xFFFFFFFF
|
||||
expt_r14: .int 0x8C20BDE6
|
||||
expt_r15: .int 0xFFFFFFFF
|
||||
expt_r16: .int 0x08AEBF68
|
||||
expt_r17: .int 0x80000001
|
||||
expt_r18: .int 0xFFFFFFFF
|
||||
expt_r19: .int 0x00000000
|
||||
expt_r20: .int 0xFFFFFFFF
|
||||
expt_r21: .int 0xFFFFFFFF
|
||||
expt_r22: .int 0x328A0CED
|
||||
expt_r23: .int 0xFFFFFFFF
|
||||
expt_r24: .int 0xFFFFFFFF
|
||||
expt_r25: .int 0xAF224C19
|
||||
expt_r26: .int 0xFFFFFFFF
|
||||
expt_r27: .int 0xFFFFFFFF
|
||||
expt_r28: .int 0xD624B27A
|
||||
expt_r29: .int 0xFFFFFFFF
|
||||
expt_r30: .int 0xFFFFFFFF
|
||||
expt_r31: .int 0xFFFFFFFF
|
||||
|
||||
expt_cr: .int 0x9BFD3628
|
||||
expt_xer: .int 0x98F0006E
|
||||
expt_ctr: .int 0xFFFFFFFF
|
||||
expt_lr: .int 0xFFFFFFFF
|
||||
expt_tar: .int 0xFFFFFFFF
|
||||
expt_msr: .int 0x00001104
|
||||
|
||||
expt_iar: .int 0x00010038
|
||||
|
||||
@ -0,0 +1 @@
|
||||
../bin
|
||||
@ -0,0 +1,121 @@
|
||||
#include <stdint.h>
|
||||
|
||||
#include "bios.h"
|
||||
|
||||
// arci stuff1
|
||||
void tst_done(unsigned int rc);
|
||||
unsigned int checkResult(unsigned int r, char* name);
|
||||
// shouldn't need any of these if i use the .o from bios build???
|
||||
//#include "generated/soc.h"
|
||||
extern unsigned int tst_start;
|
||||
extern unsigned int tst_end;
|
||||
extern unsigned int tst_inits;
|
||||
extern unsigned int tst_results;
|
||||
extern unsigned int tst_expects;
|
||||
|
||||
|
||||
int main(int tid) {
|
||||
int *p;
|
||||
int *fdata = _fdata;
|
||||
unsigned int *inits = &tst_inits;
|
||||
|
||||
if (tid != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// r/w memory init
|
||||
|
||||
// copy
|
||||
for (p = _fdata_rom; p < _edata_rom; p++){
|
||||
*(fdata++) = *p;
|
||||
}
|
||||
// zero
|
||||
for (p = _fbss; p < _ebss; p++) {
|
||||
*_fbss = 0;
|
||||
}
|
||||
|
||||
// core init
|
||||
set_epcr(0x03000000); // icm=gicm=1
|
||||
set_dec(0);
|
||||
set_tbh(0);
|
||||
set_tbl(0);
|
||||
set_tsr(0xFE000000); // mask: clear enw,wis,wrs,dis,fis,udis
|
||||
set_xucr0(get_xucr0() & 0x00000200); // set tcs=0
|
||||
set_tsr(0);
|
||||
set_tcr(0); // disable all timers
|
||||
|
||||
// thread enable
|
||||
// set_tens(0x3);
|
||||
|
||||
// run a .tst
|
||||
// danger! once r1 is whacked, any c code like bad int handler, etc. needs
|
||||
// to make sure it has a safe stack for calls
|
||||
asm (
|
||||
"mr 3,%0\n"
|
||||
//"lis 4,init_tst@h\n"
|
||||
//"ori 4,4,init_tst@l\n"
|
||||
//"mtctr 4\n"
|
||||
//"bcctr\n"
|
||||
"b init_tst\n"
|
||||
: // outputs
|
||||
: "r"(inits) // inputs
|
||||
: "r3" // clobbers
|
||||
);
|
||||
|
||||
while(1) {}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define MAGIC 0x08675309
|
||||
|
||||
//void __attribute__((noreturn)) tst_done(unsigned int rc) {
|
||||
void tst_done(unsigned int rc) {
|
||||
unsigned int i, ok = 1, done = 0;
|
||||
/*
|
||||
char c;
|
||||
char name[10];
|
||||
unsigned int r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15;
|
||||
unsigned int cr, xer, ctr, lr, tar;
|
||||
unsigned int op, *cia;
|
||||
*/
|
||||
|
||||
if (rc != MAGIC) {
|
||||
ok = 0;
|
||||
}
|
||||
|
||||
// ops
|
||||
|
||||
// cr, xer, ctr, lr, tar
|
||||
ok = ok && checkResult(32, "CR");
|
||||
ok = ok && checkResult(33, "XER");
|
||||
ok = ok && checkResult(34, "CTR");
|
||||
ok = ok && checkResult(35, "LR");
|
||||
ok = ok && checkResult(36, "TAR");
|
||||
}
|
||||
|
||||
unsigned int checkResult(unsigned int r, char* name) {
|
||||
unsigned int init, act, exp, ok = 1;
|
||||
|
||||
init = *(&tst_inits + r);
|
||||
act = *(&tst_results + r);
|
||||
exp = *(&tst_expects + r);
|
||||
|
||||
ok = act != exp;
|
||||
|
||||
return ok;
|
||||
}
|
||||
|
||||
// these are branched to!
|
||||
void int_sc(int code, int srr0) {
|
||||
asm (
|
||||
"b tst_end\n"
|
||||
: // outputs
|
||||
: // inputs
|
||||
: // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
void int_unhandled(void) {
|
||||
while(1) {}
|
||||
}
|
||||
@ -0,0 +1,123 @@
|
||||
#ifndef BIOS_H
|
||||
|
||||
#define BIOS_H
|
||||
|
||||
extern int *_fdata_rom;
|
||||
extern int *_edata_rom;
|
||||
extern int *_fdata;
|
||||
extern int *_fbss;
|
||||
extern int *_ebss;
|
||||
|
||||
void int_sc(int code, int srr0);
|
||||
void int_unhandled(void);
|
||||
|
||||
inline void set_epcr(int v) __attribute__((always_inline));
|
||||
inline void set_dec(int v) __attribute__((always_inline));
|
||||
inline void set_tbh(int v) __attribute__((always_inline));
|
||||
inline void set_tbl(int v) __attribute__((always_inline));
|
||||
inline void set_tsr(int v) __attribute__((always_inline));
|
||||
inline void set_tcr(int v) __attribute__((always_inline));
|
||||
inline void set_tens(int v) __attribute__((always_inline));
|
||||
inline void set_xucr0(int v) __attribute__((always_inline));
|
||||
inline int get_xucr0(void) __attribute__((always_inline));
|
||||
|
||||
inline void set_epcr(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 307,4\n" // epcr
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_dec(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 22,4\n" // dec
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tbh(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 285,4\n" // tbh
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tbl(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 284,4\n" // tbl
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tsr(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 336,4\n" // tsr
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tcr(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 340,4\n" // tcr
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline int get_xucr0(void) {
|
||||
int v;
|
||||
asm volatile(
|
||||
"mfspr %0,1014\n" // xucr0
|
||||
: "=r"(v) // outputs
|
||||
: // inputs
|
||||
: // clobbers
|
||||
);
|
||||
return v;
|
||||
}
|
||||
|
||||
inline void set_xucr0(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 1014,4\n" // xucr0
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
inline void set_tens(int v) {
|
||||
asm volatile(
|
||||
"lis 4,%0@h\n"
|
||||
"ori 4,4,%0@l\n"
|
||||
"mtspr 438,4\n" // tens
|
||||
: // outputs
|
||||
: "r"(v) // inputs
|
||||
: "r4" // clobbers
|
||||
);
|
||||
}
|
||||
|
||||
#endif
|
||||
Binary file not shown.
@ -0,0 +1,356 @@
|
||||
# © IBM Corp. 2022
|
||||
# Licensed under and subject to the terms of the CC-BY 4.0
|
||||
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
# Additional rights, including the right to physically implement a softcore
|
||||
# that is compliant with the required sections of the Power ISA
|
||||
# Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
# This README will be updated with additional information when OpenPOWER's
|
||||
# license is available.
|
||||
|
||||
# boot kernel
|
||||
# resets to 32BE
|
||||
# set up translations for starting bios (inc. BE/LE)
|
||||
# copy modifiable rom data to ram - or do in bios?
|
||||
# set up msr for running bios (inc. 32/64)
|
||||
# jump to bios
|
||||
|
||||
|
||||
.include "defines.s"
|
||||
|
||||
.macro load32 rx,v
|
||||
li \rx,0
|
||||
oris \rx,\rx,\v>>16
|
||||
ori \rx,\rx,\v&0x0000FFFF
|
||||
.endm
|
||||
|
||||
.macro load16swiz rx,v
|
||||
li \rx,0
|
||||
ori \rx,\rx,(\v<<8)&0xFF00
|
||||
ori \rx,\rx,(\v>>8)&0x00FF
|
||||
.endm
|
||||
|
||||
# constants from linker script, or defsym
|
||||
|
||||
.ifdef BIOS_32
|
||||
# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.set BIOS_MSR,0x0002B000
|
||||
.else
|
||||
# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.set BIOS_MSR,0x8002B000
|
||||
.endif
|
||||
|
||||
# erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
.ifdef BIOS_LE
|
||||
.set BIOS_ERATW2,0x000000BF
|
||||
.else
|
||||
.set BIOS_ERATW2,0x0000003F
|
||||
.endif
|
||||
|
||||
# bios might be able to use one stack during thread startup if careful
|
||||
.ifndef BIOS_STACK_0
|
||||
.set BIOS_STACK_0,_stack_0
|
||||
.endif
|
||||
|
||||
.ifndef BIOS_STACK_1
|
||||
.set BIOS_STACK_1,_stack_1
|
||||
.endif
|
||||
|
||||
.ifndef BIOS_START
|
||||
.set BIOS_START,0x00010000
|
||||
.endif
|
||||
|
||||
.section .text
|
||||
|
||||
.global _start
|
||||
|
||||
.org 0x000
|
||||
_start:
|
||||
int_000:
|
||||
b boot_start
|
||||
|
||||
.ifdef TST_END
|
||||
b tst_end
|
||||
.endif
|
||||
|
||||
# critical input
|
||||
.org 0x020
|
||||
int_020:
|
||||
.ifdef INT_UNHANDLED
|
||||
b int_unhandled
|
||||
.else
|
||||
b .
|
||||
.endif
|
||||
|
||||
# debug
|
||||
.org 0x040
|
||||
int_040:
|
||||
b .
|
||||
|
||||
# dsi
|
||||
.org 0x060
|
||||
int_060:
|
||||
b .
|
||||
|
||||
# isi
|
||||
.org 0x080
|
||||
int_080:
|
||||
b .
|
||||
|
||||
# external
|
||||
.org 0x0A0
|
||||
int_0A0:
|
||||
b .
|
||||
|
||||
# alignment
|
||||
.org 0x0C0
|
||||
int_0C0:
|
||||
b .
|
||||
|
||||
# program
|
||||
.org 0x0E0
|
||||
int_0E0:
|
||||
b .
|
||||
|
||||
# fp unavailable
|
||||
.org 0x100
|
||||
int_100:
|
||||
b .
|
||||
|
||||
# sc
|
||||
.org 0x120
|
||||
int_120:
|
||||
.ifdef INT_SC
|
||||
# lev is in 20:26, but supposed to use scv now
|
||||
li r3,0
|
||||
mfsrr0 r4
|
||||
b int_sc
|
||||
.else
|
||||
.ifdef INT_UNHANDLED
|
||||
b int_unhandled
|
||||
.else
|
||||
b .
|
||||
.endif
|
||||
.endif
|
||||
|
||||
# apu unavailable
|
||||
.org 0x140
|
||||
int_140:
|
||||
b .
|
||||
|
||||
# decrementer
|
||||
.org 0x160
|
||||
int_160:
|
||||
b .
|
||||
|
||||
# fit
|
||||
.org 0x180
|
||||
int_180:
|
||||
b .
|
||||
|
||||
# watchdog
|
||||
.org 0x1A0
|
||||
int_1A0:
|
||||
b .
|
||||
|
||||
# dtlb
|
||||
.org 0x1C0
|
||||
int_1C0:
|
||||
b .
|
||||
|
||||
# itlb
|
||||
.org 0x1E0
|
||||
int_1E0:
|
||||
b .
|
||||
|
||||
# vector unavailable
|
||||
.org 0x200
|
||||
int_200:
|
||||
b .
|
||||
|
||||
#
|
||||
.org 0x220
|
||||
int_220:
|
||||
b .
|
||||
|
||||
#
|
||||
.org 0x240
|
||||
int_240:
|
||||
b .
|
||||
|
||||
#
|
||||
.org 0x260
|
||||
int_260:
|
||||
b .
|
||||
|
||||
# doorbell
|
||||
.org 0x280
|
||||
int_280:
|
||||
b .
|
||||
|
||||
# doorbell critical
|
||||
.org 0x2A0
|
||||
int_2A0:
|
||||
b .
|
||||
|
||||
# doorbell guest
|
||||
.org 0x2C0
|
||||
int_2C0:
|
||||
b .
|
||||
|
||||
# doorbell guest critical
|
||||
.org 0x2E0
|
||||
int_2E0:
|
||||
b .
|
||||
|
||||
# hvsc
|
||||
.org 0x300
|
||||
int_300:
|
||||
b .
|
||||
|
||||
# hvpriv
|
||||
.org 0x320
|
||||
int_320:
|
||||
b .
|
||||
|
||||
# lrat
|
||||
.org 0x340
|
||||
int_340:
|
||||
b .
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# initial translation
|
||||
# both erats:
|
||||
# 00000000 64K: (rom, BE)
|
||||
# 00010000 64K: (ram, BE or LE)
|
||||
#
|
||||
.org 0x400
|
||||
boot_start:
|
||||
|
||||
mfspr r5,tir # who am i?
|
||||
cmpdi r5,0x00 # skip unless T0
|
||||
bne init_t123
|
||||
|
||||
lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
|
||||
# derat 31 @00000000
|
||||
li r0,0x001F # entry #31
|
||||
li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
mtspr mmucr0,r3
|
||||
eratwe r2,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
|
||||
# derat 30 @<BIOS_START>
|
||||
li r0,0x001E # entry #30
|
||||
load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
load32 r8,BIOS_START
|
||||
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
eratwe r10,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
|
||||
# ierat 15 @00000000
|
||||
li r0,0x000F # entry #15
|
||||
li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
mtspr mmucr0,r3
|
||||
eratwe r2,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
# *** leave the init'd entry 14 for MT access to FFFFFFC0
|
||||
# ierat 13 @<BIOS_START>
|
||||
li r0,0x000D # entry #13
|
||||
load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
load32 r8,BIOS_START
|
||||
ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
eratwe r10,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
b init_t0
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# init
|
||||
#
|
||||
|
||||
# T0
|
||||
|
||||
init_t0:
|
||||
|
||||
# set up BIOS msr
|
||||
|
||||
load32 r10,BIOS_MSR
|
||||
mtmsr r10
|
||||
isync
|
||||
# can't use load32 unless you can .set BIOS_STACK_0 to the linked value
|
||||
# load32 r1,BIOS_STACK_0 # @stack_0
|
||||
# this ignores def
|
||||
# lis r1,_stack_0@h
|
||||
# ori r1,r1,_stack_0@l
|
||||
# this requires data load
|
||||
lwz r1,stack_0(r0)
|
||||
|
||||
b boot_complete
|
||||
|
||||
# except T0
|
||||
|
||||
init_t123:
|
||||
|
||||
# set up BIOS msr
|
||||
|
||||
load32 r10,BIOS_MSR
|
||||
mtmsr r10
|
||||
isync
|
||||
# check tir if more than 2 threads possible
|
||||
lwz r1,stack_1(r0)
|
||||
|
||||
b boot_complete
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
boot_complete:
|
||||
|
||||
# set up thread and hop to it
|
||||
|
||||
lis r3,main@h
|
||||
ori r3,r3,main@l
|
||||
mtctr r3
|
||||
mfspr r3,tir # who am i?
|
||||
bctrl
|
||||
b kernel_return
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
.org 0x7FC
|
||||
kernel_return:
|
||||
b .
|
||||
|
||||
# dec
|
||||
.org 0x800
|
||||
int_800:
|
||||
b .
|
||||
|
||||
# perf
|
||||
.org 0x820
|
||||
int_820:
|
||||
b .
|
||||
|
||||
.org 0x8F0
|
||||
.section .rodata
|
||||
stack_0: .long BIOS_STACK_0
|
||||
stack_1: .long BIOS_STACK_1
|
||||
@ -0,0 +1,93 @@
|
||||
#!/usr/bin/bash
|
||||
|
||||
export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
|
||||
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"
|
||||
|
||||
# defines
|
||||
|
||||
## define vars to init rom with csr's it uses...
|
||||
|
||||
#
|
||||
#csr_base=`grep '#define CSR_BASE' generated/csr.h | cut -d ' ' -f 3 | cut -c 1-6`
|
||||
#uart_base=`grep 'CSR_UART_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#UART_ADDR="${csr_base}${uart_base}"
|
||||
#defsyms="-defsym $UART_ADDR"
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_1_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_1_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_1_ADDR"
|
||||
#fi
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_2_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_2_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_2_ADDR"
|
||||
#fi
|
||||
#
|
||||
#leds_base=`grep 'CSR_LEDS_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$leds_base" != "" ]] ; then
|
||||
# LEDS_ADDR="${csr_base}${leds_base}"
|
||||
# defsyms="$defsyms -defsym $LEDS_ADDR"
|
||||
#fi
|
||||
#
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_1_ADDR}"
|
||||
|
||||
# a2o nanokernel
|
||||
|
||||
echo -n "Compiling..."
|
||||
|
||||
echo -n "boot.s "
|
||||
#powerpc-linux-gnu-as -mbig-endian -ma2 -defsym INT_SC=1 -defsym INT_UNHANDLED=1 -I. boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
powerpc-linux-gnu-as -mbig-endian -ma2 -defsym TST_END=1 -defsym INT_UNHANDLED=1 -I. boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
echo -n "arcitst.s "
|
||||
#powerpc-linux-gnu-as -defsym UART_ADDR=$UART_ADDR -defsym LEDS_ADDR=$LEDS_ADDR -defsym UNHANDLED=1 -mbig-endian -mpower9 -I./asm asm/cmod7-boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
powerpc-linux-gnu-as -mbig-endian -ma2 -I. arcitst.s -ahlnd -o arcitst.o > arcitst.lst
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
echo ""
|
||||
echo -n "bios.c "
|
||||
powerpc-linux-gnu-gcc -c -I. $CFLAGS bios.c
|
||||
|
||||
echo ""
|
||||
echo "Linking..."
|
||||
powerpc-linux-gnu-ld -nostdlib -nodefaultlibs -T linker.ld crt0.o bios.o arcitst.o -o rom
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
powerpc-linux-gnu-objdump -d rom > rom.d #wtf: why not getting labels in asm code?
|
||||
powerpc-linux-gnu-objdump -s rom > rom.s
|
||||
#powerpc-linux-gnu-objcopy --change-section-lma .bios=0x10000 -O binary rom rom.bin
|
||||
powerpc-linux-gnu-objcopy -O binary rom rom.bin
|
||||
|
||||
#python3 -m litex.soc.software.memusage rom ./generated/regions.ld powerpc-linux-gnu
|
||||
|
||||
# make rom.bin.hex
|
||||
bin/bin2init rom.bin
|
||||
mv rom.bin.hex rom.init
|
||||
|
||||
echo "Built rom.d, rom.s, rom.init."
|
||||
|
||||
romsize=`grep rom regions.ld | cut -d " " -f 8 | cut -c 3-10`
|
||||
|
||||
echo "Hardware ROM Size $romsize"
|
||||
#echo ""
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_2_ADDR}"
|
||||
#
|
||||
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 2.7 MiB |
@ -0,0 +1,640 @@
|
||||
1 # © IBM Corp. 2022
|
||||
2 # Licensed under and subject to the terms of the CC-BY 4.0
|
||||
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
4 # Additional rights, including the right to physically implement a softcore
|
||||
5 # that is compliant with the required sections of the Power ISA
|
||||
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
7 # This README will be updated with additional information when OpenPOWER's
|
||||
8 # license is available.
|
||||
9
|
||||
10 # boot kernel
|
||||
11 # resets to 32BE
|
||||
12 # set up translations for starting bios (inc. BE/LE)
|
||||
13 # copy modifiable rom data to ram - or do in bios?
|
||||
14 # set up msr for running bios (inc. 32/64)
|
||||
15 # jump to bios
|
||||
16
|
||||
17
|
||||