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Bill Flynn 2 years ago committed by GitHub
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@ -112,6 +112,9 @@ verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt(
* tri_256x144_8w_1r1w * tri_256x144_8w_1r1w
verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr( verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr(


* tri_128x34_4w_1r1w idir(
verilog/work/iuq_ic_dir.v: tri_128x34_4w_1r1w idir(

* tri_64x34_8w_1r1w * tri_64x34_8w_1r1w
verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(
verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr(

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