verilator litex
openpowerwtf
3 years ago
parent
5532d33b52
commit
5c12356d95
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// simple verilator top
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// uses a2owb with sim mem interface
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#define TRACING
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#include <cstddef>
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#include <iostream>
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#include <fstream>
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#include <iomanip>
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#include "verilated.h"
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#include "Va2owb.h"
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// internal nets
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#include "Va2owb___024root.h"
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#include "Va2owb_a2owb.h"
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#include "Va2owb_a2l2wb.h"
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#ifdef TRACING
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#include "verilated_vcd_c.h"
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VerilatedVcdC *t;
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#else
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unsigned int t = 0;
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#endif
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/*
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#include "uart/uartsim.h"
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*/
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Va2owb* m;
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vluint64_t main_time = 0; // in units of timeprecision used in verilog or --timescale-override
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// what is it? it changed to 941621251 after calling loadmem()
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double sc_time_stamp() { // $time in verilog
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return main_time;
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}
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const int resetCycle = 10;
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const int threadRunCycle = resetCycle + 5;
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const int runCycles = 500;
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const int hbCycles = 500;
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const int threads = 1;
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const std::string testFile = "../mem/test1/rom.init";
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// Cythonize this and use it for cocotb too...
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class Memory {
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std::unordered_map<unsigned int, unsigned int> mem;
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public:
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bool le;
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bool logStores;
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int defaultVal;
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Memory();
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void loadFile(std::string filename, unsigned int adr=0, bool le=false, std::string format="ascii");
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int read(unsigned int adr);
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void write(unsigned int adr, unsigned int dat);
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void write(unsigned int adr, unsigned int be, unsigned int dat);
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};
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Memory::Memory() {
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this->defaultVal = 0;
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this->le = false;
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this->logStores = true;
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}
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void Memory::loadFile(std::string filename, unsigned int adr, bool le, std::string format) {
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unsigned int dat;
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std::ifstream f;
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f.open(filename, std::fstream::in);
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// "ascii"
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//while (f.peek()!=EOF) {
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//f >> std::hex >> dat;
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// f >> dat;
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while (f >> std::hex >> dat) {
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this->write(adr, dat);
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adr += 4;
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}
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}
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// adr is word-aligned byte address
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int Memory::read(unsigned int adr) {
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if (this->mem.find(adr) != this->mem.end()) {
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return this->mem[adr];
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} else {
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return this->defaultVal;
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}
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}
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// adr is word-aligned byte address
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void Memory::write(unsigned int adr, unsigned int dat) {
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unsigned int startDat = this->read(adr);
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this->mem[adr] = dat;
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if (this->logStores) {
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std::cout << std::setw(8) << std::hex << " * Mem Update @" << adr << " " << startDat << "->" << dat << std::endl;
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}
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}
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void Memory::write(unsigned int adr, unsigned int be, unsigned int dat) {
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if (be == 0) return;
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int mask, startDat;
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if (be >= 8) {
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be = be - 8;
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mask = 0xFF000000;
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} else {
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mask = 0;
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}
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if (be >= 4) {
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be = be - 4;
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mask |= 0x00FF0000;
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}
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if (be >= 2) {
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be = be - 2;
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mask |= 0x0000FF00;
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}
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if (be = 1) {
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mask |= 0x000000FF;
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}
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startDat = this->read(adr);
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this->mem[adr] = (startDat & ~mask) | (dat & mask);
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if (this->logStores) {
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std::cout << std::setw(8) << std::hex << " * Mem Update @" << adr << " " << startDat << "->" << dat << std::endl;
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}
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}
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Memory mem;
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int main(int argc, char **argv) {
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using namespace std;
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cout << setfill('0');
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Verilated::commandArgs(argc, argv);
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m = new Va2owb;
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#ifdef TRACING
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Verilated::traceEverOn(true);
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t = new VerilatedVcdC;
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m->trace(t, 99);
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t->open("a2onode.vcd");
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cout << "Tracing enabled." << endl;
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#endif
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bool resetDone = false;
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unsigned int threadStop = 0x3;
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unsigned int tick = 0;
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unsigned int cycle = 1;
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unsigned int readPending = 0;
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unsigned int readAddr = 0;
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unsigned int readTag = 0;
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unsigned int readTID = 0;
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unsigned int countReads = 0;
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bool wbRdPending = false, wbWrPending = false;
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//unsigned int iu0Comp = m->rootp->a2owb->c0->iu_lq_i0_completed;
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//unsigned int iu0Comp = m->rootp->a2owb__DOT__c0__DOT__lq0__DOT__lsq__DOT__odq__DOT__iu_lq_i0_completed_itag_int;
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/*
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iu0CompIFAR = sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar
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iu1Comp = sim.a2o.root.iu_lq_i1_completed
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iu1CompIFAR = sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar
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iuCompFlushIFAR = sim.a2o.root.cp_t0_flush_ifar
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cp3NIA = sim.a2o.root.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp3_nia_q # nia after last cycle's completions
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*/
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mem.write(0xFFFFFFFC, 0x48000002);
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mem.loadFile(testFile);
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m->rst = 1;
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cout << dec << setw(8) << cycle << " Resetting..." << endl;
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//m->an_ac_pm_thread_stop = threadStop;
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//cout << dec << setw(8) << cycle << " Thread stop=" << threadStop << endl;
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const int clocks[4] = {0x3, 0x2, 0x1, 0x0}; // 1x, 2x
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const int ticks1x = 4;
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while (!Verilated::gotFinish()) {
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if (!resetDone && (cycle > resetCycle)) {
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m->rst = 0;
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cout << dec << setw(8) << cycle << " Releasing reset." << endl;
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resetDone = true;
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}
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if (threadStop && (cycle > threadRunCycle)) {
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//threadStop = 0x0;
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//m->an_ac_pm_thread_stop = threadStop;
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//cout << dec << setw(8) << cycle << " Thread stop=" << threadStop << endl;
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}
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m->clk_1x = clocks[tick % ticks1x] >> 1;
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m->clk_2x = clocks[tick % ticks1x] & 0x1;
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tick++;
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m->eval();
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// bus is 1x clock
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if ((tick % ticks1x) == 0) {
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// wb
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m->wb_ack = 0;
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if (wbRdPending) {
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m->wb_datr = mem.read(m->wb_adr);
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m->wb_ack = 1;
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wbRdPending = false;
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} else if (wbWrPending) {
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mem.write(m->wb_adr, m->wb_datw, m->wb_sel);
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m->wb_ack = 1;
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wbWrPending = false;
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}
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if (!wbRdPending && !wbWrPending && m->wb_cyc && m->wb_stb) {
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if (!m->wb_we) {
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD RA=" << setw(8) << hex << setfill('0') << m->wb_adr << endl;
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wbRdPending = true;
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} else {
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cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR RA=" << setw(8) << hex << setfill('0') << m->wb_adr <<
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" SEL=" << m->wb_sel << " DATA=" << m->wb_datw << endl;
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wbWrPending = true;
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}
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}
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}
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// finish clock stuff
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if ((tick % ticks1x) == 0) {
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cycle++;
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if ((cycle % hbCycles) == 0) {
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cout << dec << setw(8) << setfill('0') << cycle << " ...tick..." << endl;
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}
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}
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#ifdef TRACING
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t->dump(tick);
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t->flush();
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#endif
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// check for fails
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// hit limit
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if (cycle > runCycles) {
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break;
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}
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}
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#ifdef TRACING
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t->close();
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#endif
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m->final();
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exit(EXIT_SUCCESS);
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}
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