add source
parent
8fca112828
commit
4177984080
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,138 @@
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# ila parms
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set ila u_ila_0
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set depth 32768
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set stages 3
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set trigin false
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set trigout false
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set basic true
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set advanced true
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# F/F 1-16 T/F 2-16 F/T 1-16 T/T 2-16
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set comp 4
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# make sure synth is open
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open_run synth_1
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# delete if exists
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# delete_debug_core -quiet [get_debug_cores -quiet $ila]
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catch {delete_debug_core [get_debug_cores $ila]}
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# add
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create_debug_core $ila ila
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set_property C_DATA_DEPTH $depth [get_debug_cores $ila]
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set_property C_INPUT_PIPE_STAGES $stages [get_debug_cores $ila]
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set_property C_TRIGIN_EN $trigin [get_debug_cores $ila]
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set_property C_TRIGOUT_EN $trigout [get_debug_cores $ila]
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set_property C_EN_STRG_QUAL $basic [get_debug_cores $ila]
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set_property C_ADV_TRIGGER $advanced [get_debug_cores $ila]
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set_property ALL_PROBE_SAME_MU true [get_debug_cores $ila]
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set_property ALL_PROBE_SAME_MU_CNT $comp [get_debug_cores $ila]
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# add nets
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connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_0/inst/clk ]]
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set_property port_width 128 [get_debug_ports u_ila_0/probe0]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
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connect_debug_port u_ila_0/probe0 [get_nets [list {a2l2_axi_0_an_ac_reld_data[127]} {a2l2_axi_0_an_ac_reld_data[126]} {a2l2_axi_0_an_ac_reld_data[125]} {a2l2_axi_0_an_ac_reld_data[124]} {a2l2_axi_0_an_ac_reld_data[123]} {a2l2_axi_0_an_ac_reld_data[122]} {a2l2_axi_0_an_ac_reld_data[121]} {a2l2_axi_0_an_ac_reld_data[120]} {a2l2_axi_0_an_ac_reld_data[119]} {a2l2_axi_0_an_ac_reld_data[118]} {a2l2_axi_0_an_ac_reld_data[117]} {a2l2_axi_0_an_ac_reld_data[116]} {a2l2_axi_0_an_ac_reld_data[115]} {a2l2_axi_0_an_ac_reld_data[114]} {a2l2_axi_0_an_ac_reld_data[113]} {a2l2_axi_0_an_ac_reld_data[112]} {a2l2_axi_0_an_ac_reld_data[111]} {a2l2_axi_0_an_ac_reld_data[110]} {a2l2_axi_0_an_ac_reld_data[109]} {a2l2_axi_0_an_ac_reld_data[108]} {a2l2_axi_0_an_ac_reld_data[107]} {a2l2_axi_0_an_ac_reld_data[106]} {a2l2_axi_0_an_ac_reld_data[105]} {a2l2_axi_0_an_ac_reld_data[104]} {a2l2_axi_0_an_ac_reld_data[103]} {a2l2_axi_0_an_ac_reld_data[102]} {a2l2_axi_0_an_ac_reld_data[101]} {a2l2_axi_0_an_ac_reld_data[100]} {a2l2_axi_0_an_ac_reld_data[99]} {a2l2_axi_0_an_ac_reld_data[98]} {a2l2_axi_0_an_ac_reld_data[97]} {a2l2_axi_0_an_ac_reld_data[96]} {a2l2_axi_0_an_ac_reld_data[95]} {a2l2_axi_0_an_ac_reld_data[94]} {a2l2_axi_0_an_ac_reld_data[93]} {a2l2_axi_0_an_ac_reld_data[92]} {a2l2_axi_0_an_ac_reld_data[91]} {a2l2_axi_0_an_ac_reld_data[90]} {a2l2_axi_0_an_ac_reld_data[89]} {a2l2_axi_0_an_ac_reld_data[88]} {a2l2_axi_0_an_ac_reld_data[87]} {a2l2_axi_0_an_ac_reld_data[86]} {a2l2_axi_0_an_ac_reld_data[85]} {a2l2_axi_0_an_ac_reld_data[84]} {a2l2_axi_0_an_ac_reld_data[83]} {a2l2_axi_0_an_ac_reld_data[82]} {a2l2_axi_0_an_ac_reld_data[81]} {a2l2_axi_0_an_ac_reld_data[80]} {a2l2_axi_0_an_ac_reld_data[79]} {a2l2_axi_0_an_ac_reld_data[78]} {a2l2_axi_0_an_ac_reld_data[77]} {a2l2_axi_0_an_ac_reld_data[76]} {a2l2_axi_0_an_ac_reld_data[75]} {a2l2_axi_0_an_ac_reld_data[74]} {a2l2_axi_0_an_ac_reld_data[73]} {a2l2_axi_0_an_ac_reld_data[72]} {a2l2_axi_0_an_ac_reld_data[71]} {a2l2_axi_0_an_ac_reld_data[70]} {a2l2_axi_0_an_ac_reld_data[69]} {a2l2_axi_0_an_ac_reld_data[68]} {a2l2_axi_0_an_ac_reld_data[67]} {a2l2_axi_0_an_ac_reld_data[66]} {a2l2_axi_0_an_ac_reld_data[65]} {a2l2_axi_0_an_ac_reld_data[64]} {a2l2_axi_0_an_ac_reld_data[63]} {a2l2_axi_0_an_ac_reld_data[62]} {a2l2_axi_0_an_ac_reld_data[61]} {a2l2_axi_0_an_ac_reld_data[60]} {a2l2_axi_0_an_ac_reld_data[59]} {a2l2_axi_0_an_ac_reld_data[58]} {a2l2_axi_0_an_ac_reld_data[57]} {a2l2_axi_0_an_ac_reld_data[56]} {a2l2_axi_0_an_ac_reld_data[55]} {a2l2_axi_0_an_ac_reld_data[54]} {a2l2_axi_0_an_ac_reld_data[53]} {a2l2_axi_0_an_ac_reld_data[52]} {a2l2_axi_0_an_ac_reld_data[51]} {a2l2_axi_0_an_ac_reld_data[50]} {a2l2_axi_0_an_ac_reld_data[49]} {a2l2_axi_0_an_ac_reld_data[48]} {a2l2_axi_0_an_ac_reld_data[47]} {a2l2_axi_0_an_ac_reld_data[46]} {a2l2_axi_0_an_ac_reld_data[45]} {a2l2_axi_0_an_ac_reld_data[44]} {a2l2_axi_0_an_ac_reld_data[43]} {a2l2_axi_0_an_ac_reld_data[42]} {a2l2_axi_0_an_ac_reld_data[41]} {a2l2_axi_0_an_ac_reld_data[40]} {a2l2_axi_0_an_ac_reld_data[39]} {a2l2_axi_0_an_ac_reld_data[38]} {a2l2_axi_0_an_ac_reld_data[37]} {a2l2_axi_0_an_ac_reld_data[36]} {a2l2_axi_0_an_ac_reld_data[35]} {a2l2_axi_0_an_ac_reld_data[34]} {a2l2_axi_0_an_ac_reld_data[33]} {a2l2_axi_0_an_ac_reld_data[32]} {a2l2_axi_0_an_ac_reld_data[31]} {a2l2_axi_0_an_ac_reld_data[30]} {a2l2_axi_0_an_ac_reld_data[29]} {a2l2_axi_0_an_ac_reld_data[28]} {a2l2_axi_0_an_ac_reld_data[27]} {a2l2_axi_0_an_ac_reld_data[26]} {a2l2_axi_0_an_ac_reld_data[25]} {a2l2_axi_0_an_ac_reld_data[24]} {a2l2_axi_0_an_ac_reld_data[23]} {a2l2_axi_0_an_ac_reld_data[22]} {a2l2_axi_0_an_ac_reld_data[21]} {a2l2_axi_0_an_ac_reld_data[20]} {a2l2_axi_0_an_ac_reld_data[19]} {a2l2_axi_0_an_ac_reld_data[18]} {a2l2_axi_0_an_ac_reld_data[17]} {a2l2_axi_0_an_ac_reld_data[16]} {a2l2_axi_0_an_ac_reld_data[15]} {a2l2_axi_0_an_ac_reld_data[14]} {a2l2_axi_0_an_ac_reld_data[13]} {a2l2_axi_0_an_ac_reld_data[12]} {a2l2_axi_0_an_ac_reld_data[11]} {a2l2_axi_0_an_ac_reld_data[10]} {a2l2_axi_0_an_ac_reld_data[9]} {a2l2_axi_0_an_ac_reld_data[8]} {a2l2_axi_0_an_ac_reld_data[7]} {a2l2_axi_0_an_ac_reld_data[6]} {a2l2_axi_0_an_ac_reld_data[5]} {a2l2_axi_0_an_ac_reld_data[4]} {a2l2_axi_0_an_ac_reld_data[3]} {a2l2_axi_0_an_ac_reld_data[2]} {a2l2_axi_0_an_ac_reld_data[1]} {a2l2_axi_0_an_ac_reld_data[0]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 4 [get_debug_ports u_ila_0/probe1]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
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connect_debug_port u_ila_0/probe1 [get_nets [list {a2l2_axi_0_an_ac_sync_ack[3]} {a2l2_axi_0_an_ac_sync_ack[2]} {a2l2_axi_0_an_ac_sync_ack[1]} {a2l2_axi_0_an_ac_sync_ack[0]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 2 [get_debug_ports u_ila_0/probe2]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
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connect_debug_port u_ila_0/probe2 [get_nets [list {a2l2_axi_0_an_ac_reld_qw[59]} {a2l2_axi_0_an_ac_reld_qw[58]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 128 [get_debug_ports u_ila_0/probe3]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
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connect_debug_port u_ila_0/probe3 [get_nets [list {c_wrapper_0_ac_an_st_data[127]} {c_wrapper_0_ac_an_st_data[126]} {c_wrapper_0_ac_an_st_data[125]} {c_wrapper_0_ac_an_st_data[124]} {c_wrapper_0_ac_an_st_data[123]} {c_wrapper_0_ac_an_st_data[122]} {c_wrapper_0_ac_an_st_data[121]} {c_wrapper_0_ac_an_st_data[120]} {c_wrapper_0_ac_an_st_data[119]} {c_wrapper_0_ac_an_st_data[118]} {c_wrapper_0_ac_an_st_data[117]} {c_wrapper_0_ac_an_st_data[116]} {c_wrapper_0_ac_an_st_data[115]} {c_wrapper_0_ac_an_st_data[114]} {c_wrapper_0_ac_an_st_data[113]} {c_wrapper_0_ac_an_st_data[112]} {c_wrapper_0_ac_an_st_data[111]} {c_wrapper_0_ac_an_st_data[110]} {c_wrapper_0_ac_an_st_data[109]} {c_wrapper_0_ac_an_st_data[108]} {c_wrapper_0_ac_an_st_data[107]} {c_wrapper_0_ac_an_st_data[106]} {c_wrapper_0_ac_an_st_data[105]} {c_wrapper_0_ac_an_st_data[104]} {c_wrapper_0_ac_an_st_data[103]} {c_wrapper_0_ac_an_st_data[102]} {c_wrapper_0_ac_an_st_data[101]} {c_wrapper_0_ac_an_st_data[100]} {c_wrapper_0_ac_an_st_data[99]} {c_wrapper_0_ac_an_st_data[98]} {c_wrapper_0_ac_an_st_data[97]} {c_wrapper_0_ac_an_st_data[96]} {c_wrapper_0_ac_an_st_data[95]} {c_wrapper_0_ac_an_st_data[94]} {c_wrapper_0_ac_an_st_data[93]} {c_wrapper_0_ac_an_st_data[92]} {c_wrapper_0_ac_an_st_data[91]} {c_wrapper_0_ac_an_st_data[90]} {c_wrapper_0_ac_an_st_data[89]} {c_wrapper_0_ac_an_st_data[88]} {c_wrapper_0_ac_an_st_data[87]} {c_wrapper_0_ac_an_st_data[86]} {c_wrapper_0_ac_an_st_data[85]} {c_wrapper_0_ac_an_st_data[84]} {c_wrapper_0_ac_an_st_data[83]} {c_wrapper_0_ac_an_st_data[82]} {c_wrapper_0_ac_an_st_data[81]} {c_wrapper_0_ac_an_st_data[80]} {c_wrapper_0_ac_an_st_data[79]} {c_wrapper_0_ac_an_st_data[78]} {c_wrapper_0_ac_an_st_data[77]} {c_wrapper_0_ac_an_st_data[76]} {c_wrapper_0_ac_an_st_data[75]} {c_wrapper_0_ac_an_st_data[74]} {c_wrapper_0_ac_an_st_data[73]} {c_wrapper_0_ac_an_st_data[72]} {c_wrapper_0_ac_an_st_data[71]} {c_wrapper_0_ac_an_st_data[70]} {c_wrapper_0_ac_an_st_data[69]} {c_wrapper_0_ac_an_st_data[68]} {c_wrapper_0_ac_an_st_data[67]} {c_wrapper_0_ac_an_st_data[66]} {c_wrapper_0_ac_an_st_data[65]} {c_wrapper_0_ac_an_st_data[64]} {c_wrapper_0_ac_an_st_data[63]} {c_wrapper_0_ac_an_st_data[62]} {c_wrapper_0_ac_an_st_data[61]} {c_wrapper_0_ac_an_st_data[60]} {c_wrapper_0_ac_an_st_data[59]} {c_wrapper_0_ac_an_st_data[58]} {c_wrapper_0_ac_an_st_data[57]} {c_wrapper_0_ac_an_st_data[56]} {c_wrapper_0_ac_an_st_data[55]} {c_wrapper_0_ac_an_st_data[54]} {c_wrapper_0_ac_an_st_data[53]} {c_wrapper_0_ac_an_st_data[52]} {c_wrapper_0_ac_an_st_data[51]} {c_wrapper_0_ac_an_st_data[50]} {c_wrapper_0_ac_an_st_data[49]} {c_wrapper_0_ac_an_st_data[48]} {c_wrapper_0_ac_an_st_data[47]} {c_wrapper_0_ac_an_st_data[46]} {c_wrapper_0_ac_an_st_data[45]} {c_wrapper_0_ac_an_st_data[44]} {c_wrapper_0_ac_an_st_data[43]} {c_wrapper_0_ac_an_st_data[42]} {c_wrapper_0_ac_an_st_data[41]} {c_wrapper_0_ac_an_st_data[40]} {c_wrapper_0_ac_an_st_data[39]} {c_wrapper_0_ac_an_st_data[38]} {c_wrapper_0_ac_an_st_data[37]} {c_wrapper_0_ac_an_st_data[36]} {c_wrapper_0_ac_an_st_data[35]} {c_wrapper_0_ac_an_st_data[34]} {c_wrapper_0_ac_an_st_data[33]} {c_wrapper_0_ac_an_st_data[32]} {c_wrapper_0_ac_an_st_data[31]} {c_wrapper_0_ac_an_st_data[30]} {c_wrapper_0_ac_an_st_data[29]} {c_wrapper_0_ac_an_st_data[28]} {c_wrapper_0_ac_an_st_data[27]} {c_wrapper_0_ac_an_st_data[26]} {c_wrapper_0_ac_an_st_data[25]} {c_wrapper_0_ac_an_st_data[24]} {c_wrapper_0_ac_an_st_data[23]} {c_wrapper_0_ac_an_st_data[22]} {c_wrapper_0_ac_an_st_data[21]} {c_wrapper_0_ac_an_st_data[20]} {c_wrapper_0_ac_an_st_data[19]} {c_wrapper_0_ac_an_st_data[18]} {c_wrapper_0_ac_an_st_data[17]} {c_wrapper_0_ac_an_st_data[16]} {c_wrapper_0_ac_an_st_data[15]} {c_wrapper_0_ac_an_st_data[14]} {c_wrapper_0_ac_an_st_data[13]} {c_wrapper_0_ac_an_st_data[12]} {c_wrapper_0_ac_an_st_data[11]} {c_wrapper_0_ac_an_st_data[10]} {c_wrapper_0_ac_an_st_data[9]} {c_wrapper_0_ac_an_st_data[8]} {c_wrapper_0_ac_an_st_data[7]} {c_wrapper_0_ac_an_st_data[6]} {c_wrapper_0_ac_an_st_data[5]} {c_wrapper_0_ac_an_st_data[4]} {c_wrapper_0_ac_an_st_data[3]} {c_wrapper_0_ac_an_st_data[2]} {c_wrapper_0_ac_an_st_data[1]} {c_wrapper_0_ac_an_st_data[0]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 6 [get_debug_ports u_ila_0/probe4]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
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connect_debug_port u_ila_0/probe4 [get_nets [list {c_wrapper_0_ac_an_req_ttype[5]} {c_wrapper_0_ac_an_req_ttype[4]} {c_wrapper_0_ac_an_req_ttype[3]} {c_wrapper_0_ac_an_req_ttype[2]} {c_wrapper_0_ac_an_req_ttype[1]} {c_wrapper_0_ac_an_req_ttype[0]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 1 [get_debug_ports u_ila_0/probe5]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
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connect_debug_port u_ila_0/probe5 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/icd_icm_addr_real[51]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 4 [get_debug_ports u_ila_0/probe6]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
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connect_debug_port u_ila_0/probe6 [get_nets [list {a2l2_axi_0/inst/ldq_count_q_reg[3]} {a2l2_axi_0/inst/ldq_count_q_reg[2]} {a2l2_axi_0/inst/ldq_count_q_reg[1]} {a2l2_axi_0/inst/ldq_count_q_reg[0]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 22 [get_debug_ports u_ila_0/probe7]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
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connect_debug_port u_ila_0/probe7 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[32]} ]]
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create_debug_port u_ila_0 probe
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set_property port_width 32 [get_debug_ports u_ila_0/probe8]
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set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[63]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[55]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[53]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[49]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[45]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[43]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[41]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[39]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[37]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[33]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[32]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {c_wrapper_0_ac_an_req_ra[63]} {c_wrapper_0_ac_an_req_ra[62]} {c_wrapper_0_ac_an_req_ra[61]} {c_wrapper_0_ac_an_req_ra[60]} {c_wrapper_0_ac_an_req_ra[59]} {c_wrapper_0_ac_an_req_ra[58]} {c_wrapper_0_ac_an_req_ra[57]} {c_wrapper_0_ac_an_req_ra[56]} {c_wrapper_0_ac_an_req_ra[55]} {c_wrapper_0_ac_an_req_ra[54]} {c_wrapper_0_ac_an_req_ra[53]} {c_wrapper_0_ac_an_req_ra[52]} {c_wrapper_0_ac_an_req_ra[51]} {c_wrapper_0_ac_an_req_ra[50]} {c_wrapper_0_ac_an_req_ra[49]} {c_wrapper_0_ac_an_req_ra[48]} {c_wrapper_0_ac_an_req_ra[47]} {c_wrapper_0_ac_an_req_ra[46]} {c_wrapper_0_ac_an_req_ra[45]} {c_wrapper_0_ac_an_req_ra[44]} {c_wrapper_0_ac_an_req_ra[43]} {c_wrapper_0_ac_an_req_ra[42]} {c_wrapper_0_ac_an_req_ra[41]} {c_wrapper_0_ac_an_req_ra[40]} {c_wrapper_0_ac_an_req_ra[39]} {c_wrapper_0_ac_an_req_ra[38]} {c_wrapper_0_ac_an_req_ra[37]} {c_wrapper_0_ac_an_req_ra[36]} {c_wrapper_0_ac_an_req_ra[35]} {c_wrapper_0_ac_an_req_ra[34]} {c_wrapper_0_ac_an_req_ra[33]} {c_wrapper_0_ac_an_req_ra[32]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe10]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {c_wrapper_0_ac_an_req_ld_xfr_len[2]} {c_wrapper_0_ac_an_req_ld_xfr_len[1]} {c_wrapper_0_ac_an_req_ld_xfr_len[0]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 62 [get_debug_ports u_ila_0/probe11]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[61]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[60]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[59]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[58]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[57]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[56]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[55]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[54]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[53]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[52]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[51]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[50]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[49]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[48]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[47]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[46]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[45]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[44]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[43]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[42]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[41]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[40]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[39]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[38]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[37]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[36]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[35]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[34]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[33]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[32]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[31]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[30]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[29]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[28]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[27]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[26]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[25]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[24]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[23]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[22]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[21]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[20]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[19]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[18]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[17]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[16]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[15]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[14]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[13]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[12]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[11]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[10]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[9]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[8]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[7]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[6]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[5]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[4]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[3]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[2]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[1]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[0]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 5 [get_debug_ports u_ila_0/probe12]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {c_wrapper_0_ac_an_req_ld_core_tag[4]} {c_wrapper_0_ac_an_req_ld_core_tag[3]} {c_wrapper_0_ac_an_req_ld_core_tag[2]} {c_wrapper_0_ac_an_req_ld_core_tag[1]} {c_wrapper_0_ac_an_req_ld_core_tag[0]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 58 [get_debug_ports u_ila_0/probe13]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[29]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[28]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[27]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[26]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[25]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[24]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[23]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[22]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[21]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[20]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[19]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[18]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[17]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[16]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[15]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[14]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[13]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[12]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[11]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[10]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[9]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[8]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[7]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[6]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[5]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[4]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[3]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[2]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[1]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[0]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe14]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[53]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[59]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[60]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[61]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe15]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {a2l2_axi_0/inst/stq_count_q_reg[5]} {a2l2_axi_0/inst/stq_count_q_reg[4]} {a2l2_axi_0/inst/stq_count_q_reg[3]} {a2l2_axi_0/inst/stq_count_q_reg[2]} {a2l2_axi_0/inst/stq_count_q_reg[1]} {a2l2_axi_0/inst/stq_count_q_reg[0]} ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list a2l2_axi_0_an_ac_reld_crit_qw ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list a2l2_axi_0_an_ac_reld_data_vld ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list a2l2_axi_0_an_ac_req_ld_pop ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list a2l2_axi_0_an_ac_req_st_pop ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list c_wrapper_0_ac_an_req ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list c_wrapper_0_ac_an_req_wimg_i ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/icd_icm_miss ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/ics_icd_iu1_flush ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_enable_q ]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_pulse_q ]]
|
||||
|
@ -0,0 +1,44 @@
|
||||
#synth_design -top a2o_bd -part xcvu3p-ffvc1517-2-e -verbose
|
||||
#source ila_axi.tcl
|
||||
|
||||
# ----------------------------------------------------------------------------------------
|
||||
# opt place phys_opt route phys_opt
|
||||
# ----------------------------------------------------------------------------------------
|
||||
# v0 (1) Explore Explore Explore Explore
|
||||
# v1 Explore Explore Explore Explore Explore
|
||||
# ----------------------------------------------------------------------------------------
|
||||
# (1) -retarget -propconst -bram_power_opt
|
||||
#
|
||||
set version v0
|
||||
|
||||
# make sure synth is open
|
||||
open_run synth_1
|
||||
|
||||
write_checkpoint -force a2o_synth_${version}.dcp
|
||||
|
||||
if {$version == {v0}} {
|
||||
opt_design -retarget -propconst -bram_power_opt -debug_log
|
||||
} elseif {$version == {v1}} {
|
||||
opt_design -directive Explore -debug_log
|
||||
} else {
|
||||
opt_design -debug_log
|
||||
}
|
||||
|
||||
place_design -directive Explore
|
||||
#place_design -directive Explore -no_bufg_opt
|
||||
|
||||
phys_opt_design -directive Explore
|
||||
route_design -directive Explore
|
||||
phys_opt_design -directive Explore
|
||||
|
||||
write_checkpoint -force a2o_routed_${version}.dcp
|
||||
|
||||
report_utilization -file utilization_route_design_${version}.rpt
|
||||
report_timing_summary -max_paths 100 -file timing_routed_summary_${version}.rpt
|
||||
report_bus_skew -file timing_bus_skew_${version}.rpt
|
||||
report_qor_suggestions -file qor_suggestions_${version}.rpt
|
||||
|
||||
write_bitstream -force -bin_file a2o_${version}
|
||||
write_debug_probes -force a2o_${version}
|
||||
write_cfgmem -force -format BIN -interface SPIx8 -size 256 -loadbit "up 0 a2o_${version}.bit" a2o_${version}
|
||||
|
@ -0,0 +1,31 @@
|
||||
# create/build project
|
||||
|
||||
```
|
||||
$VIVADO -mode tcl -source create_project.tcl
|
||||
|
||||
$VIVADO a2o_bd/a2o_bd.xpr
|
||||
|
||||
>run synthesis
|
||||
|
||||
source ./ila.tcl ;# to update ila_0, or set up debug manually
|
||||
|
||||
source ./impl.tcl
|
||||
```
|
||||
|
||||
```
|
||||
a2o_bd_routed_v0.dcp
|
||||
a2o_bd_synth_v0.dcp
|
||||
|
||||
utilization_route_design_v0.rpt
|
||||
timing_routed_summary_v0.rpt
|
||||
timing_bus_skew_v0.rpt
|
||||
qor_suggestions_v0.rpt
|
||||
|
||||
a2o_bd_v0.bin
|
||||
a2o_bd_v0.bit
|
||||
a2o_bd_v0.ltx
|
||||
a2o_bd_v0_primary.bin
|
||||
a2o_bd_v0_primary.prm
|
||||
a2o_bd_v0_secondary.bin
|
||||
a2o_bd_v0_secondary.prm
|
||||
```
|
@ -0,0 +1,126 @@
|
||||
set_property DONT_TOUCH true [get_cells a2l2_axi_0]
|
||||
# added by vivado...
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 32768 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_0_clk]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 128 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {a2l2_axi_0_an_ac_reld_data[127]} {a2l2_axi_0_an_ac_reld_data[126]} {a2l2_axi_0_an_ac_reld_data[125]} {a2l2_axi_0_an_ac_reld_data[124]} {a2l2_axi_0_an_ac_reld_data[123]} {a2l2_axi_0_an_ac_reld_data[122]} {a2l2_axi_0_an_ac_reld_data[121]} {a2l2_axi_0_an_ac_reld_data[120]} {a2l2_axi_0_an_ac_reld_data[119]} {a2l2_axi_0_an_ac_reld_data[118]} {a2l2_axi_0_an_ac_reld_data[117]} {a2l2_axi_0_an_ac_reld_data[116]} {a2l2_axi_0_an_ac_reld_data[115]} {a2l2_axi_0_an_ac_reld_data[114]} {a2l2_axi_0_an_ac_reld_data[113]} {a2l2_axi_0_an_ac_reld_data[112]} {a2l2_axi_0_an_ac_reld_data[111]} {a2l2_axi_0_an_ac_reld_data[110]} {a2l2_axi_0_an_ac_reld_data[109]} {a2l2_axi_0_an_ac_reld_data[108]} {a2l2_axi_0_an_ac_reld_data[107]} {a2l2_axi_0_an_ac_reld_data[106]} {a2l2_axi_0_an_ac_reld_data[105]} {a2l2_axi_0_an_ac_reld_data[104]} {a2l2_axi_0_an_ac_reld_data[103]} {a2l2_axi_0_an_ac_reld_data[102]} {a2l2_axi_0_an_ac_reld_data[101]} {a2l2_axi_0_an_ac_reld_data[100]} {a2l2_axi_0_an_ac_reld_data[99]} {a2l2_axi_0_an_ac_reld_data[98]} {a2l2_axi_0_an_ac_reld_data[97]} {a2l2_axi_0_an_ac_reld_data[96]} {a2l2_axi_0_an_ac_reld_data[95]} {a2l2_axi_0_an_ac_reld_data[94]} {a2l2_axi_0_an_ac_reld_data[93]} {a2l2_axi_0_an_ac_reld_data[92]} {a2l2_axi_0_an_ac_reld_data[91]} {a2l2_axi_0_an_ac_reld_data[90]} {a2l2_axi_0_an_ac_reld_data[89]} {a2l2_axi_0_an_ac_reld_data[88]} {a2l2_axi_0_an_ac_reld_data[87]} {a2l2_axi_0_an_ac_reld_data[86]} {a2l2_axi_0_an_ac_reld_data[85]} {a2l2_axi_0_an_ac_reld_data[84]} {a2l2_axi_0_an_ac_reld_data[83]} {a2l2_axi_0_an_ac_reld_data[82]} {a2l2_axi_0_an_ac_reld_data[81]} {a2l2_axi_0_an_ac_reld_data[80]} {a2l2_axi_0_an_ac_reld_data[79]} {a2l2_axi_0_an_ac_reld_data[78]} {a2l2_axi_0_an_ac_reld_data[77]} {a2l2_axi_0_an_ac_reld_data[76]} {a2l2_axi_0_an_ac_reld_data[75]} {a2l2_axi_0_an_ac_reld_data[74]} {a2l2_axi_0_an_ac_reld_data[73]} {a2l2_axi_0_an_ac_reld_data[72]} {a2l2_axi_0_an_ac_reld_data[71]} {a2l2_axi_0_an_ac_reld_data[70]} {a2l2_axi_0_an_ac_reld_data[69]} {a2l2_axi_0_an_ac_reld_data[68]} {a2l2_axi_0_an_ac_reld_data[67]} {a2l2_axi_0_an_ac_reld_data[66]} {a2l2_axi_0_an_ac_reld_data[65]} {a2l2_axi_0_an_ac_reld_data[64]} {a2l2_axi_0_an_ac_reld_data[63]} {a2l2_axi_0_an_ac_reld_data[62]} {a2l2_axi_0_an_ac_reld_data[61]} {a2l2_axi_0_an_ac_reld_data[60]} {a2l2_axi_0_an_ac_reld_data[59]} {a2l2_axi_0_an_ac_reld_data[58]} {a2l2_axi_0_an_ac_reld_data[57]} {a2l2_axi_0_an_ac_reld_data[56]} {a2l2_axi_0_an_ac_reld_data[55]} {a2l2_axi_0_an_ac_reld_data[54]} {a2l2_axi_0_an_ac_reld_data[53]} {a2l2_axi_0_an_ac_reld_data[52]} {a2l2_axi_0_an_ac_reld_data[51]} {a2l2_axi_0_an_ac_reld_data[50]} {a2l2_axi_0_an_ac_reld_data[49]} {a2l2_axi_0_an_ac_reld_data[48]} {a2l2_axi_0_an_ac_reld_data[47]} {a2l2_axi_0_an_ac_reld_data[46]} {a2l2_axi_0_an_ac_reld_data[45]} {a2l2_axi_0_an_ac_reld_data[44]} {a2l2_axi_0_an_ac_reld_data[43]} {a2l2_axi_0_an_ac_reld_data[42]} {a2l2_axi_0_an_ac_reld_data[41]} {a2l2_axi_0_an_ac_reld_data[40]} {a2l2_axi_0_an_ac_reld_data[39]} {a2l2_axi_0_an_ac_reld_data[38]} {a2l2_axi_0_an_ac_reld_data[37]} {a2l2_axi_0_an_ac_reld_data[36]} {a2l2_axi_0_an_ac_reld_data[35]} {a2l2_axi_0_an_ac_reld_data[34]} {a2l2_axi_0_an_ac_reld_data[33]} {a2l2_axi_0_an_ac_reld_data[32]} {a2l2_axi_0_an_ac_reld_data[31]} {a2l2_axi_0_an_ac_reld_data[30]} {a2l2_axi_0_an_ac_reld_data[29]} {a2l2_axi_0_an_ac_reld_data[28]} {a2l2_axi_0_an_ac_reld_data[27]} {a2l2_axi_0_an_ac_reld_data[26]} {a2l2_axi_0_an_ac_reld_data[25]} {a2l2_axi_0_an_ac_reld_data[24]} {a2l2_axi_0_an_ac_reld_data[23]} {a2l2_axi_0_an_ac_reld_data[22]} {a2l2_axi_0_an_ac_reld_data[21]} {a2l2_axi_0_an_ac_reld_data[20]} {a2l2_axi_0_an_ac_reld_data[19]} {a2l2_axi_0_an_ac_reld_data[18]} {a2l2_axi_0_an_ac_reld_data[17]} {a2l2_axi_0_an_ac_reld_data[16]} {a2l2_axi_0_an_ac_reld_data[15]} {a2l2_axi_0_an_ac_reld_data[14]} {a2l2_axi_0_an_ac_reld_data[13]} {a2l2_axi_0_an_ac_reld_data[12]} {a2l2_axi_0_an_ac_reld_data[11]} {a2l2_axi_0_an_ac_reld_data[10]} {a2l2_axi_0_an_ac_reld_data[9]} {a2l2_axi_0_an_ac_reld_data[8]} {a2l2_axi_0_an_ac_reld_data[7]} {a2l2_axi_0_an_ac_reld_data[6]} {a2l2_axi_0_an_ac_reld_data[5]} {a2l2_axi_0_an_ac_reld_data[4]} {a2l2_axi_0_an_ac_reld_data[3]} {a2l2_axi_0_an_ac_reld_data[2]} {a2l2_axi_0_an_ac_reld_data[1]} {a2l2_axi_0_an_ac_reld_data[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {a2l2_axi_0_an_ac_sync_ack[3]} {a2l2_axi_0_an_ac_sync_ack[2]} {a2l2_axi_0_an_ac_sync_ack[1]} {a2l2_axi_0_an_ac_sync_ack[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {a2l2_axi_0_an_ac_reld_qw[59]} {a2l2_axi_0_an_ac_reld_qw[58]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 128 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {c_wrapper_0_ac_an_st_data[127]} {c_wrapper_0_ac_an_st_data[126]} {c_wrapper_0_ac_an_st_data[125]} {c_wrapper_0_ac_an_st_data[124]} {c_wrapper_0_ac_an_st_data[123]} {c_wrapper_0_ac_an_st_data[122]} {c_wrapper_0_ac_an_st_data[121]} {c_wrapper_0_ac_an_st_data[120]} {c_wrapper_0_ac_an_st_data[119]} {c_wrapper_0_ac_an_st_data[118]} {c_wrapper_0_ac_an_st_data[117]} {c_wrapper_0_ac_an_st_data[116]} {c_wrapper_0_ac_an_st_data[115]} {c_wrapper_0_ac_an_st_data[114]} {c_wrapper_0_ac_an_st_data[113]} {c_wrapper_0_ac_an_st_data[112]} {c_wrapper_0_ac_an_st_data[111]} {c_wrapper_0_ac_an_st_data[110]} {c_wrapper_0_ac_an_st_data[109]} {c_wrapper_0_ac_an_st_data[108]} {c_wrapper_0_ac_an_st_data[107]} {c_wrapper_0_ac_an_st_data[106]} {c_wrapper_0_ac_an_st_data[105]} {c_wrapper_0_ac_an_st_data[104]} {c_wrapper_0_ac_an_st_data[103]} {c_wrapper_0_ac_an_st_data[102]} {c_wrapper_0_ac_an_st_data[101]} {c_wrapper_0_ac_an_st_data[100]} {c_wrapper_0_ac_an_st_data[99]} {c_wrapper_0_ac_an_st_data[98]} {c_wrapper_0_ac_an_st_data[97]} {c_wrapper_0_ac_an_st_data[96]} {c_wrapper_0_ac_an_st_data[95]} {c_wrapper_0_ac_an_st_data[94]} {c_wrapper_0_ac_an_st_data[93]} {c_wrapper_0_ac_an_st_data[92]} {c_wrapper_0_ac_an_st_data[91]} {c_wrapper_0_ac_an_st_data[90]} {c_wrapper_0_ac_an_st_data[89]} {c_wrapper_0_ac_an_st_data[88]} {c_wrapper_0_ac_an_st_data[87]} {c_wrapper_0_ac_an_st_data[86]} {c_wrapper_0_ac_an_st_data[85]} {c_wrapper_0_ac_an_st_data[84]} {c_wrapper_0_ac_an_st_data[83]} {c_wrapper_0_ac_an_st_data[82]} {c_wrapper_0_ac_an_st_data[81]} {c_wrapper_0_ac_an_st_data[80]} {c_wrapper_0_ac_an_st_data[79]} {c_wrapper_0_ac_an_st_data[78]} {c_wrapper_0_ac_an_st_data[77]} {c_wrapper_0_ac_an_st_data[76]} {c_wrapper_0_ac_an_st_data[75]} {c_wrapper_0_ac_an_st_data[74]} {c_wrapper_0_ac_an_st_data[73]} {c_wrapper_0_ac_an_st_data[72]} {c_wrapper_0_ac_an_st_data[71]} {c_wrapper_0_ac_an_st_data[70]} {c_wrapper_0_ac_an_st_data[69]} {c_wrapper_0_ac_an_st_data[68]} {c_wrapper_0_ac_an_st_data[67]} {c_wrapper_0_ac_an_st_data[66]} {c_wrapper_0_ac_an_st_data[65]} {c_wrapper_0_ac_an_st_data[64]} {c_wrapper_0_ac_an_st_data[63]} {c_wrapper_0_ac_an_st_data[62]} {c_wrapper_0_ac_an_st_data[61]} {c_wrapper_0_ac_an_st_data[60]} {c_wrapper_0_ac_an_st_data[59]} {c_wrapper_0_ac_an_st_data[58]} {c_wrapper_0_ac_an_st_data[57]} {c_wrapper_0_ac_an_st_data[56]} {c_wrapper_0_ac_an_st_data[55]} {c_wrapper_0_ac_an_st_data[54]} {c_wrapper_0_ac_an_st_data[53]} {c_wrapper_0_ac_an_st_data[52]} {c_wrapper_0_ac_an_st_data[51]} {c_wrapper_0_ac_an_st_data[50]} {c_wrapper_0_ac_an_st_data[49]} {c_wrapper_0_ac_an_st_data[48]} {c_wrapper_0_ac_an_st_data[47]} {c_wrapper_0_ac_an_st_data[46]} {c_wrapper_0_ac_an_st_data[45]} {c_wrapper_0_ac_an_st_data[44]} {c_wrapper_0_ac_an_st_data[43]} {c_wrapper_0_ac_an_st_data[42]} {c_wrapper_0_ac_an_st_data[41]} {c_wrapper_0_ac_an_st_data[40]} {c_wrapper_0_ac_an_st_data[39]} {c_wrapper_0_ac_an_st_data[38]} {c_wrapper_0_ac_an_st_data[37]} {c_wrapper_0_ac_an_st_data[36]} {c_wrapper_0_ac_an_st_data[35]} {c_wrapper_0_ac_an_st_data[34]} {c_wrapper_0_ac_an_st_data[33]} {c_wrapper_0_ac_an_st_data[32]} {c_wrapper_0_ac_an_st_data[31]} {c_wrapper_0_ac_an_st_data[30]} {c_wrapper_0_ac_an_st_data[29]} {c_wrapper_0_ac_an_st_data[28]} {c_wrapper_0_ac_an_st_data[27]} {c_wrapper_0_ac_an_st_data[26]} {c_wrapper_0_ac_an_st_data[25]} {c_wrapper_0_ac_an_st_data[24]} {c_wrapper_0_ac_an_st_data[23]} {c_wrapper_0_ac_an_st_data[22]} {c_wrapper_0_ac_an_st_data[21]} {c_wrapper_0_ac_an_st_data[20]} {c_wrapper_0_ac_an_st_data[19]} {c_wrapper_0_ac_an_st_data[18]} {c_wrapper_0_ac_an_st_data[17]} {c_wrapper_0_ac_an_st_data[16]} {c_wrapper_0_ac_an_st_data[15]} {c_wrapper_0_ac_an_st_data[14]} {c_wrapper_0_ac_an_st_data[13]} {c_wrapper_0_ac_an_st_data[12]} {c_wrapper_0_ac_an_st_data[11]} {c_wrapper_0_ac_an_st_data[10]} {c_wrapper_0_ac_an_st_data[9]} {c_wrapper_0_ac_an_st_data[8]} {c_wrapper_0_ac_an_st_data[7]} {c_wrapper_0_ac_an_st_data[6]} {c_wrapper_0_ac_an_st_data[5]} {c_wrapper_0_ac_an_st_data[4]} {c_wrapper_0_ac_an_st_data[3]} {c_wrapper_0_ac_an_st_data[2]} {c_wrapper_0_ac_an_st_data[1]} {c_wrapper_0_ac_an_st_data[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {c_wrapper_0_ac_an_req_ttype[5]} {c_wrapper_0_ac_an_req_ttype[4]} {c_wrapper_0_ac_an_req_ttype[3]} {c_wrapper_0_ac_an_req_ttype[2]} {c_wrapper_0_ac_an_req_ttype[1]} {c_wrapper_0_ac_an_req_ttype[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/icd_icm_addr_real[51]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {a2l2_axi_0/inst/ldq_count_q_reg[3]} {a2l2_axi_0/inst/ldq_count_q_reg[2]} {a2l2_axi_0/inst/ldq_count_q_reg[1]} {a2l2_axi_0/inst/ldq_count_q_reg[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 22 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[32]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[63]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[55]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[53]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[49]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[45]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[43]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[41]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[39]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[37]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[33]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[32]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {c_wrapper_0_ac_an_req_ra[63]} {c_wrapper_0_ac_an_req_ra[62]} {c_wrapper_0_ac_an_req_ra[61]} {c_wrapper_0_ac_an_req_ra[60]} {c_wrapper_0_ac_an_req_ra[59]} {c_wrapper_0_ac_an_req_ra[58]} {c_wrapper_0_ac_an_req_ra[57]} {c_wrapper_0_ac_an_req_ra[56]} {c_wrapper_0_ac_an_req_ra[55]} {c_wrapper_0_ac_an_req_ra[54]} {c_wrapper_0_ac_an_req_ra[53]} {c_wrapper_0_ac_an_req_ra[52]} {c_wrapper_0_ac_an_req_ra[51]} {c_wrapper_0_ac_an_req_ra[50]} {c_wrapper_0_ac_an_req_ra[49]} {c_wrapper_0_ac_an_req_ra[48]} {c_wrapper_0_ac_an_req_ra[47]} {c_wrapper_0_ac_an_req_ra[46]} {c_wrapper_0_ac_an_req_ra[45]} {c_wrapper_0_ac_an_req_ra[44]} {c_wrapper_0_ac_an_req_ra[43]} {c_wrapper_0_ac_an_req_ra[42]} {c_wrapper_0_ac_an_req_ra[41]} {c_wrapper_0_ac_an_req_ra[40]} {c_wrapper_0_ac_an_req_ra[39]} {c_wrapper_0_ac_an_req_ra[38]} {c_wrapper_0_ac_an_req_ra[37]} {c_wrapper_0_ac_an_req_ra[36]} {c_wrapper_0_ac_an_req_ra[35]} {c_wrapper_0_ac_an_req_ra[34]} {c_wrapper_0_ac_an_req_ra[33]} {c_wrapper_0_ac_an_req_ra[32]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {c_wrapper_0_ac_an_req_ld_xfr_len[2]} {c_wrapper_0_ac_an_req_ld_xfr_len[1]} {c_wrapper_0_ac_an_req_ld_xfr_len[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 62 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[61]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[60]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[59]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[58]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[57]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[56]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[55]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[54]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[53]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[52]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[51]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[50]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[49]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[48]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[47]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[46]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[45]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[44]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[43]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[42]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[41]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[40]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[39]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[38]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[37]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[36]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[35]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[34]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[33]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[32]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[31]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[30]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[29]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[28]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[27]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[26]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[25]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[24]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[23]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[22]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[21]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[20]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[19]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[18]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[17]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[16]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[15]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[14]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[13]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[12]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[11]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[10]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[9]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[8]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[7]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[6]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[5]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[4]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[3]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[2]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[1]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 5 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {c_wrapper_0_ac_an_req_ld_core_tag[4]} {c_wrapper_0_ac_an_req_ld_core_tag[3]} {c_wrapper_0_ac_an_req_ld_core_tag[2]} {c_wrapper_0_ac_an_req_ld_core_tag[1]} {c_wrapper_0_ac_an_req_ld_core_tag[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 58 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[29]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[28]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[27]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[26]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[25]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[24]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[23]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[22]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[21]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[20]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[19]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[18]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[17]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[16]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[15]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[14]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[13]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[12]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[11]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[10]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[9]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[8]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[7]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[6]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[5]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[4]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[3]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[2]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[1]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[53]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[59]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[60]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[61]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {a2l2_axi_0/inst/stq_count_q_reg[5]} {a2l2_axi_0/inst/stq_count_q_reg[4]} {a2l2_axi_0/inst/stq_count_q_reg[3]} {a2l2_axi_0/inst/stq_count_q_reg[2]} {a2l2_axi_0/inst/stq_count_q_reg[1]} {a2l2_axi_0/inst/stq_count_q_reg[0]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list a2l2_axi_0_an_ac_reld_crit_qw]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list a2l2_axi_0_an_ac_reld_data_vld]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list a2l2_axi_0_an_ac_req_ld_pop]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list a2l2_axi_0_an_ac_req_st_pop]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list c_wrapper_0_ac_an_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list c_wrapper_0_ac_an_req_wimg_i]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/icd_icm_miss]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/ics_icd_iu1_flush]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_enable_q]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_pulse_q]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets clk_wiz_0_clk]
|
@ -0,0 +1,5 @@
|
||||
set_property IOSTANDARD LVDS [get_ports clk_in1_n_0]
|
||||
set_property PACKAGE_PIN AP26 [get_ports clk_in1_p_0]
|
||||
set_property PACKAGE_PIN AP27 [get_ports clk_in1_n_0]
|
||||
set_property IOSTANDARD LVDS [get_ports clk_in1_p_0]
|
||||
|
@ -0,0 +1,14 @@
|
||||
## Settings to generate MSC file
|
||||
# Configuration from SPI Flash as per XAPP1233
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
# Set CFGBVS to GND to match schematics
|
||||
set_property CFGBVS GND [current_design]
|
||||
# Set CONFIG_VOLTAGE to 1.8V to match schematics
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
# Set safety trigger to power down FPGA at 125degC
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
@ -0,0 +1,4 @@
|
||||
create_generated_clock -name clk [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0]
|
||||
create_generated_clock -name clk2x [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1]
|
||||
create_generated_clock -name clk4x [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT2]
|
||||
|
@ -0,0 +1,8 @@
|
||||
# create IP: a2l2_axi
|
||||
|
||||
```
|
||||
$VIVADO -mode tcl -source tcl/create_ip_a2l2_axi.tcl
|
||||
rm -r ../../ip_repo/a2l2_axi
|
||||
cp -r a2l2_axi ../../ip_repo
|
||||
```
|
||||
|
@ -0,0 +1 @@
|
||||
../../tcl
|
@ -0,0 +1 @@
|
||||
../../../src/vhdl
|
@ -0,0 +1 @@
|
||||
../../../src/vhdl
|
@ -0,0 +1,8 @@
|
||||
# create IP: a2o_axi_reg
|
||||
|
||||
```
|
||||
$VIVADO -mode tcl -source tcl/create_ip_a2o_axi_reg.tcl
|
||||
rm -r ../../ip_repo/a2o_axi_reg
|
||||
cp -r a2o_axi_reg ../../ip_repo
|
||||
```
|
||||
|
@ -0,0 +1 @@
|
||||
../../tcl
|
@ -0,0 +1 @@
|
||||
../../../src/vhdl
|
@ -0,0 +1 @@
|
||||
../../../src/vhdl
|
@ -0,0 +1,8 @@
|
||||
# create IP: a2o_core
|
||||
|
||||
```
|
||||
$VIVADO -mode tcl -source tcl/create_ip_a2o_core.tcl
|
||||
rm -r ../../ip_repo/c_wrapper
|
||||
cp -r c_wrapper ../../ip_repo
|
||||
```
|
||||
|
@ -0,0 +1 @@
|
||||
../../tcl
|
@ -0,0 +1 @@
|
||||
../../../src/verilog
|
@ -0,0 +1 @@
|
||||
../../../src/vhdl
|
@ -0,0 +1,8 @@
|
||||
# create IP: a2o_dbug
|
||||
|
||||
```
|
||||
$VIVADO -mode tcl -source tcl/create_ip_a2o_dbug.tcl
|
||||
rm -r ../../ip_repo/a2o_dbug
|
||||
cp -r a2o_dbug ../../ip_repo
|
||||
```
|
||||
|
@ -0,0 +1 @@
|
||||
../../tcl
|
@ -0,0 +1 @@
|
||||
../../../src/vhdl
|
@ -0,0 +1 @@
|
||||
../../../src/vhdl
|
@ -0,0 +1,62 @@
|
||||
# ip creator
|
||||
|
||||
set project reverserator_3 ;# also top
|
||||
set keep 0 ;# keep project
|
||||
set xdc "" ;# set to xdc file if exists
|
||||
set synth_check 1
|
||||
|
||||
proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} {
|
||||
|
||||
set vhdl_dir [file normalize ./vhdl]
|
||||
set output_dir .
|
||||
set project_dir ./prj
|
||||
|
||||
create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e
|
||||
|
||||
add_files -norecurse $vhdl_dir
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
set_property top $project [current_fileset]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property default_lib work [current_project]
|
||||
set_property top $project [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property simulator_language VHDL [current_project]
|
||||
|
||||
if {$xdc != ""} {
|
||||
set xdc_dir [file normalize ./xdc]
|
||||
read_xdc $xdc_dir/$xdc
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
if {$synth_check} {
|
||||
synth_design -rtl -name elab_for_sanity_check
|
||||
}
|
||||
|
||||
ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
|
||||
ipx::unload_core $output_dir/$project/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision 2 [ipx::current_core]
|
||||
ipx::update_source_project_archive -component [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
ipx::move_temp_component_back -component [ipx::current_core]
|
||||
|
||||
if {$keep_project} {
|
||||
close_project
|
||||
puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
|
||||
} else {
|
||||
close_project -delete
|
||||
exec rm -rf $output_dir/$project_dir
|
||||
puts "Project built; only IP files kept."
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
create_ip $project $keep $synth_check $xdc
|
||||
|
@ -0,0 +1,8 @@
|
||||
# create IP: reverserator_3
|
||||
|
||||
```
|
||||
$VIVADO -mode tcl -source ./create_ip.tcl
|
||||
rm -r ../../ip_repo/reverserator_3
|
||||
cp -r reverserator_3 ../../ip_repo
|
||||
```
|
||||
|
@ -0,0 +1,48 @@
|
||||
-- © IBM Corp. 2020
|
||||
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
-- the terms below; you may not use the files in this repository except in
|
||||
-- compliance with the License as modified.
|
||||
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
--
|
||||
-- Modified Terms:
|
||||
--
|
||||
-- 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
-- License, the "Work" hereby includes implementations of the work of authorship
|
||||
-- in physical form.
|
||||
--
|
||||
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
-- necessary for implementation of the Work that are available from OpenPOWER
|
||||
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
-- of the EULA.
|
||||
--
|
||||
-- Unless required by applicable law or agreed to in writing, the reference design
|
||||
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
-- for the specific language governing permissions and limitations under the License.
|
||||
--
|
||||
-- Additional rights, including the ability to physically implement a softcore that
|
||||
-- is compliant with the required sections of the Power ISA Specification, are
|
||||
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
-- terminate yet another rare xil bug
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity reverserator_3 is
|
||||
port (
|
||||
outdoor : in std_logic_vector(0 to 2);
|
||||
inndoor : out std_logic_vector(2 downto 0)
|
||||
);
|
||||
end reverserator_3;
|
||||
|
||||
architecture reverserator_3 of reverserator_3 is
|
||||
begin
|
||||
|
||||
inndoor <= outdoor;
|
||||
|
||||
end reverserator_3;
|
||||
|
@ -0,0 +1,62 @@
|
||||
# ip creator
|
||||
|
||||
set project reverserator_4 ;# also top
|
||||
set keep 0 ;# keep project
|
||||
set xdc "" ;# set to xdc file if exists
|
||||
set synth_check 1
|
||||
|
||||
proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} {
|
||||
|
||||
set vhdl_dir [file normalize ./vhdl]
|
||||
set output_dir .
|
||||
set project_dir ./prj
|
||||
|
||||
create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e
|
||||
|
||||
add_files -norecurse $vhdl_dir
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
set_property top $project [current_fileset]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property default_lib work [current_project]
|
||||
set_property top $project [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property simulator_language VHDL [current_project]
|
||||
|
||||
if {$xdc != ""} {
|
||||
set xdc_dir [file normalize ./xdc]
|
||||
read_xdc $xdc_dir/$xdc
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
if {$synth_check} {
|
||||
synth_design -rtl -name elab_for_sanity_check
|
||||
}
|
||||
|
||||
ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
|
||||
ipx::unload_core $output_dir/$project/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision 2 [ipx::current_core]
|
||||
ipx::update_source_project_archive -component [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
ipx::move_temp_component_back -component [ipx::current_core]
|
||||
|
||||
if {$keep_project} {
|
||||
close_project
|
||||
puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
|
||||
} else {
|
||||
close_project -delete
|
||||
exec rm -rf $output_dir/$project_dir
|
||||
puts "Project built; only IP files kept."
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
create_ip $project $keep $synth_check $xdc
|
||||
|
@ -0,0 +1,8 @@
|
||||
# create IP: reverserator_4
|
||||
|
||||
```
|
||||
$VIVADO -mode tcl -source ./create_ip.tcl
|
||||
rm -r ../../ip_repo/reverserator_4
|
||||
cp -r reverserator_4 ../../ip_repo
|
||||
```
|
||||
|
@ -0,0 +1,48 @@
|
||||
-- © IBM Corp. 2020
|
||||
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
-- the terms below; you may not use the files in this repository except in
|
||||
-- compliance with the License as modified.
|
||||
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
--
|
||||
-- Modified Terms:
|
||||
--
|
||||
-- 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
-- License, the "Work" hereby includes implementations of the work of authorship
|
||||
-- in physical form.
|
||||
--
|
||||
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
-- necessary for implementation of the Work that are available from OpenPOWER
|
||||
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
-- of the EULA.
|
||||
--
|
||||
-- Unless required by applicable law or agreed to in writing, the reference design
|
||||
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
-- for the specific language governing permissions and limitations under the License.
|
||||
--
|
||||
-- Additional rights, including the ability to physically implement a softcore that
|
||||
-- is compliant with the required sections of the Power ISA Specification, are
|
||||
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
-- terminate yet another rare xil bug
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity reverserator_4 is
|
||||
port (
|
||||
innnie : in std_logic_vector(0 to 3);
|
||||
outtie : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end reverserator_4;
|
||||
|
||||
architecture reverserator_4 of reverserator_4 is
|
||||
begin
|
||||
|
||||
outtie <= innnie;
|
||||
|
||||
end reverserator_4;
|
||||
|
@ -0,0 +1,62 @@
|
||||
# ip creator
|
||||
|
||||
set project reverserator_64 ;# also top
|
||||
set keep 0 ;# keep project
|
||||
set xdc "" ;# set to xdc file if exists
|
||||
set synth_check 1
|
||||
|
||||
proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} {
|
||||
|
||||
set vhdl_dir [file normalize ./vhdl]
|
||||
set output_dir .
|
||||
set project_dir ./prj
|
||||
|
||||
create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e
|
||||
|
||||
add_files -norecurse $vhdl_dir
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
set_property top $project [current_fileset]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property default_lib work [current_project]
|
||||
set_property top $project [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property simulator_language VHDL [current_project]
|
||||
|
||||
if {$xdc != ""} {
|
||||
set xdc_dir [file normalize ./xdc]
|
||||
read_xdc $xdc_dir/$xdc
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
if {$synth_check} {
|
||||
synth_design -rtl -name elab_for_sanity_check
|
||||
}
|
||||
|
||||
ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
|
||||
ipx::unload_core $output_dir/$project/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision 2 [ipx::current_core]
|
||||
ipx::update_source_project_archive -component [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
ipx::move_temp_component_back -component [ipx::current_core]
|
||||
|
||||
if {$keep_project} {
|
||||
close_project
|
||||
puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
|
||||
} else {
|
||||
close_project -delete
|
||||
exec rm -rf $output_dir/$project_dir
|
||||
puts "Project built; only IP files kept."
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
create_ip $project $keep $synth_check $xdc
|
||||
|
@ -0,0 +1,8 @@
|
||||
# create IP: reverserator_64
|
||||
|
||||
```
|
||||
$VIVADO -mode tcl -source ./create_ip.tcl
|
||||
rm -r ../../ip_repo/reverserator_64
|
||||
cp -r reverserator_64 ../../ip_repo
|
||||
```
|
||||
|
@ -0,0 +1,48 @@
|
||||
-- © IBM Corp. 2020
|
||||
-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
-- the terms below; you may not use the files in this repository except in
|
||||
-- compliance with the License as modified.
|
||||
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
--
|
||||
-- Modified Terms:
|
||||
--
|
||||
-- 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
-- License, the "Work" hereby includes implementations of the work of authorship
|
||||
-- in physical form.
|
||||
--
|
||||
-- 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
-- necessary for implementation of the Work that are available from OpenPOWER
|
||||
-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
-- of the EULA.
|
||||
--
|
||||
-- Unless required by applicable law or agreed to in writing, the reference design
|
||||
-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
-- for the specific language governing permissions and limitations under the License.
|
||||
--
|
||||
-- Additional rights, including the ability to physically implement a softcore that
|
||||
-- is compliant with the required sections of the Power ISA Specification, are
|
||||
-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
-- terminate yet another rare xil bug
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity reverserator_64 is
|
||||
port (
|
||||
parkavenue : in std_logic_vector(0 to 63);
|
||||
skidrowwww : out std_logic_vector(63 downto 0)
|
||||
);
|
||||
end reverserator_64;
|
||||
|
||||
architecture reverserator_64 of reverserator_64 is
|
||||
begin
|
||||
|
||||
skidrowwww <= parkavenue;
|
||||
|
||||
end reverserator_64;
|
||||
|
@ -0,0 +1,69 @@
|
||||
# ip creator
|
||||
|
||||
set project a2l2_axi ;# also top
|
||||
set keep 0 ;# keep project
|
||||
set xdc "" ;# set to xdc file if exists
|
||||
set synth_check 1
|
||||
set vhdl2008 1
|
||||
|
||||
proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} {
|
||||
|
||||
set vhdl_dir [file normalize ./vhdl]
|
||||
set output_dir .
|
||||
set project_dir ./prj
|
||||
|
||||
create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e
|
||||
|
||||
add_files -norecurse $vhdl_dir
|
||||
|
||||
set_property library work [get_files $vhdl_dir/*]
|
||||
|
||||
if {$vhdl2008} {
|
||||
set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*]
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
set_property top $project [current_fileset]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property default_lib work [current_project]
|
||||
set_property top $project [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property simulator_language VHDL [current_project]
|
||||
|
||||
if {$xdc != ""} {
|
||||
set xdc_dir [file normalize ./xdc]
|
||||
read_xdc $xdc_dir/$xdc
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
if {$synth_check} {
|
||||
synth_design -rtl -name elab_for_sanity_check
|
||||
}
|
||||
|
||||
ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
|
||||
ipx::unload_core $output_dir/$project/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision 2 [ipx::current_core]
|
||||
ipx::update_source_project_archive -component [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
ipx::move_temp_component_back -component [ipx::current_core]
|
||||
|
||||
if {$keep_project} {
|
||||
close_project
|
||||
puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
|
||||
} else {
|
||||
close_project -delete
|
||||
exec rm -rf $output_dir/$project_dir
|
||||
puts "Project built; only IP files kept."
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
create_ip $project $keep $synth_check $xdc $vhdl2008
|
||||
|
@ -0,0 +1,69 @@
|
||||
# ip creator
|
||||
|
||||
set project a2o_axi_reg ;# also top
|
||||
set keep 0 ;# keep project
|
||||
set xdc "" ;# set to xdc file if exists
|
||||
set synth_check 1
|
||||
set vhdl2008 1
|
||||
|
||||
proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} {
|
||||
|
||||
set vhdl_dir [file normalize ./vhdl]
|
||||
set output_dir .
|
||||
set project_dir ./prj
|
||||
|
||||
create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e
|
||||
|
||||
add_files -norecurse $vhdl_dir
|
||||
|
||||
set_property library work [get_files $vhdl_dir/*]
|
||||
|
||||
if {$vhdl2008} {
|
||||
set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*]
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
set_property top $project [current_fileset]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property default_lib work [current_project]
|
||||
set_property top $project [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property simulator_language VHDL [current_project]
|
||||
|
||||
if {$xdc != ""} {
|
||||
set xdc_dir [file normalize ./xdc]
|
||||
read_xdc $xdc_dir/$xdc
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
if {$synth_check} {
|
||||
synth_design -rtl -name elab_for_sanity_check
|
||||
}
|
||||
|
||||
ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
|
||||
ipx::unload_core $output_dir/$project/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision 2 [ipx::current_core]
|
||||
ipx::update_source_project_archive -component [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
ipx::move_temp_component_back -component [ipx::current_core]
|
||||
|
||||
if {$keep_project} {
|
||||
close_project
|
||||
puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
|
||||
} else {
|
||||
close_project -delete
|
||||
exec rm -rf $output_dir/$project_dir
|
||||
puts "Project built; only IP files kept."
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
create_ip $project $keep $synth_check $xdc $vhdl2008
|
||||
|
@ -0,0 +1,61 @@
|
||||
# ip creator
|
||||
|
||||
set project c_wrapper ;# also top
|
||||
set rev "1"
|
||||
set keep 0 ;# keep project
|
||||
set xdc "" ;# set to xdc file if exists
|
||||
set synth_check 1
|
||||
|
||||
proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {rev 0.1} } {
|
||||
|
||||
set verilog_dir [file normalize ./verilog]
|
||||
set output_dir .
|
||||
set project_dir ./prj
|
||||
|
||||
create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e
|
||||
|
||||
add_files -norecurse $verilog_dir/trilib
|
||||
add_files -norecurse $verilog_dir/work
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
set_property top $project [current_fileset]
|
||||
set_property target_language VERILOG [current_project]
|
||||
set_property top $project [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property simulator_language MIXED [current_project]
|
||||
|
||||
if {$xdc != ""} {
|
||||
set xdc_dir [file normalize ./xdc]
|
||||
read_xdc $xdc_dir/$xdc
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
if {$synth_check} {
|
||||
synth_design -rtl -name elab_for_sanity_check
|
||||
}
|
||||
|
||||
ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
|
||||
ipx::unload_core $output_dir/$project/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name a2o_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision $rev [ipx::current_core]
|
||||
ipx::update_source_project_archive -component [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
ipx::move_temp_component_back -component [ipx::current_core]
|
||||
|
||||
if {$keep_project} {
|
||||
close_project
|
||||
puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
|
||||
} else {
|
||||
close_project -delete
|
||||
exec rm -rf $output_dir/$project_dir
|
||||
puts "Project built; only IP files kept."
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
create_ip $project $keep $synth_check $xdc $rev
|
@ -0,0 +1,69 @@
|
||||
# ip creator
|
||||
|
||||
set project a2o_dbug ;# also top
|
||||
set keep 0 ;# keep project
|
||||
set xdc "" ;# set to xdc file if exists
|
||||
set synth_check 1
|
||||
set vhdl2008 1
|
||||
|
||||
proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} {
|
||||
|
||||
set vhdl_dir [file normalize ./vhdl]
|
||||
set output_dir .
|
||||
set project_dir ./prj
|
||||
|
||||
create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e
|
||||
|
||||
add_files -norecurse $vhdl_dir
|
||||
|
||||
set_property library work [get_files $vhdl_dir/*]
|
||||
|
||||
if {$vhdl2008} {
|
||||
set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*]
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
set_property top $project [current_fileset]
|
||||
set_property target_language VHDL [current_project]
|
||||
set_property default_lib work [current_project]
|
||||
set_property top $project [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1]
|
||||
set_property simulator_language VHDL [current_project]
|
||||
|
||||
if {$xdc != ""} {
|
||||
set xdc_dir [file normalize ./xdc]
|
||||
read_xdc $xdc_dir/$xdc
|
||||
}
|
||||
|
||||
update_compile_order -fileset sources_1
|
||||
|
||||
if {$synth_check} {
|
||||
synth_design -rtl -name elab_for_sanity_check
|
||||
}
|
||||
|
||||
ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false
|
||||
ipx::unload_core $output_dir/$project/component.xml
|
||||
ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml
|
||||
update_compile_order -fileset sources_1
|
||||
set_property core_revision 2 [ipx::current_core]
|
||||
ipx::update_source_project_archive -component [ipx::current_core]
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::update_checksums [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
ipx::move_temp_component_back -component [ipx::current_core]
|
||||
|
||||
if {$keep_project} {
|
||||
close_project
|
||||
puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]"
|
||||
} else {
|
||||
close_project -delete
|
||||
exec rm -rf $output_dir/$project_dir
|
||||
puts "Project built; only IP files kept."
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
create_ip $project $keep $synth_check $xdc $vhdl2008
|
||||
|
@ -0,0 +1,14 @@
|
||||
# init.tcl
|
||||
#
|
||||
|
||||
set TCL [file dirname [info script]]
|
||||
|
||||
proc include {f} {
|
||||
global TCL
|
||||
source -notrace [file join $TCL $f]
|
||||
}
|
||||
|
||||
include "utils.tcl"
|
||||
include "waimea.tcl"
|
||||
|
||||
|
@ -0,0 +1,26 @@
|
||||
# utils.tcl
|
||||
#
|
||||
|
||||
proc timestamp {{t ""}} {
|
||||
if {$t == ""} {
|
||||
set t [clock seconds]
|
||||
}
|
||||
return [clock format $t -format %y%m%d%H%M%S]
|
||||
}
|
||||
|
||||
proc datetime {{t ""}} {
|
||||
if {$t == ""} {
|
||||
set t [clock seconds]
|
||||
}
|
||||
return [clock format $t -format "%m-%d-%y %I:%M:%S %p %Z"]
|
||||
}
|
||||
|
||||
proc now {} {
|
||||
return [clock seconds]
|
||||
}
|
||||
|
||||
proc vivado_year {} {
|
||||
regexp -- {Vivado v(\d\d\d\d)\.*} [version] s year
|
||||
return $year
|
||||
}
|
||||
|
@ -0,0 +1,179 @@
|
||||
# waimea board/core command interface
|
||||
|
||||
|
||||
####################################################################
|
||||
# system commands
|
||||
|
||||
set version 1 ;#coremark_1
|
||||
|
||||
proc reset {} {
|
||||
global version
|
||||
|
||||
if {$version == 1} {
|
||||
set filter "CELL_NAME=~\"*vio*\""
|
||||
set probe "vio_0_probe_out1"
|
||||
} else {
|
||||
set filter "CELL_NAME=~\"*marvio*\""
|
||||
set probe "vio_0_probe_out1"
|
||||
}
|
||||
|
||||
set obj_vio [get_hw_vios -of_objects [get_hw_devices xcvu3p_0] -filter $filter]
|
||||
set rst [get_hw_probes a2x_axi_bd_i/vio_0_probe_out1 -of_objects $obj_vio]
|
||||
startgroup
|
||||
set_property OUTPUT_VALUE 0 $rst
|
||||
commit_hw_vio $rst
|
||||
endgroup
|
||||
startgroup
|
||||
set_property OUTPUT_VALUE 1 $rst
|
||||
commit_hw_vio $rst
|
||||
endgroup
|
||||
puts "[datetime] Reset"
|
||||
}
|
||||
|
||||
proc threadstop {{val F}} {
|
||||
global version
|
||||
|
||||
if {$version == 1} {
|
||||
set filter "CELL_NAME=~\"*vio*\""
|
||||
set probe "vio_0_probe_out0"
|
||||
} else {
|
||||
set filter "CELL_NAME=~\"*marvio*\""
|
||||
set probe "marvio_probe_out0"
|
||||
}
|
||||
|
||||
set obj_vio [get_hw_vios -of_objects [get_hw_devices xcvu3p_0] -filter $filter]
|
||||
set thread_stop [get_hw_probes a2x_axi_bd_i/$probe -of_objects $obj_vio]
|
||||
set_property OUTPUT_VALUE $val $thread_stop
|
||||
commit_hw_vio $thread_stop
|
||||
puts "[datetime] ThreadStop=$val"
|
||||
}
|
||||
|
||||
####################################################################
|
||||
# ila commands
|
||||
|
||||
proc ila_arm {{n 0}} {
|
||||
set filter "CELL_NAME=~\"u_ila_$n\""
|
||||
set res [run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]]
|
||||
puts "[datetime] ILA$n armed."
|
||||
}
|
||||
|
||||
proc ila_wait {{n 0}} {
|
||||
set filter "CELL_NAME=~\"u_ila_$n\""
|
||||
puts "[datetime] ILA$n waiting..."
|
||||
set res [wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]]
|
||||
display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]]
|
||||
puts "[datetime] ILA$n triggered."
|
||||
}
|
||||
|
||||
####################################################################
|
||||
# axi slave commands
|
||||
|
||||
proc raxi {addr {len 8} {dev 0} {width 8}} {
|
||||
|
||||
if {$dev == 0} {
|
||||
set dev [get_hw_axis hw_axi_1]
|
||||
}
|
||||
|
||||
create_hw_axi_txn -f raxi_txn $dev -address $addr -len $len -type read
|
||||
run_hw_axi -quiet raxi_txn
|
||||
set res [report_hw_axi_txn -w $width raxi_txn]
|
||||
return $res
|
||||
|
||||
}
|
||||
|
||||
proc waxi {addr data {len 8} {dev 0}} {
|
||||
|
||||
if {$dev == 0} {
|
||||
set dev [get_hw_axis hw_axi_1]
|
||||
}
|
||||
|
||||
create_hw_axi_txn -f waxi_txn $dev -address $addr -len $len -type write -data $data
|
||||
run_hw_axi -quiet waxi_txn
|
||||
set res [report_hw_axi_txn waxi_txn]
|
||||
return $res
|
||||
|
||||
}
|
||||
|
||||
proc waxiq {addr data {len 8} {dev 0}} {
|
||||
|
||||
set res [waxi $addr $data $len $dev]
|
||||
|
||||
}
|
||||
|
||||
|
||||
proc testwrites {addr xfers} {
|
||||
|
||||
set start [datetime]
|
||||
for {set i 0} {$i < $xfers} {incr i} {
|
||||
waxi $addr 00000000_11111111_22222222_33333333_44444444_55555555_66666666_77777777
|
||||
}
|
||||
set end [datetime]
|
||||
|
||||
puts "Finished $xfers 32B writes."
|
||||
puts "Start: $start"
|
||||
puts " End: $end"
|
||||
|
||||
}
|
||||
|
||||
proc testwrites_128B {addr xfers} {
|
||||
|
||||
set start [datetime]
|
||||
for {set i 0} {$i < $xfers} {incr i} {
|
||||
waxi $addr {
|
||||
00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007
|
||||
00000008 00000009 0000000A 0000000B 0000000C 0000000D 0000000E 0000000F
|
||||
00000010 00000011 00000012 00000013 00000014 00000015 00000006 00000017
|
||||
00000018 00000019 0000001A 0000001B 0000001C 0000001D 0000000E 0000001F
|
||||
} 32
|
||||
}
|
||||
set end [datetime]
|
||||
|
||||
puts "Finished $xfers 122B writes."
|
||||
puts "Start: $start"
|
||||
puts " End: $end"
|
||||
|
||||
}
|
||||
|
||||
proc map {lambda list} {
|
||||
set res {}
|
||||
foreach i $list {
|
||||
lappend res [apply $lambda $i]
|
||||
}
|
||||
return $res
|
||||
}
|
||||
|
||||
proc bytereverse {x} {
|
||||
set res ""
|
||||
for {set i 0} {$i < [string length $x]} {incr i 2} {
|
||||
set res "[string range $x $i [expr $i+1]]$res"
|
||||
}
|
||||
return $res
|
||||
}
|
||||
|
||||
proc ascii {start {len 32} {dev 0}} {
|
||||
set w 128
|
||||
set res ""
|
||||
set count [expr ($len-1)/$w + 1]
|
||||
set ptr $start
|
||||
|
||||
for {set i 0} {$i < $count} {incr i} {
|
||||
|
||||
set mem [raxi $ptr [expr $w/4] $dev $w]
|
||||
set ptr [format %x [expr [expr 0x$ptr] + $w]]
|
||||
|
||||
# split and remove addr
|
||||
set tokens [regexp -all -inline {\S+} $mem]
|
||||
set tokens [lrange $tokens 1 end]
|
||||
|
||||
# bytereverse and ascii
|
||||
set tokens [map {x {return [bytereverse $x]}} $tokens]
|
||||
set bytes [join $tokens {}]
|
||||
set chars [binary format H* $bytes]
|
||||
|
||||
set res "$res$chars"
|
||||
|
||||
}
|
||||
return $res
|
||||
}
|
||||
|
||||
|
@ -0,0 +1,43 @@
|
||||
// © IBM Corp. 2020
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
// *!****************************************************************
|
||||
// *! FILENAME : tri_a2o.param
|
||||
// *! DESCRIPTION : Constants for use throughout core
|
||||
// *! CONTENTS :
|
||||
// *!
|
||||
// *!****************************************************************
|
||||
|
||||
`ifndef _tri_vh_
|
||||
`define _tri_vh_
|
||||
|
||||
`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk
|
||||
//`define EXPAND_TYPE 1
|
||||
|
||||
// Do NOT add any defines below this line
|
||||
`endif //_tri_vh_
|
@ -0,0 +1,258 @@
|
||||
// © IBM Corp. 2020
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||
//
|
||||
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||||
// License, the "Work" hereby includes implementations of the work of authorship
|
||||
// in physical form.
|
||||
//
|
||||
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||||
// necessary for implementation of the Work that are available from OpenPOWER
|
||||
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||||
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||||
// of the EULA.
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, the reference design
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||||
// for the specific language governing permissions and limitations under the License.
|
||||
//
|
||||
// Additional rights, including the ability to physically implement a softcore that
|
||||
// is compliant with the required sections of the Power ISA Specification, are
|
||||
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||||
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
// *!****************************************************************
|
||||
// *! FILENAME : tri_128x168_1w_0.v
|
||||
// *! DESCRIPTION : 128 Entry x 168 bit x 1 way array
|
||||
// *!
|
||||
// *!****************************************************************
|
||||
|
||||
`include "tri_a2o.vh"
|
||||
|
||||
module tri_128x168_1w_0(
|
||||
gnd,
|
||||
vdd,
|
||||
vcs,
|
||||
nclk,
|
||||
act,
|
||||
ccflush_dc,
|
||||
scan_dis_dc_b,
|
||||
scan_diag_dc,
|
||||
abst_scan_in,
|
||||
repr_scan_in,
|
||||
time_scan_in,
|
||||
abst_scan_out,
|
||||
repr_scan_out,
|
||||
time_scan_out,
|
||||
lcb_d_mode_dc,
|
||||
lcb_clkoff_dc_b,
|
||||
lcb_act_dis_dc,
|
||||
lcb_mpw1_dc_b,
|
||||
lcb_mpw2_dc_b,
|
||||
lcb_delay_lclkr_dc,
|
||||
lcb_sg_1,
|
||||
lcb_time_sg_0,
|
||||
lcb_repr_sg_0,
|
||||
lcb_abst_sl_thold_0,
|
||||
lcb_repr_sl_thold_0,
|
||||
lcb_time_sl_thold_0,
|
||||
lcb_ary_nsl_thold_0,
|
||||
lcb_bolt_sl_thold_0,
|
||||
tc_lbist_ary_wrt_thru_dc,
|
||||
abist_en_1,
|
||||
din_abist,
|
||||
abist_cmp_en,
|
||||
abist_raw_b_dc,
|
||||
data_cmp_abist,
|
||||
addr_abist,
|
||||
r_wb_abist,
|
||||
pc_bo_enable_2,
|
||||
pc_bo_reset,
|
||||
pc_bo_unload,
|
||||
pc_bo_repair,
|
||||
pc_bo_shdata,
|
||||
pc_bo_select,
|
||||
bo_pc_failout,
|
||||
bo_pc_diagloop,
|
||||
tri_lcb_mpw1_dc_b,
|
||||
tri_lcb_mpw2_dc_b,
|
||||
tri_lcb_delay_lclkr_dc,
|
||||
tri_lcb_clkoff_dc_b,
|
||||
tri_lcb_act_dis_dc,
|
||||
write_enable,
|
||||
addr,
|
||||
data_in,
|
||||
data_out
|
||||
);
|
||||
parameter addressable_ports = 128; // number of addressable register in this array
|
||||
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
|
||||
parameter port_bitwidth = 168; // bitwidth of ports
|
||||
parameter ways = 1; // number of ways
|
||||
|
||||
// POWER PINS
|
||||
inout gnd;
|
||||
inout vdd;
|
||||
inout vcs;
|
||||
|
||||
// CLOCK and CLOCKCONTROL ports
|
||||
input [0:`NCLK_WIDTH-1] nclk;
|
||||
input act;
|
||||
input ccflush_dc;
|
||||
input scan_dis_dc_b;
|
||||
input scan_diag_dc;
|
||||
|
||||
input abst_scan_in;
|
||||
input repr_scan_in;
|
||||
input time_scan_in;
|
||||
output abst_scan_out;
|
||||
output repr_scan_out;
|
||||
output time_scan_out;
|
||||
|
||||
input lcb_d_mode_dc;
|
||||
input lcb_clkoff_dc_b;
|
||||
input lcb_act_dis_dc;
|
||||
input [0:4] lcb_mpw1_dc_b;
|
||||
input lcb_mpw2_dc_b;
|
||||
input [0:4] lcb_delay_lclkr_dc;
|
||||
|
||||
input lcb_sg_1;
|
||||
input lcb_time_sg_0;
|
||||
input lcb_repr_sg_0;
|
||||
|
||||
input lcb_abst_sl_thold_0;
|
||||
input lcb_repr_sl_thold_0;
|
||||
input lcb_time_sl_thold_0;
|
||||
input lcb_ary_nsl_thold_0;
|
||||
input lcb_bolt_sl_thold_0; // thold for any regs inside backend
|
||||
|
||||
input tc_lbist_ary_wrt_thru_dc;
|
||||
input abist_en_1;
|
||||
input [0:3] din_abist;
|
||||
input abist_cmp_en;
|
||||
input abist_raw_b_dc;
|
||||
input [0:3] data_cmp_abist;
|
||||
input [0:6] addr_abist;
|
||||
input r_wb_abist;
|
||||
|
||||
// BOLT-ON
|
||||
input pc_bo_enable_2; // general bolt-on enable, probably DC
|
||||
input pc_bo_reset; // execute sticky bit decode
|
||||
input pc_bo_unload;
|
||||
input pc_bo_repair; // load repair reg
|
||||
input pc_bo_shdata; // shift data for timing write
|
||||
input pc_bo_select; // select for mask and hier writes
|
||||
output bo_pc_failout; // fail/no-fix reg
|
||||
output bo_pc_diagloop;
|
||||
input tri_lcb_mpw1_dc_b;
|
||||
input tri_lcb_mpw2_dc_b;
|
||||
input tri_lcb_delay_lclkr_dc;
|
||||
input tri_lcb_clkoff_dc_b;
|
||||
input tri_lcb_act_dis_dc;
|
||||
|
||||
// PORTS
|
||||
input write_enable;
|
||||
input [0:addressbus_width-1] addr;
|
||||
input [0:port_bitwidth-1] data_in;
|
||||
output [0:port_bitwidth-1] data_out;
|
||||
|
||||
// tri_128x168_1w_0
|
||||
|
||||
parameter ramb_base_width = 36;
|
||||
parameter ramb_base_addr = 9;
|
||||
parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way
|
||||
|
||||
|
||||
// Configuration Statement for NCsim
|
||||
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
|
||||
|
||||
wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in;
|
||||
wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1];
|
||||
wire [0:ramb_base_addr-1] ramb_addr;
|
||||
|
||||
wire [0:ways-1] write;
|
||||
wire tidn;
|
||||
(* analysis_not_referenced="true" *)
|
||||
wire unused;
|
||||
wire [0:(ramb_base_width*ramb_width_mult-1)] unused_dob;
|
||||
|
||||
|
||||
generate
|
||||
begin
|
||||
assign tidn = 1'b0;
|
||||
|
||||
if (addressbus_width < ramb_base_addr)
|
||||
begin
|
||||
assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
|
||||
assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr;
|
||||
end
|
||||
if (addressbus_width >= ramb_base_addr)
|
||||
begin
|
||||
assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
|
||||
end
|
||||
|
||||
genvar i;
|
||||
for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1)
|
||||
begin : din
|
||||
if (i < port_bitwidth)
|
||||
begin
|
||||
assign ramb_data_in[i] = data_in[i];
|
||||
end
|
||||
if (i >= port_bitwidth)
|
||||
begin
|
||||
assign ramb_data_in[i] = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
genvar w;
|
||||
for (w = 0; w < ways; w = w + 1)
|
||||
begin : aw
|
||||
assign write[w] = write_enable;
|
||||
|
||||
genvar x;
|
||||
for (x = 0; x < ramb_width_mult; x = x + 1)
|
||||
begin : ax
|
||||
|
||||
RAMB16_S36_S36
|
||||
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
|
||||
ram(
|
||||
.DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
|
||||
.DOB(unused_dob[x * ramb_base_width:x * ramb_base_width + 31]),
|
||||
.DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
|
||||
.DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]),
|
||||
.ADDRA(ramb_addr),
|
||||
.ADDRB(ramb_addr),
|
||||
.CLKA(nclk[0]),
|
||||
.CLKB(tidn),
|
||||
.DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
|
||||
.DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
|
||||
.DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
|
||||
.DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
|
||||
.ENA(act),
|
||||
.ENB(tidn),
|
||||
.SSRA(nclk[1]),
|
||||
.SSRB(tidn),
|
||||
.WEA(write[w]),
|
||||
.WEB(tidn)
|
||||
);
|
||||
end //ax
|
||||
assign data_out[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
|
||||
end //aw
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign abst_scan_out = abst_scan_in;
|
||||
assign repr_scan_out = repr_scan_in;
|
||||
assign time_scan_out = time_scan_in;
|
||||
|
||||
assign bo_pc_failout = 1'b0;
|
||||
assign bo_pc_diagloop = 1'b0;
|
||||
|
||||
assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob});
|
||||
endmodule
|
@ -0,0 +1,335 @@
|
||||
// © IBM Corp. 2020
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||||
// the terms below; you may not use the files in this repository except in
|
||||
// compliance with the License as modified.
|
||||
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Modified Terms:
|
||||