diff --git a/rel/build/bd/create_project.tcl b/rel/build/bd/create_project.tcl new file mode 100644 index 0000000..5a0c962 --- /dev/null +++ b/rel/build/bd/create_project.tcl @@ -0,0 +1,1211 @@ + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "a2o_bd" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "create_project.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/"]" + +# Create project +create_project -force ${_xil_proj_name_} ./${_xil_proj_name_} -part xcvu3p-ffvc1517-2-e + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "default_lib" -value "work" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$origin_dir/../ip_cache" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "source_mgmt_mode" -value "DisplayOnly" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "73" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "73" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "73" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "73" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "73" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "73" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "73" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "95" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/../ip_repo"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "a2o_bd" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/xdc/main_pinout.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/xdc/main_pinout.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "library" -value "work" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/xdc/main_spi.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/xdc/main_spi.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "library" -value "work" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/xdc/main_timing.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/xdc/main_timing.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "library" -value "work" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/xdc/main_extras.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/xdc/main_extras.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj +set_property -name "library" -value "work" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "target_constrs_file" -value "[file normalize "$origin_dir/xdc/main_extras.xdc"]" -objects $obj +set_property -name "target_part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "target_ucf" -value "[file normalize "$origin_dir/xdc/main_extras.xdc"]" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "incremental" -value "0" -objects $obj +set_property -name "nl.mode" -value "funcsim" -objects $obj +set_property -name "sim_mode" -value "post-synthesis" -objects $obj +set_property -name "top" -value "a2o_bd" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "xsim.simulate.log_all_signals" -value "1" -objects $obj +set_property -name "xsim.simulate.runtime" -value "40000ns" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added + + +# Proc to create BD a2o_bd +proc cr_bd_a2o_bd { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name a2o_bd + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + user.org:user:a2l2_axi:1.0\ + user.org:user:a2o_axi_reg:1.0\ + user.org:user:a2o_dbug:1.0\ + xilinx.com:ip:axi_bram_ctrl:4.1\ + xilinx.com:ip:axi_protocol_checker:2.0\ + xilinx.com:ip:blk_mem_gen:8.4\ + user.org:user:c_wrapper:1.0\ + xilinx.com:ip:clk_wiz:6.0\ + xilinx.com:ip:jtag_axi:1.2\ + xilinx.com:ip:proc_sys_reset:5.0\ + user.org:user:reverserator_3:1.0\ + user.org:user:reverserator_4:1.0\ + user.org:user:reverserator_64:1.0\ + xilinx.com:ip:smartconnect:1.0\ + xilinx.com:ip:system_ila:1.1\ + xilinx.com:ip:vio:3.0\ + xilinx.com:ip:xlconstant:1.1\ + " + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + + # Create ports + set clk_in1_n_0 [ create_bd_port -dir I -type clk clk_in1_n_0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $clk_in1_n_0 + set clk_in1_p_0 [ create_bd_port -dir I -type clk clk_in1_p_0 ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {300000000} \ + ] $clk_in1_p_0 + + # Create instance: a2l2_axi_0, and set properties + set a2l2_axi_0 [ create_bd_cell -type ip -vlnv user.org:user:a2l2_axi:1.0 a2l2_axi_0 ] + set_property -dict [ list \ + CONFIG.ld_queue_size {8} \ + CONFIG.st_queue_size {32} \ + CONFIG.threads {2} \ + ] $a2l2_axi_0 + + # Create instance: a2o_axi_reg_0, and set properties + set a2o_axi_reg_0 [ create_bd_cell -type ip -vlnv user.org:user:a2o_axi_reg:1.0 a2o_axi_reg_0 ] + + # Create instance: a2o_dbug_0, and set properties + set a2o_dbug_0 [ create_bd_cell -type ip -vlnv user.org:user:a2o_dbug:1.0 a2o_dbug_0 ] + + # Create instance: axi_bram_ctrl_0, and set properties + set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ] + set_property -dict [ list \ + CONFIG.SINGLE_PORT_BRAM {1} \ + CONFIG.SUPPORTS_NARROW_BURST {0} \ + ] $axi_bram_ctrl_0 + + # Create instance: axi_bram_ctrl_1, and set properties + set axi_bram_ctrl_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_1 ] + set_property -dict [ list \ + CONFIG.SINGLE_PORT_BRAM {1} \ + ] $axi_bram_ctrl_1 + + # Create instance: axi_protocol_checker_0, and set properties + set axi_protocol_checker_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_protocol_checker:2.0 axi_protocol_checker_0 ] + set_property -dict [ list \ + CONFIG.ARUSER_WIDTH {4} \ + CONFIG.AWUSER_WIDTH {4} \ + CONFIG.BUSER_WIDTH {4} \ + CONFIG.ENABLE_CONTROL {1} \ + CONFIG.ENABLE_MARK_DEBUG {0} \ + CONFIG.HAS_SYSTEM_RESET {1} \ + CONFIG.ID_WIDTH {4} \ + CONFIG.MAX_RD_BURSTS {8} \ + CONFIG.MAX_WR_BURSTS {32} \ + CONFIG.RUSER_WIDTH {4} \ + CONFIG.SUPPORTS_NARROW_BURST {1} \ + CONFIG.WUSER_WIDTH {4} \ + ] $axi_protocol_checker_0 + + # Create instance: blk_mem_gen_0, and set properties + set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ] + set_property -dict [ list \ + CONFIG.Assume_Synchronous_Clk {true} \ + CONFIG.Byte_Size {8} \ + CONFIG.Coe_File {no_coe_file_loaded} \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_32bit_Address {true} \ + CONFIG.Fill_Remaining_Memory_Locations {false} \ + CONFIG.Load_Init_File {false} \ + CONFIG.Memory_Type {Single_Port_RAM} \ + CONFIG.PRIM_type_to_Implement {URAM} \ + CONFIG.Port_A_Write_Rate {50} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Use_Byte_Write_Enable {true} \ + CONFIG.Use_RSTA_Pin {true} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $blk_mem_gen_0 + + # Create instance: blk_mem_gen_1, and set properties + set blk_mem_gen_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_1 ] + set_property -dict [ list \ + CONFIG.Assume_Synchronous_Clk {true} \ + CONFIG.Byte_Size {8} \ + CONFIG.Coe_File {no_coe_file_loaded} \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_32bit_Address {true} \ + CONFIG.Enable_B {Always_Enabled} \ + CONFIG.Load_Init_File {false} \ + CONFIG.Memory_Type {Single_Port_RAM} \ + CONFIG.PRIM_type_to_Implement {URAM} \ + CONFIG.Port_A_Write_Rate {50} \ + CONFIG.Port_B_Clock {0} \ + CONFIG.Port_B_Enable_Rate {0} \ + CONFIG.Port_B_Write_Rate {0} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Use_Byte_Write_Enable {true} \ + CONFIG.Use_RSTA_Pin {true} \ + CONFIG.Use_RSTB_Pin {false} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $blk_mem_gen_1 + + # Create instance: c_wrapper_0, and set properties + set c_wrapper_0 [ create_bd_cell -type ip -vlnv user.org:user:c_wrapper:1.0 c_wrapper_0 ] + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.AUTO_PRIMITIVE {MMCM} \ + CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \ + CONFIG.CLKOUT1_DRIVES {Buffer} \ + CONFIG.CLKOUT1_JITTER {116.415} \ + CONFIG.CLKOUT1_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT2_DRIVES {Buffer} \ + CONFIG.CLKOUT2_JITTER {101.475} \ + CONFIG.CLKOUT2_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {100.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_DRIVES {Buffer} \ + CONFIG.CLKOUT3_JITTER {88.577} \ + CONFIG.CLKOUT3_PHASE_ERROR {77.836} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {200.000} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_DRIVES {Buffer} \ + CONFIG.CLKOUT5_DRIVES {Buffer} \ + CONFIG.CLKOUT6_DRIVES {Buffer} \ + CONFIG.CLKOUT7_DRIVES {Buffer} \ + CONFIG.CLK_OUT1_PORT {clk} \ + CONFIG.CLK_OUT2_PORT {clk2x} \ + CONFIG.CLK_OUT3_PORT {clk4x} \ + CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ + CONFIG.MMCM_BANDWIDTH {OPTIMIZED} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {3.333} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {24.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {12} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {6} \ + CONFIG.MMCM_COMPENSATION {AUTO} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {3} \ + CONFIG.PRIMITIVE {MMCM} \ + CONFIG.PRIM_IN_FREQ {300.000} \ + CONFIG.PRIM_SOURCE {Differential_clock_capable_pin} \ + CONFIG.USE_LOCKED {true} \ + CONFIG.USE_RESET {false} \ + ] $clk_wiz_0 + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi:1.2 jtag_axi_0 ] + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + set_property -dict [ list \ + CONFIG.C_AUX_RESET_HIGH {0} \ + CONFIG.C_AUX_RST_WIDTH {1} \ + CONFIG.C_EXT_RST_WIDTH {4} \ + ] $proc_sys_reset_0 + + # Create instance: reverserator_3_0, and set properties + set reverserator_3_0 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_3:1.0 reverserator_3_0 ] + + # Create instance: reverserator_3_1, and set properties + set reverserator_3_1 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_3:1.0 reverserator_3_1 ] + + # Create instance: reverserator_3_2, and set properties + set reverserator_3_2 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_3:1.0 reverserator_3_2 ] + + # Create instance: reverserator_4_0, and set properties + set reverserator_4_0 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_4:1.0 reverserator_4_0 ] + + # Create instance: reverserator_4_1, and set properties + set reverserator_4_1 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_4:1.0 reverserator_4_1 ] + + # Create instance: reverserator_4_2, and set properties + set reverserator_4_2 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_4:1.0 reverserator_4_2 ] + + # Create instance: reverserator_4_3, and set properties + set reverserator_4_3 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_4:1.0 reverserator_4_3 ] + + # Create instance: reverserator_64_0, and set properties + set reverserator_64_0 [ create_bd_cell -type ip -vlnv user.org:user:reverserator_64:1.0 reverserator_64_0 ] + + # Create instance: smartconnect_0, and set properties + set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ] + set_property -dict [ list \ + CONFIG.NUM_MI {5} \ + CONFIG.NUM_SI {2} \ + ] $smartconnect_0 + + # Create instance: system_ila_0, and set properties + set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ] + set_property -dict [ list \ + CONFIG.ALL_PROBE_SAME_MU_CNT {2} \ + CONFIG.C_ADV_TRIGGER {true} \ + CONFIG.C_BRAM_CNT {48} \ + CONFIG.C_DATA_DEPTH {8192} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_INPUT_PIPE_STAGES {3} \ + CONFIG.C_PROBE0_MU_CNT {2} \ + CONFIG.C_SLOT_0_MAX_RD_BURSTS {8} \ + CONFIG.C_SLOT_0_MAX_WR_BURSTS {32} \ + CONFIG.C_TRIGIN_EN {true} \ + CONFIG.C_TRIGOUT_EN {true} \ + ] $system_ila_0 + + # Create instance: system_ila_1, and set properties + set system_ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_1 ] + set_property -dict [ list \ + CONFIG.ALL_PROBE_SAME_MU {true} \ + CONFIG.ALL_PROBE_SAME_MU_CNT {4} \ + CONFIG.C_BRAM_CNT {9} \ + CONFIG.C_DATA_DEPTH {2048} \ + CONFIG.C_EN_STRG_QUAL {1} \ + CONFIG.C_MON_TYPE {NATIVE} \ + CONFIG.C_NUM_OF_PROBES {2} \ + CONFIG.C_PROBE0_MU_CNT {4} \ + CONFIG.C_PROBE0_WIDTH {160} \ + CONFIG.C_PROBE1_MU_CNT {4} \ + CONFIG.C_PROBE_WIDTH_PROPAGATION {MANUAL} \ + CONFIG.C_TRIGOUT_EN {true} \ + ] $system_ila_1 + + # Create instance: vio_0, and set properties + set vio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_0 ] + set_property -dict [ list \ + CONFIG.C_NUM_PROBE_IN {6} \ + CONFIG.C_NUM_PROBE_OUT {7} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT2_WIDTH {4} \ + CONFIG.C_PROBE_OUT3_WIDTH {6} \ + CONFIG.C_PROBE_OUT4_WIDTH {64} \ + ] $vio_0 + + # Create instance: vio_1, and set properties + set vio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_1 ] + set_property -dict [ list \ + CONFIG.C_NUM_PROBE_IN {5} \ + CONFIG.C_NUM_PROBE_OUT {19} \ + CONFIG.C_PROBE_OUT0_INIT_VAL {0xf} \ + CONFIG.C_PROBE_OUT0_WIDTH {4} \ + CONFIG.C_PROBE_OUT12_WIDTH {4} \ + CONFIG.C_PROBE_OUT13_WIDTH {4} \ + CONFIG.C_PROBE_OUT15_WIDTH {4} \ + CONFIG.C_PROBE_OUT17_INIT_VAL {0xf} \ + CONFIG.C_PROBE_OUT17_WIDTH {4} \ + CONFIG.C_PROBE_OUT18_INIT_VAL {0xf} \ + CONFIG.C_PROBE_OUT18_WIDTH {4} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT2_WIDTH {1} \ + CONFIG.C_PROBE_OUT3_WIDTH {8} \ + CONFIG.C_PROBE_OUT4_WIDTH {4} \ + CONFIG.C_PROBE_OUT6_WIDTH {4} \ + CONFIG.C_PROBE_OUT7_WIDTH {4} \ + CONFIG.C_PROBE_OUT8_WIDTH {4} \ + CONFIG.C_PROBE_OUT9_INIT_VAL {0x1} \ + ] $vio_1 + + # Create instance: vio_2, and set properties + set vio_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_2 ] + set_property -dict [ list \ + CONFIG.C_NUM_PROBE_IN {5} \ + CONFIG.C_NUM_PROBE_OUT {0} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT2_WIDTH {4} \ + CONFIG.C_PROBE_OUT3_WIDTH {6} \ + CONFIG.C_PROBE_OUT4_WIDTH {64} \ + ] $vio_2 + + # Create instance: vio_3, and set properties + set vio_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:vio:3.0 vio_3 ] + set_property -dict [ list \ + CONFIG.C_NUM_PROBE_IN {2} \ + CONFIG.C_NUM_PROBE_OUT {2} \ + CONFIG.C_PROBE_IN2_WIDTH {3} \ + CONFIG.C_PROBE_IN3_WIDTH {4} \ + CONFIG.C_PROBE_OUT0_WIDTH {32} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x1} \ + CONFIG.C_PROBE_OUT1_WIDTH {2} \ + CONFIG.C_PROBE_OUT2_WIDTH {4} \ + CONFIG.C_PROBE_OUT3_WIDTH {6} \ + CONFIG.C_PROBE_OUT4_WIDTH {64} \ + ] $vio_3 + + # Create instance: xlconstant_1, and set properties + set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {2} \ + ] $xlconstant_1 + + # Create instance: xlconstant_2, and set properties + set xlconstant_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + CONFIG.CONST_WIDTH {32} \ + ] $xlconstant_2 + + # Create instance: xlconstant_3, and set properties + set xlconstant_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_3 ] + + # Create instance: xlconstant_4, and set properties + set xlconstant_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_4 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {0} \ + ] $xlconstant_4 + + # Create interface connections + connect_bd_intf_net -intf_net a2l2_axi_0_m00_axi [get_bd_intf_pins a2l2_axi_0/m00_axi] [get_bd_intf_pins smartconnect_0/S00_AXI] +connect_bd_intf_net -intf_net [get_bd_intf_nets a2l2_axi_0_m00_axi] [get_bd_intf_pins smartconnect_0/S00_AXI] [get_bd_intf_pins system_ila_0/SLOT_0_AXI] +connect_bd_intf_net -intf_net [get_bd_intf_nets a2l2_axi_0_m00_axi] [get_bd_intf_pins axi_protocol_checker_0/PC_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI] + connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA] + connect_bd_intf_net -intf_net axi_bram_ctrl_3_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_1/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_1/BRAM_PORTA] + connect_bd_intf_net -intf_net jtag_axi_0_M_AXI [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins smartconnect_0/S01_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins a2o_axi_reg_0/s00_axi] [get_bd_intf_pins smartconnect_0/M00_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins a2o_axi_reg_0/s_axi_intr] [get_bd_intf_pins smartconnect_0/M01_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_bram_ctrl_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI] + connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_protocol_checker_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI] + + # Create port connections + connect_bd_net -net Net2 [get_bd_pins a2o_dbug_0/trigger_in] [get_bd_pins system_ila_1/TRIG_OUT_trig] [get_bd_pins vio_1/probe_in1] + connect_bd_net -net a2l2_axi_0_an_ac_reld_core_tag [get_bd_pins a2l2_axi_0/an_ac_reld_core_tag] [get_bd_pins c_wrapper_0/an_ac_reld_core_tag] + connect_bd_net -net a2l2_axi_0_an_ac_reld_crit_qw [get_bd_pins a2l2_axi_0/an_ac_reld_crit_qw] [get_bd_pins c_wrapper_0/an_ac_reld_crit_qw] + connect_bd_net -net a2l2_axi_0_an_ac_reld_data [get_bd_pins a2l2_axi_0/an_ac_reld_data] [get_bd_pins c_wrapper_0/an_ac_reld_data] + connect_bd_net -net a2l2_axi_0_an_ac_reld_data_coming [get_bd_pins a2l2_axi_0/an_ac_reld_data_coming] [get_bd_pins c_wrapper_0/an_ac_reld_data_coming] + connect_bd_net -net a2l2_axi_0_an_ac_reld_data_vld [get_bd_pins a2l2_axi_0/an_ac_reld_data_vld] [get_bd_pins c_wrapper_0/an_ac_reld_data_vld] + connect_bd_net -net a2l2_axi_0_an_ac_reld_ecc_err [get_bd_pins a2l2_axi_0/an_ac_reld_ecc_err] [get_bd_pins c_wrapper_0/an_ac_reld_ecc_err] + connect_bd_net -net a2l2_axi_0_an_ac_reld_ecc_err_ue [get_bd_pins a2l2_axi_0/an_ac_reld_ecc_err_ue] [get_bd_pins c_wrapper_0/an_ac_reld_ecc_err_ue] + connect_bd_net -net a2l2_axi_0_an_ac_reld_l1_dump [get_bd_pins a2l2_axi_0/an_ac_reld_l1_dump] [get_bd_pins c_wrapper_0/an_ac_reld_l1_dump] + connect_bd_net -net a2l2_axi_0_an_ac_reld_qw [get_bd_pins a2l2_axi_0/an_ac_reld_qw] [get_bd_pins c_wrapper_0/an_ac_reld_qw] + connect_bd_net -net a2l2_axi_0_an_ac_req_ld_pop [get_bd_pins a2l2_axi_0/an_ac_req_ld_pop] [get_bd_pins c_wrapper_0/an_ac_req_ld_pop] + connect_bd_net -net a2l2_axi_0_an_ac_req_st_gather [get_bd_pins a2l2_axi_0/an_ac_req_st_gather] [get_bd_pins c_wrapper_0/an_ac_req_st_gather] + connect_bd_net -net a2l2_axi_0_an_ac_req_st_pop [get_bd_pins a2l2_axi_0/an_ac_req_st_pop] [get_bd_pins c_wrapper_0/an_ac_req_st_pop] + connect_bd_net -net a2l2_axi_0_an_ac_reservation_vld [get_bd_pins a2l2_axi_0/an_ac_reservation_vld] [get_bd_pins c_wrapper_0/an_ac_reservation_vld] + connect_bd_net -net a2l2_axi_0_an_ac_stcx_complete [get_bd_pins a2l2_axi_0/an_ac_stcx_complete] [get_bd_pins c_wrapper_0/an_ac_stcx_complete] + connect_bd_net -net a2l2_axi_0_an_ac_stcx_pass [get_bd_pins a2l2_axi_0/an_ac_stcx_pass] [get_bd_pins c_wrapper_0/an_ac_stcx_pass] + connect_bd_net -net a2l2_axi_0_an_ac_sync_ack [get_bd_pins a2l2_axi_0/an_ac_sync_ack] [get_bd_pins c_wrapper_0/an_ac_sync_ack] + connect_bd_net -net a2l2_axi_0_err [get_bd_pins a2l2_axi_0/err] [get_bd_pins reverserator_4_2/innnie] + connect_bd_net -net a2o_axi_reg_0_irq [get_bd_pins a2o_axi_reg_0/irq] [get_bd_pins vio_3/probe_in0] + connect_bd_net -net a2o_axi_reg_0_reg_out_00 [get_bd_pins a2o_axi_reg_0/reg_out_00] [get_bd_pins vio_3/probe_in1] + connect_bd_net -net a2o_dbug_0_cch_out [get_bd_pins a2o_dbug_0/cch_out] [get_bd_pins vio_0/probe_in4] + connect_bd_net -net a2o_dbug_0_dch_out [get_bd_pins a2o_dbug_0/dch_out] [get_bd_pins vio_0/probe_in5] + connect_bd_net -net a2o_dbug_0_err [get_bd_pins a2o_dbug_0/err] [get_bd_pins vio_0/probe_in1] + connect_bd_net -net a2o_dbug_0_rsp_data [get_bd_pins a2o_dbug_0/rsp_data] [get_bd_pins reverserator_64_0/parkavenue] + connect_bd_net -net a2o_dbug_0_rsp_valid [get_bd_pins a2o_dbug_0/rsp_valid] [get_bd_pins vio_0/probe_in0] + connect_bd_net -net a2o_dbug_0_threadstop_out [get_bd_pins a2o_dbug_0/threadstop_out] [get_bd_pins c_wrapper_0/an_ac_pm_thread_stop] + connect_bd_net -net a2o_dbug_0_trigger_ack_out [get_bd_pins a2o_dbug_0/trigger_ack_out] [get_bd_pins vio_0/probe_in3] + connect_bd_net -net a2o_dbug_0_trigger_out [get_bd_pins a2o_dbug_0/trigger_out] [get_bd_pins system_ila_0/TRIG_IN_trig] + connect_bd_net -net a2o_reset_0_reset [get_bd_pins a2l2_axi_0/reset_n] [get_bd_pins a2o_axi_reg_0/s00_axi_aresetn] [get_bd_pins a2o_axi_reg_0/s_axi_intr_aresetn] [get_bd_pins a2o_dbug_0/reset_n] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_bram_ctrl_1/s_axi_aresetn] [get_bd_pins axi_protocol_checker_0/aresetn] [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn] [get_bd_pins system_ila_0/resetn] + connect_bd_net -net axi_protocol_checker_0_pc_asserted [get_bd_pins axi_protocol_checker_0/pc_asserted] [get_bd_pins system_ila_1/probe1] [get_bd_pins vio_1/probe_in0] + connect_bd_net -net axi_protocol_checker_0_pc_status [get_bd_pins axi_protocol_checker_0/pc_status] [get_bd_pins system_ila_1/probe0] + connect_bd_net -net c_wrapper_0_ac_an_checkstop [get_bd_pins c_wrapper_0/ac_an_checkstop] [get_bd_pins reverserator_3_1/outdoor] + connect_bd_net -net c_wrapper_0_ac_an_debug_trigger [get_bd_pins c_wrapper_0/ac_an_debug_trigger] [get_bd_pins reverserator_4_3/innnie] + connect_bd_net -net c_wrapper_0_ac_an_local_checkstop [get_bd_pins c_wrapper_0/ac_an_local_checkstop] [get_bd_pins reverserator_3_2/outdoor] + connect_bd_net -net c_wrapper_0_ac_an_machine_check [get_bd_pins c_wrapper_0/ac_an_machine_check] [get_bd_pins reverserator_4_0/innnie] + connect_bd_net -net c_wrapper_0_ac_an_pm_thread_running [get_bd_pins c_wrapper_0/ac_an_pm_thread_running] [get_bd_pins reverserator_4_1/innnie] + connect_bd_net -net c_wrapper_0_ac_an_recov_err [get_bd_pins c_wrapper_0/ac_an_recov_err] [get_bd_pins reverserator_3_0/outdoor] + connect_bd_net -net c_wrapper_0_ac_an_req [get_bd_pins a2l2_axi_0/ac_an_req] [get_bd_pins c_wrapper_0/ac_an_req] + connect_bd_net -net c_wrapper_0_ac_an_req_endian [get_bd_pins a2l2_axi_0/ac_an_req_endian] [get_bd_pins c_wrapper_0/ac_an_req_endian] + connect_bd_net -net c_wrapper_0_ac_an_req_ld_core_tag [get_bd_pins a2l2_axi_0/ac_an_req_ld_core_tag] [get_bd_pins c_wrapper_0/ac_an_req_ld_core_tag] + connect_bd_net -net c_wrapper_0_ac_an_req_ld_xfr_len [get_bd_pins a2l2_axi_0/ac_an_req_ld_xfr_len] [get_bd_pins c_wrapper_0/ac_an_req_ld_xfr_len] + connect_bd_net -net c_wrapper_0_ac_an_req_pwr_token [get_bd_pins a2l2_axi_0/ac_an_req_pwr_token] [get_bd_pins c_wrapper_0/ac_an_req_pwr_token] + connect_bd_net -net c_wrapper_0_ac_an_req_ra [get_bd_pins a2l2_axi_0/ac_an_req_ra] [get_bd_pins c_wrapper_0/ac_an_req_ra] + connect_bd_net -net c_wrapper_0_ac_an_req_thread [get_bd_pins a2l2_axi_0/ac_an_req_thread] [get_bd_pins c_wrapper_0/ac_an_req_thread] + connect_bd_net -net c_wrapper_0_ac_an_req_ttype [get_bd_pins a2l2_axi_0/ac_an_req_ttype] [get_bd_pins c_wrapper_0/ac_an_req_ttype] + connect_bd_net -net c_wrapper_0_ac_an_req_user_defined [get_bd_pins a2l2_axi_0/ac_an_req_user_defined] [get_bd_pins c_wrapper_0/ac_an_req_user_defined] + connect_bd_net -net c_wrapper_0_ac_an_req_wimg_g [get_bd_pins a2l2_axi_0/ac_an_req_wimg_g] [get_bd_pins c_wrapper_0/ac_an_req_wimg_g] + connect_bd_net -net c_wrapper_0_ac_an_req_wimg_i [get_bd_pins a2l2_axi_0/ac_an_req_wimg_i] [get_bd_pins c_wrapper_0/ac_an_req_wimg_i] + connect_bd_net -net c_wrapper_0_ac_an_req_wimg_m [get_bd_pins a2l2_axi_0/ac_an_req_wimg_m] [get_bd_pins c_wrapper_0/ac_an_req_wimg_m] + connect_bd_net -net c_wrapper_0_ac_an_req_wimg_w [get_bd_pins a2l2_axi_0/ac_an_req_wimg_w] [get_bd_pins c_wrapper_0/ac_an_req_wimg_w] + connect_bd_net -net c_wrapper_0_ac_an_st_byte_enbl [get_bd_pins a2l2_axi_0/ac_an_st_byte_enbl] [get_bd_pins c_wrapper_0/ac_an_st_byte_enbl] + connect_bd_net -net c_wrapper_0_ac_an_st_data [get_bd_pins a2l2_axi_0/ac_an_st_data] [get_bd_pins c_wrapper_0/ac_an_st_data] + connect_bd_net -net c_wrapper_0_ac_an_st_data_pwr_token [get_bd_pins a2l2_axi_0/ac_an_st_data_pwr_token] [get_bd_pins c_wrapper_0/ac_an_st_data_pwr_token] + connect_bd_net -net clk_in1_n_0_1 [get_bd_ports clk_in1_n_0] [get_bd_pins clk_wiz_0/clk_in1_n] + connect_bd_net -net clk_in1_p_0_1 [get_bd_ports clk_in1_p_0] [get_bd_pins clk_wiz_0/clk_in1_p] + connect_bd_net -net clk_wiz_0_clk [get_bd_pins a2l2_axi_0/clk] [get_bd_pins a2o_axi_reg_0/s00_axi_aclk] [get_bd_pins a2o_axi_reg_0/s_axi_intr_aclk] [get_bd_pins a2o_dbug_0/clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_bram_ctrl_1/s_axi_aclk] [get_bd_pins axi_protocol_checker_0/aclk] [get_bd_pins c_wrapper_0/clk] [get_bd_pins clk_wiz_0/clk] [get_bd_pins jtag_axi_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk] [get_bd_pins system_ila_0/clk] [get_bd_pins system_ila_1/clk] [get_bd_pins vio_0/clk] [get_bd_pins vio_1/clk] [get_bd_pins vio_2/clk] [get_bd_pins vio_3/clk] + connect_bd_net -net clk_wiz_0_clk2x [get_bd_pins c_wrapper_0/clk2x] [get_bd_pins clk_wiz_0/clk2x] + connect_bd_net -net clk_wiz_0_clk4x [get_bd_pins c_wrapper_0/clk4x] [get_bd_pins clk_wiz_0/clk4x] + connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_0/dcm_locked] + connect_bd_net -net proc_sys_reset_0_mb_reset [get_bd_pins c_wrapper_0/reset] [get_bd_pins proc_sys_reset_0/mb_reset] + connect_bd_net -net reverserator_3_0_inndoor [get_bd_pins reverserator_3_0/inndoor] [get_bd_pins vio_2/probe_in1] + connect_bd_net -net reverserator_3_1_inndoor [get_bd_pins reverserator_3_1/inndoor] [get_bd_pins vio_2/probe_in2] + connect_bd_net -net reverserator_3_2_inndoor [get_bd_pins reverserator_3_2/inndoor] [get_bd_pins vio_2/probe_in3] + connect_bd_net -net reverserator_4_0_outtie [get_bd_pins reverserator_4_0/outtie] [get_bd_pins vio_2/probe_in0] + connect_bd_net -net reverserator_4_1_outtie [get_bd_pins reverserator_4_1/outtie] [get_bd_pins vio_1/probe_in2] + connect_bd_net -net reverserator_4_2_outtie [get_bd_pins reverserator_4_2/outtie] [get_bd_pins vio_2/probe_in4] + connect_bd_net -net reverserator_4_3_outtie [get_bd_pins reverserator_4_3/outtie] [get_bd_pins vio_1/probe_in4] + connect_bd_net -net reverserator_64_0_skidrowwww [get_bd_pins reverserator_64_0/skidrowwww] [get_bd_pins vio_0/probe_in2] + connect_bd_net -net vio_0_probe_out0 [get_bd_pins a2o_dbug_0/req_valid] [get_bd_pins vio_0/probe_out0] + connect_bd_net -net vio_0_probe_out1 [get_bd_pins a2o_dbug_0/req_rw] [get_bd_pins vio_0/probe_out1] + connect_bd_net -net vio_0_probe_out2 [get_bd_pins a2o_dbug_0/req_id] [get_bd_pins vio_0/probe_out2] + connect_bd_net -net vio_0_probe_out3 [get_bd_pins a2o_dbug_0/req_addr] [get_bd_pins vio_0/probe_out3] + connect_bd_net -net vio_0_probe_out4 [get_bd_pins a2o_dbug_0/req_wr_data] [get_bd_pins vio_0/probe_out4] + connect_bd_net -net vio_0_probe_out5 [get_bd_pins a2o_dbug_0/dch_in] [get_bd_pins vio_0/probe_out5] + connect_bd_net -net vio_0_probe_out6 [get_bd_pins a2o_dbug_0/cch_in] [get_bd_pins vio_0/probe_out6] + connect_bd_net -net vio_1_probe_out0 [get_bd_pins a2o_dbug_0/threadstop_in] [get_bd_pins vio_1/probe_out0] + connect_bd_net -net vio_1_probe_out1 [get_bd_pins proc_sys_reset_0/aux_reset_in] [get_bd_pins vio_1/probe_out1] + connect_bd_net -net vio_1_probe_out2 [get_bd_pins system_ila_1/TRIG_OUT_ack] [get_bd_pins vio_1/probe_out2] + connect_bd_net -net vio_1_probe_out3 [get_bd_pins c_wrapper_0/an_ac_coreid] [get_bd_pins vio_1/probe_out3] + connect_bd_net -net vio_1_probe_out4 [get_bd_pins c_wrapper_0/an_ac_external_mchk] [get_bd_pins vio_1/probe_out4] + connect_bd_net -net vio_1_probe_out5 [get_bd_pins vio_1/probe_in3] [get_bd_pins vio_1/probe_out5] + connect_bd_net -net vio_1_probe_out6 [get_bd_pins c_wrapper_0/an_ac_crit_interrupt] [get_bd_pins vio_1/probe_out6] + connect_bd_net -net vio_1_probe_out7 [get_bd_pins c_wrapper_0/an_ac_ext_interrupt] [get_bd_pins vio_1/probe_out7] + connect_bd_net -net vio_1_probe_out8 [get_bd_pins c_wrapper_0/an_ac_perf_interrupt] [get_bd_pins vio_1/probe_out8] + connect_bd_net -net vio_1_probe_out9 [get_bd_pins c_wrapper_0/an_ac_tb_update_enable] [get_bd_pins vio_1/probe_out9] + connect_bd_net -net vio_1_probe_out10 [get_bd_pins c_wrapper_0/an_ac_tb_update_pulse] [get_bd_pins vio_1/probe_out10] + connect_bd_net -net vio_1_probe_out11 [get_bd_pins c_wrapper_0/an_ac_flh2l2_gate] [get_bd_pins vio_1/probe_out11] + connect_bd_net -net vio_1_probe_out12 [get_bd_pins c_wrapper_0/an_ac_hang_pulse] [get_bd_pins vio_1/probe_out12] + #wtf connect_bd_net -net vio_1_probe_out13 [get_bd_pins c_wrapper_0/ac_an_debug_trigger] [get_bd_pins vio_1/probe_out13] + connect_bd_net -net vio_1_probe_out14 [get_bd_pins a2o_dbug_0/trigger_ack_enable] [get_bd_pins vio_1/probe_out14] + connect_bd_net -net vio_1_probe_out15 [get_bd_pins a2o_dbug_0/trigger_threadstop] [get_bd_pins vio_1/probe_out15] + connect_bd_net -net vio_1_probe_out16 [get_bd_pins c_wrapper_0/an_ac_debug_stop] [get_bd_pins vio_1/probe_out16] + connect_bd_net -net vio_1_probe_out17 [get_bd_pins a2l2_axi_0/axi_loads_max] [get_bd_pins vio_1/probe_out17] + connect_bd_net -net vio_1_probe_out18 [get_bd_pins a2l2_axi_0/axi_stores_max] [get_bd_pins vio_1/probe_out18] + connect_bd_net -net vio_3_probe_out0 [get_bd_pins a2o_axi_reg_0/reg_in_00] [get_bd_pins vio_3/probe_out0] + connect_bd_net -net vio_3_probe_out1 [get_bd_pins a2o_axi_reg_0/reg_cmd_00] [get_bd_pins vio_3/probe_out1] + connect_bd_net -net xlconstant_1_dout [get_bd_pins a2o_axi_reg_0/reg_cmd_01] [get_bd_pins a2o_axi_reg_0/reg_cmd_02] [get_bd_pins a2o_axi_reg_0/reg_cmd_03] [get_bd_pins a2o_axi_reg_0/reg_cmd_04] [get_bd_pins a2o_axi_reg_0/reg_cmd_05] [get_bd_pins a2o_axi_reg_0/reg_cmd_06] [get_bd_pins a2o_axi_reg_0/reg_cmd_07] [get_bd_pins a2o_axi_reg_0/reg_cmd_08] [get_bd_pins a2o_axi_reg_0/reg_cmd_09] [get_bd_pins a2o_axi_reg_0/reg_cmd_0A] [get_bd_pins a2o_axi_reg_0/reg_cmd_0B] [get_bd_pins a2o_axi_reg_0/reg_cmd_0C] [get_bd_pins a2o_axi_reg_0/reg_cmd_0D] [get_bd_pins a2o_axi_reg_0/reg_cmd_0E] [get_bd_pins a2o_axi_reg_0/reg_cmd_0F] [get_bd_pins xlconstant_1/dout] + connect_bd_net -net xlconstant_2_dout [get_bd_pins a2o_axi_reg_0/reg_in_01] [get_bd_pins a2o_axi_reg_0/reg_in_02] [get_bd_pins a2o_axi_reg_0/reg_in_03] [get_bd_pins a2o_axi_reg_0/reg_in_04] [get_bd_pins a2o_axi_reg_0/reg_in_05] [get_bd_pins a2o_axi_reg_0/reg_in_06] [get_bd_pins a2o_axi_reg_0/reg_in_07] [get_bd_pins a2o_axi_reg_0/reg_in_08] [get_bd_pins a2o_axi_reg_0/reg_in_09] [get_bd_pins a2o_axi_reg_0/reg_in_0A] [get_bd_pins a2o_axi_reg_0/reg_in_0B] [get_bd_pins a2o_axi_reg_0/reg_in_0C] [get_bd_pins a2o_axi_reg_0/reg_in_0D] [get_bd_pins a2o_axi_reg_0/reg_in_0E] [get_bd_pins a2o_axi_reg_0/reg_in_0F] [get_bd_pins xlconstant_2/dout] + connect_bd_net -net xlconstant_3_dout [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins xlconstant_3/dout] + connect_bd_net -net xlconstant_4_dout [get_bd_pins proc_sys_reset_0/mb_debug_sys_rst] [get_bd_pins xlconstant_4/dout] + + # Create address segments + create_bd_addr_seg -range 0x00001000 -offset 0xFFFFF000 [get_bd_addr_spaces a2l2_axi_0/m00_axi] [get_bd_addr_segs a2o_axi_reg_0/s00_axi/reg0] SEG_a2o_axi_reg_0_reg0 + create_bd_addr_seg -range 0x00001000 -offset 0xFFFFE000 [get_bd_addr_spaces a2l2_axi_0/m00_axi] [get_bd_addr_segs a2o_axi_reg_0/s_axi_intr/reg0] SEG_a2o_axi_reg_0_reg01 + create_bd_addr_seg -range 0x00040000 -offset 0x00000000 [get_bd_addr_spaces a2l2_axi_0/m00_axi] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 + create_bd_addr_seg -range 0x00100000 -offset 0x10000000 [get_bd_addr_spaces a2l2_axi_0/m00_axi] [get_bd_addr_segs axi_bram_ctrl_1/S_AXI/Mem0] SEG_axi_bram_ctrl_3_Mem0 + create_bd_addr_seg -range 0x00010000 -offset 0xFE000000 [get_bd_addr_spaces a2l2_axi_0/m00_axi] [get_bd_addr_segs axi_protocol_checker_0/S_AXI/Reg] SEG_axi_protocol_checker_0_Reg + create_bd_addr_seg -range 0x00001000 -offset 0xFFFFF000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs a2o_axi_reg_0/s00_axi/reg0] SEG_a2o_axi_reg_0_reg0 + create_bd_addr_seg -range 0x00001000 -offset 0xFFFFE000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs a2o_axi_reg_0/s_axi_intr/reg0] SEG_a2o_axi_reg_0_reg04 + create_bd_addr_seg -range 0x00040000 -offset 0x00000000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0 + create_bd_addr_seg -range 0x00100000 -offset 0x10000000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_bram_ctrl_1/S_AXI/Mem0] SEG_axi_bram_ctrl_1_Mem0 + create_bd_addr_seg -range 0x00010000 -offset 0xFE000000 [get_bd_addr_spaces jtag_axi_0/Data] [get_bd_addr_segs axi_protocol_checker_0/S_AXI/Reg] SEG_axi_protocol_checker_0_Reg + + # Customize + set_property SCREENSIZE {10 10} [get_bd_cells /reverserator_3_0] + set_property SCREENSIZE {10 10} [get_bd_cells /reverserator_3_1] + set_property SCREENSIZE {10 10} [get_bd_cells /reverserator_3_2] + set_property SCREENSIZE {10 10} [get_bd_cells /reverserator_4_0] + set_property SCREENSIZE {10 10} [get_bd_cells /reverserator_4_1] + set_property SCREENSIZE {10 10} [get_bd_cells /reverserator_4_2] + set_property SCREENSIZE {10 10} [get_bd_cells /reverserator_4_3] + set_property SCREENSIZE {10 10} [get_bd_cells /reverserator_64_0] + set_property SCREENSIZE {10 10} [get_bd_cells /xlconstant_1] + set_property SCREENSIZE {10 10} [get_bd_cells /xlconstant_2] + set_property SCREENSIZE {10 10} [get_bd_cells /xlconstant_4] + set_property SCREENSIZE {10 10} [get_bd_cells /xlconstant_3] + + # Perform GUI Layout + regenerate_bd_layout -layout_string { + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0.19 2019-03-26 bk=1.5019 VDI=41 GEI=35 GUI=JA:9.0 TLS +# -string -flagsOSRD +preplace port clk_in1_n_0 -pg 1 -lvl 0 -x -10 -y 1610 -defaultsOSRD +preplace port clk_in1_p_0 -pg 1 -lvl 0 -x -10 -y 1630 -defaultsOSRD +preplace inst a2l2_axi_0 -pg 1 -lvl 8 -x 3730 -y 1090 -defaultsOSRD +preplace inst a2o_axi_reg_0 -pg 1 -lvl 10 -x 4700 -y 390 -defaultsOSRD +preplace inst a2o_dbug_0 -pg 1 -lvl 3 -x 990 -y 1350 -defaultsOSRD +preplace inst axi_bram_ctrl_0 -pg 1 -lvl 10 -x 4700 -y 880 -defaultsOSRD +preplace inst axi_bram_ctrl_1 -pg 1 -lvl 10 -x 4700 -y 1020 -defaultsOSRD +preplace inst axi_protocol_checker_0 -pg 1 -lvl 10 -x 4700 -y 1630 -defaultsOSRD +preplace inst blk_mem_gen_0 -pg 1 -lvl 11 -x 5020 -y 940 -defaultsOSRD +preplace inst blk_mem_gen_1 -pg 1 -lvl 11 -x 5020 -y 1080 -defaultsOSRD +preplace inst c_wrapper_0 -pg 1 -lvl 4 -x 1750 -y 1320 -defaultsOSRD +preplace inst clk_wiz_0 -pg 1 -lvl 1 -x 170 -y 1610 -defaultsOSRD +preplace inst jtag_axi_0 -pg 1 -lvl 8 -x 3730 -y 1480 -defaultsOSRD +preplace inst proc_sys_reset_0 -pg 1 -lvl 7 -x 3220 -y 1640 -defaultsOSRD +preplace inst reverserator_3_0 -pg 1 -lvl 10 -x 4700 -y 1780 -defaultsOSRD -resize 83 88 +preplace inst reverserator_3_1 -pg 1 -lvl 10 -x 4700 -y 1370 -defaultsOSRD -resize 83 88 +preplace inst reverserator_3_2 -pg 1 -lvl 10 -x 4700 -y 1480 -defaultsOSRD -resize 83 88 +preplace inst reverserator_4_0 -pg 1 -lvl 10 -x 4700 -y 1260 -defaultsOSRD -resize 83 88 +preplace inst reverserator_4_1 -pg 1 -lvl 5 -x 2360 -y 1220 -defaultsOSRD -resize 83 88 +preplace inst reverserator_4_2 -pg 1 -lvl 10 -x 4700 -y 1150 -defaultsOSRD -resize 83 88 +preplace inst reverserator_64_0 -pg 1 -lvl 1 -x 170 -y 1410 -defaultsOSRD -resize 83 88 +preplace inst smartconnect_0 -pg 1 -lvl 9 -x 4260 -y 1040 -defaultsOSRD +preplace inst system_ila_0 -pg 1 -lvl 9 -x 4260 -y 1500 -defaultsOSRD +preplace inst system_ila_1 -pg 1 -lvl 2 -x 570 -y 1720 -defaultsOSRD +preplace inst vio_0 -pg 1 -lvl 2 -x 570 -y 1410 -defaultsOSRD +preplace inst vio_1 -pg 1 -lvl 6 -x 2720 -y 2050 -defaultsOSRD +preplace inst vio_2 -pg 1 -lvl 11 -x 5020 -y 1470 -defaultsOSRD +preplace inst vio_3 -pg 1 -lvl 9 -x 4260 -y 650 -defaultsOSRD +preplace inst xlconstant_1 -pg 1 -lvl 9 -x 4260 -y 110 -defaultsOSRD -resize 83 88 +preplace inst xlconstant_2 -pg 1 -lvl 9 -x 4260 -y 800 -defaultsOSRD -resize 83 88 +preplace inst xlconstant_3 -pg 1 -lvl 6 -x 2720 -y 1590 -defaultsOSRD -resize 83 88 +preplace inst xlconstant_4 -pg 1 -lvl 6 -x 2720 -y 1700 -defaultsOSRD -resize 83 88 +preplace inst reverserator_4_3 -pg 1 -lvl 5 -x 2360 -y 2130 -defaultsOSRD -resize 83 88 +preplace netloc Net2 1 2 4 760 1730 NJ 1730 NJ 1730 2470J +preplace netloc a2l2_axi_0_an_ac_reld_core_tag 1 3 6 1490 1680 2130J 1660 2500J 1470 3020J 1530 3410J 1550 4020 +preplace netloc a2l2_axi_0_an_ac_reld_crit_qw 1 3 6 1270 710 NJ 710 NJ 710 NJ 710 NJ 710 4050 +preplace netloc a2l2_axi_0_an_ac_reld_data 1 3 6 1390 730 NJ 730 NJ 730 NJ 730 NJ 730 3970 +preplace netloc a2l2_axi_0_an_ac_reld_data_coming 1 3 6 1260 690 NJ 690 NJ 690 NJ 690 NJ 690 4020 +preplace netloc a2l2_axi_0_an_ac_reld_data_vld 1 3 6 1380 720 NJ 720 NJ 720 NJ 720 NJ 720 4010 +preplace netloc a2l2_axi_0_an_ac_reld_ecc_err 1 3 6 1410 770 NJ 770 NJ 770 NJ 770 NJ 770 3950 +preplace netloc a2l2_axi_0_an_ac_reld_ecc_err_ue 1 3 6 1330 740 NJ 740 NJ 740 NJ 740 NJ 740 4000 +preplace netloc a2l2_axi_0_an_ac_reld_l1_dump 1 3 6 1290 750 NJ 750 NJ 750 NJ 750 NJ 750 4040 +preplace netloc a2l2_axi_0_an_ac_reld_qw 1 3 6 1430 780 NJ 780 NJ 780 NJ 780 NJ 780 3960 +preplace netloc a2l2_axi_0_an_ac_req_ld_pop 1 3 6 1340 790 NJ 790 NJ 790 NJ 790 NJ 790 3990 +preplace netloc a2l2_axi_0_an_ac_req_st_gather 1 3 6 1310 800 NJ 800 NJ 800 NJ 800 NJ 800 4030 +preplace netloc a2l2_axi_0_an_ac_req_st_pop 1 3 6 1360 810 NJ 810 NJ 810 NJ 810 NJ 810 3980 +preplace netloc a2l2_axi_0_an_ac_reservation_vld 1 3 6 1440 1710 2200J 1410 NJ 1410 NJ 1410 NJ 1410 3950 +preplace netloc a2l2_axi_0_an_ac_stcx_complete 1 3 6 1470 2330 NJ 2330 NJ 2330 NJ 2330 NJ 2330 3980 +preplace netloc a2l2_axi_0_an_ac_stcx_pass 1 3 6 1460 2350 NJ 2350 NJ 2350 NJ 2350 NJ 2350 3970 +preplace netloc a2l2_axi_0_an_ac_sync_ack 1 3 6 1480 2360 NJ 2360 NJ 2360 NJ 2360 NJ 2360 3960 +preplace netloc a2l2_axi_0_err 1 8 2 NJ 930 4450J +preplace netloc a2o_axi_reg_0_irq 1 8 3 4100 -20 4410J -50 4880 +preplace netloc a2o_axi_reg_0_reg_out_00 1 8 3 4110 -10 4420J -40 4870 +preplace netloc a2o_dbug_0_cch_out 1 1 3 350 1530 NJ 1530 1170 +preplace netloc a2o_dbug_0_dch_out 1 1 3 360 1540 NJ 1540 1190 +preplace netloc a2o_dbug_0_err 1 1 3 340 1550 NJ 1550 1180 +preplace netloc a2o_dbug_0_rsp_data 1 0 4 10 1520 290J 1560 NJ 1560 1200 +preplace netloc a2o_dbug_0_rsp_valid 1 1 3 320 1570 NJ 1570 1210 +preplace netloc a2o_dbug_0_threadstop_out 1 3 1 1250 1120n +preplace netloc a2o_dbug_0_trigger_ack_out 1 1 3 330 1580 NJ 1580 1220 +preplace netloc a2o_dbug_0_trigger_out 1 3 6 1230 1690 2210J 1670 2510J 1480 3040J 1510 3420J 1560 4110J +preplace netloc a2o_reset_0_reset 1 2 8 790 1740 NJ 1740 2220J 1680 2520J 1490 3000J 1520 3460 760 4090 730 4510 +preplace netloc axi_protocol_checker_0_pc_asserted 1 1 10 360 2020 NJ 2020 NJ 2020 NJ 2020 2520 2320 NJ 2320 NJ 2320 NJ 2320 NJ 2320 4870 +preplace netloc axi_protocol_checker_0_pc_status 1 1 10 350 1810 NJ 1810 NJ 1810 NJ 1810 NJ 1810 2970J 1840 NJ 1840 NJ 1840 4420J 1850 4890 +preplace netloc c_wrapper_0_ac_an_checkstop 1 4 6 2000J 820 NJ 820 NJ 820 NJ 820 4110J 870 4470J +preplace netloc c_wrapper_0_ac_an_local_checkstop 1 4 6 2140J 1390 NJ 1390 NJ 1390 NJ 1390 NJ 1390 4450J +preplace netloc c_wrapper_0_ac_an_machine_check 1 4 6 1980J 830 NJ 830 NJ 830 NJ 830 4100J 880 4460J +preplace netloc c_wrapper_0_ac_an_pm_thread_running 1 4 1 2010J 1130n +preplace netloc c_wrapper_0_ac_an_recov_err 1 4 6 2020J 840 NJ 840 NJ 840 NJ 840 4060J 890 4430J +preplace netloc c_wrapper_0_ac_an_req 1 4 4 2040 1000 NJ 1000 NJ 1000 NJ +preplace netloc c_wrapper_0_ac_an_req_endian 1 4 4 2110J 1070 2550J 1080 NJ 1080 3410 +preplace netloc c_wrapper_0_ac_an_req_ld_core_tag 1 4 4 2080J 1080 2540J 1090 NJ 1090 3420 +preplace netloc c_wrapper_0_ac_an_req_ld_xfr_len 1 4 4 2100J 1090 2530J 1100 NJ 1100 3430 +preplace netloc c_wrapper_0_ac_an_req_pwr_token 1 4 4 2030 990 NJ 990 NJ 990 3430J +preplace netloc c_wrapper_0_ac_an_req_ra 1 4 4 2050 1100 2520J 1110 NJ 1110 3440J +preplace netloc c_wrapper_0_ac_an_req_thread 1 4 4 2060 1110 2510J 1120 NJ 1120 3500J +preplace netloc c_wrapper_0_ac_an_req_ttype 1 4 4 2070 1120 2500J 1130 NJ 1130 3510J +preplace netloc c_wrapper_0_ac_an_req_user_defined 1 4 4 2150J 1140 2470J 1150 NJ 1150 3510 +preplace netloc c_wrapper_0_ac_an_req_wimg_g 1 4 4 2120J 1150 2460J 1160 NJ 1160 N +preplace netloc c_wrapper_0_ac_an_req_wimg_i 1 4 4 2090J 1130 2490J 1140 NJ 1140 3500 +preplace netloc c_wrapper_0_ac_an_req_wimg_m 1 4 4 2160J 1350 2520J 1330 NJ 1330 3470 +preplace netloc c_wrapper_0_ac_an_req_wimg_w 1 4 4 2130J 1380 2550J 1340 NJ 1340 3480 +preplace netloc c_wrapper_0_ac_an_st_byte_enbl 1 4 4 2180J 1360 NJ 1360 NJ 1360 3500 +preplace netloc c_wrapper_0_ac_an_st_data 1 4 4 2170J 1340 2540J 1370 NJ 1370 3510 +preplace netloc c_wrapper_0_ac_an_st_data_pwr_token 1 4 4 2190J 1370 2530J 1350 NJ 1350 3490 +preplace netloc clk_in1_n_0_1 1 0 1 NJ 1610 +preplace netloc clk_in1_p_0_1 1 0 1 NJ 1630 +preplace netloc clk_wiz_0_clk 1 1 10 310 1290 750 1590 1240 1770 NJ 1770 2460 1460 3030 1470 3450 700 4080 900 4480 1860 4900J +preplace netloc clk_wiz_0_clk2x 1 1 3 280J 1160 NJ 1160 1190 +preplace netloc clk_wiz_0_clk4x 1 1 3 300J 1180 750J 1170 1220 +preplace netloc clk_wiz_0_locked 1 1 6 NJ 1640 NJ 1640 1180J 1780 NJ 1780 NJ 1780 3040 +preplace netloc proc_sys_reset_0_mb_reset 1 3 5 1440 940 NJ 940 NJ 940 NJ 940 3400 +preplace netloc reverserator_3_0_inndoor 1 10 1 4910 1460n +preplace netloc reverserator_3_1_inndoor 1 10 1 4870 1370n +preplace netloc reverserator_3_2_inndoor 1 10 1 4860 1480n +preplace netloc reverserator_4_0_outtie 1 10 1 4890 1260n +preplace netloc reverserator_4_1_outtie 1 5 1 2490 1220n +preplace netloc reverserator_4_2_outtie 1 10 1 4880 1150n +preplace netloc reverserator_64_0_skidrowwww 1 1 1 NJ 1410 +preplace netloc vio_0_probe_out0 1 2 1 N 1350 +preplace netloc vio_0_probe_out1 1 2 1 730 1370n +preplace netloc vio_0_probe_out2 1 2 1 740 1370n +preplace netloc vio_0_probe_out3 1 2 1 770 1390n +preplace netloc vio_0_probe_out4 1 2 1 N 1430 +preplace netloc vio_0_probe_out5 1 2 1 N 1450 +preplace netloc vio_0_probe_out6 1 2 1 N 1470 +preplace netloc vio_1_probe_out0 1 2 5 780 1790 NJ 1790 NJ 1790 NJ 1790 2900 +preplace netloc vio_1_probe_out1 1 6 1 3000 1640n +preplace netloc vio_1_probe_out2 1 2 5 740 1750 1170J 1800 NJ 1800 NJ 1800 2880 +preplace netloc vio_1_probe_out3 1 3 4 1450 950 NJ 950 NJ 950 2950 +preplace netloc vio_1_probe_out4 1 3 4 1280 2370 NJ 2370 NJ 2370 2950 +preplace netloc vio_1_probe_out5 1 5 2 2550 2290 2900 +preplace netloc vio_1_probe_out6 1 3 4 1470 960 NJ 960 NJ 960 2940 +preplace netloc vio_1_probe_out7 1 3 4 1350 1750 NJ 1750 2480J 1770 2910 +preplace netloc vio_1_probe_out8 1 3 4 1420 1700 NJ 1700 2540J 1510 2930 +preplace netloc vio_1_probe_out9 1 3 4 1300 2380 NJ 2380 NJ 2380 2930 +preplace netloc vio_1_probe_out10 1 3 4 1450 2310 NJ 2310 NJ 2310 2890 +preplace netloc vio_1_probe_out11 1 3 4 1400 2300 NJ 2300 NJ 2300 2880 +preplace netloc vio_1_probe_out12 1 3 4 1320 2390 NJ 2390 NJ 2390 2910 +preplace netloc vio_1_probe_out14 1 2 5 800 1760 NJ 1760 2240J 1710 2550J 1520 2920 +preplace netloc vio_1_probe_out15 1 2 5 810 1720 NJ 1720 2230J 1690 2530J 1500 2960 +preplace netloc vio_1_probe_out16 1 3 4 1370 2340 NJ 2340 NJ 2340 2870 +preplace netloc vio_1_probe_out17 1 6 2 2980J 970 3410 +preplace netloc vio_1_probe_out18 1 6 2 3010J 980 3420 +preplace netloc vio_3_probe_out0 1 9 1 4430 380n +preplace netloc vio_3_probe_out1 1 9 1 4420 60n +preplace netloc xlconstant_1_dout 1 9 1 4470 80n +preplace netloc xlconstant_2_dout 1 9 1 4470 400n +preplace netloc xlconstant_3_dout 1 6 1 2970J 1590n +preplace netloc xlconstant_4_dout 1 6 1 2990J 1660n +preplace netloc reverserator_4_3_outtie 1 5 1 2540 2100n +preplace netloc c_wrapper_0_ac_an_debug_trigger 1 4 1 1990 1110n +preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 10 1 4870J 880n +preplace netloc smartconnect_0_M03_AXI 1 9 1 4500 1000n +preplace netloc smartconnect_0_M02_AXI 1 9 1 4490 860n +preplace netloc jtag_axi_0_M_AXI 1 8 1 4070 1030n +preplace netloc smartconnect_0_M01_AXI 1 9 1 4440 40n +preplace netloc a2l2_axi_0_m00_axi 1 8 2 4060 1400 4410 +preplace netloc smartconnect_0_M04_AXI 1 9 1 4420 1080n +preplace netloc smartconnect_0_M00_AXI 1 9 1 4410 20n +preplace netloc axi_bram_ctrl_3_BRAM_PORTA 1 10 1 4880J 1020n +levelinfo -pg 1 -10 170 570 990 1750 2360 2720 3220 3730 4260 4700 5020 5140 +pagesize -pg 1 -db -bbox -sgen -150 -60 5140 2430 +" +} + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design + close_bd_design $design_name +} +# End of cr_bd_a2o_bd() +cr_bd_a2o_bd "" +set_property LIBRARY "work" [get_files a2o_bd.bd ] +set_property REGISTERED_WITH_MANAGER "1" [get_files a2o_bd.bd ] +set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files a2o_bd.bd ] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xcvu3p-ffvc1517-2-e -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2019" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj +set_property -name "steps.synth_design.args.flatten_hierarchy" -value "none" -objects $obj +set_property -name "steps.synth_design.args.bufg" -value "0" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xcvu3p-ffvc1517-2-e -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2019" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "part" -value "xcvu3p-ffvc1517-2-e" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.opt_design.args.more options" -value "-retarget -propconst -bram_power_opt -debug_log" -objects $obj +set_property -name "steps.place_design.args.directive" -value "Explore" -objects $obj +set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj +set_property -name "steps.route_design.args.directive" -value "Explore" -objects $obj +set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "1" -objects $obj +set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Explore" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/rel/build/bd/ila.tcl b/rel/build/bd/ila.tcl new file mode 100644 index 0000000..1475e2e --- /dev/null +++ b/rel/build/bd/ila.tcl @@ -0,0 +1,138 @@ +# ila parms +set ila u_ila_0 + +set depth 32768 +set stages 3 + +set trigin false +set trigout false + +set basic true +set advanced true +# F/F 1-16 T/F 2-16 F/T 1-16 T/T 2-16 +set comp 4 + +# make sure synth is open +open_run synth_1 + +# delete if exists +# delete_debug_core -quiet [get_debug_cores -quiet $ila] +catch {delete_debug_core [get_debug_cores $ila]} + +# add +create_debug_core $ila ila +set_property C_DATA_DEPTH $depth [get_debug_cores $ila] +set_property C_INPUT_PIPE_STAGES $stages [get_debug_cores $ila] +set_property C_TRIGIN_EN $trigin [get_debug_cores $ila] +set_property C_TRIGOUT_EN $trigout [get_debug_cores $ila] +set_property C_EN_STRG_QUAL $basic [get_debug_cores $ila] +set_property C_ADV_TRIGGER $advanced [get_debug_cores $ila] +set_property ALL_PROBE_SAME_MU true [get_debug_cores $ila] +set_property ALL_PROBE_SAME_MU_CNT $comp [get_debug_cores $ila] + +# add nets +connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_0/inst/clk ]] +set_property port_width 128 [get_debug_ports u_ila_0/probe0] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {a2l2_axi_0_an_ac_reld_data[127]} {a2l2_axi_0_an_ac_reld_data[126]} {a2l2_axi_0_an_ac_reld_data[125]} {a2l2_axi_0_an_ac_reld_data[124]} {a2l2_axi_0_an_ac_reld_data[123]} {a2l2_axi_0_an_ac_reld_data[122]} {a2l2_axi_0_an_ac_reld_data[121]} {a2l2_axi_0_an_ac_reld_data[120]} {a2l2_axi_0_an_ac_reld_data[119]} {a2l2_axi_0_an_ac_reld_data[118]} {a2l2_axi_0_an_ac_reld_data[117]} {a2l2_axi_0_an_ac_reld_data[116]} {a2l2_axi_0_an_ac_reld_data[115]} {a2l2_axi_0_an_ac_reld_data[114]} {a2l2_axi_0_an_ac_reld_data[113]} {a2l2_axi_0_an_ac_reld_data[112]} {a2l2_axi_0_an_ac_reld_data[111]} {a2l2_axi_0_an_ac_reld_data[110]} {a2l2_axi_0_an_ac_reld_data[109]} {a2l2_axi_0_an_ac_reld_data[108]} {a2l2_axi_0_an_ac_reld_data[107]} {a2l2_axi_0_an_ac_reld_data[106]} {a2l2_axi_0_an_ac_reld_data[105]} {a2l2_axi_0_an_ac_reld_data[104]} {a2l2_axi_0_an_ac_reld_data[103]} {a2l2_axi_0_an_ac_reld_data[102]} {a2l2_axi_0_an_ac_reld_data[101]} {a2l2_axi_0_an_ac_reld_data[100]} {a2l2_axi_0_an_ac_reld_data[99]} {a2l2_axi_0_an_ac_reld_data[98]} {a2l2_axi_0_an_ac_reld_data[97]} {a2l2_axi_0_an_ac_reld_data[96]} {a2l2_axi_0_an_ac_reld_data[95]} {a2l2_axi_0_an_ac_reld_data[94]} {a2l2_axi_0_an_ac_reld_data[93]} {a2l2_axi_0_an_ac_reld_data[92]} {a2l2_axi_0_an_ac_reld_data[91]} {a2l2_axi_0_an_ac_reld_data[90]} {a2l2_axi_0_an_ac_reld_data[89]} {a2l2_axi_0_an_ac_reld_data[88]} {a2l2_axi_0_an_ac_reld_data[87]} {a2l2_axi_0_an_ac_reld_data[86]} {a2l2_axi_0_an_ac_reld_data[85]} {a2l2_axi_0_an_ac_reld_data[84]} {a2l2_axi_0_an_ac_reld_data[83]} {a2l2_axi_0_an_ac_reld_data[82]} {a2l2_axi_0_an_ac_reld_data[81]} {a2l2_axi_0_an_ac_reld_data[80]} {a2l2_axi_0_an_ac_reld_data[79]} {a2l2_axi_0_an_ac_reld_data[78]} {a2l2_axi_0_an_ac_reld_data[77]} {a2l2_axi_0_an_ac_reld_data[76]} {a2l2_axi_0_an_ac_reld_data[75]} {a2l2_axi_0_an_ac_reld_data[74]} {a2l2_axi_0_an_ac_reld_data[73]} {a2l2_axi_0_an_ac_reld_data[72]} {a2l2_axi_0_an_ac_reld_data[71]} {a2l2_axi_0_an_ac_reld_data[70]} {a2l2_axi_0_an_ac_reld_data[69]} {a2l2_axi_0_an_ac_reld_data[68]} {a2l2_axi_0_an_ac_reld_data[67]} {a2l2_axi_0_an_ac_reld_data[66]} {a2l2_axi_0_an_ac_reld_data[65]} {a2l2_axi_0_an_ac_reld_data[64]} {a2l2_axi_0_an_ac_reld_data[63]} {a2l2_axi_0_an_ac_reld_data[62]} {a2l2_axi_0_an_ac_reld_data[61]} {a2l2_axi_0_an_ac_reld_data[60]} {a2l2_axi_0_an_ac_reld_data[59]} {a2l2_axi_0_an_ac_reld_data[58]} {a2l2_axi_0_an_ac_reld_data[57]} {a2l2_axi_0_an_ac_reld_data[56]} {a2l2_axi_0_an_ac_reld_data[55]} {a2l2_axi_0_an_ac_reld_data[54]} {a2l2_axi_0_an_ac_reld_data[53]} {a2l2_axi_0_an_ac_reld_data[52]} {a2l2_axi_0_an_ac_reld_data[51]} {a2l2_axi_0_an_ac_reld_data[50]} {a2l2_axi_0_an_ac_reld_data[49]} {a2l2_axi_0_an_ac_reld_data[48]} {a2l2_axi_0_an_ac_reld_data[47]} {a2l2_axi_0_an_ac_reld_data[46]} {a2l2_axi_0_an_ac_reld_data[45]} {a2l2_axi_0_an_ac_reld_data[44]} {a2l2_axi_0_an_ac_reld_data[43]} {a2l2_axi_0_an_ac_reld_data[42]} {a2l2_axi_0_an_ac_reld_data[41]} {a2l2_axi_0_an_ac_reld_data[40]} {a2l2_axi_0_an_ac_reld_data[39]} {a2l2_axi_0_an_ac_reld_data[38]} {a2l2_axi_0_an_ac_reld_data[37]} {a2l2_axi_0_an_ac_reld_data[36]} {a2l2_axi_0_an_ac_reld_data[35]} {a2l2_axi_0_an_ac_reld_data[34]} {a2l2_axi_0_an_ac_reld_data[33]} {a2l2_axi_0_an_ac_reld_data[32]} {a2l2_axi_0_an_ac_reld_data[31]} {a2l2_axi_0_an_ac_reld_data[30]} {a2l2_axi_0_an_ac_reld_data[29]} {a2l2_axi_0_an_ac_reld_data[28]} {a2l2_axi_0_an_ac_reld_data[27]} {a2l2_axi_0_an_ac_reld_data[26]} {a2l2_axi_0_an_ac_reld_data[25]} {a2l2_axi_0_an_ac_reld_data[24]} {a2l2_axi_0_an_ac_reld_data[23]} {a2l2_axi_0_an_ac_reld_data[22]} {a2l2_axi_0_an_ac_reld_data[21]} {a2l2_axi_0_an_ac_reld_data[20]} {a2l2_axi_0_an_ac_reld_data[19]} {a2l2_axi_0_an_ac_reld_data[18]} {a2l2_axi_0_an_ac_reld_data[17]} {a2l2_axi_0_an_ac_reld_data[16]} {a2l2_axi_0_an_ac_reld_data[15]} {a2l2_axi_0_an_ac_reld_data[14]} {a2l2_axi_0_an_ac_reld_data[13]} {a2l2_axi_0_an_ac_reld_data[12]} {a2l2_axi_0_an_ac_reld_data[11]} {a2l2_axi_0_an_ac_reld_data[10]} {a2l2_axi_0_an_ac_reld_data[9]} {a2l2_axi_0_an_ac_reld_data[8]} {a2l2_axi_0_an_ac_reld_data[7]} {a2l2_axi_0_an_ac_reld_data[6]} {a2l2_axi_0_an_ac_reld_data[5]} {a2l2_axi_0_an_ac_reld_data[4]} {a2l2_axi_0_an_ac_reld_data[3]} {a2l2_axi_0_an_ac_reld_data[2]} {a2l2_axi_0_an_ac_reld_data[1]} {a2l2_axi_0_an_ac_reld_data[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe1] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {a2l2_axi_0_an_ac_sync_ack[3]} {a2l2_axi_0_an_ac_sync_ack[2]} {a2l2_axi_0_an_ac_sync_ack[1]} {a2l2_axi_0_an_ac_sync_ack[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 2 [get_debug_ports u_ila_0/probe2] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {a2l2_axi_0_an_ac_reld_qw[59]} {a2l2_axi_0_an_ac_reld_qw[58]} ]] +create_debug_port u_ila_0 probe +set_property port_width 128 [get_debug_ports u_ila_0/probe3] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {c_wrapper_0_ac_an_st_data[127]} {c_wrapper_0_ac_an_st_data[126]} {c_wrapper_0_ac_an_st_data[125]} {c_wrapper_0_ac_an_st_data[124]} {c_wrapper_0_ac_an_st_data[123]} {c_wrapper_0_ac_an_st_data[122]} {c_wrapper_0_ac_an_st_data[121]} {c_wrapper_0_ac_an_st_data[120]} {c_wrapper_0_ac_an_st_data[119]} {c_wrapper_0_ac_an_st_data[118]} {c_wrapper_0_ac_an_st_data[117]} {c_wrapper_0_ac_an_st_data[116]} {c_wrapper_0_ac_an_st_data[115]} {c_wrapper_0_ac_an_st_data[114]} {c_wrapper_0_ac_an_st_data[113]} {c_wrapper_0_ac_an_st_data[112]} {c_wrapper_0_ac_an_st_data[111]} {c_wrapper_0_ac_an_st_data[110]} {c_wrapper_0_ac_an_st_data[109]} {c_wrapper_0_ac_an_st_data[108]} {c_wrapper_0_ac_an_st_data[107]} {c_wrapper_0_ac_an_st_data[106]} {c_wrapper_0_ac_an_st_data[105]} {c_wrapper_0_ac_an_st_data[104]} {c_wrapper_0_ac_an_st_data[103]} {c_wrapper_0_ac_an_st_data[102]} {c_wrapper_0_ac_an_st_data[101]} {c_wrapper_0_ac_an_st_data[100]} {c_wrapper_0_ac_an_st_data[99]} {c_wrapper_0_ac_an_st_data[98]} {c_wrapper_0_ac_an_st_data[97]} {c_wrapper_0_ac_an_st_data[96]} {c_wrapper_0_ac_an_st_data[95]} {c_wrapper_0_ac_an_st_data[94]} {c_wrapper_0_ac_an_st_data[93]} {c_wrapper_0_ac_an_st_data[92]} {c_wrapper_0_ac_an_st_data[91]} {c_wrapper_0_ac_an_st_data[90]} {c_wrapper_0_ac_an_st_data[89]} {c_wrapper_0_ac_an_st_data[88]} {c_wrapper_0_ac_an_st_data[87]} {c_wrapper_0_ac_an_st_data[86]} {c_wrapper_0_ac_an_st_data[85]} {c_wrapper_0_ac_an_st_data[84]} {c_wrapper_0_ac_an_st_data[83]} {c_wrapper_0_ac_an_st_data[82]} {c_wrapper_0_ac_an_st_data[81]} {c_wrapper_0_ac_an_st_data[80]} {c_wrapper_0_ac_an_st_data[79]} {c_wrapper_0_ac_an_st_data[78]} {c_wrapper_0_ac_an_st_data[77]} {c_wrapper_0_ac_an_st_data[76]} {c_wrapper_0_ac_an_st_data[75]} {c_wrapper_0_ac_an_st_data[74]} {c_wrapper_0_ac_an_st_data[73]} {c_wrapper_0_ac_an_st_data[72]} {c_wrapper_0_ac_an_st_data[71]} {c_wrapper_0_ac_an_st_data[70]} {c_wrapper_0_ac_an_st_data[69]} {c_wrapper_0_ac_an_st_data[68]} {c_wrapper_0_ac_an_st_data[67]} {c_wrapper_0_ac_an_st_data[66]} {c_wrapper_0_ac_an_st_data[65]} {c_wrapper_0_ac_an_st_data[64]} {c_wrapper_0_ac_an_st_data[63]} {c_wrapper_0_ac_an_st_data[62]} {c_wrapper_0_ac_an_st_data[61]} {c_wrapper_0_ac_an_st_data[60]} {c_wrapper_0_ac_an_st_data[59]} {c_wrapper_0_ac_an_st_data[58]} {c_wrapper_0_ac_an_st_data[57]} {c_wrapper_0_ac_an_st_data[56]} {c_wrapper_0_ac_an_st_data[55]} {c_wrapper_0_ac_an_st_data[54]} {c_wrapper_0_ac_an_st_data[53]} {c_wrapper_0_ac_an_st_data[52]} {c_wrapper_0_ac_an_st_data[51]} {c_wrapper_0_ac_an_st_data[50]} {c_wrapper_0_ac_an_st_data[49]} {c_wrapper_0_ac_an_st_data[48]} {c_wrapper_0_ac_an_st_data[47]} {c_wrapper_0_ac_an_st_data[46]} {c_wrapper_0_ac_an_st_data[45]} {c_wrapper_0_ac_an_st_data[44]} {c_wrapper_0_ac_an_st_data[43]} {c_wrapper_0_ac_an_st_data[42]} {c_wrapper_0_ac_an_st_data[41]} {c_wrapper_0_ac_an_st_data[40]} {c_wrapper_0_ac_an_st_data[39]} {c_wrapper_0_ac_an_st_data[38]} {c_wrapper_0_ac_an_st_data[37]} {c_wrapper_0_ac_an_st_data[36]} {c_wrapper_0_ac_an_st_data[35]} {c_wrapper_0_ac_an_st_data[34]} {c_wrapper_0_ac_an_st_data[33]} {c_wrapper_0_ac_an_st_data[32]} {c_wrapper_0_ac_an_st_data[31]} {c_wrapper_0_ac_an_st_data[30]} {c_wrapper_0_ac_an_st_data[29]} {c_wrapper_0_ac_an_st_data[28]} {c_wrapper_0_ac_an_st_data[27]} {c_wrapper_0_ac_an_st_data[26]} {c_wrapper_0_ac_an_st_data[25]} {c_wrapper_0_ac_an_st_data[24]} {c_wrapper_0_ac_an_st_data[23]} {c_wrapper_0_ac_an_st_data[22]} {c_wrapper_0_ac_an_st_data[21]} {c_wrapper_0_ac_an_st_data[20]} {c_wrapper_0_ac_an_st_data[19]} {c_wrapper_0_ac_an_st_data[18]} {c_wrapper_0_ac_an_st_data[17]} {c_wrapper_0_ac_an_st_data[16]} {c_wrapper_0_ac_an_st_data[15]} {c_wrapper_0_ac_an_st_data[14]} {c_wrapper_0_ac_an_st_data[13]} {c_wrapper_0_ac_an_st_data[12]} {c_wrapper_0_ac_an_st_data[11]} {c_wrapper_0_ac_an_st_data[10]} {c_wrapper_0_ac_an_st_data[9]} {c_wrapper_0_ac_an_st_data[8]} {c_wrapper_0_ac_an_st_data[7]} {c_wrapper_0_ac_an_st_data[6]} {c_wrapper_0_ac_an_st_data[5]} {c_wrapper_0_ac_an_st_data[4]} {c_wrapper_0_ac_an_st_data[3]} {c_wrapper_0_ac_an_st_data[2]} {c_wrapper_0_ac_an_st_data[1]} {c_wrapper_0_ac_an_st_data[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 6 [get_debug_ports u_ila_0/probe4] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {c_wrapper_0_ac_an_req_ttype[5]} {c_wrapper_0_ac_an_req_ttype[4]} {c_wrapper_0_ac_an_req_ttype[3]} {c_wrapper_0_ac_an_req_ttype[2]} {c_wrapper_0_ac_an_req_ttype[1]} {c_wrapper_0_ac_an_req_ttype[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/icd_icm_addr_real[51]} ]] +create_debug_port u_ila_0 probe +set_property port_width 4 [get_debug_ports u_ila_0/probe6] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {a2l2_axi_0/inst/ldq_count_q_reg[3]} {a2l2_axi_0/inst/ldq_count_q_reg[2]} {a2l2_axi_0/inst/ldq_count_q_reg[1]} {a2l2_axi_0/inst/ldq_count_q_reg[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 22 [get_debug_ports u_ila_0/probe7] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[32]} ]] +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe8] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[63]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[55]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[53]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[49]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[45]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[43]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[41]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[39]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[37]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[33]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[32]} ]] +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe9] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {c_wrapper_0_ac_an_req_ra[63]} {c_wrapper_0_ac_an_req_ra[62]} {c_wrapper_0_ac_an_req_ra[61]} {c_wrapper_0_ac_an_req_ra[60]} {c_wrapper_0_ac_an_req_ra[59]} {c_wrapper_0_ac_an_req_ra[58]} {c_wrapper_0_ac_an_req_ra[57]} {c_wrapper_0_ac_an_req_ra[56]} {c_wrapper_0_ac_an_req_ra[55]} {c_wrapper_0_ac_an_req_ra[54]} {c_wrapper_0_ac_an_req_ra[53]} {c_wrapper_0_ac_an_req_ra[52]} {c_wrapper_0_ac_an_req_ra[51]} {c_wrapper_0_ac_an_req_ra[50]} {c_wrapper_0_ac_an_req_ra[49]} {c_wrapper_0_ac_an_req_ra[48]} {c_wrapper_0_ac_an_req_ra[47]} {c_wrapper_0_ac_an_req_ra[46]} {c_wrapper_0_ac_an_req_ra[45]} {c_wrapper_0_ac_an_req_ra[44]} {c_wrapper_0_ac_an_req_ra[43]} {c_wrapper_0_ac_an_req_ra[42]} {c_wrapper_0_ac_an_req_ra[41]} {c_wrapper_0_ac_an_req_ra[40]} {c_wrapper_0_ac_an_req_ra[39]} {c_wrapper_0_ac_an_req_ra[38]} {c_wrapper_0_ac_an_req_ra[37]} {c_wrapper_0_ac_an_req_ra[36]} {c_wrapper_0_ac_an_req_ra[35]} {c_wrapper_0_ac_an_req_ra[34]} {c_wrapper_0_ac_an_req_ra[33]} {c_wrapper_0_ac_an_req_ra[32]} ]] +create_debug_port u_ila_0 probe +set_property port_width 3 [get_debug_ports u_ila_0/probe10] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {c_wrapper_0_ac_an_req_ld_xfr_len[2]} {c_wrapper_0_ac_an_req_ld_xfr_len[1]} {c_wrapper_0_ac_an_req_ld_xfr_len[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 62 [get_debug_ports u_ila_0/probe11] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[61]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[60]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[59]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[58]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[57]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[56]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[55]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[54]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[53]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[52]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[51]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[50]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[49]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[48]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[47]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[46]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[45]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[44]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[43]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[42]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[41]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[40]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[39]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[38]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[37]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[36]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[35]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[34]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[33]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[32]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[31]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[30]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[29]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[28]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[27]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[26]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[25]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[24]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[23]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[22]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[21]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[20]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[19]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[18]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[17]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[16]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[15]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[14]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[13]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[12]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[11]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[10]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[9]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[8]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[7]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[6]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[5]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[4]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[3]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[2]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[1]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 5 [get_debug_ports u_ila_0/probe12] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list {c_wrapper_0_ac_an_req_ld_core_tag[4]} {c_wrapper_0_ac_an_req_ld_core_tag[3]} {c_wrapper_0_ac_an_req_ld_core_tag[2]} {c_wrapper_0_ac_an_req_ld_core_tag[1]} {c_wrapper_0_ac_an_req_ld_core_tag[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 58 [get_debug_ports u_ila_0/probe13] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[29]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[28]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[27]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[26]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[25]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[24]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[23]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[22]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[21]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[20]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[19]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[18]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[17]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[16]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[15]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[14]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[13]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[12]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[11]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[10]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[9]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[8]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[7]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[6]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[5]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[4]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[3]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[2]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[1]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 32 [get_debug_ports u_ila_0/probe14] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[53]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[59]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[60]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[61]} ]] +create_debug_port u_ila_0 probe +set_property port_width 6 [get_debug_ports u_ila_0/probe15] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list {a2l2_axi_0/inst/stq_count_q_reg[5]} {a2l2_axi_0/inst/stq_count_q_reg[4]} {a2l2_axi_0/inst/stq_count_q_reg[3]} {a2l2_axi_0/inst/stq_count_q_reg[2]} {a2l2_axi_0/inst/stq_count_q_reg[1]} {a2l2_axi_0/inst/stq_count_q_reg[0]} ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list a2l2_axi_0_an_ac_reld_crit_qw ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list a2l2_axi_0_an_ac_reld_data_vld ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list a2l2_axi_0_an_ac_req_ld_pop ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list a2l2_axi_0_an_ac_req_st_pop ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list c_wrapper_0_ac_an_req ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe21] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list c_wrapper_0_ac_an_req_wimg_i ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/icd_icm_miss ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe23] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/ics_icd_iu1_flush ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe24] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_enable_q ]] +create_debug_port u_ila_0 probe +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_pulse_q ]] + diff --git a/rel/build/bd/impl.tcl b/rel/build/bd/impl.tcl new file mode 100644 index 0000000..fe1dcd0 --- /dev/null +++ b/rel/build/bd/impl.tcl @@ -0,0 +1,44 @@ +#synth_design -top a2o_bd -part xcvu3p-ffvc1517-2-e -verbose +#source ila_axi.tcl + +# ---------------------------------------------------------------------------------------- +# opt place phys_opt route phys_opt +# ---------------------------------------------------------------------------------------- +# v0 (1) Explore Explore Explore Explore +# v1 Explore Explore Explore Explore Explore +# ---------------------------------------------------------------------------------------- +# (1) -retarget -propconst -bram_power_opt +# +set version v0 + +# make sure synth is open +open_run synth_1 + +write_checkpoint -force a2o_synth_${version}.dcp + +if {$version == {v0}} { + opt_design -retarget -propconst -bram_power_opt -debug_log +} elseif {$version == {v1}} { + opt_design -directive Explore -debug_log +} else { + opt_design -debug_log +} + +place_design -directive Explore +#place_design -directive Explore -no_bufg_opt + +phys_opt_design -directive Explore +route_design -directive Explore +phys_opt_design -directive Explore + +write_checkpoint -force a2o_routed_${version}.dcp + +report_utilization -file utilization_route_design_${version}.rpt +report_timing_summary -max_paths 100 -file timing_routed_summary_${version}.rpt +report_bus_skew -file timing_bus_skew_${version}.rpt +report_qor_suggestions -file qor_suggestions_${version}.rpt + +write_bitstream -force -bin_file a2o_${version} +write_debug_probes -force a2o_${version} +write_cfgmem -force -format BIN -interface SPIx8 -size 256 -loadbit "up 0 a2o_${version}.bit" a2o_${version} + diff --git a/rel/build/bd/readme.md b/rel/build/bd/readme.md new file mode 100644 index 0000000..de3795f --- /dev/null +++ b/rel/build/bd/readme.md @@ -0,0 +1,31 @@ +# create/build project + +``` +$VIVADO -mode tcl -source create_project.tcl + +$VIVADO a2o_bd/a2o_bd.xpr + +>run synthesis + +source ./ila.tcl ;# to update ila_0, or set up debug manually + +source ./impl.tcl +``` + +``` +a2o_bd_routed_v0.dcp +a2o_bd_synth_v0.dcp + +utilization_route_design_v0.rpt +timing_routed_summary_v0.rpt +timing_bus_skew_v0.rpt +qor_suggestions_v0.rpt + +a2o_bd_v0.bin +a2o_bd_v0.bit +a2o_bd_v0.ltx +a2o_bd_v0_primary.bin +a2o_bd_v0_primary.prm +a2o_bd_v0_secondary.bin +a2o_bd_v0_secondary.prm +``` diff --git a/rel/build/bd/xdc/main_extras.xdc b/rel/build/bd/xdc/main_extras.xdc new file mode 100644 index 0000000..d989cdd --- /dev/null +++ b/rel/build/bd/xdc/main_extras.xdc @@ -0,0 +1,126 @@ +set_property DONT_TOUCH true [get_cells a2l2_axi_0] +# added by vivado... + + + + + + +create_debug_core u_ila_0 ila +set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] +set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0] +set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 32768 [get_debug_cores u_ila_0] +set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0] +set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores u_ila_0] +set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] +set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] +set_property port_width 1 [get_debug_ports u_ila_0/clk] +connect_debug_port u_ila_0/clk [get_nets [list clk_wiz_0_clk]] +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] +set_property port_width 128 [get_debug_ports u_ila_0/probe0] +connect_debug_port u_ila_0/probe0 [get_nets [list {a2l2_axi_0_an_ac_reld_data[127]} {a2l2_axi_0_an_ac_reld_data[126]} {a2l2_axi_0_an_ac_reld_data[125]} {a2l2_axi_0_an_ac_reld_data[124]} {a2l2_axi_0_an_ac_reld_data[123]} {a2l2_axi_0_an_ac_reld_data[122]} {a2l2_axi_0_an_ac_reld_data[121]} {a2l2_axi_0_an_ac_reld_data[120]} {a2l2_axi_0_an_ac_reld_data[119]} {a2l2_axi_0_an_ac_reld_data[118]} {a2l2_axi_0_an_ac_reld_data[117]} {a2l2_axi_0_an_ac_reld_data[116]} {a2l2_axi_0_an_ac_reld_data[115]} {a2l2_axi_0_an_ac_reld_data[114]} {a2l2_axi_0_an_ac_reld_data[113]} {a2l2_axi_0_an_ac_reld_data[112]} {a2l2_axi_0_an_ac_reld_data[111]} {a2l2_axi_0_an_ac_reld_data[110]} {a2l2_axi_0_an_ac_reld_data[109]} {a2l2_axi_0_an_ac_reld_data[108]} {a2l2_axi_0_an_ac_reld_data[107]} {a2l2_axi_0_an_ac_reld_data[106]} {a2l2_axi_0_an_ac_reld_data[105]} {a2l2_axi_0_an_ac_reld_data[104]} {a2l2_axi_0_an_ac_reld_data[103]} {a2l2_axi_0_an_ac_reld_data[102]} {a2l2_axi_0_an_ac_reld_data[101]} {a2l2_axi_0_an_ac_reld_data[100]} {a2l2_axi_0_an_ac_reld_data[99]} {a2l2_axi_0_an_ac_reld_data[98]} {a2l2_axi_0_an_ac_reld_data[97]} {a2l2_axi_0_an_ac_reld_data[96]} {a2l2_axi_0_an_ac_reld_data[95]} {a2l2_axi_0_an_ac_reld_data[94]} {a2l2_axi_0_an_ac_reld_data[93]} {a2l2_axi_0_an_ac_reld_data[92]} {a2l2_axi_0_an_ac_reld_data[91]} {a2l2_axi_0_an_ac_reld_data[90]} {a2l2_axi_0_an_ac_reld_data[89]} {a2l2_axi_0_an_ac_reld_data[88]} {a2l2_axi_0_an_ac_reld_data[87]} {a2l2_axi_0_an_ac_reld_data[86]} {a2l2_axi_0_an_ac_reld_data[85]} {a2l2_axi_0_an_ac_reld_data[84]} {a2l2_axi_0_an_ac_reld_data[83]} {a2l2_axi_0_an_ac_reld_data[82]} {a2l2_axi_0_an_ac_reld_data[81]} {a2l2_axi_0_an_ac_reld_data[80]} {a2l2_axi_0_an_ac_reld_data[79]} {a2l2_axi_0_an_ac_reld_data[78]} {a2l2_axi_0_an_ac_reld_data[77]} {a2l2_axi_0_an_ac_reld_data[76]} {a2l2_axi_0_an_ac_reld_data[75]} {a2l2_axi_0_an_ac_reld_data[74]} {a2l2_axi_0_an_ac_reld_data[73]} {a2l2_axi_0_an_ac_reld_data[72]} {a2l2_axi_0_an_ac_reld_data[71]} {a2l2_axi_0_an_ac_reld_data[70]} {a2l2_axi_0_an_ac_reld_data[69]} {a2l2_axi_0_an_ac_reld_data[68]} {a2l2_axi_0_an_ac_reld_data[67]} {a2l2_axi_0_an_ac_reld_data[66]} {a2l2_axi_0_an_ac_reld_data[65]} {a2l2_axi_0_an_ac_reld_data[64]} {a2l2_axi_0_an_ac_reld_data[63]} {a2l2_axi_0_an_ac_reld_data[62]} {a2l2_axi_0_an_ac_reld_data[61]} {a2l2_axi_0_an_ac_reld_data[60]} {a2l2_axi_0_an_ac_reld_data[59]} {a2l2_axi_0_an_ac_reld_data[58]} {a2l2_axi_0_an_ac_reld_data[57]} {a2l2_axi_0_an_ac_reld_data[56]} {a2l2_axi_0_an_ac_reld_data[55]} {a2l2_axi_0_an_ac_reld_data[54]} {a2l2_axi_0_an_ac_reld_data[53]} {a2l2_axi_0_an_ac_reld_data[52]} {a2l2_axi_0_an_ac_reld_data[51]} {a2l2_axi_0_an_ac_reld_data[50]} {a2l2_axi_0_an_ac_reld_data[49]} {a2l2_axi_0_an_ac_reld_data[48]} {a2l2_axi_0_an_ac_reld_data[47]} {a2l2_axi_0_an_ac_reld_data[46]} {a2l2_axi_0_an_ac_reld_data[45]} {a2l2_axi_0_an_ac_reld_data[44]} {a2l2_axi_0_an_ac_reld_data[43]} {a2l2_axi_0_an_ac_reld_data[42]} {a2l2_axi_0_an_ac_reld_data[41]} {a2l2_axi_0_an_ac_reld_data[40]} {a2l2_axi_0_an_ac_reld_data[39]} {a2l2_axi_0_an_ac_reld_data[38]} {a2l2_axi_0_an_ac_reld_data[37]} {a2l2_axi_0_an_ac_reld_data[36]} {a2l2_axi_0_an_ac_reld_data[35]} {a2l2_axi_0_an_ac_reld_data[34]} {a2l2_axi_0_an_ac_reld_data[33]} {a2l2_axi_0_an_ac_reld_data[32]} {a2l2_axi_0_an_ac_reld_data[31]} {a2l2_axi_0_an_ac_reld_data[30]} {a2l2_axi_0_an_ac_reld_data[29]} {a2l2_axi_0_an_ac_reld_data[28]} {a2l2_axi_0_an_ac_reld_data[27]} {a2l2_axi_0_an_ac_reld_data[26]} {a2l2_axi_0_an_ac_reld_data[25]} {a2l2_axi_0_an_ac_reld_data[24]} {a2l2_axi_0_an_ac_reld_data[23]} {a2l2_axi_0_an_ac_reld_data[22]} {a2l2_axi_0_an_ac_reld_data[21]} {a2l2_axi_0_an_ac_reld_data[20]} {a2l2_axi_0_an_ac_reld_data[19]} {a2l2_axi_0_an_ac_reld_data[18]} {a2l2_axi_0_an_ac_reld_data[17]} {a2l2_axi_0_an_ac_reld_data[16]} {a2l2_axi_0_an_ac_reld_data[15]} {a2l2_axi_0_an_ac_reld_data[14]} {a2l2_axi_0_an_ac_reld_data[13]} {a2l2_axi_0_an_ac_reld_data[12]} {a2l2_axi_0_an_ac_reld_data[11]} {a2l2_axi_0_an_ac_reld_data[10]} {a2l2_axi_0_an_ac_reld_data[9]} {a2l2_axi_0_an_ac_reld_data[8]} {a2l2_axi_0_an_ac_reld_data[7]} {a2l2_axi_0_an_ac_reld_data[6]} {a2l2_axi_0_an_ac_reld_data[5]} {a2l2_axi_0_an_ac_reld_data[4]} {a2l2_axi_0_an_ac_reld_data[3]} {a2l2_axi_0_an_ac_reld_data[2]} {a2l2_axi_0_an_ac_reld_data[1]} {a2l2_axi_0_an_ac_reld_data[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] +set_property port_width 4 [get_debug_ports u_ila_0/probe1] +connect_debug_port u_ila_0/probe1 [get_nets [list {a2l2_axi_0_an_ac_sync_ack[3]} {a2l2_axi_0_an_ac_sync_ack[2]} {a2l2_axi_0_an_ac_sync_ack[1]} {a2l2_axi_0_an_ac_sync_ack[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] +set_property port_width 2 [get_debug_ports u_ila_0/probe2] +connect_debug_port u_ila_0/probe2 [get_nets [list {a2l2_axi_0_an_ac_reld_qw[59]} {a2l2_axi_0_an_ac_reld_qw[58]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] +set_property port_width 128 [get_debug_ports u_ila_0/probe3] +connect_debug_port u_ila_0/probe3 [get_nets [list {c_wrapper_0_ac_an_st_data[127]} {c_wrapper_0_ac_an_st_data[126]} {c_wrapper_0_ac_an_st_data[125]} {c_wrapper_0_ac_an_st_data[124]} {c_wrapper_0_ac_an_st_data[123]} {c_wrapper_0_ac_an_st_data[122]} {c_wrapper_0_ac_an_st_data[121]} {c_wrapper_0_ac_an_st_data[120]} {c_wrapper_0_ac_an_st_data[119]} {c_wrapper_0_ac_an_st_data[118]} {c_wrapper_0_ac_an_st_data[117]} {c_wrapper_0_ac_an_st_data[116]} {c_wrapper_0_ac_an_st_data[115]} {c_wrapper_0_ac_an_st_data[114]} {c_wrapper_0_ac_an_st_data[113]} {c_wrapper_0_ac_an_st_data[112]} {c_wrapper_0_ac_an_st_data[111]} {c_wrapper_0_ac_an_st_data[110]} {c_wrapper_0_ac_an_st_data[109]} {c_wrapper_0_ac_an_st_data[108]} {c_wrapper_0_ac_an_st_data[107]} {c_wrapper_0_ac_an_st_data[106]} {c_wrapper_0_ac_an_st_data[105]} {c_wrapper_0_ac_an_st_data[104]} {c_wrapper_0_ac_an_st_data[103]} {c_wrapper_0_ac_an_st_data[102]} {c_wrapper_0_ac_an_st_data[101]} {c_wrapper_0_ac_an_st_data[100]} {c_wrapper_0_ac_an_st_data[99]} {c_wrapper_0_ac_an_st_data[98]} {c_wrapper_0_ac_an_st_data[97]} {c_wrapper_0_ac_an_st_data[96]} {c_wrapper_0_ac_an_st_data[95]} {c_wrapper_0_ac_an_st_data[94]} {c_wrapper_0_ac_an_st_data[93]} {c_wrapper_0_ac_an_st_data[92]} {c_wrapper_0_ac_an_st_data[91]} {c_wrapper_0_ac_an_st_data[90]} {c_wrapper_0_ac_an_st_data[89]} {c_wrapper_0_ac_an_st_data[88]} {c_wrapper_0_ac_an_st_data[87]} {c_wrapper_0_ac_an_st_data[86]} {c_wrapper_0_ac_an_st_data[85]} {c_wrapper_0_ac_an_st_data[84]} {c_wrapper_0_ac_an_st_data[83]} {c_wrapper_0_ac_an_st_data[82]} {c_wrapper_0_ac_an_st_data[81]} {c_wrapper_0_ac_an_st_data[80]} {c_wrapper_0_ac_an_st_data[79]} {c_wrapper_0_ac_an_st_data[78]} {c_wrapper_0_ac_an_st_data[77]} {c_wrapper_0_ac_an_st_data[76]} {c_wrapper_0_ac_an_st_data[75]} {c_wrapper_0_ac_an_st_data[74]} {c_wrapper_0_ac_an_st_data[73]} {c_wrapper_0_ac_an_st_data[72]} {c_wrapper_0_ac_an_st_data[71]} {c_wrapper_0_ac_an_st_data[70]} {c_wrapper_0_ac_an_st_data[69]} {c_wrapper_0_ac_an_st_data[68]} {c_wrapper_0_ac_an_st_data[67]} {c_wrapper_0_ac_an_st_data[66]} {c_wrapper_0_ac_an_st_data[65]} {c_wrapper_0_ac_an_st_data[64]} {c_wrapper_0_ac_an_st_data[63]} {c_wrapper_0_ac_an_st_data[62]} {c_wrapper_0_ac_an_st_data[61]} {c_wrapper_0_ac_an_st_data[60]} {c_wrapper_0_ac_an_st_data[59]} {c_wrapper_0_ac_an_st_data[58]} {c_wrapper_0_ac_an_st_data[57]} {c_wrapper_0_ac_an_st_data[56]} {c_wrapper_0_ac_an_st_data[55]} {c_wrapper_0_ac_an_st_data[54]} {c_wrapper_0_ac_an_st_data[53]} {c_wrapper_0_ac_an_st_data[52]} {c_wrapper_0_ac_an_st_data[51]} {c_wrapper_0_ac_an_st_data[50]} {c_wrapper_0_ac_an_st_data[49]} {c_wrapper_0_ac_an_st_data[48]} {c_wrapper_0_ac_an_st_data[47]} {c_wrapper_0_ac_an_st_data[46]} {c_wrapper_0_ac_an_st_data[45]} {c_wrapper_0_ac_an_st_data[44]} {c_wrapper_0_ac_an_st_data[43]} {c_wrapper_0_ac_an_st_data[42]} {c_wrapper_0_ac_an_st_data[41]} {c_wrapper_0_ac_an_st_data[40]} {c_wrapper_0_ac_an_st_data[39]} {c_wrapper_0_ac_an_st_data[38]} {c_wrapper_0_ac_an_st_data[37]} {c_wrapper_0_ac_an_st_data[36]} {c_wrapper_0_ac_an_st_data[35]} {c_wrapper_0_ac_an_st_data[34]} {c_wrapper_0_ac_an_st_data[33]} {c_wrapper_0_ac_an_st_data[32]} {c_wrapper_0_ac_an_st_data[31]} {c_wrapper_0_ac_an_st_data[30]} {c_wrapper_0_ac_an_st_data[29]} {c_wrapper_0_ac_an_st_data[28]} {c_wrapper_0_ac_an_st_data[27]} {c_wrapper_0_ac_an_st_data[26]} {c_wrapper_0_ac_an_st_data[25]} {c_wrapper_0_ac_an_st_data[24]} {c_wrapper_0_ac_an_st_data[23]} {c_wrapper_0_ac_an_st_data[22]} {c_wrapper_0_ac_an_st_data[21]} {c_wrapper_0_ac_an_st_data[20]} {c_wrapper_0_ac_an_st_data[19]} {c_wrapper_0_ac_an_st_data[18]} {c_wrapper_0_ac_an_st_data[17]} {c_wrapper_0_ac_an_st_data[16]} {c_wrapper_0_ac_an_st_data[15]} {c_wrapper_0_ac_an_st_data[14]} {c_wrapper_0_ac_an_st_data[13]} {c_wrapper_0_ac_an_st_data[12]} {c_wrapper_0_ac_an_st_data[11]} {c_wrapper_0_ac_an_st_data[10]} {c_wrapper_0_ac_an_st_data[9]} {c_wrapper_0_ac_an_st_data[8]} {c_wrapper_0_ac_an_st_data[7]} {c_wrapper_0_ac_an_st_data[6]} {c_wrapper_0_ac_an_st_data[5]} {c_wrapper_0_ac_an_st_data[4]} {c_wrapper_0_ac_an_st_data[3]} {c_wrapper_0_ac_an_st_data[2]} {c_wrapper_0_ac_an_st_data[1]} {c_wrapper_0_ac_an_st_data[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] +set_property port_width 6 [get_debug_ports u_ila_0/probe4] +connect_debug_port u_ila_0/probe4 [get_nets [list {c_wrapper_0_ac_an_req_ttype[5]} {c_wrapper_0_ac_an_req_ttype[4]} {c_wrapper_0_ac_an_req_ttype[3]} {c_wrapper_0_ac_an_req_ttype[2]} {c_wrapper_0_ac_an_req_ttype[1]} {c_wrapper_0_ac_an_req_ttype[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] +set_property port_width 1 [get_debug_ports u_ila_0/probe5] +connect_debug_port u_ila_0/probe5 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/icd_icm_addr_real[51]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6] +set_property port_width 4 [get_debug_ports u_ila_0/probe6] +connect_debug_port u_ila_0/probe6 [get_nets [list {a2l2_axi_0/inst/ldq_count_q_reg[3]} {a2l2_axi_0/inst/ldq_count_q_reg[2]} {a2l2_axi_0/inst/ldq_count_q_reg[1]} {a2l2_axi_0/inst/ldq_count_q_reg[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7] +set_property port_width 22 [get_debug_ports u_ila_0/probe7] +connect_debug_port u_ila_0/probe7 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbl_q[32]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8] +set_property port_width 32 [get_debug_ports u_ila_0/probe8] +connect_debug_port u_ila_0/probe8 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[63]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[62]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[61]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[60]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[59]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[58]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[57]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[56]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[55]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[54]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[53]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[52]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[51]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[50]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[49]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[48]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[47]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[46]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[45]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[44]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[43]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[42]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[41]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[40]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[39]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[38]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[37]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[36]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[35]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[34]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[33]} {c_wrapper_0/inst/c0/xu0/spr/xu_spr_cspr/tbu_q[32]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] +set_property port_width 32 [get_debug_ports u_ila_0/probe9] +connect_debug_port u_ila_0/probe9 [get_nets [list {c_wrapper_0_ac_an_req_ra[63]} {c_wrapper_0_ac_an_req_ra[62]} {c_wrapper_0_ac_an_req_ra[61]} {c_wrapper_0_ac_an_req_ra[60]} {c_wrapper_0_ac_an_req_ra[59]} {c_wrapper_0_ac_an_req_ra[58]} {c_wrapper_0_ac_an_req_ra[57]} {c_wrapper_0_ac_an_req_ra[56]} {c_wrapper_0_ac_an_req_ra[55]} {c_wrapper_0_ac_an_req_ra[54]} {c_wrapper_0_ac_an_req_ra[53]} {c_wrapper_0_ac_an_req_ra[52]} {c_wrapper_0_ac_an_req_ra[51]} {c_wrapper_0_ac_an_req_ra[50]} {c_wrapper_0_ac_an_req_ra[49]} {c_wrapper_0_ac_an_req_ra[48]} {c_wrapper_0_ac_an_req_ra[47]} {c_wrapper_0_ac_an_req_ra[46]} {c_wrapper_0_ac_an_req_ra[45]} {c_wrapper_0_ac_an_req_ra[44]} {c_wrapper_0_ac_an_req_ra[43]} {c_wrapper_0_ac_an_req_ra[42]} {c_wrapper_0_ac_an_req_ra[41]} {c_wrapper_0_ac_an_req_ra[40]} {c_wrapper_0_ac_an_req_ra[39]} {c_wrapper_0_ac_an_req_ra[38]} {c_wrapper_0_ac_an_req_ra[37]} {c_wrapper_0_ac_an_req_ra[36]} {c_wrapper_0_ac_an_req_ra[35]} {c_wrapper_0_ac_an_req_ra[34]} {c_wrapper_0_ac_an_req_ra[33]} {c_wrapper_0_ac_an_req_ra[32]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] +set_property port_width 3 [get_debug_ports u_ila_0/probe10] +connect_debug_port u_ila_0/probe10 [get_nets [list {c_wrapper_0_ac_an_req_ld_xfr_len[2]} {c_wrapper_0_ac_an_req_ld_xfr_len[1]} {c_wrapper_0_ac_an_req_ld_xfr_len[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] +set_property port_width 62 [get_debug_ports u_ila_0/probe11] +connect_debug_port u_ila_0/probe11 [get_nets [list {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[61]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[60]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[59]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[58]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[57]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[56]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[55]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[54]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[53]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[52]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[51]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[50]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[49]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[48]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[47]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[46]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[45]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[44]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[43]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[42]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[41]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[40]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[39]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[38]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[37]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[36]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[35]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[34]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[33]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[32]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[31]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[30]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[29]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[28]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[27]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[26]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[25]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[24]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[23]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[22]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[21]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[20]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[19]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[18]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[17]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[16]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[15]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[14]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[13]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[12]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[11]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[10]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[9]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[8]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[7]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[6]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[5]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[4]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[3]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[2]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[1]} {c_wrapper_0/inst/c0/xu0/spr/threads.thread[0].xu_spr_tspr/iu_nia_q[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] +set_property port_width 5 [get_debug_ports u_ila_0/probe12] +connect_debug_port u_ila_0/probe12 [get_nets [list {c_wrapper_0_ac_an_req_ld_core_tag[4]} {c_wrapper_0_ac_an_req_ld_core_tag[3]} {c_wrapper_0_ac_an_req_ld_core_tag[2]} {c_wrapper_0_ac_an_req_ld_core_tag[1]} {c_wrapper_0_ac_an_req_ld_core_tag[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13] +set_property port_width 58 [get_debug_ports u_ila_0/probe13] +connect_debug_port u_ila_0/probe13 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[29]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[28]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[27]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[26]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[25]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[24]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[23]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[22]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[21]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[20]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[19]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[18]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[17]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[16]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[15]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[14]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[13]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[12]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[11]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[10]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[9]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[8]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[7]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[6]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[5]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[4]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[3]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[2]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[1]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_ctrl/cp4_exc_nia_q[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14] +set_property port_width 32 [get_debug_ports u_ila_0/probe14] +connect_debug_port u_ila_0/probe14 [get_nets [list {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[30]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[31]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[32]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[33]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[34]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[35]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[36]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[37]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[38]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[39]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[40]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[41]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[42]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[43]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[44]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[45]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[46]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[47]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[48]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[49]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[50]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[51]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[52]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[53]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[54]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[55]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[56]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[57]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[58]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[59]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[60]} {c_wrapper_0/inst/c0/iuq0/iuq_cpl_top0/iuq_cpl0/cp2_nia4[61]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15] +set_property port_width 6 [get_debug_ports u_ila_0/probe15] +connect_debug_port u_ila_0/probe15 [get_nets [list {a2l2_axi_0/inst/stq_count_q_reg[5]} {a2l2_axi_0/inst/stq_count_q_reg[4]} {a2l2_axi_0/inst/stq_count_q_reg[3]} {a2l2_axi_0/inst/stq_count_q_reg[2]} {a2l2_axi_0/inst/stq_count_q_reg[1]} {a2l2_axi_0/inst/stq_count_q_reg[0]}]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16] +set_property port_width 1 [get_debug_ports u_ila_0/probe16] +connect_debug_port u_ila_0/probe16 [get_nets [list a2l2_axi_0_an_ac_reld_crit_qw]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] +set_property port_width 1 [get_debug_ports u_ila_0/probe17] +connect_debug_port u_ila_0/probe17 [get_nets [list a2l2_axi_0_an_ac_reld_data_vld]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] +set_property port_width 1 [get_debug_ports u_ila_0/probe18] +connect_debug_port u_ila_0/probe18 [get_nets [list a2l2_axi_0_an_ac_req_ld_pop]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] +set_property port_width 1 [get_debug_ports u_ila_0/probe19] +connect_debug_port u_ila_0/probe19 [get_nets [list a2l2_axi_0_an_ac_req_st_pop]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] +set_property port_width 1 [get_debug_ports u_ila_0/probe20] +connect_debug_port u_ila_0/probe20 [get_nets [list c_wrapper_0_ac_an_req]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] +set_property port_width 1 [get_debug_ports u_ila_0/probe21] +connect_debug_port u_ila_0/probe21 [get_nets [list c_wrapper_0_ac_an_req_wimg_i]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] +set_property port_width 1 [get_debug_ports u_ila_0/probe22] +connect_debug_port u_ila_0/probe22 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/icd_icm_miss]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] +set_property port_width 1 [get_debug_ports u_ila_0/probe23] +connect_debug_port u_ila_0/probe23 [get_nets [list c_wrapper_0/inst/c0/iuq0/iuq_ifetch0/iuq_ic0/ics_icd_iu1_flush]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] +set_property port_width 1 [get_debug_ports u_ila_0/probe24] +connect_debug_port u_ila_0/probe24 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_enable_q]] +create_debug_port u_ila_0 probe +set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25] +set_property port_width 1 [get_debug_ports u_ila_0/probe25] +connect_debug_port u_ila_0/probe25 [get_nets [list c_wrapper_0/inst/c0/spr/xu_spr_cspr/tb_update_pulse_q]] +set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] +set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] +set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] +connect_debug_port dbg_hub/clk [get_nets clk_wiz_0_clk] diff --git a/rel/build/bd/xdc/main_pinout.xdc b/rel/build/bd/xdc/main_pinout.xdc new file mode 100644 index 0000000..ea2bca0 --- /dev/null +++ b/rel/build/bd/xdc/main_pinout.xdc @@ -0,0 +1,5 @@ +set_property IOSTANDARD LVDS [get_ports clk_in1_n_0] +set_property PACKAGE_PIN AP26 [get_ports clk_in1_p_0] +set_property PACKAGE_PIN AP27 [get_ports clk_in1_n_0] +set_property IOSTANDARD LVDS [get_ports clk_in1_p_0] + diff --git a/rel/build/bd/xdc/main_spi.xdc b/rel/build/bd/xdc/main_spi.xdc new file mode 100644 index 0000000..3583cc0 --- /dev/null +++ b/rel/build/bd/xdc/main_spi.xdc @@ -0,0 +1,14 @@ +## Settings to generate MSC file +# Configuration from SPI Flash as per XAPP1233 +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DIV-1 [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +# Set CFGBVS to GND to match schematics +set_property CFGBVS GND [current_design] +# Set CONFIG_VOLTAGE to 1.8V to match schematics +set_property CONFIG_VOLTAGE 1.8 [current_design] +# Set safety trigger to power down FPGA at 125degC +set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design] + diff --git a/rel/build/bd/xdc/main_timing.xdc b/rel/build/bd/xdc/main_timing.xdc new file mode 100644 index 0000000..33195e2 --- /dev/null +++ b/rel/build/bd/xdc/main_timing.xdc @@ -0,0 +1,4 @@ +create_generated_clock -name clk [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0] +create_generated_clock -name clk2x [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT1] +create_generated_clock -name clk4x [get_pins clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT2] + diff --git a/rel/build/ip_user/a2l2_axi/readme.md b/rel/build/ip_user/a2l2_axi/readme.md new file mode 100644 index 0000000..af84ae2 --- /dev/null +++ b/rel/build/ip_user/a2l2_axi/readme.md @@ -0,0 +1,8 @@ +# create IP: a2l2_axi + +``` +$VIVADO -mode tcl -source tcl/create_ip_a2l2_axi.tcl +rm -r ../../ip_repo/a2l2_axi +cp -r a2l2_axi ../../ip_repo +``` + diff --git a/rel/build/ip_user/a2l2_axi/tcl b/rel/build/ip_user/a2l2_axi/tcl new file mode 120000 index 0000000..f528630 --- /dev/null +++ b/rel/build/ip_user/a2l2_axi/tcl @@ -0,0 +1 @@ +../../tcl \ No newline at end of file diff --git a/rel/build/ip_user/a2l2_axi/verilog b/rel/build/ip_user/a2l2_axi/verilog new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2l2_axi/verilog @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2l2_axi/vhdl b/rel/build/ip_user/a2l2_axi/vhdl new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2l2_axi/vhdl @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2o_axi_reg/readme.md b/rel/build/ip_user/a2o_axi_reg/readme.md new file mode 100644 index 0000000..79c25ff --- /dev/null +++ b/rel/build/ip_user/a2o_axi_reg/readme.md @@ -0,0 +1,8 @@ +# create IP: a2o_axi_reg + +``` +$VIVADO -mode tcl -source tcl/create_ip_a2o_axi_reg.tcl +rm -r ../../ip_repo/a2o_axi_reg +cp -r a2o_axi_reg ../../ip_repo +``` + diff --git a/rel/build/ip_user/a2o_axi_reg/tcl b/rel/build/ip_user/a2o_axi_reg/tcl new file mode 120000 index 0000000..f528630 --- /dev/null +++ b/rel/build/ip_user/a2o_axi_reg/tcl @@ -0,0 +1 @@ +../../tcl \ No newline at end of file diff --git a/rel/build/ip_user/a2o_axi_reg/verilog b/rel/build/ip_user/a2o_axi_reg/verilog new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2o_axi_reg/verilog @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2o_axi_reg/vhdl b/rel/build/ip_user/a2o_axi_reg/vhdl new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2o_axi_reg/vhdl @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2o_core/readme.md b/rel/build/ip_user/a2o_core/readme.md new file mode 100644 index 0000000..406028a --- /dev/null +++ b/rel/build/ip_user/a2o_core/readme.md @@ -0,0 +1,8 @@ +# create IP: a2o_core + +``` +$VIVADO -mode tcl -source tcl/create_ip_a2o_core.tcl +rm -r ../../ip_repo/c_wrapper +cp -r c_wrapper ../../ip_repo +``` + diff --git a/rel/build/ip_user/a2o_core/tcl b/rel/build/ip_user/a2o_core/tcl new file mode 120000 index 0000000..f528630 --- /dev/null +++ b/rel/build/ip_user/a2o_core/tcl @@ -0,0 +1 @@ +../../tcl \ No newline at end of file diff --git a/rel/build/ip_user/a2o_core/verilog b/rel/build/ip_user/a2o_core/verilog new file mode 120000 index 0000000..4c6f6b3 --- /dev/null +++ b/rel/build/ip_user/a2o_core/verilog @@ -0,0 +1 @@ +../../../src/verilog \ No newline at end of file diff --git a/rel/build/ip_user/a2o_core/vhdl b/rel/build/ip_user/a2o_core/vhdl new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2o_core/vhdl @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2o_dbug/readme.md b/rel/build/ip_user/a2o_dbug/readme.md new file mode 100644 index 0000000..af8dfbe --- /dev/null +++ b/rel/build/ip_user/a2o_dbug/readme.md @@ -0,0 +1,8 @@ +# create IP: a2o_dbug + +``` +$VIVADO -mode tcl -source tcl/create_ip_a2o_dbug.tcl +rm -r ../../ip_repo/a2o_dbug +cp -r a2o_dbug ../../ip_repo +``` + diff --git a/rel/build/ip_user/a2o_dbug/tcl b/rel/build/ip_user/a2o_dbug/tcl new file mode 120000 index 0000000..f528630 --- /dev/null +++ b/rel/build/ip_user/a2o_dbug/tcl @@ -0,0 +1 @@ +../../tcl \ No newline at end of file diff --git a/rel/build/ip_user/a2o_dbug/verilog b/rel/build/ip_user/a2o_dbug/verilog new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2o_dbug/verilog @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/a2o_dbug/vhdl b/rel/build/ip_user/a2o_dbug/vhdl new file mode 120000 index 0000000..655de1a --- /dev/null +++ b/rel/build/ip_user/a2o_dbug/vhdl @@ -0,0 +1 @@ +../../../src/vhdl \ No newline at end of file diff --git a/rel/build/ip_user/reverserator_3/create_ip.tcl b/rel/build/ip_user/reverserator_3/create_ip.tcl new file mode 100644 index 0000000..6a510e8 --- /dev/null +++ b/rel/build/ip_user/reverserator_3/create_ip.tcl @@ -0,0 +1,62 @@ +# ip creator + +set project reverserator_3 ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/ip_user/reverserator_3/readme.md b/rel/build/ip_user/reverserator_3/readme.md new file mode 100644 index 0000000..5b0ec32 --- /dev/null +++ b/rel/build/ip_user/reverserator_3/readme.md @@ -0,0 +1,8 @@ +# create IP: reverserator_3 + +``` +$VIVADO -mode tcl -source ./create_ip.tcl +rm -r ../../ip_repo/reverserator_3 +cp -r reverserator_3 ../../ip_repo +``` + diff --git a/rel/build/ip_user/reverserator_3/vhdl/reverserator_3.vhdl b/rel/build/ip_user/reverserator_3/vhdl/reverserator_3.vhdl new file mode 100644 index 0000000..50021a4 --- /dev/null +++ b/rel/build/ip_user/reverserator_3/vhdl/reverserator_3.vhdl @@ -0,0 +1,48 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- terminate yet another rare xil bug + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity reverserator_3 is + port ( + outdoor : in std_logic_vector(0 to 2); + inndoor : out std_logic_vector(2 downto 0) + ); +end reverserator_3; + +architecture reverserator_3 of reverserator_3 is +begin + + inndoor <= outdoor; + +end reverserator_3; + diff --git a/rel/build/ip_user/reverserator_4/create_ip.tcl b/rel/build/ip_user/reverserator_4/create_ip.tcl new file mode 100644 index 0000000..c61e6cd --- /dev/null +++ b/rel/build/ip_user/reverserator_4/create_ip.tcl @@ -0,0 +1,62 @@ +# ip creator + +set project reverserator_4 ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/ip_user/reverserator_4/readme.md b/rel/build/ip_user/reverserator_4/readme.md new file mode 100644 index 0000000..ba5e735 --- /dev/null +++ b/rel/build/ip_user/reverserator_4/readme.md @@ -0,0 +1,8 @@ +# create IP: reverserator_4 + +``` +$VIVADO -mode tcl -source ./create_ip.tcl +rm -r ../../ip_repo/reverserator_4 +cp -r reverserator_4 ../../ip_repo +``` + diff --git a/rel/build/ip_user/reverserator_4/vhdl/reverserator_4.vhdl b/rel/build/ip_user/reverserator_4/vhdl/reverserator_4.vhdl new file mode 100644 index 0000000..8362b74 --- /dev/null +++ b/rel/build/ip_user/reverserator_4/vhdl/reverserator_4.vhdl @@ -0,0 +1,48 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- terminate yet another rare xil bug + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity reverserator_4 is + port ( + innnie : in std_logic_vector(0 to 3); + outtie : out std_logic_vector(3 downto 0) + ); +end reverserator_4; + +architecture reverserator_4 of reverserator_4 is +begin + + outtie <= innnie; + +end reverserator_4; + diff --git a/rel/build/ip_user/reverserator_64/create_ip.tcl b/rel/build/ip_user/reverserator_64/create_ip.tcl new file mode 100644 index 0000000..357da11 --- /dev/null +++ b/rel/build/ip_user/reverserator_64/create_ip.tcl @@ -0,0 +1,62 @@ +# ip creator + +set project reverserator_64 ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $output_dir/$project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2x_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc + diff --git a/rel/build/ip_user/reverserator_64/readme.md b/rel/build/ip_user/reverserator_64/readme.md new file mode 100644 index 0000000..bfa6797 --- /dev/null +++ b/rel/build/ip_user/reverserator_64/readme.md @@ -0,0 +1,8 @@ +# create IP: reverserator_64 + +``` +$VIVADO -mode tcl -source ./create_ip.tcl +rm -r ../../ip_repo/reverserator_64 +cp -r reverserator_64 ../../ip_repo +``` + diff --git a/rel/build/ip_user/reverserator_64/vhdl/reverserator_64.vhdl b/rel/build/ip_user/reverserator_64/vhdl/reverserator_64.vhdl new file mode 100644 index 0000000..a1370f5 --- /dev/null +++ b/rel/build/ip_user/reverserator_64/vhdl/reverserator_64.vhdl @@ -0,0 +1,48 @@ +-- © IBM Corp. 2020 +-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by +-- the terms below; you may not use the files in this repository except in +-- compliance with the License as modified. +-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Modified Terms: +-- +-- 1) For the purpose of the patent license granted to you in Section 3 of the +-- License, the "Work" hereby includes implementations of the work of authorship +-- in physical form. +-- +-- 2) Notwithstanding any terms to the contrary in the License, any licenses +-- necessary for implementation of the Work that are available from OpenPOWER +-- via the Power ISA End User License Agreement (EULA) are explicitly excluded +-- hereunder, and may be obtained from OpenPOWER under the terms and conditions +-- of the EULA. +-- +-- Unless required by applicable law or agreed to in writing, the reference design +-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +-- for the specific language governing permissions and limitations under the License. +-- +-- Additional rights, including the ability to physically implement a softcore that +-- is compliant with the required sections of the Power ISA Specification, are +-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +-- obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +-- terminate yet another rare xil bug + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity reverserator_64 is + port ( + parkavenue : in std_logic_vector(0 to 63); + skidrowwww : out std_logic_vector(63 downto 0) + ); +end reverserator_64; + +architecture reverserator_64 of reverserator_64 is +begin + + skidrowwww <= parkavenue; + +end reverserator_64; + diff --git a/rel/build/tcl/create_ip_a2l2_axi.tcl b/rel/build/tcl/create_ip_a2l2_axi.tcl new file mode 100644 index 0000000..0c0d35d --- /dev/null +++ b/rel/build/tcl/create_ip_a2l2_axi.tcl @@ -0,0 +1,69 @@ +# ip creator + +set project a2l2_axi ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 +set vhdl2008 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + set_property library work [get_files $vhdl_dir/*] + + if {$vhdl2008} { + set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*] + } + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc $vhdl2008 + diff --git a/rel/build/tcl/create_ip_a2o_axi_reg.tcl b/rel/build/tcl/create_ip_a2o_axi_reg.tcl new file mode 100644 index 0000000..17735cd --- /dev/null +++ b/rel/build/tcl/create_ip_a2o_axi_reg.tcl @@ -0,0 +1,69 @@ +# ip creator + +set project a2o_axi_reg ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 +set vhdl2008 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + set_property library work [get_files $vhdl_dir/*] + + if {$vhdl2008} { + set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*] + } + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc $vhdl2008 + diff --git a/rel/build/tcl/create_ip_a2o_core.tcl b/rel/build/tcl/create_ip_a2o_core.tcl new file mode 100644 index 0000000..84edb41 --- /dev/null +++ b/rel/build/tcl/create_ip_a2o_core.tcl @@ -0,0 +1,61 @@ +# ip creator + +set project c_wrapper ;# also top +set rev "1" +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {rev 0.1} } { + + set verilog_dir [file normalize ./verilog] + set output_dir . + set project_dir ./prj + + create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $verilog_dir/trilib + add_files -norecurse $verilog_dir/work + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VERILOG [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language MIXED [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name a2o_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision $rev [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc $rev diff --git a/rel/build/tcl/create_ip_a2o_dbug.tcl b/rel/build/tcl/create_ip_a2o_dbug.tcl new file mode 100644 index 0000000..a9b81f1 --- /dev/null +++ b/rel/build/tcl/create_ip_a2o_dbug.tcl @@ -0,0 +1,69 @@ +# ip creator + +set project a2o_dbug ;# also top +set keep 0 ;# keep project +set xdc "" ;# set to xdc file if exists +set synth_check 1 +set vhdl2008 1 + +proc create_ip {project {keep_project 0} {synth_check 1} {xdc ""} {vhdl2008 1}} { + + set vhdl_dir [file normalize ./vhdl] + set output_dir . + set project_dir ./prj + + create_project -force $project $project_dir -part xcvu3p-ffvc1517-2-e + + add_files -norecurse $vhdl_dir + + set_property library work [get_files $vhdl_dir/*] + + if {$vhdl2008} { + set_property FILE_TYPE {VHDL 2008} [get_files $vhdl_dir/*] + } + + update_compile_order -fileset sources_1 + + set_property top $project [current_fileset] + set_property target_language VHDL [current_project] + set_property default_lib work [current_project] + set_property top $project [get_filesets sim_1] + set_property -name {xsim.compile.xvhdl.nosort} -value {false} -objects [get_filesets sim_1] + set_property -name {xsim.compile.xvlog.nosort} -value {false} -objects [get_filesets sim_1] + set_property simulator_language VHDL [current_project] + + if {$xdc != ""} { + set xdc_dir [file normalize ./xdc] + read_xdc $xdc_dir/$xdc + } + + update_compile_order -fileset sources_1 + + if {$synth_check} { + synth_design -rtl -name elab_for_sanity_check + } + + ipx::package_project -root_dir $output_dir/$project -vendor user.org -library user -taxonomy /UserIP -import_files -set_current false + ipx::unload_core $output_dir/$project/component.xml + ipx::edit_ip_in_project -upgrade true -name ${project}_edit_project -directory $output_dir/$project $output_dir/$project/component.xml + update_compile_order -fileset sources_1 + set_property core_revision 2 [ipx::current_core] + ipx::update_source_project_archive -component [ipx::current_core] + ipx::create_xgui_files [ipx::current_core] + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] + ipx::move_temp_component_back -component [ipx::current_core] + + if {$keep_project} { + close_project + puts "Project built; project dir saved: [file normalize $output_dir/$project_dir]" + } else { + close_project -delete + exec rm -rf $output_dir/$project_dir + puts "Project built; only IP files kept." + } + +} + +create_ip $project $keep $synth_check $xdc $vhdl2008 + diff --git a/rel/fpga/init.tcl b/rel/fpga/init.tcl new file mode 100644 index 0000000..38ebe3b --- /dev/null +++ b/rel/fpga/init.tcl @@ -0,0 +1,14 @@ +# init.tcl +# + +set TCL [file dirname [info script]] + +proc include {f} { + global TCL + source -notrace [file join $TCL $f] +} + +include "utils.tcl" +include "waimea.tcl" + + diff --git a/rel/fpga/utils.tcl b/rel/fpga/utils.tcl new file mode 100644 index 0000000..0b2b774 --- /dev/null +++ b/rel/fpga/utils.tcl @@ -0,0 +1,26 @@ +# utils.tcl +# + +proc timestamp {{t ""}} { + if {$t == ""} { + set t [clock seconds] + } + return [clock format $t -format %y%m%d%H%M%S] +} + +proc datetime {{t ""}} { + if {$t == ""} { + set t [clock seconds] + } + return [clock format $t -format "%m-%d-%y %I:%M:%S %p %Z"] +} + +proc now {} { + return [clock seconds] +} + +proc vivado_year {} { + regexp -- {Vivado v(\d\d\d\d)\.*} [version] s year + return $year +} + diff --git a/rel/fpga/waimea.tcl b/rel/fpga/waimea.tcl new file mode 100644 index 0000000..58b9edc --- /dev/null +++ b/rel/fpga/waimea.tcl @@ -0,0 +1,179 @@ +# waimea board/core command interface + + +#################################################################### +# system commands + +set version 1 ;#coremark_1 + +proc reset {} { +global version + + if {$version == 1} { + set filter "CELL_NAME=~\"*vio*\"" + set probe "vio_0_probe_out1" + } else { + set filter "CELL_NAME=~\"*marvio*\"" + set probe "vio_0_probe_out1" + } + + set obj_vio [get_hw_vios -of_objects [get_hw_devices xcvu3p_0] -filter $filter] + set rst [get_hw_probes a2x_axi_bd_i/vio_0_probe_out1 -of_objects $obj_vio] + startgroup + set_property OUTPUT_VALUE 0 $rst + commit_hw_vio $rst + endgroup + startgroup + set_property OUTPUT_VALUE 1 $rst + commit_hw_vio $rst + endgroup + puts "[datetime] Reset" +} + +proc threadstop {{val F}} { +global version + + if {$version == 1} { + set filter "CELL_NAME=~\"*vio*\"" + set probe "vio_0_probe_out0" + } else { + set filter "CELL_NAME=~\"*marvio*\"" + set probe "marvio_probe_out0" + } + + set obj_vio [get_hw_vios -of_objects [get_hw_devices xcvu3p_0] -filter $filter] + set thread_stop [get_hw_probes a2x_axi_bd_i/$probe -of_objects $obj_vio] + set_property OUTPUT_VALUE $val $thread_stop + commit_hw_vio $thread_stop + puts "[datetime] ThreadStop=$val" +} + +#################################################################### +# ila commands + +proc ila_arm {{n 0}} { + set filter "CELL_NAME=~\"u_ila_$n\"" + set res [run_hw_ila [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]] + puts "[datetime] ILA$n armed." +} + +proc ila_wait {{n 0}} { + set filter "CELL_NAME=~\"u_ila_$n\"" + puts "[datetime] ILA$n waiting..." + set res [wait_on_hw_ila [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]] + display_hw_ila_data [upload_hw_ila_data [get_hw_ilas -of_objects [get_hw_devices xcvu3p_0] -filter $filter]] + puts "[datetime] ILA$n triggered." +} + +#################################################################### +# axi slave commands + +proc raxi {addr {len 8} {dev 0} {width 8}} { + + if {$dev == 0} { + set dev [get_hw_axis hw_axi_1] + } + + create_hw_axi_txn -f raxi_txn $dev -address $addr -len $len -type read + run_hw_axi -quiet raxi_txn + set res [report_hw_axi_txn -w $width raxi_txn] + return $res + +} + +proc waxi {addr data {len 8} {dev 0}} { + + if {$dev == 0} { + set dev [get_hw_axis hw_axi_1] + } + + create_hw_axi_txn -f waxi_txn $dev -address $addr -len $len -type write -data $data + run_hw_axi -quiet waxi_txn + set res [report_hw_axi_txn waxi_txn] + return $res + +} + +proc waxiq {addr data {len 8} {dev 0}} { + + set res [waxi $addr $data $len $dev] + +} + + +proc testwrites {addr xfers} { + + set start [datetime] + for {set i 0} {$i < $xfers} {incr i} { + waxi $addr 00000000_11111111_22222222_33333333_44444444_55555555_66666666_77777777 + } + set end [datetime] + + puts "Finished $xfers 32B writes." + puts "Start: $start" + puts " End: $end" + +} + +proc testwrites_128B {addr xfers} { + + set start [datetime] + for {set i 0} {$i < $xfers} {incr i} { + waxi $addr { + 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 + 00000008 00000009 0000000A 0000000B 0000000C 0000000D 0000000E 0000000F + 00000010 00000011 00000012 00000013 00000014 00000015 00000006 00000017 + 00000018 00000019 0000001A 0000001B 0000001C 0000001D 0000000E 0000001F + } 32 + } + set end [datetime] + + puts "Finished $xfers 122B writes." + puts "Start: $start" + puts " End: $end" + +} + +proc map {lambda list} { + set res {} + foreach i $list { + lappend res [apply $lambda $i] + } + return $res +} + +proc bytereverse {x} { + set res "" + for {set i 0} {$i < [string length $x]} {incr i 2} { + set res "[string range $x $i [expr $i+1]]$res" + } + return $res +} + +proc ascii {start {len 32} {dev 0}} { + set w 128 + set res "" + set count [expr ($len-1)/$w + 1] + set ptr $start + + for {set i 0} {$i < $count} {incr i} { + + set mem [raxi $ptr [expr $w/4] $dev $w] + set ptr [format %x [expr [expr 0x$ptr] + $w]] + + # split and remove addr + set tokens [regexp -all -inline {\S+} $mem] + set tokens [lrange $tokens 1 end] + + # bytereverse and ascii + set tokens [map {x {return [bytereverse $x]}} $tokens] + set bytes [join $tokens {}] + set chars [binary format H* $bytes] + + set res "$res$chars" + + } + return $res +} + + diff --git a/rel/src/verilog/trilib/tri.vh b/rel/src/verilog/trilib/tri.vh new file mode 100644 index 0000000..893ad12 --- /dev/null +++ b/rel/src/verilog/trilib/tri.vh @@ -0,0 +1,43 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// *!**************************************************************** +// *! FILENAME : tri_a2o.param +// *! DESCRIPTION : Constants for use throughout core +// *! CONTENTS : +// *! +// *!**************************************************************** + +`ifndef _tri_vh_ +`define _tri_vh_ + +`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk +//`define EXPAND_TYPE 1 + +// Do NOT add any defines below this line +`endif //_tri_vh_ diff --git a/rel/src/verilog/trilib/tri_128x168_1w_0.v b/rel/src/verilog/trilib/tri_128x168_1w_0.v new file mode 100644 index 0000000..a81df61 --- /dev/null +++ b/rel/src/verilog/trilib/tri_128x168_1w_0.v @@ -0,0 +1,258 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_128x168_1w_0.v +// *! DESCRIPTION : 128 Entry x 168 bit x 1 way array +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_128x168_1w_0( + gnd, + vdd, + vcs, + nclk, + act, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + abst_scan_in, + repr_scan_in, + time_scan_in, + abst_scan_out, + repr_scan_out, + time_scan_out, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_act_dis_dc, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + lcb_sg_1, + lcb_time_sg_0, + lcb_repr_sg_0, + lcb_abst_sl_thold_0, + lcb_repr_sl_thold_0, + lcb_time_sl_thold_0, + lcb_ary_nsl_thold_0, + lcb_bolt_sl_thold_0, + tc_lbist_ary_wrt_thru_dc, + abist_en_1, + din_abist, + abist_cmp_en, + abist_raw_b_dc, + data_cmp_abist, + addr_abist, + r_wb_abist, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + write_enable, + addr, + data_in, + data_out +); + parameter addressable_ports = 128; // number of addressable register in this array + parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 168; // bitwidth of ports + parameter ways = 1; // number of ways + + // POWER PINS + inout gnd; + inout vdd; + inout vcs; + + // CLOCK and CLOCKCONTROL ports + input [0:`NCLK_WIDTH-1] nclk; + input act; + input ccflush_dc; + input scan_dis_dc_b; + input scan_diag_dc; + + input abst_scan_in; + input repr_scan_in; + input time_scan_in; + output abst_scan_out; + output repr_scan_out; + output time_scan_out; + + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input lcb_act_dis_dc; + input [0:4] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:4] lcb_delay_lclkr_dc; + + input lcb_sg_1; + input lcb_time_sg_0; + input lcb_repr_sg_0; + + input lcb_abst_sl_thold_0; + input lcb_repr_sl_thold_0; + input lcb_time_sl_thold_0; + input lcb_ary_nsl_thold_0; + input lcb_bolt_sl_thold_0; // thold for any regs inside backend + + input tc_lbist_ary_wrt_thru_dc; + input abist_en_1; + input [0:3] din_abist; + input abist_cmp_en; + input abist_raw_b_dc; + input [0:3] data_cmp_abist; + input [0:6] addr_abist; + input r_wb_abist; + + // BOLT-ON + input pc_bo_enable_2; // general bolt-on enable, probably DC + input pc_bo_reset; // execute sticky bit decode + input pc_bo_unload; + input pc_bo_repair; // load repair reg + input pc_bo_shdata; // shift data for timing write + input pc_bo_select; // select for mask and hier writes + output bo_pc_failout; // fail/no-fix reg + output bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + + // PORTS + input write_enable; + input [0:addressbus_width-1] addr; + input [0:port_bitwidth-1] data_in; + output [0:port_bitwidth-1] data_out; + + // tri_128x168_1w_0 + + parameter ramb_base_width = 36; + parameter ramb_base_addr = 9; + parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way + + + // Configuration Statement for NCsim + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in; + wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1]; + wire [0:ramb_base_addr-1] ramb_addr; + + wire [0:ways-1] write; + wire tidn; + (* analysis_not_referenced="true" *) + wire unused; + wire [0:(ramb_base_width*ramb_width_mult-1)] unused_dob; + + + generate + begin + assign tidn = 1'b0; + + if (addressbus_width < ramb_base_addr) + begin + assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}}; + assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr; + end + if (addressbus_width >= ramb_base_addr) + begin + assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1]; + end + + genvar i; + for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1) + begin : din + if (i < port_bitwidth) + begin + assign ramb_data_in[i] = data_in[i]; + end + if (i >= port_bitwidth) + begin + assign ramb_data_in[i] = 1'b0; + end + end + + genvar w; + for (w = 0; w < ways; w = w + 1) + begin : aw + assign write[w] = write_enable; + + genvar x; + for (x = 0; x < ramb_width_mult; x = x + 1) + begin : ax + + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + ram( + .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DOB(unused_dob[x * ramb_base_width:x * ramb_base_width + 31]), + .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .ADDRA(ramb_addr), + .ADDRB(ramb_addr), + .CLKA(nclk[0]), + .CLKB(tidn), + .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), + .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), + .DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .ENA(act), + .ENB(tidn), + .SSRA(nclk[1]), + .SSRB(tidn), + .WEA(write[w]), + .WEB(tidn) + ); + end //ax + assign data_out[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1]; + end //aw + end + endgenerate + + assign abst_scan_out = abst_scan_in; + assign repr_scan_out = repr_scan_in; + assign time_scan_out = time_scan_in; + + assign bo_pc_failout = 1'b0; + assign bo_pc_diagloop = 1'b0; + + assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob}); +endmodule diff --git a/rel/src/verilog/trilib/tri_128x16_1r1w_1.v b/rel/src/verilog/trilib/tri_128x16_1r1w_1.v new file mode 100644 index 0000000..1890411 --- /dev/null +++ b/rel/src/verilog/trilib/tri_128x16_1r1w_1.v @@ -0,0 +1,335 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: Tri Array Wrapper +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_128x16_1r1w_1( + vdd, + vcs, + gnd, + nclk, + rd_act, + wr_act, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + func_scan_in, + func_scan_out, + lcb_sg_0, + lcb_sl_thold_0_b, + lcb_time_sl_thold_0, + lcb_abst_sl_thold_0, + lcb_ary_nsl_thold_0, + lcb_repr_sl_thold_0, + time_scan_in, + time_scan_out, + abst_scan_in, + abst_scan_out, + repr_scan_in, + repr_scan_out, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + wr_abst_act, + abist_rd0_adr, + rd0_abst_act, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + bw, + wr_adr, + rd_adr, + di, + do +); + parameter addressable_ports = 128; // number of addressable register in this array + parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 16; // bitwidth of ports + parameter ways = 1; // number of ways + + // POWER PINS + inout vdd; + inout vcs; + inout gnd; + + input [0:`NCLK_WIDTH-1] nclk; + + input rd_act; + input wr_act; + + // DC TEST PINS + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input [0:4] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:4] lcb_delay_lclkr_dc; + + input ccflush_dc; + input scan_dis_dc_b; + input scan_diag_dc; + input func_scan_in; + output func_scan_out; + + input lcb_sg_0; + input lcb_sl_thold_0_b; + input lcb_time_sl_thold_0; + input lcb_abst_sl_thold_0; + input lcb_ary_nsl_thold_0; + input lcb_repr_sl_thold_0; + input time_scan_in; + output time_scan_out; + input abst_scan_in; + output abst_scan_out; + input repr_scan_in; + output repr_scan_out; + + input [0:3] abist_di; + input abist_bw_odd; + input abist_bw_even; + input [0:6] abist_wr_adr; + input wr_abst_act; + input [0:6] abist_rd0_adr; + input rd0_abst_act; + input tc_lbist_ary_wrt_thru_dc; + input abist_ena_1; + input abist_g8t_rd0_comp_ena; + input abist_raw_dc_b; + input [0:3] obs0_abist_cmp; + + // BOLT-ON + input lcb_bolt_sl_thold_0; + input pc_bo_enable_2; // general bolt-on enable + input pc_bo_reset; // reset + input pc_bo_unload; // unload sticky bits + input pc_bo_repair; // execute sticky bit decode + input pc_bo_shdata; // shift data for timing write and diag loop + input pc_bo_select; // select for mask and hier writes + output bo_pc_failout; // fail/no-fix reg + output bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + + input [0:15] bw; + input [0:6] wr_adr; + input [0:6] rd_adr; + input [0:15] di; + + output [0:15] do; + + // tri_128x16_1r1w_1 + + // Configuration Statement for NCsim + //for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36; + + wire clk; + wire clk2x; + wire [0:8] b0addra; + wire [0:8] b0addrb; + wire wea; + wire web; + wire wren_a; + // Latches + reg reset_q; + reg gate_fq; + wire gate_d; + wire [0:35] r_data_out_1_d; + reg [0:35] r_data_out_1_fq; + wire [0:35] w_data_in_0; + + wire [0:35] r_data_out_0_bram; + wire [0:35] r_data_out_1_bram; + + wire toggle_d; + reg toggle_q; + wire toggle2x_d; + reg toggle2x_q; + + (* analysis_not_referenced="true" *) + wire unused; + + assign clk = nclk[0]; + assign clk2x = nclk[2]; + + + always @(posedge clk) + begin: rlatch + reset_q <= nclk[1]; + end + + // + // NEW clk2x gate logic start + // + + always @(posedge nclk[0]) + begin: tlatch + if (reset_q == 1'b1) + toggle_q <= 1'b1; + else + toggle_q <= toggle_d; + end + + + always @(posedge nclk[2]) + begin: flatch + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + r_data_out_1_fq <= r_data_out_1_d; + end + + assign toggle_d = (~toggle_q); + assign toggle2x_d = toggle_q; + + // should force gate_fq to be on during odd 2x clock (second half of 1x clock). + //gate_d <= toggle_q xor toggle2x_q; + // if you want the first half do the following + assign gate_d = (~(toggle_q ^ toggle2x_q)); + + assign b0addra[2:8] = wr_adr; + assign b0addrb[2:8] = rd_adr; + + // Unused Address Bits + assign b0addra[0:1] = 2'b00; + assign b0addrb[0:1] = 2'b00; + + // port a is a read-modify-write port + assign wren_a = ((bw != 16'b0000000000000000 & wr_act == 1'b1)) ? 1'b1 : + 1'b0; + assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk + assign web = 1'b0; + assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] : + r_data_out_0_bram[0]; + assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] : + r_data_out_0_bram[1]; + assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] : + r_data_out_0_bram[2]; + assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] : + r_data_out_0_bram[3]; + assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] : + r_data_out_0_bram[4]; + assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] : + r_data_out_0_bram[5]; + assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] : + r_data_out_0_bram[6]; + assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] : + r_data_out_0_bram[7]; + assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] : + r_data_out_0_bram[8]; + assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] : + r_data_out_0_bram[9]; + assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] : + r_data_out_0_bram[10]; + assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] : + r_data_out_0_bram[11]; + assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] : + r_data_out_0_bram[12]; + assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] : + r_data_out_0_bram[13]; + assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] : + r_data_out_0_bram[14]; + assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] : + r_data_out_0_bram[15]; + assign w_data_in_0[16:35] = {20{1'b0}}; + + assign r_data_out_1_d = r_data_out_1_bram; + + + + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram0a( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(reset_q), + .SSRB(reset_q), + .ADDRA(b0addra), + .ADDRB(b0addrb), + .DIA(w_data_in_0[0:31]), + .DIB({32{1'b0}}), + .DOA(r_data_out_0_bram[0:31]), + .DOB(r_data_out_1_bram[0:31]), + .DOPA(r_data_out_0_bram[32:35]), + .DOPB(r_data_out_1_bram[32:35]), + .DIPA(w_data_in_0[32:35]), + .DIPB(4'b0000), + .ENA(1'b1), + .ENB(1'b1), + .WEA(wea), + .WEB(web) + ); + + assign do = r_data_out_1_fq[0:15]; + + assign func_scan_out = func_scan_in; + assign time_scan_out = time_scan_in; + assign abst_scan_out = abst_scan_in; + assign repr_scan_out = repr_scan_in; + + assign bo_pc_failout = 1'b0; + assign bo_pc_diagloop = 1'b0; + + assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, + lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, + abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, + tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, + lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, + pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_bram[16:35], r_data_out_1_fq[16:35]}; +endmodule diff --git a/rel/src/verilog/trilib/tri_128x34_4w_1r1w.v b/rel/src/verilog/trilib/tri_128x34_4w_1r1w.v new file mode 100644 index 0000000..dfd3d82 --- /dev/null +++ b/rel/src/verilog/trilib/tri_128x34_4w_1r1w.v @@ -0,0 +1,324 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_128x34_4w_1r1w.v +// *! DESCRIPTION : 128 entry x 34 bit x 4 way array, +// *! 1 read & 1 write port +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_128x34_4w_1r1w( + gnd, + vdd, + vcs, + nclk, + rd_act, + wr_act, + sg_0, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + func_sl_thold_0_b, + func_force, + clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + wr_way, + wr_addr, + data_in, + rd_addr, + data_out +); + parameter addressable_ports = 128; // number of addressable register in this array + parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 34; // bitwidth of ports + parameter ways = 4; // number of ways + + // POWER PINS + inout gnd; + inout vdd; + (* analysis_not_referenced="true" *) + inout vcs; + // CLOCK and CLOCKCONTROL ports + input [0:`NCLK_WIDTH-1] nclk; + input rd_act; + input wr_act; + input sg_0; + input abst_sl_thold_0; + input ary_nsl_thold_0; + input time_sl_thold_0; + input repr_sl_thold_0; + input func_sl_thold_0_b; + input func_force; + input clkoff_dc_b; + input ccflush_dc; + input scan_dis_dc_b; + input scan_diag_dc; + input d_mode_dc; + input [0:4] mpw1_dc_b; + input mpw2_dc_b; + input [0:4] delay_lclkr_dc; + // ABIST + input wr_abst_act; + input rd0_abst_act; + input [0:3] abist_di; + input abist_bw_odd; + input abist_bw_even; + input [0:addressbus_width-1] abist_wr_adr; + input [0:addressbus_width-1] abist_rd0_adr; + input tc_lbist_ary_wrt_thru_dc; + input abist_ena_1; + input abist_g8t_rd0_comp_ena; + input abist_raw_dc_b; + input [0:3] obs0_abist_cmp; + // Scan + input [0:1] abst_scan_in; + input time_scan_in; + input repr_scan_in; + input func_scan_in; + output [0:1] abst_scan_out; + output time_scan_out; + output repr_scan_out; + output func_scan_out; + // BOLT-ON + input lcb_bolt_sl_thold_0; + input pc_bo_enable_2; // general bolt-on enable + input pc_bo_reset; // reset + input pc_bo_unload; // unload sticky bits + input pc_bo_repair; // execute sticky bit decode + input pc_bo_shdata; // shift data for timing write and diag loop + input [0:1] pc_bo_select; // select for mask and hier writes + output [0:1] bo_pc_failout; // fail/no-fix reg + output [0:1] bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + // Write Ports + input [0:ways-1] wr_way; + input [0:addressbus_width-1] wr_addr; + input [0:port_bitwidth*ways-1] data_in; + // Read Ports + input [0:addressbus_width-1] rd_addr; + output [0:port_bitwidth*ways-1] data_out; + + // tri_128x34_4w_1r1w + + parameter ramb_base_width = 36; + parameter ramb_base_addr = 9; + parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way + + + // Configuration Statement for NCsim + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + localparam rd_act_offset = 0; + localparam data_out_offset = rd_act_offset + 1; + localparam scan_right = data_out_offset + port_bitwidth*ways - 1; + + wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in[0:ways-1]; + wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1]; + wire [0:ramb_base_addr-1] ramb_rd_addr; + wire [0:ramb_base_addr-1] ramb_wr_addr; + + wire rd_act_l2; + wire [0:port_bitwidth*ways-1] data_out_d; + wire [0:port_bitwidth*ways-1] data_out_l2; + + wire tidn; + (* analysis_not_referenced="true" *) + wire unused; + wire [31:0] dob; + wire [3:0] dopb; + wire [0:scan_right] func_sov; + + generate + begin + assign tidn = 1'b0; + + if (addressbus_width < ramb_base_addr) + begin + assign ramb_rd_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}}; + assign ramb_rd_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = rd_addr; + + assign ramb_wr_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}}; + assign ramb_wr_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = wr_addr; + end + if (addressbus_width >= ramb_base_addr) + begin + assign ramb_rd_addr = rd_addr[addressbus_width - ramb_base_addr:addressbus_width - 1]; + assign ramb_wr_addr = wr_addr[addressbus_width - ramb_base_addr:addressbus_width - 1]; + end + + genvar w; + for (w = 0; w < ways; w = w + 1) + begin : dw + genvar i; + for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1) + begin : din + if (i < port_bitwidth) + begin + assign ramb_data_in[w][i] = data_in[w * port_bitwidth + i]; + end + if (i >= port_bitwidth) + begin + assign ramb_data_in[w][i] = 1'b0; + end + end + end + + //genvar w; + for (w = 0; w < ways; w = w + 1) + begin : aw + genvar x; + for (x = 0; x < ramb_width_mult; x = x + 1) + begin : ax + + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + arr( + .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DOB(dob), + .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DOPB(dopb), + .ADDRA(ramb_rd_addr), + .ADDRB(ramb_wr_addr), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DIB(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DIPA(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DIPB(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .ENA(rd_act), + .ENB(wr_act), + .SSRA(nclk[1]), + .SSRB(nclk[1]), + .WEA(tidn), + .WEB(wr_way[w]) + ); + end //ax + assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1]; + end //aw + end + endgenerate + + assign data_out = data_out_l2; + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(1'b1), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_force), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .d_mode(d_mode_dc), + .scin(1'b0), + .scout(func_sov[rd_act_offset]), + .din(rd_act), + .dout(rd_act_l2) + ); + + tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_l2), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_force), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .d_mode(d_mode_dc), + .scin({port_bitwidth*ways{1'b0}}), + .scout(func_sov[data_out_offset:data_out_offset + (port_bitwidth*ways) - 1]), + .din(data_out_d), + .dout(data_out_l2) + ); + + assign abst_scan_out = {tidn, tidn}; + assign time_scan_out = tidn; + assign repr_scan_out = tidn; + assign func_scan_out = tidn; + + assign bo_pc_failout = {tidn, tidn}; + assign bo_pc_diagloop = {tidn, tidn}; + + assign unused = | ({nclk[2:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]}); + +endmodule diff --git a/rel/src/verilog/trilib/tri_144x78_2r4w.v b/rel/src/verilog/trilib/tri_144x78_2r4w.v new file mode 100644 index 0000000..fcb5771 --- /dev/null +++ b/rel/src/verilog/trilib/tri_144x78_2r4w.v @@ -0,0 +1,604 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 fs / 1 fs + +//***************************************************************************** +// Description: Tri-Lam Array Wrapper +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_144x78_2r4w( + // Inputs + // Power + inout vdd, + inout gnd, + // Clock & Scan + input [0:`NCLK_WIDTH-1] nclk, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_slp_sl_force, + input func_slp_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Read Port + //------------------------------------------------------------------- + input r_late_en_1, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1, + output [64-`GPR_WIDTH:77] r_data_out_1, + input r_late_en_2, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2, + output [64-`GPR_WIDTH:77] r_data_out_2, + + //------------------------------------------------------------------- + // Write Port + //------------------------------------------------------------------- + input w_late_en_1, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1, + input [64-`GPR_WIDTH:77] w_data_in_1, + input w_late_en_2, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2, + input [64-`GPR_WIDTH:77] w_data_in_2, + input w_late_en_3, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3, + input [64-`GPR_WIDTH:77] w_data_in_3, + input w_late_en_4, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4, + input [64-`GPR_WIDTH:77] w_data_in_4 +); + + // Configuration Statement for NCsim + //for all:RAM64X1D use entity unisim.RAM64X1D; + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + //------------------------------------------------------------------- + // Signals + //------------------------------------------------------------------- + reg write_en; + reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr; + reg [64-`GPR_WIDTH:77] write_data; + wire [0:(`GPR_POOL*`THREADS-1)/64] write_en_arr; + wire [0:5] write_addr_arr; + wire [0:1] wr_mux_ctrl; + + //------------------------------------------------------------------- + // Latch Signals + //------------------------------------------------------------------- + wire w1e_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a_q; + wire [64-`GPR_WIDTH:77] w1d_q; + wire w2e_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a_q; + wire [64-`GPR_WIDTH:77] w2d_q; + wire w3e_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a_q; + wire [64-`GPR_WIDTH:77] w3d_q; + wire w4e_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w4a_q; + wire [64-`GPR_WIDTH:77] w4d_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q; + wire [0:5] read1_addr_arr; + wire [0:5] read2_addr_arr; + wire [0:(`GPR_POOL*`THREADS-1)/64] read1_en_arr; + wire [0:(`GPR_POOL*`THREADS-1)/64] read2_en_arr; + reg [64-`GPR_WIDTH:77] read1_data; + reg [64-`GPR_WIDTH:77] read2_data; + wire [64-`GPR_WIDTH:77] r1d_array[0:(`GPR_POOL*`THREADS-1)/64]; + wire [64-`GPR_WIDTH:77] r2d_array[0:(`GPR_POOL*`THREADS-1)/64]; + wire [64-`GPR_WIDTH:77] r1d_d; + wire [64-`GPR_WIDTH:77] r2d_d; + wire [64-`GPR_WIDTH:77] r1d_q; + wire [64-`GPR_WIDTH:77] r2d_q; + + (* analysis_not_referenced="true" *) + wire unused; + wire [64-`GPR_WIDTH:77] unused_port; + wire [64-`GPR_WIDTH:77] unused_port2; + + //------------------------------------------------------------------- + // Scanchain + //------------------------------------------------------------------- + parameter w1e_offset = 0; + parameter w1a_offset = w1e_offset + 1; + parameter w1d_offset = w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter w2e_offset = w1d_offset + (`GPR_WIDTH+14); + parameter w2a_offset = w2e_offset + 1; + parameter w2d_offset = w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter w3e_offset = w2d_offset + (`GPR_WIDTH+14); + parameter w3a_offset = w3e_offset + 1; + parameter w3d_offset = w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter w4e_offset = w3d_offset + (`GPR_WIDTH+14); + parameter w4a_offset = w4e_offset + 1; + parameter w4d_offset = w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter r1a_offset = w4d_offset + (`GPR_WIDTH+14); + parameter r2a_offset = r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter r1d_offset = r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter r2d_offset = r1d_offset + (`GPR_WIDTH+14); + parameter scan_right = r2d_offset + (`GPR_WIDTH+14); + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + generate + begin + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Read Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // BYPASS + + assign r1d_d = read1_data; + + assign r2d_d = read2_data; + + assign r_data_out_1 = r1d_q; + assign r_data_out_2 = r2d_q; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Write Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + assign wr_mux_ctrl = {nclk[0], nclk[2]}; + + always @ ( * ) + begin + write_addr <= #10 ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 : + (wr_mux_ctrl == 2'b01) ? w_addr_in_2 : + (wr_mux_ctrl == 2'b10) ? w_addr_in_3 : + w_addr_in_4); + + write_en <= #10 ((wr_mux_ctrl == 2'b00) ? w_late_en_1 : + (wr_mux_ctrl == 2'b01) ? w_late_en_2 : + (wr_mux_ctrl == 2'b10) ? w_late_en_3 : + w_late_en_4); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Depth Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + write_data <= #10 ((wr_mux_ctrl == 2'b00) ? w_data_in_1 : + (wr_mux_ctrl == 2'b01) ? w_data_in_2 : + (wr_mux_ctrl == 2'b10) ? w_data_in_3 : + w_data_in_4); + end + + if (((`GPR_POOL*`THREADS - 1)/64) == 0) + begin : depth1 + if (`GPR_POOL_ENC+`THREADS_POOL_ENC < 6) + begin + assign write_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; + assign read1_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; + assign read2_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; + end + + assign write_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = write_addr; + assign read1_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r1a_q; + assign read2_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r2a_q; + assign write_en_arr[0] = write_en; + assign read1_en_arr[0] = 1'b1; + assign read2_en_arr[0] = 1'b1; + end + + if (((`GPR_POOL*`THREADS - 1)/64) != 0) + begin : depthMulti + assign write_addr_arr = write_addr[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; + assign read1_addr_arr = r1a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; + assign read2_addr_arr = r2a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; + + genvar wen; + for (wen = 0; wen <= ((`GPR_POOL*`THREADS - 1)/64); wen = wen + 1) + begin : wrenGen + wire wen_match = wen; + assign write_en_arr[wen] = write_en & (write_addr[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match); + assign read1_en_arr[wen] = r1a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match; + assign read2_en_arr[wen] = r2a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match; + end + end + + always @( * ) + begin: rdDataMux + reg [64-`GPR_WIDTH:77] rd1_data; + reg [64-`GPR_WIDTH:77] rd2_data; + (* analysis_not_referenced="true" *) + integer rdArr; + rd1_data = {`GPR_WIDTH+14{1'b0}}; + rd2_data = {`GPR_WIDTH+14{1'b0}}; + + for (rdArr = 0; rdArr <= ((`GPR_POOL*`THREADS - 1)/64); rdArr = rdArr + 1) + begin + rd1_data = (r1d_array[rdArr] & {`GPR_WIDTH+14{read1_en_arr[rdArr]}}) | rd1_data; + rd2_data = (r2d_array[rdArr] & {`GPR_WIDTH+14{read2_en_arr[rdArr]}}) | rd2_data; + end + read1_data <= rd1_data; + read2_data <= rd2_data; + end + + genvar depth; + for (depth = 0; depth <= ((`GPR_POOL*`THREADS - 1)/64); depth = depth + 1) + begin : depth_loop + genvar i; + for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1) + begin : r1 + RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_1( + .SPO(unused_port[i]), + .DPO(r1d_array[depth][i]), // Port A 1-bit data output + .A0(write_addr_arr[5]), // Port A - Write Address (A0-A5) + .A1(write_addr_arr[4]), + .A2(write_addr_arr[3]), + .A3(write_addr_arr[2]), + .A4(write_addr_arr[1]), + .A5(write_addr_arr[0]), + .D(write_data[i]), // Port A 1-bit data input + .DPRA0(read1_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5) + .DPRA1(read1_addr_arr[4]), + .DPRA2(read1_addr_arr[3]), + .DPRA3(read1_addr_arr[2]), + .DPRA4(read1_addr_arr[1]), + .DPRA5(read1_addr_arr[0]), + .WCLK(nclk[3]), // Port A write clock input : clk4x + .WE(write_en_arr[depth]) // Port A write enable input + ); + end + + //genvar i; + for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1) + begin : r2 + RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_2( + .SPO(unused_port2[i]), + .DPO(r2d_array[depth][i]), // Port A 1-bit data output + .A0(write_addr_arr[5]), // Port A - Write Address (A0-A5) + .A1(write_addr_arr[4]), + .A2(write_addr_arr[3]), + .A3(write_addr_arr[2]), + .A4(write_addr_arr[1]), + .A5(write_addr_arr[0]), + .D(write_data[i]), // Port A 1-bit data input + .DPRA0(read2_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5) + .DPRA1(read2_addr_arr[4]), + .DPRA2(read2_addr_arr[3]), + .DPRA3(read2_addr_arr[2]), + .DPRA4(read2_addr_arr[1]), + .DPRA5(read2_addr_arr[0]), + .WCLK(nclk[3]), // Port A write clock input : clk4x + .WE(write_en_arr[depth]) // Port A write enable input + ); + end + end + end + endgenerate + + //---------------------------------------------------------------------------------------------------------------------------------------- + // Latches + //---------------------------------------------------------------------------------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w1e_offset]), + .scout(sov[w1e_offset]), + .din(w_late_en_1), + .dout(w1e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(w_addr_in_1), + .dout(w1a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w1d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]), + .din(w_data_in_1[64 - `GPR_WIDTH:77]), + .dout(w1d_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w2e_offset]), + .scout(sov[w2e_offset]), + .din(w_late_en_2), + .dout(w2e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(w_addr_in_2), + .dout(w2a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w2d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]), + .din(w_data_in_2[64 - `GPR_WIDTH:77]), + .dout(w2d_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w3e_offset]), + .scout(sov[w3e_offset]), + .din(w_late_en_3), + .dout(w3e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(w_addr_in_3), + .dout(w3a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w3d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]), + .din(w_data_in_3[64 - `GPR_WIDTH:77]), + .dout(w3d_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w4e_offset]), + .scout(sov[w4e_offset]), + .din(w_late_en_4), + .dout(w4e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(w_addr_in_4), + .dout(w4a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w4d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]), + .din(w_data_in_4[64 - `GPR_WIDTH:77]), + .dout(w4d_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(r_addr_in_1), + .dout(r1a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(r_addr_in_2), + .dout(r2a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r1d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]), + .din(r1d_d), + .dout(r1d_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r2d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]), + .din(r2d_d), + .dout(r2d_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + assign unused = | {unused_port, unused_port2, func_slp_sl_force, func_slp_sl_thold_0_b}; +endmodule diff --git a/rel/src/verilog/trilib/tri_256x144_8w_1r1w.v b/rel/src/verilog/trilib/tri_256x144_8w_1r1w.v new file mode 100644 index 0000000..4c98f3a --- /dev/null +++ b/rel/src/verilog/trilib/tri_256x144_8w_1r1w.v @@ -0,0 +1,513 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_256x144_8w_1r1w.v +// *! DESCRIPTION : 256 Entry x 144 bit x 8 way array, 9 bit writeable +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_256x144_8w_1r1w( + gnd, + vdd, + vcs, + nclk, + rd_act, + wr_act, + sg_0, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + func_sl_force, + func_sl_thold_0_b, + g8t_clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + wr_way, + wr_addr, + data_in0, + data_in1, + rd_addr, + data_out +); +parameter addressable_ports = 256; // number of addressable register in this array +parameter addressbus_width = 8; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) +parameter port_bitwidth = 144; // bitwidth of ports (per way) +parameter bit_write_type = 9; // gives the number of bits that shares one write-enable; must divide evenly into array +parameter ways = 8; // number of ways + +// POWER PINS +inout gnd; +inout vdd; +inout vcs; + +// CLOCK and CLOCKCONTROL ports +input [0:`NCLK_WIDTH-1] nclk; +input [0:7] rd_act; +input [0:7] wr_act; +input sg_0; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input func_sl_force; +input func_sl_thold_0_b; +input g8t_clkoff_dc_b; +input ccflush_dc; +input scan_dis_dc_b; +input scan_diag_dc; +input g8t_d_mode_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input [0:4] g8t_delay_lclkr_dc; +input d_mode_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input delay_lclkr_dc; + +// ABIST +input wr_abst_act; +input rd0_abst_act; +input [0:3] abist_di; +input abist_bw_odd; +input abist_bw_even; +input [0:addressbus_width-1] abist_wr_adr; +input [0:addressbus_width-1] abist_rd0_adr; +input tc_lbist_ary_wrt_thru_dc; +input abist_ena_1; +input abist_g8t_rd0_comp_ena; +input abist_raw_dc_b; +input [0:3] obs0_abist_cmp; + +// SCAN +input [0:3] abst_scan_in; +input time_scan_in; +input repr_scan_in; +input [0:3] func_scan_in; +output [0:3] abst_scan_out; +output time_scan_out; +output repr_scan_out; +output [0:3] func_scan_out; + +// BOLT-ON +input lcb_bolt_sl_thold_0; +input pc_bo_enable_2; // general bolt-on enable +input pc_bo_reset; // reset +input pc_bo_unload; // unload sticky bits +input pc_bo_repair; // execute sticky bit decode +input pc_bo_shdata; // shift data for timing write and diag loop +input [0:3] pc_bo_select; // select for mask and hier writes +output [0:3] bo_pc_failout; // fail/no-fix reg +output [0:3] bo_pc_diagloop; +input tri_lcb_mpw1_dc_b; +input tri_lcb_mpw2_dc_b; +input tri_lcb_delay_lclkr_dc; +input tri_lcb_clkoff_dc_b; +input tri_lcb_act_dis_dc; + +// FUNCTIONAL PORTS +input [0:ways-1] wr_way; +input [0:(addressbus_width-1)] wr_addr; +input [0:(port_bitwidth-1)] data_in0; +input [0:(port_bitwidth-1)] data_in1; +input [0:(addressbus_width-1)] rd_addr; +output [0:(port_bitwidth*ways-1)] data_out; + +parameter ramb_base_addr = 16; +parameter dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1; +parameter numBytes = (dataWidth/9); +parameter addresswidth = addressbus_width; +parameter rd_act_offset = 0; +parameter data_out_offset = rd_act_offset + ways; +parameter scan_right = data_out_offset + (port_bitwidth*ways) - 1; + +wire [0:dataWidth] data_in0_pad; +wire [0:dataWidth] data_in1_pad; +wire [0:dataWidth] data_in_swzl[0:ways-1]; +wire [0:dataWidth] p0_data_out_pad[0:ways-1]; +wire [0:dataWidth] p1_data_out_pad[0:ways-1]; +wire [0:(dataWidth-(dataWidth)/9)-1] p0_arr_data_in[0:ways-1]; +wire [0:(dataWidth)/9] p0_arr_par_in[0:ways-1]; +wire [0:(dataWidth-(dataWidth)/9)-1] p1_arr_data_in[0:ways-1]; +wire [0:(dataWidth)/9] p1_arr_par_in[0:ways-1]; +wire [0:(dataWidth-(dataWidth)/9)-1] p0_arr_data_out[0:ways-1]; +wire [0:(dataWidth)/9] p0_arr_par_out[0:ways-1]; +wire [0:(dataWidth-(dataWidth)/9)-1] p1_arr_data_out[0:ways-1]; +wire [0:(dataWidth)/9] p1_arr_par_out[0:ways-1]; +wire [0:ramb_base_addr-1] ramb_rd_addr; +wire [0:ramb_base_addr-1] ramb_wr_addr; +wire [0:((((port_bitwidth-1)/36)+1)*4)-1] p0_wayEn[0:ways-1]; +wire [0:((((port_bitwidth-1)/36)+1)*4)-1] p1_wayEn[0:ways-1]; +wire [0:(port_bitwidth*ways-1)] p0_data_out_swzl; +wire [0:(port_bitwidth*ways-1)] p1_data_out_swzl; +wire [0:(port_bitwidth*ways-1)] data_out_fix; +wire [0:((port_bitwidth-1)/36)] cascadeoutlata; +wire [0:((port_bitwidth-1)/36)] cascadeoutlatb; +wire [0:((port_bitwidth-1)/36)] cascadeoutrega; +wire [0:((port_bitwidth-1)/36)] cascadeoutregb; +wire [0:ways-1] rd_act_d; +wire [0:ways-1] rd_act_q; +wire [0:(port_bitwidth*ways)-1] data_out_d; +wire [0:(port_bitwidth*ways)-1] data_out_b_q; + +wire [0:ways-1] my_d1clk; +wire [0:ways-1] my_d2clk; +wire [0:`NCLK_WIDTH-1] my_lclk[0:ways-1]; +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +(* analysis_not_referenced="true" *) +wire unused; + +generate begin + // Read/Write Port Address Generate + assign ramb_rd_addr[11:15] = 5'b0; + assign ramb_wr_addr[11:15] = 5'b0; + assign rd_act_d = rd_act; + assign tiup = 1'b1; + + genvar byte; + genvar way; + genvar bit; + for (byte = 0; byte <= numBytes; byte = byte + 1) begin : swzl + for (way = 0; way < ways; way = way + 1) begin : perWay + if (way < (ways/2)) begin : fhalf + assign data_in_swzl[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = {data_in0_pad[byte + (0 * (numBytes + 1))], data_in0_pad[byte + (1 * (numBytes + 1))], + data_in0_pad[byte + (2 * (numBytes + 1))], data_in0_pad[byte + (3 * (numBytes + 1))], + data_in0_pad[byte + (4 * (numBytes + 1))], data_in0_pad[byte + (5 * (numBytes + 1))], + data_in0_pad[byte + (6 * (numBytes + 1))], data_in0_pad[byte + (7 * (numBytes + 1))]}; + assign data_in_swzl[way][(((byte * 8) + byte) + 8)] = data_in0_pad[byte + (8 * (numBytes + 1))]; + end + if (way >= (ways/2)) begin : shalf + assign data_in_swzl[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = {data_in1_pad[byte + (0 * (numBytes + 1))], data_in1_pad[byte + (1 * (numBytes + 1))], + data_in1_pad[byte + (2 * (numBytes + 1))], data_in1_pad[byte + (3 * (numBytes + 1))], + data_in1_pad[byte + (4 * (numBytes + 1))], data_in1_pad[byte + (5 * (numBytes + 1))], + data_in1_pad[byte + (6 * (numBytes + 1))], data_in1_pad[byte + (7 * (numBytes + 1))]}; + assign data_in_swzl[way][(((byte * 8) + byte) + 8)] = data_in1_pad[byte + (8 * (numBytes + 1))]; + end + end + end + + genvar t; + for (t = 0; t < 11; t = t + 1) begin : rambAddrCalc + if (t < (11-addresswidth)) begin + assign ramb_rd_addr[t] = 1'b0; + assign ramb_wr_addr[t] = 1'b0; + end + if (t >= (11-addresswidth)) begin + assign ramb_rd_addr[t] = rd_addr[t - (11 - addresswidth)]; + assign ramb_wr_addr[t] = wr_addr[t - (11 - addresswidth)]; + end + end + + for (bit = 0; bit <= dataWidth; bit = bit + 1) begin : dFixUp + if (bit < port_bitwidth) begin + assign data_in0_pad[bit] = data_in0[bit]; + assign data_in1_pad[bit] = data_in1[bit]; + end + if (bit >= port_bitwidth) begin + assign data_in0_pad[bit] = 1'b0; + assign data_in1_pad[bit] = 1'b0; + end + end + + //genvar way; + for (way = 0; way < ways; way = way + 1) begin : NwayDatInFix + //genvar byte; + for (byte = 0; byte <= (dataWidth)/9; byte = byte + 1) begin : dFixUp + assign p0_arr_data_in[way][byte * 8:(byte * 8) + 7] = 8'h00; + assign p0_arr_par_in[way][byte] = 1'b0; + assign p1_arr_data_in[way][byte * 8:(byte * 8) + 7] = data_in_swzl[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)]; + assign p1_arr_par_in[way][byte] = data_in_swzl[way][(((byte * 8) + byte) + 8)]; + end + end + + //genvar way; + for (way = 0; way < ways; way = way + 1) begin : NwayDatOutFix + //genvar byte; + for (byte = 0; byte <= (dataWidth)/9; byte = byte + 1) begin : dFixUp + assign p0_data_out_pad[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = p0_arr_data_out[way][byte * 8:(byte * 8) + 7]; + assign p0_data_out_pad[way][(((byte * 8) + byte) + 8)] = p0_arr_par_out[way][byte]; + assign p1_data_out_pad[way][(byte * 8) + byte:(((byte * 8) + 7) + byte)] = p1_arr_data_out[way][byte * 8:(byte * 8) + 7]; + assign p1_data_out_pad[way][(((byte * 8) + byte) + 8)] = p1_arr_par_out[way][byte]; + end + end + + //genvar way; + for (way = 0; way < ways; way = way + 1) begin : NwayDatOut + assign p0_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p0_data_out_pad[way][0:port_bitwidth - 1]; + assign p1_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p1_data_out_pad[way][0:port_bitwidth - 1]; + + //genvar byte; + for (byte = 0; byte <= numBytes; byte = byte + 1) begin : swzl + assign data_out_fix[(way * port_bitwidth) + (0 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 0]; + assign data_out_fix[(way * port_bitwidth) + (1 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 1]; + assign data_out_fix[(way * port_bitwidth) + (2 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 2]; + assign data_out_fix[(way * port_bitwidth) + (3 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 3]; + assign data_out_fix[(way * port_bitwidth) + (4 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 4]; + assign data_out_fix[(way * port_bitwidth) + (5 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 5]; + assign data_out_fix[(way * port_bitwidth) + (6 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 6]; + assign data_out_fix[(way * port_bitwidth) + (7 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 7]; + assign data_out_fix[(way * port_bitwidth) + (8 * (numBytes + 1)) + byte] = p0_data_out_swzl[(way * port_bitwidth) + ((byte * 8) + byte) + 8]; + end + end + assign data_out_d = data_out_fix; + + assign data_out = ~data_out_b_q; + + //genvar way; + for (way = 0; way < ways; way = way + 1) begin : Nways + //genvar byte; + for (byte = 0; byte < ((((port_bitwidth - 1)/36) + 1) * 4); byte = byte + 1) begin : BEn + if (byte <= (port_bitwidth - 1)/9) begin + assign p0_wayEn[way][byte] = 1'b0; + assign p1_wayEn[way][byte] = wr_way[way]; + end + if (byte > (port_bitwidth - 1)/9) begin + assign p0_wayEn[way][byte] = 1'b0; + assign p1_wayEn[way][byte] = 1'b0; + end + end + + // Port A => Read Port + // Port B => Write Port + genvar arr; + for (arr = 0; arr <= ((port_bitwidth - 1)/36); arr = arr + 1) begin : Narrs + RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) wayArr( + .CASCADEOUTLATA(cascadeoutlata[arr]), + .CASCADEOUTLATB(cascadeoutlatb[arr]), + .CASCADEOUTREGA(cascadeoutrega[arr]), + .CASCADEOUTREGB(cascadeoutregb[arr]), + .DOA(p0_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]), + .DOB(p1_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]), + .DOPA(p0_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]), + .DOPB(p1_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]), + .ADDRA(ramb_rd_addr), + .ADDRB(ramb_wr_addr), + .CASCADEINLATA(1'b0), + .CASCADEINLATB(1'b0), + .CASCADEINREGA(1'b0), + .CASCADEINREGB(1'b0), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(p0_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]), + .DIB(p1_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]), + .DIPA(p0_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]), + .DIPB(p1_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]), + .ENA(rd_act[way]), + .ENB(wr_act[way]), + .REGCEA(1'b0), + .REGCEB(1'b0), + .SSRA(nclk[1]), //sreset + .SSRB(nclk[1]), //sreset + .WEA(p0_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]), + .WEB(p1_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]) + ); + end + end //Nways + + assign abst_scan_out = 4'b0; + assign time_scan_out = 1'b0; + assign repr_scan_out = 1'b0; + assign bo_pc_failout = 4'h0; + assign bo_pc_diagloop = 4'h0; +end +endgenerate + +assign unused = |({ + cascadeoutlata , + cascadeoutlatb , + cascadeoutrega , + cascadeoutregb , + nclk[0:`NCLK_WIDTH-1] , + gnd , + vdd , + vcs , + sg_0 , + ary_nsl_thold_0 , + abst_sl_thold_0 , + time_sl_thold_0 , + repr_sl_thold_0 , + g8t_clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + p1_data_out_swzl}); + +// ############################################################### +// ## Latches +// ############################################################### +tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rd_act_offset:rd_act_offset + ways - 1]), + .scout(sov[rd_act_offset:rd_act_offset + ways - 1]), + .din(rd_act_d), + .dout(rd_act_q) +); + +generate begin : wayReg + genvar way; + for (way=0; way= addressable_ports) +parameter port_bitwidth = 70; // bitwidth of ports +parameter ways = 2; // number of ways + +// POWER PINS +inout gnd; +inout vdd; +inout vcs; +// CLOCK and CLOCKCONTROL ports +input [0:`NCLK_WIDTH-1] nclk; +input [0:1] rd_act; +input [0:1] wr_act; +input sg_0; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input func_sl_force; +input func_sl_thold_0_b; +input g8t_clkoff_dc_b; +input ccflush_dc; +input scan_dis_dc_b; +input scan_diag_dc; +input g8t_d_mode_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input [0:4] g8t_delay_lclkr_dc; +input d_mode_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input delay_lclkr_dc; + +// ABIST +input wr_abst_act; +input rd0_abst_act; +input [0:3] abist_di; +input abist_bw_odd; +input abist_bw_even; +input [0:addressbus_width-1] abist_wr_adr; +input [0:addressbus_width-1] abist_rd0_adr; +input tc_lbist_ary_wrt_thru_dc; +input abist_ena_1; +input abist_g8t_rd0_comp_ena; +input abist_raw_dc_b; +input [0:3] obs0_abist_cmp; + +// Scan +input [0:1] abst_scan_in; +input time_scan_in; +input repr_scan_in; +input func_scan_in; +output [0:1] abst_scan_out; +output time_scan_out; +output repr_scan_out; +output func_scan_out; + +// BOLT-ON +input lcb_bolt_sl_thold_0; +input pc_bo_enable_2; // general bolt-on enable +input pc_bo_reset; // reset +input pc_bo_unload; // unload sticky bits +input pc_bo_repair; // execute sticky bit decode +input pc_bo_shdata; // shift data for timing write and diag loop +input [0:1] pc_bo_select; // select for mask and hier writes +output [0:1] bo_pc_failout; // fail/no-fix reg +output [0:1] bo_pc_diagloop; +input tri_lcb_mpw1_dc_b; +input tri_lcb_mpw2_dc_b; +input tri_lcb_delay_lclkr_dc; +input tri_lcb_clkoff_dc_b; +input tri_lcb_act_dis_dc; + +// Write Ports +input [0:ways-1] wr_way; +input [0:addressbus_width-1] wr_addr; +input [0:port_bitwidth-1] data_in; + +// Read Ports +input [0:addressbus_width-1] rd_addr; +output [0:port_bitwidth*ways-1] data_out; + +// tri_32x70_2w_1r1w + +parameter ramb_base_width = 36; +parameter ramb_base_addr = 9; + +// Configuration Statement for NCsim +//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; +parameter rd_act_offset = 0; +parameter data_out0_offset = rd_act_offset + 2; +parameter data_out1_offset = data_out0_offset + port_bitwidth - 1; +parameter scan_right = data_out1_offset + port_bitwidth - 1; + +wire [0:port_bitwidth-1] array_wr_data; +wire [0:35] ramb_data_in_l; +wire [0:35] ramb_data_in_r; +wire [0:35] ramb_data_p0_outA; +wire [0:35] ramb_data_p0_outB; +wire [0:35] ramb_data_p0_outC; +wire [0:35] ramb_data_p0_outD; +wire [0:35] ramb_data_p1_outA; +wire [0:35] ramb_data_p1_outB; +wire [0:35] ramb_data_p1_outC; +wire [0:35] ramb_data_p1_outD; +wire [0:ramb_base_addr-1] ramb_addr_rd1; +wire [0:ramb_base_addr-1] ramb_addr_wr_rd0; + +wire [0:ramb_base_addr-1] rd_addr0; +wire [0:ramb_base_addr-1] wr_addr1; +wire write_enable_AB; +wire write_enable_CD; +wire tiup; +wire [0:35] tidn; +wire [0:1] act; +wire ary_nsl_thold_0_b; +wire [0:addressable_ports-1] arrA_bit0_scanout; +wire [0:addressable_ports-1] arrC_bit0_scanout; +wire [0:addressable_ports-1] arrA_bit0_d; +wire [0:addressable_ports-1] arrA_bit0_q; +wire [0:addressable_ports-1] arrC_bit0_d; +wire [0:addressable_ports-1] arrC_bit0_q; +wire [0:addressable_ports-1] arrA_bit0_wen; +wire [0:addressable_ports-1] arrC_bit0_wen; +reg arrA_bit0_out_d; +reg arrC_bit0_out_d; +wire arrA_bit0_out_q; +wire arrC_bit0_out_q; +wire arrA_bit0_out_scanout; +wire arrC_bit0_out_scanout; +wire [0:port_bitwidth*ways-1] data_out_d; +wire [0:port_bitwidth*ways-1] data_out_q; +wire [0:1] rd_act_d; +wire [0:1] rd_act_q; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +(* analysis_not_referenced="true" *) +wire unused; + +assign unused = | {ramb_data_p1_outA[0], ramb_data_p1_outA[35], ramb_data_p1_outB[35], ramb_data_p1_outC[0], ramb_data_p1_outC[35], ramb_data_p1_outD[35], + ramb_data_p0_outA, ramb_data_p0_outB, ramb_data_p0_outC, ramb_data_p0_outD, gnd, vdd, vcs, + sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b, + scan_diag_dc, g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, + abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, + obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, + pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, arrA_bit0_scanout, arrC_bit0_scanout, arrA_bit0_out_scanout, arrC_bit0_out_scanout}; + +assign tiup = 1'b1; +assign tidn = 36'b0; +assign act = rd_act | wr_act; +assign rd_act_d = rd_act; + +// Data Generate +assign array_wr_data = data_in; + +assign ramb_data_in_l = {array_wr_data[0:34], 1'b0}; +assign ramb_data_in_r = {array_wr_data[35:69], 1'b0}; + +assign write_enable_AB = wr_act[0] & wr_way[0]; +assign write_enable_CD = wr_act[1] & wr_way[1]; + +// Read/Write Port Address Generate +generate +begin + genvar t; + for (t = 0; t < ramb_base_addr; t = t + 1) + begin : rambAddrCalc + if (t < ramb_base_addr - addressbus_width) + begin + assign rd_addr0[t] = 1'b0; + assign wr_addr1[t] = 1'b0; + end + if (t >= ramb_base_addr - addressbus_width) + begin + assign rd_addr0[t] = rd_addr[t - (ramb_base_addr - addressbus_width)]; + assign wr_addr1[t] = wr_addr[t - (ramb_base_addr - addressbus_width)]; + end + end +end +endgenerate + +// Writing on PortA +// Reading on PortB +assign ramb_addr_rd1 = rd_addr0; +assign ramb_addr_wr_rd0 = wr_addr1; + +assign data_out_d = {arrA_bit0_out_q, ramb_data_p1_outA[1:34], ramb_data_p1_outB[0:34], arrC_bit0_out_q, ramb_data_p1_outC[1:34], ramb_data_p1_outD[0:34]}; +assign data_out = data_out_q; + +generate + begin : arr_bit0 + genvar i; + for (i = 0; i <= addressable_ports - 1; i = i + 1) + begin : arr_bit0 + wire [0:addressbus_width-1] iDummy=i; + assign arrA_bit0_wen[i] = write_enable_AB & (wr_addr == iDummy); + assign arrC_bit0_wen[i] = write_enable_CD & (wr_addr == iDummy); + assign arrA_bit0_d[i] = (arrA_bit0_wen[i] == 1'b1) ? array_wr_data[0] : + arrA_bit0_q[i]; + assign arrC_bit0_d[i] = (arrC_bit0_wen[i] == 1'b1) ? array_wr_data[0] : + arrC_bit0_q[i]; + end + end +endgenerate + +always @(*) + begin: bit0_read_proc + reg rd_arrA_bit0; + reg rd_arrC_bit0; + (* analysis_not_referenced="true" *) + reg [0:31] i; + rd_arrA_bit0 = 1'b0; + rd_arrC_bit0 = 1'b0; + for (i = 0; i <= addressable_ports - 1; i = i + 1) + begin + rd_arrA_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrA_bit0_q[i]) | rd_arrA_bit0; + rd_arrC_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrC_bit0_q[i]) | rd_arrC_bit0; + end + arrA_bit0_out_d <= rd_arrA_bit0; + arrC_bit0_out_d <= rd_arrC_bit0; + end + + +assign ary_nsl_thold_0_b = ~ ary_nsl_thold_0; + +tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(write_enable_AB), + .force_t(tidn[0]), + .d_mode(tidn[0]), + .delay_lclkr(tidn[0]), + .mpw1_b(tidn[0]), + .mpw2_b(tidn[0]), + .thold_b(ary_nsl_thold_0_b), + .sg(tidn[0]), + .scin({addressable_ports{tidn[0]}}), + .scout(arrA_bit0_scanout), + .din(arrA_bit0_d), + .dout(arrA_bit0_q) +); + +tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(write_enable_CD), + .force_t(tidn[0]), + .d_mode(tidn[0]), + .delay_lclkr(tidn[0]), + .mpw1_b(tidn[0]), + .mpw2_b(tidn[0]), + .thold_b(ary_nsl_thold_0_b), + .sg(tidn[0]), + .scin({addressable_ports{tidn[0]}}), + .scout(arrC_bit0_scanout), + .din(arrC_bit0_d), + .dout(arrC_bit0_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(tidn[0]), + .d_mode(tidn[0]), + .delay_lclkr(tidn[0]), + .mpw1_b(tidn[0]), + .mpw2_b(tidn[0]), + .thold_b(ary_nsl_thold_0_b), + .sg(tidn[0]), + .scin(tidn[0]), + .scout(arrA_bit0_out_scanout), + .din(arrA_bit0_out_d), + .dout(arrA_bit0_out_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(tidn[0]), + .d_mode(tidn[0]), + .delay_lclkr(tidn[0]), + .mpw1_b(tidn[0]), + .mpw2_b(tidn[0]), + .thold_b(ary_nsl_thold_0_b), + .sg(tidn[0]), + .scin(tidn[0]), + .scout(arrC_bit0_out_scanout), + .din(arrC_bit0_out_d), + .dout(arrC_bit0_out_q) +); + + +RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only +arr0_A( + .DOA(ramb_data_p0_outA[0:31]), + .DOB(ramb_data_p1_outA[0:31]), + .DOPA(ramb_data_p0_outA[32:35]), + .DOPB(ramb_data_p1_outA[32:35]), + .ADDRA(ramb_addr_wr_rd0), + .ADDRB(ramb_addr_rd1), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in_l[0:31]), + .DIB(tidn[0:31]), + .DIPA(ramb_data_in_l[32:35]), + .DIPB(tidn[32:35]), + .ENA(act[0]), + .ENB(act[0]), + .SSRA(nclk[1]), //sreset + .SSRB(nclk[1]), //sreset + .WEA(write_enable_AB), + .WEB(tidn[0]) +); + +RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only +arr1_B( + .DOA(ramb_data_p0_outB[0:31]), + .DOB(ramb_data_p1_outB[0:31]), + .DOPA(ramb_data_p0_outB[32:35]), + .DOPB(ramb_data_p1_outB[32:35]), + .ADDRA(ramb_addr_wr_rd0), + .ADDRB(ramb_addr_rd1), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in_r[0:31]), + .DIB(tidn[0:31]), + .DIPA(ramb_data_in_r[32:35]), + .DIPB(tidn[32:35]), + .ENA(act[0]), + .ENB(act[0]), + .SSRA(nclk[1]), + .SSRB(nclk[1]), + .WEA(write_enable_AB), + .WEB(tidn[0]) +); + +RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only +arr2_C( + .DOA(ramb_data_p0_outC[0:31]), + .DOB(ramb_data_p1_outC[0:31]), + .DOPA(ramb_data_p0_outC[32:35]), + .DOPB(ramb_data_p1_outC[32:35]), + .ADDRA(ramb_addr_wr_rd0), + .ADDRB(ramb_addr_rd1), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in_l[0:31]), + .DIB(tidn[0:31]), + .DIPA(ramb_data_in_l[32:35]), + .DIPB(tidn[32:35]), + .ENA(act[1]), + .ENB(act[1]), + .SSRA(nclk[1]), + .SSRB(nclk[1]), + .WEA(write_enable_CD), + .WEB(tidn[0]) +); + +RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only +arr3_D( + .DOA(ramb_data_p0_outD[0:31]), + .DOB(ramb_data_p1_outD[0:31]), + .DOPA(ramb_data_p0_outD[32:35]), + .DOPB(ramb_data_p1_outD[32:35]), + .ADDRA(ramb_addr_wr_rd0), + .ADDRB(ramb_addr_rd1), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in_r[0:31]), + .DIB(tidn[0:31]), + .DIPA(ramb_data_in_r[32:35]), + .DIPB(tidn[32:35]), + .ENA(act[1]), + .ENB(act[1]), + .SSRA(nclk[1]), + .SSRB(nclk[1]), + .WEA(write_enable_CD), + .WEB(tidn[0]) +); + +// #################################################### +// Registers +// #################################################### + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rd_act_offset:rd_act_offset + 2 - 1]), + .scout(sov[rd_act_offset:rd_act_offset + 2 - 1]), + .din(rd_act_d), + .dout(rd_act_q) +); + +tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_q[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[data_out0_offset:data_out0_offset + port_bitwidth - 1]), + .scout(sov[data_out0_offset:data_out0_offset + port_bitwidth - 1]), + .din(data_out_d[0:port_bitwidth - 1]), + .dout(data_out_q[0:port_bitwidth - 1]) +); + +tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_q[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[data_out1_offset:data_out1_offset + port_bitwidth - 1]), + .scout(sov[data_out1_offset:data_out1_offset + port_bitwidth - 1]), + .din(data_out_d[port_bitwidth:2 * port_bitwidth - 1]), + .dout(data_out_q[port_bitwidth:2 * port_bitwidth - 1]) +); + +assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; +assign func_scan_out = sov[0]; + +assign abst_scan_out = tidn[0:1]; +assign time_scan_out = tidn[0]; +assign repr_scan_out = tidn[0]; +assign bo_pc_failout = tidn[0:1]; +assign bo_pc_diagloop = tidn[0:1]; +endmodule diff --git a/rel/src/verilog/trilib/tri_512x162_4w_0.v b/rel/src/verilog/trilib/tri_512x162_4w_0.v new file mode 100644 index 0000000..439dd57 --- /dev/null +++ b/rel/src/verilog/trilib/tri_512x162_4w_0.v @@ -0,0 +1,338 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_512x162_4w_0.v +// *! DESCRIPTION : 512 Entry x 162 bit x 4 way array +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_512x162_4w_0( + gnd, + vdd, + vcs, + nclk, + ccflush_dc, + lcb_clkoff_dc_b, + lcb_d_mode_dc, + lcb_act_dis_dc, + lcb_ary_nsl_thold_0, + lcb_sg_1, + lcb_abst_sl_thold_0, + lcb_func_sl_thold_0_b, + func_force, + scan_diag_dc, + scan_dis_dc_b, + func_scan_in, + func_scan_out, + abst_scan_in, + abst_scan_out, + lcb_delay_lclkr_np_dc, + ctrl_lcb_delay_lclkr_np_dc, + dibw_lcb_delay_lclkr_np_dc, + ctrl_lcb_mpw1_np_dc_b, + dibw_lcb_mpw1_np_dc_b, + lcb_mpw1_pp_dc_b, + lcb_mpw1_2_pp_dc_b, + aodo_lcb_delay_lclkr_dc, + aodo_lcb_mpw1_dc_b, + aodo_lcb_mpw2_dc_b, + lcb_time_sg_0, + lcb_time_sl_thold_0, + time_scan_in, + time_scan_out, + bitw_abist, + lcb_repr_sl_thold_0, + lcb_repr_sg_0, + repr_scan_in, + repr_scan_out, + tc_lbist_ary_wrt_thru_dc, + abist_en_1, + din_abist, + abist_cmp_en, + abist_raw_b_dc, + data_cmp_abist, + addr_abist, + r_wb_abist, + write_thru_en_dc, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + read_act, + write_act, + write_enable, + write_way, + addr, + data_in, + data_out +); + parameter addressable_ports = 512; // number of addressable register in this array + parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 162; // bitwidth of ports + parameter ways = 4; // number of ways + // POWER PINS + inout gnd; + inout vdd; + (* analysis_not_referenced="true" *) + inout vcs; + // CLOCK and CLOCKCONTROL ports + input [0:`NCLK_WIDTH-1] nclk; + input ccflush_dc; + input lcb_clkoff_dc_b; + input lcb_d_mode_dc; + input lcb_act_dis_dc; + input lcb_ary_nsl_thold_0; + input lcb_sg_1; + input lcb_abst_sl_thold_0; + input lcb_func_sl_thold_0_b; + input func_force; + input scan_diag_dc; + input scan_dis_dc_b; + input func_scan_in; + output func_scan_out; + input [0:1] abst_scan_in; + output [0:1] abst_scan_out; + input lcb_delay_lclkr_np_dc; + input ctrl_lcb_delay_lclkr_np_dc; + input dibw_lcb_delay_lclkr_np_dc; + input ctrl_lcb_mpw1_np_dc_b; + input dibw_lcb_mpw1_np_dc_b; + input lcb_mpw1_pp_dc_b; + input lcb_mpw1_2_pp_dc_b; + input aodo_lcb_delay_lclkr_dc; + input aodo_lcb_mpw1_dc_b; + input aodo_lcb_mpw2_dc_b; + // Timing Scan Chain Pins + input lcb_time_sg_0; + input lcb_time_sl_thold_0; + input time_scan_in; + output time_scan_out; + input [0:1] bitw_abist; + // REDUNDANCY PINS + input lcb_repr_sl_thold_0; + input lcb_repr_sg_0; + input repr_scan_in; + output repr_scan_out; + // DATA I/O RELATED PINS: + input tc_lbist_ary_wrt_thru_dc; + input abist_en_1; + input [0:3] din_abist; + input abist_cmp_en; + input abist_raw_b_dc; + input [0:3] data_cmp_abist; + input [0:addressbus_width-1] addr_abist; + input r_wb_abist; + input write_thru_en_dc; + // BOLT-ON + input lcb_bolt_sl_thold_0; // thold for any regs inside backend + input pc_bo_enable_2; // general bolt-on enable, probably DC + input pc_bo_reset; // execute sticky bit decode + input pc_bo_unload; + input pc_bo_repair; // load repair reg + input pc_bo_shdata; // shift data for timing write + input [0:1] pc_bo_select; // select for mask and hier writes + output [0:1] bo_pc_failout; // fail/no-fix reg + output [0:1] bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + // FUNCTIONAL PORTS + input [0:1] read_act; + input [0:3] write_act; + input write_enable; + input [0:ways-1] write_way; + input [0:addressbus_width-1] addr; + input [0:port_bitwidth-1] data_in; + output [0:port_bitwidth*ways-1] data_out; + + // tri_512x162_4w_0 + + parameter ramb_base_width = 36; + parameter ramb_base_addr = 9; + parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way + + // Configuration Statement for NCsim + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire [0:ramb_base_width*ramb_width_mult-1] ramb_data_in; + wire [0:ramb_base_width*ramb_width_mult-1] ramb_data_out[0:ways-1]; + wire [0:ramb_base_addr-1] ramb_addr; + + wire rd_act_d; + wire rd_act_l2; + wire [0:port_bitwidth*ways-1] data_out_d; + wire [0:port_bitwidth*ways-1] data_out_l2; + + wire lcb_sg_0; + + wire [0:ways-1] act; + wire [0:ways-1] write; + wire tidn; + (* analysis_not_referenced="true" *) + wire unused; + wire [31:0] dob; + wire [3:0] dopb; + wire [0:port_bitwidth*ways-1] unused_scout; + + generate + begin + assign tidn = 1'b0; + + if (addressbus_width < ramb_base_addr) + begin + assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}}; + assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr; + end + if (addressbus_width >= ramb_base_addr) + begin + assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1]; + end + + genvar i; + for (i = 0; i < ramb_base_width*ramb_width_mult; i = i + 1) + begin : din + if (i < port_bitwidth) + assign ramb_data_in[i] = data_in[i]; + if (i >= port_bitwidth) + assign ramb_data_in[i] = 1'b0; + end + + genvar w; + for (w = 0; w < ways; w = w + 1) + begin : aw + assign act[w] = (|(read_act)) | write_way[w]; + assign write[w] = write_enable & write_way[w]; + + genvar x; + for (x = 0; x < ramb_width_mult; x = x + 1) + begin : ax + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + arr( + .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DOB(dob), + .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DOPB(dopb), + .ADDRA(ramb_addr), + .ADDRB(ramb_addr), + .CLKA(nclk[0]), + .CLKB(tidn), + .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), + .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), + .DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .ENA(act[w]), + .ENB(tidn), + .SSRA(nclk[1]), + .SSRB(tidn), + .WEA(write[w]), + .WEB(tidn) + ); + end //ax + + assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1]; + + end //aw + + assign data_out = data_out_l2; + + assign rd_act_d = |(read_act); // Use for data_out latch act + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(1'b1), + .thold_b(lcb_func_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(func_force), + .delay_lclkr(tri_lcb_delay_lclkr_dc), + .mpw1_b(tri_lcb_mpw1_dc_b), + .mpw2_b(tri_lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(1'b0), + .scout(func_scan_out), + .din(rd_act_d), + .dout(rd_act_l2) + ); + + tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_l2), + .thold_b(lcb_func_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(func_force), + .delay_lclkr(tri_lcb_delay_lclkr_dc), + .mpw1_b(tri_lcb_mpw1_dc_b), + .mpw2_b(tri_lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin({port_bitwidth*ways{1'b0}}), + .scout(unused_scout), + .din(data_out_d), + .dout(data_out_l2) + ); + + tri_plat #(.WIDTH(1)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din(lcb_sg_1), + .q(lcb_sg_0) + ); + + assign abst_scan_out = 2'b00; + assign time_scan_out = 1'b0; + assign repr_scan_out = 1'b0; + + assign bo_pc_failout = 2'b00; + assign bo_pc_diagloop = 2'b00; + + assign unused = | ({nclk[2:`NCLK_WIDTH-1], ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[1][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[2][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[3][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, lcb_act_dis_dc, scan_dis_dc_b, scan_diag_dc, bitw_abist, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, write_thru_en_dc, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_delay_lclkr_np_dc, ctrl_lcb_delay_lclkr_np_dc, dibw_lcb_delay_lclkr_np_dc, ctrl_lcb_mpw1_np_dc_b, dibw_lcb_mpw1_np_dc_b, lcb_mpw1_pp_dc_b, lcb_mpw1_2_pp_dc_b, aodo_lcb_delay_lclkr_dc, aodo_lcb_mpw1_dc_b, aodo_lcb_mpw2_dc_b, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, write_act, dob, dopb, unused_scout}); + end + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_512x16_1r1w_1.v b/rel/src/verilog/trilib/tri_512x16_1r1w_1.v new file mode 100644 index 0000000..62d3ca6 --- /dev/null +++ b/rel/src/verilog/trilib/tri_512x16_1r1w_1.v @@ -0,0 +1,333 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: Tri Array Wrapper +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_512x16_1r1w_1( + vdd, + vcs, + gnd, + nclk, + rd_act, + wr_act, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + func_scan_in, + func_scan_out, + lcb_sg_0, + lcb_sl_thold_0_b, + lcb_time_sl_thold_0, + lcb_abst_sl_thold_0, + lcb_ary_nsl_thold_0, + lcb_repr_sl_thold_0, + time_scan_in, + time_scan_out, + abst_scan_in, + abst_scan_out, + repr_scan_in, + repr_scan_out, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + wr_abst_act, + abist_rd0_adr, + rd0_abst_act, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + bw, + wr_adr, + rd_adr, + di, + do +); + parameter addressable_ports = 128; // number of addressable register in this array + parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 16; // bitwidth of ports + parameter ways = 1; // number of ways + + // POWER PINS + inout vdd; + inout vcs; + inout gnd; + + input [0:`NCLK_WIDTH-1] nclk; + + input rd_act; + input wr_act; + + // DC TEST PINS + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input [0:4] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:4] lcb_delay_lclkr_dc; + + input ccflush_dc; + input scan_dis_dc_b; + input scan_diag_dc; + input func_scan_in; + output func_scan_out; + + input lcb_sg_0; + input lcb_sl_thold_0_b; + input lcb_time_sl_thold_0; + input lcb_abst_sl_thold_0; + input lcb_ary_nsl_thold_0; + input lcb_repr_sl_thold_0; + input time_scan_in; + output time_scan_out; + input abst_scan_in; + output abst_scan_out; + input repr_scan_in; + output repr_scan_out; + + input [0:3] abist_di; + input abist_bw_odd; + input abist_bw_even; + input [0:6] abist_wr_adr; + input wr_abst_act; + input [0:6] abist_rd0_adr; + input rd0_abst_act; + input tc_lbist_ary_wrt_thru_dc; + input abist_ena_1; + input abist_g8t_rd0_comp_ena; + input abist_raw_dc_b; + input [0:3] obs0_abist_cmp; + + // BOLT-ON + input lcb_bolt_sl_thold_0; + input pc_bo_enable_2; // general bolt-on enable + input pc_bo_reset; // reset + input pc_bo_unload; // unload sticky bits + input pc_bo_repair; // execute sticky bit decode + input pc_bo_shdata; // shift data for timing write and diag loop + input pc_bo_select; // select for mask and hier writes + output bo_pc_failout; // fail/no-fix reg + output bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + + input [0:15] bw; + input [0:8] wr_adr; + input [0:8] rd_adr; + input [0:15] di; + + output [0:15] do; + + // Configuration Statement for NCsim + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire clk; + wire clk2x; + wire [0:8] b0addra; + wire [0:8] b0addrb; + wire wea; + wire web; + wire wren_a; + // Latches + reg reset_q; + reg gate_fq; + wire gate_d; + wire [0:35] r_data_out_1_d; + reg [0:35] r_data_out_1_fq; + wire [0:35] w_data_in_0; + + wire [0:35] r_data_out_0_bram; + wire [0:35] r_data_out_1_bram; + + wire toggle_d; + reg toggle_q; + wire toggle2x_d; + reg toggle2x_q; + + (* analysis_not_referenced="true" *) + wire unused; + + assign clk = nclk[0]; + assign clk2x = nclk[2]; + + always @(posedge clk) + begin: rlatch + reset_q <= nclk[1]; + end + + // + // NEW clk2x gate logic start + // + + always @(posedge clk) + begin: tlatch + if (reset_q == 1'b1) + toggle_q <= 1'b1; + else + toggle_q <= toggle_d; + end + + always @(posedge clk2x) + begin: flatch + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + r_data_out_1_fq <= r_data_out_1_d; + end + + assign toggle_d = (~toggle_q); + assign toggle2x_d = toggle_q; + + // should force gate_fq to be on during odd 2x clock (second half of 1x clock). + //gate_d <= toggle_q xor toggle2x_q; + // if you want the first half do the following + assign gate_d = (~(toggle_q ^ toggle2x_q)); + + // + // NEW clk2x gate logic end + // + + assign b0addra[0:8] = wr_adr; + assign b0addrb[0:8] = rd_adr; + + // Unused Address Bits + //b0addra(0 to 1) <= "00"; + //b0addrb(0 to 1) <= "00"; + + // port a is a read-modify-write port + assign wren_a = ((bw != 16'b0000000000000000) & (wr_act == 1'b1)) ? 1'b1 : + 1'b0; + assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk + assign web = 1'b0; + assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] : + r_data_out_0_bram[0]; + assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] : + r_data_out_0_bram[1]; + assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] : + r_data_out_0_bram[2]; + assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] : + r_data_out_0_bram[3]; + assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] : + r_data_out_0_bram[4]; + assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] : + r_data_out_0_bram[5]; + assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] : + r_data_out_0_bram[6]; + assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] : + r_data_out_0_bram[7]; + assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] : + r_data_out_0_bram[8]; + assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] : + r_data_out_0_bram[9]; + assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] : + r_data_out_0_bram[10]; + assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] : + r_data_out_0_bram[11]; + assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] : + r_data_out_0_bram[12]; + assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] : + r_data_out_0_bram[13]; + assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] : + r_data_out_0_bram[14]; + assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] : + r_data_out_0_bram[15]; + assign w_data_in_0[16:35] = 20'b0; + + assign r_data_out_1_d = r_data_out_1_bram; + + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram0a( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(reset_q), + .SSRB(reset_q), + .ADDRA(b0addra), + .ADDRB(b0addrb), + .DIA(w_data_in_0[0:31]), + .DIB(32'b0), + .DOA(r_data_out_0_bram[0:31]), + .DOB(r_data_out_1_bram[0:31]), + .DOPA(r_data_out_0_bram[32:35]), + .DOPB(r_data_out_1_bram[32:35]), + .DIPA(w_data_in_0[32:35]), + .DIPB(4'h0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(wea), + .WEB(web) + ); + + assign do = r_data_out_1_fq[0:15]; + + assign func_scan_out = func_scan_in; + assign time_scan_out = time_scan_in; + assign abst_scan_out = abst_scan_in; + assign repr_scan_out = repr_scan_in; + + assign bo_pc_failout = 1'b0; + assign bo_pc_diagloop = 1'b0; + + assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, + lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, + abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, + tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, + lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, + pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_fq[16:35]}; +endmodule diff --git a/rel/src/verilog/trilib/tri_64x144_1r1w.v b/rel/src/verilog/trilib/tri_64x144_1r1w.v new file mode 100644 index 0000000..4c52f53 --- /dev/null +++ b/rel/src/verilog/trilib/tri_64x144_1r1w.v @@ -0,0 +1,427 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_64x144_1r1w.v +// *! DESCRIPTION : 64 Entry x 144 bit array, 9 bit writeable +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_64x144_1r1w( + gnd, + vdd, + vcs, + nclk, + rd_act, + wr_act, + sg_0, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + func_sl_force, + func_sl_thold_0_b, + g8t_clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + write_enable, + addr_wr, + data_in, + addr_rd, + data_out +); +parameter addressable_ports = 64; // number of addressable register in this array +parameter addressbus_width = 6; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) +parameter port_bitwidth = 144; // bitwidth of ports (per way) +parameter bit_write_type = 9; // gives the number of bits that shares one write-enable; must divide evenly into array +parameter ways = 1; // number of ways + +// POWER PINS +inout gnd; +inout vdd; +inout vcs; + +// CLOCK and CLOCKCONTROL ports +input [0:`NCLK_WIDTH-1] nclk; +input rd_act; +input wr_act; +input sg_0; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input func_sl_force; +input func_sl_thold_0_b; +input g8t_clkoff_dc_b; +input ccflush_dc; +input scan_dis_dc_b; +input scan_diag_dc; +input g8t_d_mode_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input [0:4] g8t_delay_lclkr_dc; +input d_mode_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input delay_lclkr_dc; + +// ABIST +input wr_abst_act; +input rd0_abst_act; +input [0:3] abist_di; +input abist_bw_odd; +input abist_bw_even; +input [0:addressbus_width-1] abist_wr_adr; +input [0:addressbus_width-1] abist_rd0_adr; +input tc_lbist_ary_wrt_thru_dc; +input abist_ena_1; +input abist_g8t_rd0_comp_ena; +input abist_raw_dc_b; +input [0:3] obs0_abist_cmp; + +// Scan +input abst_scan_in; +input time_scan_in; +input repr_scan_in; +input func_scan_in; +output abst_scan_out; +output time_scan_out; +output repr_scan_out; +output func_scan_out; + +// BOLT-ON +input lcb_bolt_sl_thold_0; +input pc_bo_enable_2; // general bolt-on enable +input pc_bo_reset; // reset +input pc_bo_unload; // unload sticky bits +input pc_bo_repair; // execute sticky bit decode +input pc_bo_shdata; // shift data for timing write and diag loop +input [0:1] pc_bo_select; // select for mask and hier writes +output [0:1] bo_pc_failout; // fail/no-fix reg +output [0:1] bo_pc_diagloop; +input tri_lcb_mpw1_dc_b; +input tri_lcb_mpw2_dc_b; +input tri_lcb_delay_lclkr_dc; +input tri_lcb_clkoff_dc_b; +input tri_lcb_act_dis_dc; + +// Write Ports +input write_enable; +input [0:addressbus_width-1] addr_wr; +input [0:port_bitwidth-1] data_in; + +// Read Ports +input [0:addressbus_width-1] addr_rd; +output [0:port_bitwidth-1] data_out; + +// tri_64x144_1r1w + +// Configuration Statement for NCsim +//for all:RAMB36 use entity unisim.RAMB36; + +parameter data_width = ((((port_bitwidth - 1)/36) + 1) * 36) - 1; +parameter rd_act_offset = 0; +parameter data_out_offset = rd_act_offset + 1; +parameter scan_right = data_out_offset + port_bitwidth - 1; + +wire [0:data_width-(data_width/9)-1] ramb_data_in; +wire [0:data_width/9] ramb_par_in; +wire [0:data_width-(data_width/9)-1] ramb_data_out; +wire [0:data_width/9] ramb_par_out; +wire [0:data_width-(data_width/9)-1] ramb_data_dummy; +wire [0:data_width/9] ramb_par_dummy; +wire [0:15] ramb_wr_addr; +wire [0:15] ramb_rd_addr; +wire [0:data_width] data_in_pad; +wire [0:data_width] data_out_pad; +wire [0:((port_bitwidth-1)/36)] cascadeoutlata; +wire [0:((port_bitwidth-1)/36)] cascadeoutlatb; +wire [0:((port_bitwidth-1)/36)] cascadeoutrega; +wire [0:((port_bitwidth-1)/36)] cascadeoutregb; +wire rd_act_d; +wire rd_act_q; +wire [0:port_bitwidth-1] data_out_d; +wire [0:port_bitwidth-1] data_out_q; + +wire tiup; +wire tidn; +wire [0:(((((port_bitwidth-1)/36)+1)*36)/9)-1] wrt_en; +wire act; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +(* analysis_not_referenced="true" *) +wire unused; + +generate begin + assign tiup = 1'b1; + assign tidn = 1'b0; + assign wrt_en = {(((((port_bitwidth-1)/36)+1)*36)/9){write_enable}}; + assign act = rd_act | wr_act; + assign rd_act_d = rd_act; + + assign ramb_wr_addr[0] = 1'b0; + assign ramb_wr_addr[11:15] = 5'b0; + assign ramb_rd_addr[0] = 1'b0; + assign ramb_rd_addr[11:15] = 5'b0; + + genvar addr; + for (addr = 0; addr < 10; addr = addr + 1) begin : padA0 + if (addr < 10 - addressbus_width) + begin + assign ramb_wr_addr[addr + 1] = 1'b0; + assign ramb_rd_addr[addr + 1] = 1'b0; + end + if (addr >= 10 - addressbus_width) + begin + assign ramb_wr_addr[addr + 1] = addr_wr[addr - (10 - addressbus_width)]; + assign ramb_rd_addr[addr + 1] = addr_rd[addr - (10 - addressbus_width)]; + end + end + + // PORTA => Used for Writing + // PORTB => Used for Reading + genvar arr; + for (arr = 0; arr <= (port_bitwidth - 1)/36; arr = arr + 1) + begin : padD0 + genvar bit; + for (bit = 0; bit < 36; bit = bit + 1) + begin : numBit + if ((arr * 36) + bit < port_bitwidth) + begin + assign data_in_pad[(arr * 36) + bit] = data_in[(arr * 36) + bit]; + end + if ((arr * 36) + bit >= port_bitwidth) + begin + assign data_in_pad[(arr * 36) + bit] = 1'b0; + end + end + end + + genvar byte; + for (byte = 0; byte <= (data_width)/9; byte = byte + 1) + begin : dInFixUp + assign ramb_data_in[byte * 8:(byte * 8) + 7] = data_in_pad[(byte * 8) + byte:(byte * 8) + 7 + byte]; + assign ramb_par_in[byte] = data_in_pad[(byte * 8) + byte + 8]; + end + + //genvar byte; + for (byte = 0; byte <= (data_width)/9; byte = byte + 1) + begin : dOutFixUp + assign data_out_pad[(byte * 8) + byte:(byte * 8) + 7 + byte] = ramb_data_out[byte * 8:(byte * 8) + 7]; + assign data_out_pad[(byte * 8) + byte + 8] = ramb_par_out[byte]; + end + + genvar anum; + for (anum = 0; anum <= (port_bitwidth - 1)/36; anum = anum + 1) + begin : arrNum + + RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) ARR( + .CASCADEOUTLATA(cascadeoutlata[anum]), + .CASCADEOUTLATB(cascadeoutlatb[anum]), + .CASCADEOUTREGA(cascadeoutrega[anum]), + .CASCADEOUTREGB(cascadeoutregb[anum]), + .DOA(ramb_data_dummy[(32 * anum):31 + (32 * anum)]), + .DOB(ramb_data_out[(32 * anum):31 + (32 * anum)]), + .DOPA(ramb_par_dummy[(4 * anum):3 + (4 * anum)]), + .DOPB(ramb_par_out[(4 * anum):3 + (4 * anum)]), + .ADDRA(ramb_wr_addr), + .ADDRB(ramb_rd_addr), + .CASCADEINLATA(1'b0), + .CASCADEINLATB(1'b0), + .CASCADEINREGA(1'b0), + .CASCADEINREGB(1'b0), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in[(32 * anum):31 + (32 * anum)]), + .DIB(32'b0), + .DIPA(ramb_par_in[(4 * anum):3 + (4 * anum)]), + .DIPB(4'b0), + .ENA(act), + .ENB(act), + .REGCEA(1'b0), + .REGCEB(1'b0), + .SSRA(nclk[1]), //sreset + .SSRB(nclk[1]), + .WEA(wrt_en[anum * 4:anum * 4 + 3]), + .WEB(4'b0) //' + ); + end + assign data_out_d = data_out_pad[0:port_bitwidth - 1]; + assign data_out = data_out_q; + + assign abst_scan_out = tidn; + assign time_scan_out = tidn; + assign repr_scan_out = tidn; + assign bo_pc_failout = 2'b00; + assign bo_pc_diagloop = 2'b00; +end +endgenerate + +assign unused = | { + cascadeoutlata , + cascadeoutlatb , + cascadeoutrega , + cascadeoutregb , + ramb_data_dummy , + ramb_par_dummy , + nclk[2:`NCLK_WIDTH-1] , + gnd , + vdd , + vcs , + sg_0 , + abst_sl_thold_0 , + ary_nsl_thold_0 , + time_sl_thold_0 , + repr_sl_thold_0 , + g8t_clkoff_dc_b , + ccflush_dc , + scan_dis_dc_b , + scan_diag_dc , + g8t_d_mode_dc , + g8t_mpw1_dc_b , + g8t_mpw2_dc_b , + g8t_delay_lclkr_dc , + wr_abst_act , + rd0_abst_act , + abist_di , + abist_bw_odd , + abist_bw_even , + abist_wr_adr , + abist_rd0_adr , + tc_lbist_ary_wrt_thru_dc , + abist_ena_1 , + abist_g8t_rd0_comp_ena , + abist_raw_dc_b , + obs0_abist_cmp , + abst_scan_in , + time_scan_in , + repr_scan_in , + lcb_bolt_sl_thold_0 , + pc_bo_enable_2 , + pc_bo_reset , + pc_bo_unload , + pc_bo_repair , + pc_bo_shdata , + pc_bo_select , + tri_lcb_mpw1_dc_b , + tri_lcb_mpw2_dc_b , + tri_lcb_delay_lclkr_dc , + tri_lcb_clkoff_dc_b , + tri_lcb_act_dis_dc }; + +// #################################################### +// Registers +// #################################################### +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rd_act_offset]), + .scout(sov[rd_act_offset]), + .din(rd_act_d), + .dout(rd_act_q) +); + +tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[data_out_offset:data_out_offset + port_bitwidth - 1]), + .scout(sov[data_out_offset:data_out_offset + port_bitwidth - 1]), + .din(data_out_d), + .dout(data_out_q) +); + +assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; +assign func_scan_out = sov[0]; + +endmodule diff --git a/rel/src/verilog/trilib/tri_64x34_8w_1r1w.v b/rel/src/verilog/trilib/tri_64x34_8w_1r1w.v new file mode 100644 index 0000000..db70155 --- /dev/null +++ b/rel/src/verilog/trilib/tri_64x34_8w_1r1w.v @@ -0,0 +1,621 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_64x34_8w_1r1w.vhdl +// *! DESCRIPTION : 32 entry x 35 bit x 8 way array +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_64x34_8w_1r1w( + gnd, + vdd, + vcs, + nclk, + rd_act, + wr_act, + sg_0, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + func_sl_force, + func_sl_thold_0_b, + g8t_clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + write_enable, + way, + addr_wr, + data_in, + addr_rd_01, + addr_rd_23, + addr_rd_45, + addr_rd_67, + data_out +); +parameter addressable_ports = 64; // number of addressable register in this array +parameter addressbus_width = 6; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) +parameter port_bitwidth = 34; // bitwidth of ports +parameter ways = 8; // number of ways +// POWER PINS +inout gnd; +inout vdd; +inout vcs; + +// CLOCK and CLOCKCONTROL ports +input [0:`NCLK_WIDTH-1] nclk; +input rd_act; +input wr_act; +input sg_0; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input func_sl_force; +input func_sl_thold_0_b; +input g8t_clkoff_dc_b; +input ccflush_dc; +input scan_dis_dc_b; +input scan_diag_dc; +input g8t_d_mode_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input [0:4] g8t_delay_lclkr_dc; +input d_mode_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input delay_lclkr_dc; + +// ABIST +input wr_abst_act; +input rd0_abst_act; +input [0:3] abist_di; +input abist_bw_odd; +input abist_bw_even; +input [0:addressbus_width-1] abist_wr_adr; +input [0:addressbus_width-1] abist_rd0_adr; +input tc_lbist_ary_wrt_thru_dc; +input abist_ena_1; +input abist_g8t_rd0_comp_ena; +input abist_raw_dc_b; +input [0:3] obs0_abist_cmp; + +// SCAN +input abst_scan_in; +input time_scan_in; +input repr_scan_in; +input func_scan_in; +output abst_scan_out; +output time_scan_out; +output repr_scan_out; +output func_scan_out; + +// BOLT-ON +input lcb_bolt_sl_thold_0; +input pc_bo_enable_2; // general bolt-on enable +input pc_bo_reset; // reset +input pc_bo_unload; // unload sticky bits +input pc_bo_repair; // execute sticky bit decode +input pc_bo_shdata; // shift data for timing write and diag loop +input [0:3] pc_bo_select; // select for mask and hier writes +output [0:3] bo_pc_failout; // fail/no-fix reg +output [0:3] bo_pc_diagloop; +input tri_lcb_mpw1_dc_b; +input tri_lcb_mpw2_dc_b; +input tri_lcb_delay_lclkr_dc; +input tri_lcb_clkoff_dc_b; +input tri_lcb_act_dis_dc; + +// Write Ports +input [0:3] write_enable; +input [0:ways-1] way; +input [0:addressbus_width-1] addr_wr; +input [0:port_bitwidth-1] data_in; + +// Read Ports +input [0:addressbus_width-1] addr_rd_01; +input [0:addressbus_width-1] addr_rd_23; +input [0:addressbus_width-1] addr_rd_45; +input [0:addressbus_width-1] addr_rd_67; +output [0:port_bitwidth*ways-1] data_out; + +// tri_64x34_8w_1r1w +parameter ramb_base_addr = 16; +parameter dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1; +parameter numBytes = (dataWidth/9); + +// Configuration Statement for NCsim +//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; +parameter rd_act_offset = 0; +parameter data_out_offset = rd_act_offset + 1; +parameter scan_right = data_out_offset + (ways*port_bitwidth) - 1; + +wire [0:35] ramb_data_in; +wire [0:35] ramb_data_p0_out[0:ways-1]; +wire [0:(dataWidth+1)*ways-1] ramb_data_p0_concat; +wire [0:ramb_base_addr-1] ramb_addr_rd1; +wire [0:ramb_base_addr-1] ramb_addr_wr_rd0; + +wire [0:ramb_base_addr-1] rd_addr0; +wire [0:ramb_base_addr-1] wr_addr; +wire write_en; +wire [0:3] write_enable_way[0:ways-1]; +wire [0:(dataWidth-numBytes)-1] arr_data_in; +wire [0:numBytes] arr_par_in; +wire [0:(dataWidth-numBytes)-1] arr_data_out[0:ways-1]; +wire [0:numBytes] arr_par_out[0:ways-1]; +wire [0:dataWidth] arr_data_out_pad[0:ways-1]; +wire [0:(dataWidth+1)*ways-1] arr_data_concat; +wire [0:port_bitwidth*ways-1] data_out_d; +wire [0:port_bitwidth*ways-1] data_out_q; +wire [0:ways-1] cascadeoutlata; +wire [0:ways-1] cascadeoutlatb; +wire [0:ways-1] cascadeoutrega; +wire [0:ways-1] cascadeoutregb; +wire rd_act_d; +wire rd_act_q; + +(* analysis_not_referenced="true" *) +wire unused; +wire tiup; +wire [0:35] tidn; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +generate begin + + assign tiup = 1'b1; + assign tidn = 36'b0; + + // Data Generate + genvar t; + for (t = 0; t < 36; t = t + 1) + begin : addr_calc + if (t < 35 - (port_bitwidth - 1)) + begin + assign ramb_data_in[t] = 1'b0; + end + if (t >= 35 - (port_bitwidth - 1)) + begin + assign ramb_data_in[t] = data_in[t - (35 - (port_bitwidth - 1))]; + end + end + + genvar byte; + for (byte = 0; byte <= numBytes; byte = byte + 1) begin : dFixUp + assign arr_data_in[byte*8:(byte*8)+7] = ramb_data_in[(byte * 8)+byte:(((byte*8)+7)+byte)]; + assign arr_par_in[byte] = ramb_data_in[(((byte*8)+byte)+8)]; + genvar numWays; + for (numWays=0; numWays= 9 - addressbus_width) begin + assign rd_addr0[t+2] = addr_rd_01[t - (9 - addressbus_width)]; + assign wr_addr[t+2] = addr_wr[t - (9 - addressbus_width)]; + end + end + + genvar numWays; + for (numWays=0; numWays 16K L1D$, 15 => 32K L1D$ +`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE +`define LMQ_ENTRIES 8 +`define LMQ_ENTRIES_ENC 3 +`define LGQ_ENTRIES 8 +`define AXU_SPARE_ENC 3 +`define RV_FX0_ENTRIES 12 +`define RV_FX1_ENTRIES 12 +`define RV_LQ_ENTRIES 16 +`define RV_AXU0_ENTRIES 12 +`define RV_AXU1_ENTRIES 0 +`define RV_FX0_ENTRIES_ENC 4 +`define RV_FX1_ENTRIES_ENC 4 +`define RV_LQ_ENTRIES_ENC 4 +`define RV_AXU0_ENTRIES_ENC 4 +`define RV_AXU1_ENTRIES_ENC 1 +`define UCODE_ENTRIES 8 +`define UCODE_ENTRIES_ENC 3 +`define FXU1_ENABLE 1 +`define TYPE_WIDTH 3 +`define IBUFF_INSTR_WIDTH 70 +`define IBUFF_IFAR_WIDTH 20 +`define IBUFF_DEPTH 16 +`define PF_IAR_BITS 12 // number of IAR bits used by prefetch +`define FXU0_PIPE_START 1 +`define FXU0_PIPE_END 8 +`define FXU1_PIPE_START 1 +`define FXU1_PIPE_END 5 +`define LQ_LOAD_PIPE_START 4 +`define LQ_LOAD_PIPE_END 8 +`define LQ_REL_PIPE_START 2 +`define LQ_REL_PIPE_END 4 +`define LOAD_CREDITS 8 +`define STORE_CREDITS 4 +`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size +`define MMQ_ENTRIES 2 // MMU Queue Size +`define CR_WIDTH 4 +`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch +`define PF_IFAR_WIDTH 12 +`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch +`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +`define PFETCH_Q_SIZE 8 // number of entries +`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) +`define XER_WIDTH 10 +`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +`define INIT_IUCR0 16'h00FA // BP enabled +`define INIT_MASK 2'b10 +`define RELQ_INCLUDE 0 // Reload Queue Included + +`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1 + +// IERAT boot config entry values +`define IERAT_BCFG_EPN_0TO15 0 +`define IERAT_BCFG_EPN_16TO31 0 +`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G +`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define IERAT_BCFG_ATTR 0 // u0-u3, endian + +// DERAT boot config entry values +`define DERAT_BCFG_EPN_0TO15 0 +`define DERAT_BCFG_EPN_16TO31 0 +`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G +`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define DERAT_BCFG_ATTR 0 // u0-u3, endian + +// Do NOT add any defines below this line +`endif //_tri_a2o_vh_ diff --git a/rel/src/verilog/trilib/tri_addrcmp.v b/rel/src/verilog/trilib/tri_addrcmp.v new file mode 100644 index 0000000..965d970 --- /dev/null +++ b/rel/src/verilog/trilib/tri_addrcmp.v @@ -0,0 +1,101 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Address Decoder +// +//***************************************************************************** + +module tri_addrcmp( + enable_lsb, + d0, + d1, + eq +); + + input enable_lsb; // when "0" the LSB is disabled + input [0:35] d0; + input [0:35] d1; + output eq; + + // tri_addrcmp + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:35] eq01_b; + wire [0:18] eq02; + wire [0:9] eq04_b; + wire [0:4] eq08; + wire [0:1] eq24_b; + + assign eq01_b[0:35] = (d0[0:35] ^ d1[0:35]); + + assign eq02[0] = (~(eq01_b[0] | eq01_b[1])); + assign eq02[1] = (~(eq01_b[2] | eq01_b[3])); + assign eq02[2] = (~(eq01_b[4] | eq01_b[5])); + assign eq02[3] = (~(eq01_b[6] | eq01_b[7])); + assign eq02[4] = (~(eq01_b[8] | eq01_b[9])); + assign eq02[5] = (~(eq01_b[10] | eq01_b[11])); + assign eq02[6] = (~(eq01_b[12] | eq01_b[13])); + assign eq02[7] = (~(eq01_b[14] | eq01_b[15])); + assign eq02[8] = (~(eq01_b[16] | eq01_b[17])); + assign eq02[9] = (~(eq01_b[18] | eq01_b[19])); + assign eq02[10] = (~(eq01_b[20] | eq01_b[21])); + assign eq02[11] = (~(eq01_b[22] | eq01_b[23])); + assign eq02[12] = (~(eq01_b[24] | eq01_b[25])); + assign eq02[13] = (~(eq01_b[26] | eq01_b[27])); + assign eq02[14] = (~(eq01_b[28] | eq01_b[29])); + assign eq02[15] = (~(eq01_b[30] | eq01_b[31])); + assign eq02[16] = (~(eq01_b[32] | eq01_b[33])); + assign eq02[17] = (~(eq01_b[34])); + assign eq02[18] = (~(eq01_b[35] & enable_lsb)); + + assign eq04_b[0] = (~(eq02[0] & eq02[1])); + assign eq04_b[1] = (~(eq02[2] & eq02[3])); + assign eq04_b[2] = (~(eq02[4] & eq02[5])); + assign eq04_b[3] = (~(eq02[6] & eq02[7])); + assign eq04_b[4] = (~(eq02[8] & eq02[9])); + assign eq04_b[5] = (~(eq02[10] & eq02[11])); + assign eq04_b[6] = (~(eq02[12] & eq02[13])); + assign eq04_b[7] = (~(eq02[14] & eq02[15])); + assign eq04_b[8] = (~(eq02[16] & eq02[17])); + assign eq04_b[9] = (~(eq02[18])); + + assign eq08[0] = (~(eq04_b[0] | eq04_b[1])); + assign eq08[1] = (~(eq04_b[2] | eq04_b[3])); + assign eq08[2] = (~(eq04_b[4] | eq04_b[5])); + assign eq08[3] = (~(eq04_b[6] | eq04_b[7])); + assign eq08[4] = (~(eq04_b[8] | eq04_b[9])); + + assign eq24_b[0] = (~(eq08[0] & eq08[1] & eq08[2])); + assign eq24_b[1] = (~(eq08[3] & eq08[4])); + + assign eq = (~(eq24_b[0] | eq24_b[1])); // output +endmodule diff --git a/rel/src/verilog/trilib/tri_agecmp.v b/rel/src/verilog/trilib/tri_agecmp.v new file mode 100644 index 0000000..dd41064 --- /dev/null +++ b/rel/src/verilog/trilib/tri_agecmp.v @@ -0,0 +1,60 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Prioritizer +// +//***************************************************************************** + +module tri_agecmp( + a, + b, + a_newer_b +); + parameter SIZE = 8; + + input [0:SIZE-1] a; + input [0:SIZE-1] b; + output a_newer_b; + + // tri_agecmp + + wire a_lt_b; + wire a_gte_b; + wire cmp_sel; + + assign a_lt_b = (a[1:SIZE - 1] < b[1:SIZE - 1]) ? 1'b1 : + 1'b0; + + assign a_gte_b = (~a_lt_b); + + assign cmp_sel = a[0] ~^ b[0]; + + assign a_newer_b = (a_lt_b & (~cmp_sel)) | (a_gte_b & cmp_sel); +endmodule diff --git a/rel/src/verilog/trilib/tri_aoi21.v b/rel/src/verilog/trilib/tri_aoi21.v new file mode 100644 index 0000000..0038adc --- /dev/null +++ b/rel/src/verilog/trilib/tri_aoi21.v @@ -0,0 +1,68 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nand2.v +// *! DESCRIPTION : Three input, AOI21 gate +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_aoi21( + y, + a0, + a1, + b0 +); + parameter WIDTH = 1; + parameter BTR = "AOI21_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a0; + input [0:WIDTH-1] a1; + input [0:WIDTH-1] b0; + + // tri_aoi21 + genvar i; + wire [0:WIDTH-1] outA; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + and I0(outA[i], a0[i], a1[i]); + nor I2(y[i], outA[i], b0[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_aoi22.v b/rel/src/verilog/trilib/tri_aoi22.v new file mode 100644 index 0000000..729a54b --- /dev/null +++ b/rel/src/verilog/trilib/tri_aoi22.v @@ -0,0 +1,73 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_aoi22.v +// *! DESCRIPTION : AOI22 gate +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_aoi22( + y, + a0, + a1, + b0, + b1 +); + parameter WIDTH = 1; + parameter BTR = "AOI22_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a0; + input [0:WIDTH-1] a1; + input [0:WIDTH-1] b0; + input [0:WIDTH-1] b1; + + // tri_aoi22 + genvar i; + wire [0:WIDTH-1] outA; + wire [0:WIDTH-1] outB; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + and I0(outA[i], a0[i], a1[i]); + and I1(outB[i], b0[i], b1[i]); + nor I2(y[i], outA[i], outB[i]); + + + end // block: w + end + + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_aoi22_nlats_wlcb.v b/rel/src/verilog/trilib/tri_aoi22_nlats_wlcb.v new file mode 100644 index 0000000..9b8e8b6 --- /dev/null +++ b/rel/src/verilog/trilib/tri_aoi22_nlats_wlcb.v @@ -0,0 +1,145 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_aoi22_nlats_wlcb.v +// *! DESCRIPTION : Multi-bit aoi22-latch, LCB included +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_aoi22_nlats_wlcb( + vd, + gd, + nclk, + act, + force_t, + thold_b, + d_mode, + sg, + delay_lclkr, + mpw1_b, + mpw2_b, + scin, + scout, + a1, + a2, + b1, + b2, + qb +); + + parameter WIDTH = 4; + parameter OFFSET = 0; //starting bit + parameter INIT = 0; // will be converted to the least signficant + // 31 bits of init_v + parameter IBUF = 1'b0; //inverted latch IOs, if set to true. + parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius + parameter NEEDS_SRESET = 1; // for inferred latches + parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch; + //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4 + parameter SYNTHCLONEDLATCH = ""; + parameter BTR = "NLL0001_X2_A12TH"; + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] nclk; + input act; // 1: functional, 0: no clock + input force_t; // 1: force LCB active + input thold_b; // 1: functional, 0: no clock + input d_mode; // 1: disable pulse mode, 0: pulse mode + input sg; // 0: functional, 1: scan + input delay_lclkr; // 0: functional + input mpw1_b; // pulse width control bit + input mpw2_b; // pulse width control bit + input [OFFSET:OFFSET+WIDTH-1] scin; // scan in + output [OFFSET:OFFSET+WIDTH-1] scout; + input [OFFSET:OFFSET+WIDTH-1] a1; + input [OFFSET:OFFSET+WIDTH-1] a2; + input [OFFSET:OFFSET+WIDTH-1] b1; + input [OFFSET:OFFSET+WIDTH-1] b2; + output [OFFSET:OFFSET+WIDTH-1] qb; + + // tri_aoi22_nlats_wlcb + + parameter [0:WIDTH-1] init_v = INIT; + parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + wire [0:WIDTH-1] din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = nclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + + assign din = (a1 & a2) | (b1 & b2); // Output is inverted, so just AND-OR here + assign int_din = (vsreset_b & din) | (vsreset & init_v); + + assign vact = {WIDTH{act | force_t}}; + assign vact_b = {WIDTH{~(act | force_t)}}; + + assign vthold_b = {WIDTH{thold_b}}; + assign vthold = {WIDTH{~thold_b}}; + + + always @(posedge nclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + + assign qb = (~int_dout); + + assign scout = ZEROS; + + assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk) | (|scin); + end + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_bht_1024x8_1r1w.v b/rel/src/verilog/trilib/tri_bht_1024x8_1r1w.v new file mode 100644 index 0000000..e13a0f0 --- /dev/null +++ b/rel/src/verilog/trilib/tri_bht_1024x8_1r1w.v @@ -0,0 +1,577 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for tri_bht_1024x8_1r1w +// +// ********************************************************************* + +(* block_type="soft" *) +(* recursive_synthesis="2" *) +(* pin_default_power_domain="vdd" *) +(* pin_default_ground_domain ="gnd" *) + +`include "tri_a2o.vh" + +module tri_bht_1024x8_1r1w( + gnd, + vdd, + vcs, + nclk, + pc_iu_func_sl_thold_2, + pc_iu_sg_2, + pc_iu_time_sl_thold_2, + pc_iu_abst_sl_thold_2, + pc_iu_ary_nsl_thold_2, + pc_iu_repr_sl_thold_2, + pc_iu_bolt_sl_thold_2, + tc_ac_ccflush_dc, + tc_ac_scan_dis_dc_b, + clkoff_b, + scan_diag_dc, + act_dis, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + g8t_clkoff_b, + g8t_d_mode, + g8t_delay_lclkr, + g8t_mpw1_b, + g8t_mpw2_b, + func_scan_in, + time_scan_in, + abst_scan_in, + repr_scan_in, + func_scan_out, + time_scan_out, + abst_scan_out, + repr_scan_out, + pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0, + pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0, + pc_iu_abist_g8t1p_renb_0, + an_ac_lbist_ary_wrt_thru_dc, + pc_iu_abist_ena_dc, + pc_iu_abist_wl128_comp_ena, + pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp, + pc_iu_bo_enable_2, + pc_iu_bo_reset, + pc_iu_bo_unload, + pc_iu_bo_repair, + pc_iu_bo_shdata, + pc_iu_bo_select, + iu_pc_bo_fail, + iu_pc_bo_diagout, + r_act, + w_act, + r_addr, + w_addr, + data_in, + data_out0, + data_out1, + data_out2, + data_out3, + pc_iu_init_reset +); + // power pins + inout gnd; + inout vdd; + inout vcs; + + // clock and clockcontrol ports + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_2; + input pc_iu_sg_2; + input pc_iu_time_sl_thold_2; + input pc_iu_abst_sl_thold_2; + input pc_iu_ary_nsl_thold_2; + input pc_iu_repr_sl_thold_2; + input pc_iu_bolt_sl_thold_2; + input tc_ac_ccflush_dc; + input tc_ac_scan_dis_dc_b; + input clkoff_b; + input scan_diag_dc; + input act_dis; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input g8t_clkoff_b; + input g8t_d_mode; + input [0:4] g8t_delay_lclkr; + input [0:4] g8t_mpw1_b; + input g8t_mpw2_b; + input func_scan_in; + input time_scan_in; + input abst_scan_in; + input repr_scan_in; + output func_scan_out; + output time_scan_out; + output abst_scan_out; + output repr_scan_out; + + input [0:3] pc_iu_abist_di_0; + input pc_iu_abist_g8t_bw_1; + input pc_iu_abist_g8t_bw_0; + input [3:9] pc_iu_abist_waddr_0; + input pc_iu_abist_g8t_wenb; + input [3:9] pc_iu_abist_raddr_0; + input pc_iu_abist_g8t1p_renb_0; + input an_ac_lbist_ary_wrt_thru_dc; + input pc_iu_abist_ena_dc; + input pc_iu_abist_wl128_comp_ena; + input pc_iu_abist_raw_dc_b; + input [0:3] pc_iu_abist_g8t_dcomp; + + // BOLT-ON + input pc_iu_bo_enable_2; // general bolt-on enable + input pc_iu_bo_reset; // reset + input pc_iu_bo_unload; // unload sticky bits + input pc_iu_bo_repair; // execute sticky bit decode + input pc_iu_bo_shdata; // shift data for timing write and diag loop + input pc_iu_bo_select; // select for mask and hier writes + output iu_pc_bo_fail; // fail/no-fix reg + output iu_pc_bo_diagout; + + // ports + input r_act; + input [0:3] w_act; + input [0:9] r_addr; + input [0:9] w_addr; + input [0:1] data_in; + output [0:1] data_out0; + output [0:1] data_out1; + output [0:1] data_out2; + + output [0:1] data_out3; + + input pc_iu_init_reset; + + //-------------------------- + // constants + //-------------------------- + + + parameter data_in_offset = 0; + parameter w_act_offset = data_in_offset + 2; + parameter r_act_offset = w_act_offset + 4; + parameter w_addr_offset = r_act_offset + 1; + parameter r_addr_offset = w_addr_offset + 10; + parameter data_out_offset = r_addr_offset + 10; + parameter reset_w_addr_offset = data_out_offset + 8; + parameter array_offset = reset_w_addr_offset + 9; + parameter scan_right = array_offset + 1 - 1; + + //-------------------------- + // signals + //-------------------------- + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_time_sl_thold_1; + wire pc_iu_time_sl_thold_0; + wire pc_iu_ary_nsl_thold_1; + wire pc_iu_ary_nsl_thold_0; + wire pc_iu_abst_sl_thold_1; + wire pc_iu_abst_sl_thold_0; + wire pc_iu_repr_sl_thold_1; + wire pc_iu_repr_sl_thold_0; + wire pc_iu_bolt_sl_thold_1; + wire pc_iu_bolt_sl_thold_0; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tiup; + + wire [0:7] data_out_d; + wire [0:7] data_out_q; + + wire ary_w_en; + wire [0:8] ary_w_addr; + wire [0:15] ary_w_sel; + wire [0:15] ary_w_data; + + wire ary_r_en; + wire [0:8] ary_r_addr; + wire [0:15] ary_r_data; + + wire [0:7] data_out; + wire [0:3] write_thru; + + wire [0:1] data_in_d; + wire [0:1] data_in_q; + wire [0:3] w_act_d; + wire [0:3] w_act_q; + wire r_act_d; + wire r_act_q; + wire [0:9] w_addr_d; + wire [0:9] w_addr_q; + wire [0:9] r_addr_d; + wire [0:9] r_addr_q; + + wire lat_wi_act; + wire lat_ri_act; + wire lat_ro_act; + + wire reset_act; + wire [0:8] reset_w_addr_d; + wire [0:8] reset_w_addr_q; + + + assign tiup = 1'b1; + + assign reset_act = pc_iu_init_reset; + assign reset_w_addr_d[0:8] = reset_w_addr_q[0:8] + 9'b000000001; + + assign data_out0[0:1] = data_out_q[0:1]; + assign data_out1[0:1] = data_out_q[2:3]; + assign data_out2[0:1] = data_out_q[4:5]; + assign data_out3[0:1] = data_out_q[6:7]; + + assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[1:9] == r_addr[1:9]) & r_act == 1'b1))); + + assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[1:9]; + + assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b0; + assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b0; + assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b0; + assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b0; + assign ary_w_sel[4] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b0; + assign ary_w_sel[5] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b0; + assign ary_w_sel[6] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b0; + assign ary_w_sel[7] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b0; + assign ary_w_sel[8] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b1; + assign ary_w_sel[9] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b1; + assign ary_w_sel[10] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b1; + assign ary_w_sel[11] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b1; + assign ary_w_sel[12] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b1; + assign ary_w_sel[13] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b1; + assign ary_w_sel[14] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b1; + assign ary_w_sel[15] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b1; + + assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000: + {(data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK)}; + + assign ary_r_en = r_act; + + assign ary_r_addr[0:8] = r_addr[1:9]; + + assign data_out[0:7] = (r_addr_q[0] == 1'b0 ? ary_r_data[0:7] ^ ({`INIT_MASK, `INIT_MASK, `INIT_MASK, `INIT_MASK}) : 8'b00000000 ) | (r_addr_q[0] == 1'b1 ? ary_r_data[8:15] ^ ({`INIT_MASK, `INIT_MASK, `INIT_MASK, `INIT_MASK}) : 8'b00000000 ); + + //write through support + + assign data_in_d[0:1] = data_in[0:1]; + assign w_act_d[0:3] = w_act[0:3]; + assign r_act_d = r_act; + assign w_addr_d[0:9] = w_addr[0:9]; + assign r_addr_d[0:9] = r_addr[0:9]; + + assign write_thru[0:3] = ((w_addr_q[0:9] == r_addr_q[0:9]) & r_act_q == 1'b1) ? w_act_q[0:3] : + 4'b0000; + + assign data_out_d[0:1] = (write_thru[0] == 1'b1) ? data_in_q[0:1] : + data_out[0:1]; + assign data_out_d[2:3] = (write_thru[1] == 1'b1) ? data_in_q[0:1] : + data_out[2:3]; + assign data_out_d[4:5] = (write_thru[2] == 1'b1) ? data_in_q[0:1] : + data_out[4:5]; + assign data_out_d[6:7] = (write_thru[3] == 1'b1) ? data_in_q[0:1] : + data_out[6:7]; + + //latch acts + assign lat_wi_act = |(w_act[0:3]); + assign lat_ri_act = r_act; + assign lat_ro_act = r_act_q; + + //----------------------------------------------- + // array + //----------------------------------------------- + + + + tri_512x16_1r1w_1 bht0( + .gnd(gnd), + .vdd(vdd), + .vcs(vcs), + .nclk(nclk), + + .rd_act(ary_r_en), + .wr_act(ary_w_en), + + .lcb_d_mode_dc(g8t_d_mode), + .lcb_clkoff_dc_b(g8t_clkoff_b), + .lcb_mpw1_dc_b(g8t_mpw1_b), + .lcb_mpw2_dc_b(g8t_mpw2_b), + .lcb_delay_lclkr_dc(g8t_delay_lclkr), + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(scan_diag_dc), + .func_scan_in(siv[array_offset]), + .func_scan_out(sov[array_offset]), + + .lcb_sg_0(pc_iu_sg_0), + .lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .lcb_time_sl_thold_0(pc_iu_time_sl_thold_0), + .lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0), + .lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + .abst_scan_in(abst_scan_in), + .abst_scan_out(abst_scan_out), + .repr_scan_in(repr_scan_in), + .repr_scan_out(repr_scan_out), + + .abist_di(pc_iu_abist_di_0), + .abist_bw_odd(pc_iu_abist_g8t_bw_1), + .abist_bw_even(pc_iu_abist_g8t_bw_0), + .abist_wr_adr(pc_iu_abist_waddr_0), + .wr_abst_act(pc_iu_abist_g8t_wenb), + .abist_rd0_adr(pc_iu_abist_raddr_0), + .rd0_abst_act(pc_iu_abist_g8t1p_renb_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_iu_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena), + .abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .obs0_abist_cmp(pc_iu_abist_g8t_dcomp), + + .lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0), + .pc_bo_enable_2(pc_iu_bo_enable_2), + .pc_bo_reset(pc_iu_bo_reset), + .pc_bo_unload(pc_iu_bo_unload), + .pc_bo_repair(pc_iu_bo_repair), + .pc_bo_shdata(pc_iu_bo_shdata), + .pc_bo_select(pc_iu_bo_select), + .bo_pc_failout(iu_pc_bo_fail), + .bo_pc_diagloop(iu_pc_bo_diagout), + + .tri_lcb_mpw1_dc_b(mpw1_b), + .tri_lcb_mpw2_dc_b(mpw2_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr), + .tri_lcb_clkoff_dc_b(clkoff_b), + .tri_lcb_act_dis_dc(act_dis), + + .bw(ary_w_sel), + .wr_adr(ary_w_addr), + .rd_adr(ary_r_addr), + .di(ary_w_data), + .do(ary_r_data) + ); + + //----------------------------------------------- + // latches + //----------------------------------------------- + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) data_in_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_in_offset:data_in_offset + 2 - 1]), + .scout(sov[data_in_offset:data_in_offset + 2 - 1]), + .din(data_in_d), + .dout(data_in_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_act_offset:w_act_offset + 4 - 1]), + .scout(sov[w_act_offset:w_act_offset + 4 - 1]), + .din(w_act_d), + .dout(w_act_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) r_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_act_offset]), + .scout(sov[r_act_offset]), + .din(r_act_d), + .dout(r_act_q) + ); + + + tri_rlmreg_p #(.WIDTH(10), .INIT(0)) w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_addr_offset:w_addr_offset + 10 - 1]), + .scout(sov[w_addr_offset:w_addr_offset + 10 - 1]), + .din(w_addr_d), + .dout(w_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(10), .INIT(0)) r_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ri_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_addr_offset:r_addr_offset + 10 - 1]), + .scout(sov[r_addr_offset:r_addr_offset + 10 - 1]), + .din(r_addr_d), + .dout(r_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(8), .INIT(0)) data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ro_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_out_offset:data_out_offset + 8 - 1]), + .scout(sov[data_out_offset:data_out_offset + 8 - 1]), + .din(data_out_d), + .dout(data_out_q) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reset_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]), + .scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]), + .din(reset_w_addr_d), + .dout(reset_w_addr_q) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(7)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}), + .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}) + ); + + + tri_plat #(.WIDTH(7)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}), + .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + + assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]}; + assign func_scan_out = sov[scan_right]; + + +endmodule diff --git a/rel/src/verilog/trilib/tri_bht_512x4_1r1w.v b/rel/src/verilog/trilib/tri_bht_512x4_1r1w.v new file mode 100644 index 0000000..54aaef3 --- /dev/null +++ b/rel/src/verilog/trilib/tri_bht_512x4_1r1w.v @@ -0,0 +1,577 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for tri_bht_512x4_1r1w +// +// ********************************************************************* + +(* block_type="soft" *) +(* recursive_synthesis="2" *) +(* pin_default_power_domain="vdd" *) +(* pin_default_ground_domain ="gnd" *) + +`include "tri_a2o.vh" + +module tri_bht_512x4_1r1w( + gnd, + vdd, + vcs, + nclk, + pc_iu_func_sl_thold_2, + pc_iu_sg_2, + pc_iu_time_sl_thold_2, + pc_iu_abst_sl_thold_2, + pc_iu_ary_nsl_thold_2, + pc_iu_repr_sl_thold_2, + pc_iu_bolt_sl_thold_2, + tc_ac_ccflush_dc, + tc_ac_scan_dis_dc_b, + clkoff_b, + scan_diag_dc, + act_dis, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + g8t_clkoff_b, + g8t_d_mode, + g8t_delay_lclkr, + g8t_mpw1_b, + g8t_mpw2_b, + func_scan_in, + time_scan_in, + abst_scan_in, + repr_scan_in, + func_scan_out, + time_scan_out, + abst_scan_out, + repr_scan_out, + pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0, + pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0, + pc_iu_abist_g8t1p_renb_0, + an_ac_lbist_ary_wrt_thru_dc, + pc_iu_abist_ena_dc, + pc_iu_abist_wl128_comp_ena, + pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp, + pc_iu_bo_enable_2, + pc_iu_bo_reset, + pc_iu_bo_unload, + pc_iu_bo_repair, + pc_iu_bo_shdata, + pc_iu_bo_select, + iu_pc_bo_fail, + iu_pc_bo_diagout, + r_act, + w_act, + r_addr, + w_addr, + data_in, + data_out0, + data_out1, + data_out2, + data_out3, + pc_iu_init_reset +); + // power pins + inout gnd; + inout vdd; + inout vcs; + + // clock and clockcontrol ports + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_2; + input pc_iu_sg_2; + input pc_iu_time_sl_thold_2; + input pc_iu_abst_sl_thold_2; + input pc_iu_ary_nsl_thold_2; + input pc_iu_repr_sl_thold_2; + input pc_iu_bolt_sl_thold_2; + input tc_ac_ccflush_dc; + input tc_ac_scan_dis_dc_b; + input clkoff_b; + input scan_diag_dc; + input act_dis; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input g8t_clkoff_b; + input g8t_d_mode; + input [0:4] g8t_delay_lclkr; + input [0:4] g8t_mpw1_b; + input g8t_mpw2_b; + input func_scan_in; + input time_scan_in; + input abst_scan_in; + input repr_scan_in; + output func_scan_out; + output time_scan_out; + output abst_scan_out; + output repr_scan_out; + + input [0:3] pc_iu_abist_di_0; + input pc_iu_abist_g8t_bw_1; + input pc_iu_abist_g8t_bw_0; + input [3:9] pc_iu_abist_waddr_0; + input pc_iu_abist_g8t_wenb; + input [3:9] pc_iu_abist_raddr_0; + input pc_iu_abist_g8t1p_renb_0; + input an_ac_lbist_ary_wrt_thru_dc; + input pc_iu_abist_ena_dc; + input pc_iu_abist_wl128_comp_ena; + input pc_iu_abist_raw_dc_b; + input [0:3] pc_iu_abist_g8t_dcomp; + + // BOLT-ON + input pc_iu_bo_enable_2; // general bolt-on enable + input pc_iu_bo_reset; // reset + input pc_iu_bo_unload; // unload sticky bits + input pc_iu_bo_repair; // execute sticky bit decode + input pc_iu_bo_shdata; // shift data for timing write and diag loop + input pc_iu_bo_select; // select for mask and hier writes + output iu_pc_bo_fail; // fail/no-fix reg + output iu_pc_bo_diagout; + + // ports + input r_act; + input [0:3] w_act; + input [0:8] r_addr; + input [0:8] w_addr; + input data_in; + output data_out0; + output data_out1; + output data_out2; + output data_out3; + + input pc_iu_init_reset; + + //-------------------------- + // constants + //-------------------------- + + + parameter data_in_offset = 0; + parameter w_act_offset = data_in_offset + 1; + parameter r_act_offset = w_act_offset + 4; + parameter w_addr_offset = r_act_offset + 1; + parameter r_addr_offset = w_addr_offset + 9; + parameter data_out_offset = r_addr_offset + 9; + parameter reset_w_addr_offset = data_out_offset + 4; + parameter array_offset = reset_w_addr_offset + 9; + parameter scan_right = array_offset + 1 - 1; + + //-------------------------- + // signals + //-------------------------- + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_time_sl_thold_1; + wire pc_iu_time_sl_thold_0; + wire pc_iu_ary_nsl_thold_1; + wire pc_iu_ary_nsl_thold_0; + wire pc_iu_abst_sl_thold_1; + wire pc_iu_abst_sl_thold_0; + wire pc_iu_repr_sl_thold_1; + wire pc_iu_repr_sl_thold_0; + wire pc_iu_bolt_sl_thold_1; + wire pc_iu_bolt_sl_thold_0; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tiup; + + wire [0:3] data_out_d; + wire [0:3] data_out_q; + + wire ary_w_en; + wire [0:8] ary_w_addr; + wire [0:15] ary_w_sel; + wire [0:15] ary_w_data; + + wire ary_r_en; + wire [0:8] ary_r_addr; + wire [0:15] ary_r_data; + + wire [0:3] data_out; + wire [0:3] write_thru; + + wire data_in_d; + wire data_in_q; + wire [0:3] w_act_d; + wire [0:3] w_act_q; + wire r_act_d; + wire r_act_q; + wire [0:8] w_addr_d; + wire [0:8] w_addr_q; + wire [0:8] r_addr_d; + wire [0:8] r_addr_q; + + wire lat_wi_act; + wire lat_ri_act; + wire lat_ro_act; + + wire reset_act; + wire [0:8] reset_w_addr_d; + wire [0:8] reset_w_addr_q; + + + + assign tiup = 1'b1; + + assign reset_act = pc_iu_init_reset; + assign reset_w_addr_d[0:8] = reset_w_addr_q[0:8] + 9'b000000001; + + assign data_out0 = data_out_q[0]; + assign data_out1 = data_out_q[1]; + assign data_out2 = data_out_q[2]; + assign data_out3 = data_out_q[3]; + + assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[0:8] == r_addr[0:8]) & r_act == 1'b1))); + + assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[0:8]; + + assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0]; + assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[1]; + assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[2]; + assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[3]; + assign ary_w_sel[4] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[5] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[6] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[7] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[8] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[9] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[10] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[11] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[12] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[13] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[14] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[15] = reset_act ? 1'b1 : 1'b0; + + assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000: + {data_in, data_in, data_in, data_in, 12'b000000000000}; + + assign ary_r_en = r_act; + + assign ary_r_addr[0:8] = r_addr[0:8]; + + assign data_out[0:3] = ary_r_data[0:3]; + + //write through support + + assign data_in_d = data_in; + assign w_act_d[0:3] = w_act[0:3]; + assign r_act_d = r_act; + assign w_addr_d[0:8] = w_addr[0:8]; + assign r_addr_d[0:8] = r_addr[0:8]; + + assign write_thru[0:3] = ((w_addr_q[0:8] == r_addr_q[0:8]) & r_act_q == 1'b1) ? w_act_q[0:3] : + 4'b0000; + + assign data_out_d[0] = (write_thru[0] == 1'b1) ? data_in_q : + data_out[0]; + assign data_out_d[1] = (write_thru[1] == 1'b1) ? data_in_q : + data_out[1]; + assign data_out_d[2] = (write_thru[2] == 1'b1) ? data_in_q : + data_out[2]; + assign data_out_d[3] = (write_thru[3] == 1'b1) ? data_in_q : + data_out[3]; + + //latch acts + assign lat_wi_act = |(w_act[0:3]); + assign lat_ri_act = r_act; + assign lat_ro_act = r_act_q; + + //----------------------------------------------- + // array + //----------------------------------------------- + + + + tri_512x16_1r1w_1 bht0( + .gnd(gnd), + .vdd(vdd), + .vcs(vcs), + .nclk(nclk), + + .rd_act(ary_r_en), + .wr_act(ary_w_en), + + .lcb_d_mode_dc(g8t_d_mode), + .lcb_clkoff_dc_b(g8t_clkoff_b), + .lcb_mpw1_dc_b(g8t_mpw1_b), + .lcb_mpw2_dc_b(g8t_mpw2_b), + .lcb_delay_lclkr_dc(g8t_delay_lclkr), + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(scan_diag_dc), + .func_scan_in(siv[array_offset]), + .func_scan_out(sov[array_offset]), + + .lcb_sg_0(pc_iu_sg_0), + .lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .lcb_time_sl_thold_0(pc_iu_time_sl_thold_0), + .lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0), + .lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + .abst_scan_in(abst_scan_in), + .abst_scan_out(abst_scan_out), + .repr_scan_in(repr_scan_in), + .repr_scan_out(repr_scan_out), + + .abist_di(pc_iu_abist_di_0), + .abist_bw_odd(pc_iu_abist_g8t_bw_1), + .abist_bw_even(pc_iu_abist_g8t_bw_0), + .abist_wr_adr(pc_iu_abist_waddr_0), + .wr_abst_act(pc_iu_abist_g8t_wenb), + .abist_rd0_adr(pc_iu_abist_raddr_0), + .rd0_abst_act(pc_iu_abist_g8t1p_renb_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_iu_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena), + .abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .obs0_abist_cmp(pc_iu_abist_g8t_dcomp), + + .lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0), + .pc_bo_enable_2(pc_iu_bo_enable_2), + .pc_bo_reset(pc_iu_bo_reset), + .pc_bo_unload(pc_iu_bo_unload), + .pc_bo_repair(pc_iu_bo_repair), + .pc_bo_shdata(pc_iu_bo_shdata), + .pc_bo_select(pc_iu_bo_select), + .bo_pc_failout(iu_pc_bo_fail), + .bo_pc_diagloop(iu_pc_bo_diagout), + + .tri_lcb_mpw1_dc_b(mpw1_b), + .tri_lcb_mpw2_dc_b(mpw2_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr), + .tri_lcb_clkoff_dc_b(clkoff_b), + .tri_lcb_act_dis_dc(act_dis), + + .bw(ary_w_sel), + .wr_adr(ary_w_addr), + .rd_adr(ary_r_addr), + .di(ary_w_data), + .do(ary_r_data) + ); + + //----------------------------------------------- + // latches + //----------------------------------------------- + + + tri_rlmlatch_p #(.INIT(0)) data_in_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_in_offset:data_in_offset]), + .scout(sov[data_in_offset:data_in_offset]), + .din(data_in_d), + .dout(data_in_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_act_offset:w_act_offset + 4 - 1]), + .scout(sov[w_act_offset:w_act_offset + 4 - 1]), + .din(w_act_d), + .dout(w_act_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) r_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_act_offset]), + .scout(sov[r_act_offset]), + .din(r_act_d), + .dout(r_act_q) + ); + + + tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_addr_offset:w_addr_offset + 9 - 1]), + .scout(sov[w_addr_offset:w_addr_offset + 9 - 1]), + .din(w_addr_d), + .dout(w_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ri_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_addr_offset:r_addr_offset + 9 - 1]), + .scout(sov[r_addr_offset:r_addr_offset + 9 - 1]), + .din(r_addr_d), + .dout(r_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ro_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_out_offset:data_out_offset + 4 - 1]), + .scout(sov[data_out_offset:data_out_offset + 4 - 1]), + .din(data_out_d), + .dout(data_out_q) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reset_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]), + .scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]), + .din(reset_w_addr_d), + .dout(reset_w_addr_q) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(7)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}), + .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}) + ); + + + tri_plat #(.WIDTH(7)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}), + .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + + assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]}; + assign func_scan_out = sov[scan_right]; + + +endmodule diff --git a/rel/src/verilog/trilib/tri_bthmx.v b/rel/src/verilog/trilib/tri_bthmx.v new file mode 100644 index 0000000..7d0f430 --- /dev/null +++ b/rel/src/verilog/trilib/tri_bthmx.v @@ -0,0 +1,64 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU Multiplier Top +// +//***************************************************************************** +module tri_bthmx(x, sneg, sx, sx2, right, left, q, vd, gd); + +input x; +input sneg; +input sx; +input sx2; +input right; +output left; +output q; +(* ANALYSIS_NOT_ASSIGNED="TRUE" *) +(* ANALYSIS_NOT_REFERENCED="TRUE" *) +inout vd; +(* ANALYSIS_NOT_ASSIGNED="TRUE" *) +(* ANALYSIS_NOT_REFERENCED="TRUE" *) +inout gd; + + + +wire center, xn, spos; + +assign xn = ~x; +assign spos = ~sneg; + +assign center = ~(( xn & spos ) | + ( x & sneg )); + +assign left = center; // output + + +assign q = ( center & sx ) | + ( right & sx2 ) ; + +endmodule diff --git a/rel/src/verilog/trilib/tri_cam_16x143_1r1w1c.v b/rel/src/verilog/trilib/tri_cam_16x143_1r1w1c.v new file mode 100644 index 0000000..6f22617 --- /dev/null +++ b/rel/src/verilog/trilib/tri_cam_16x143_1r1w1c.v @@ -0,0 +1,2707 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Fri Mar 19 10:58:26 2010 + +//******************************************************************** +//* TITLE: I-ERAT CAM Tri-Library Model +//* NAME: tri_cam_16x143_1r1w1c +//******************************************************************** + +`include "tri_a2o.vh" + +module tri_cam_16x143_1r1w1c( + gnd, + vdd, + vcs, + nclk, + tc_ccflush_dc, + tc_scan_dis_dc_b, + tc_scan_diag_dc, + tc_lbist_en_dc, + an_ac_atpg_en_dc, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_act_dis_dc, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + pc_sg_2, + pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2, + pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, + pc_fce_2, + func_scan_in, + func_scan_out, + regfile_scan_in, + regfile_scan_out, + time_scan_in, + time_scan_out, + rd_val, + rd_val_late, + rw_entry, + wr_array_data, + wr_cam_data, + wr_array_val, + wr_cam_val, + wr_val_early, + comp_request, + comp_addr, + addr_enable, + comp_pgsize, + pgsize_enable, + comp_class, + class_enable, + comp_extclass, + extclass_enable, + comp_state, + state_enable, + comp_thdid, + thdid_enable, + comp_pid, + pid_enable, + comp_invalidate, + flash_invalidate, + array_cmp_data, + rd_array_data, + cam_cmp_data, + cam_hit, + cam_hit_entry, + entry_match, + entry_valid, + rd_cam_data, + bypass_mux_enab_np1, + bypass_attr_np1, + attr_np2, + rpn_np2 +); + parameter CAM_DATA_WIDTH = 84; + parameter ARRAY_DATA_WIDTH = 68; + parameter RPN_WIDTH = 30; + parameter NUM_ENTRY = 16; + parameter NUM_ENTRY_LOG2 = 4; + + // Power Pins + inout gnd; + inout vdd; + inout vcs; + + // Clocks and Scan Cntls + input [0:`NCLK_WIDTH-1] nclk; + input tc_ccflush_dc; + input tc_scan_dis_dc_b; + input tc_scan_diag_dc; + input tc_lbist_en_dc; + input an_ac_atpg_en_dc; + + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input lcb_act_dis_dc; + input [0:3] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:3] lcb_delay_lclkr_dc; + + input pc_sg_2; + input pc_func_slp_sl_thold_2; + input pc_func_slp_nsl_thold_2; + input pc_regf_slp_sl_thold_2; + input pc_time_sl_thold_2; + input pc_fce_2; + + input func_scan_in; + output func_scan_out; + input [0:4] regfile_scan_in; // 0:2 -> CAM, 3:4 -> RAM + output [0:4] regfile_scan_out; + input time_scan_in; + output time_scan_out; + + // Read Port + input rd_val; + input rd_val_late; + input [0:NUM_ENTRY_LOG2-1] rw_entry; + + // Write Port + input [0:ARRAY_DATA_WIDTH-1] wr_array_data; + input [0:CAM_DATA_WIDTH-1] wr_cam_data; + input [0:1] wr_array_val; + input [0:1] wr_cam_val; + input wr_val_early; + + // CAM Port + input comp_request; + input [0:51] comp_addr; + input [0:1] addr_enable; + input [0:2] comp_pgsize; + input pgsize_enable; + input [0:1] comp_class; + input [0:2] class_enable; + input [0:1] comp_extclass; + input [0:1] extclass_enable; + input [0:1] comp_state; + input [0:1] state_enable; + input [0:3] comp_thdid; + input [0:1] thdid_enable; + input [0:7] comp_pid; + input pid_enable; + input comp_invalidate; + input flash_invalidate; + + // Outputs + // Data Out + output [0:ARRAY_DATA_WIDTH-1] array_cmp_data; + output [0:ARRAY_DATA_WIDTH-1] rd_array_data; + + // CAM Output + output [0:CAM_DATA_WIDTH-1] cam_cmp_data; + output cam_hit; + output [0:NUM_ENTRY_LOG2-1] cam_hit_entry; + output [0:NUM_ENTRY-1] entry_match; + output [0:NUM_ENTRY-1] entry_valid; + output [0:CAM_DATA_WIDTH-1] rd_cam_data; + + //--- new ports for IO plus ----------------------- + input bypass_mux_enab_np1; + input [0:20] bypass_attr_np1; + output [0:20] attr_np2; + + output [22:51] rpn_np2; + + // tri_cam_16x143_1r1w1c + + // Configuration Statement for NCsim + //for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9; + //for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18; + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire clk; + wire clk2x; + wire [0:8] bram0_addra; + wire [0:8] bram0_addrb; + wire [0:10] bram1_addra; + wire [0:10] bram1_addrb; + wire [0:9] bram2_addra; + wire [0:9] bram2_addrb; + wire bram0_wea; + wire bram1_wea; + wire bram2_wea; + wire [0:55] array_cmp_data_bram; + wire [66:72] array_cmp_data_bramp; + + // Latches + reg sreset_q; + reg gate_fq; + wire gate_d; + wire [52-RPN_WIDTH:51] comp_addr_np1_d; + reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input + wire [52-RPN_WIDTH:51] rpn_np2_d; + reg [52-RPN_WIDTH:51] rpn_np2_q; + wire [0:20] attr_np2_d; + reg [0:20] attr_np2_q; + + // CAM entry signals + wire [0:51] entry0_epn_d; + reg [0:51] entry0_epn_q; + wire entry0_xbit_d; + reg entry0_xbit_q; + wire [0:2] entry0_size_d; + reg [0:2] entry0_size_q; + wire entry0_v_d; + reg entry0_v_q; + wire [0:3] entry0_thdid_d; + reg [0:3] entry0_thdid_q; + wire [0:1] entry0_class_d; + reg [0:1] entry0_class_q; + wire [0:1] entry0_extclass_d; + reg [0:1] entry0_extclass_q; + wire entry0_hv_d; + reg entry0_hv_q; + wire entry0_ds_d; + reg entry0_ds_q; + wire [0:7] entry0_pid_d; + reg [0:7] entry0_pid_q; + wire [0:8] entry0_cmpmask_d; + reg [0:8] entry0_cmpmask_q; + wire [0:9] entry0_parity_d; + reg [0:9] entry0_parity_q; + wire [0:1] wr_entry0_sel; + wire entry0_inval; + wire [0:1] entry0_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry0_cam_vec; + wire [0:51] entry1_epn_d; + reg [0:51] entry1_epn_q; + wire entry1_xbit_d; + reg entry1_xbit_q; + wire [0:2] entry1_size_d; + reg [0:2] entry1_size_q; + wire entry1_v_d; + reg entry1_v_q; + wire [0:3] entry1_thdid_d; + reg [0:3] entry1_thdid_q; + wire [0:1] entry1_class_d; + reg [0:1] entry1_class_q; + wire [0:1] entry1_extclass_d; + reg [0:1] entry1_extclass_q; + wire entry1_hv_d; + reg entry1_hv_q; + wire entry1_ds_d; + reg entry1_ds_q; + wire [0:7] entry1_pid_d; + reg [0:7] entry1_pid_q; + wire [0:8] entry1_cmpmask_d; + reg [0:8] entry1_cmpmask_q; + wire [0:9] entry1_parity_d; + reg [0:9] entry1_parity_q; + wire [0:1] wr_entry1_sel; + wire entry1_inval; + wire [0:1] entry1_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry1_cam_vec; + wire [0:51] entry2_epn_d; + reg [0:51] entry2_epn_q; + wire entry2_xbit_d; + reg entry2_xbit_q; + wire [0:2] entry2_size_d; + reg [0:2] entry2_size_q; + wire entry2_v_d; + reg entry2_v_q; + wire [0:3] entry2_thdid_d; + reg [0:3] entry2_thdid_q; + wire [0:1] entry2_class_d; + reg [0:1] entry2_class_q; + wire [0:1] entry2_extclass_d; + reg [0:1] entry2_extclass_q; + wire entry2_hv_d; + reg entry2_hv_q; + wire entry2_ds_d; + reg entry2_ds_q; + wire [0:7] entry2_pid_d; + reg [0:7] entry2_pid_q; + wire [0:8] entry2_cmpmask_d; + reg [0:8] entry2_cmpmask_q; + wire [0:9] entry2_parity_d; + reg [0:9] entry2_parity_q; + wire [0:1] wr_entry2_sel; + wire entry2_inval; + wire [0:1] entry2_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry2_cam_vec; + wire [0:51] entry3_epn_d; + reg [0:51] entry3_epn_q; + wire entry3_xbit_d; + reg entry3_xbit_q; + wire [0:2] entry3_size_d; + reg [0:2] entry3_size_q; + wire entry3_v_d; + reg entry3_v_q; + wire [0:3] entry3_thdid_d; + reg [0:3] entry3_thdid_q; + wire [0:1] entry3_class_d; + reg [0:1] entry3_class_q; + wire [0:1] entry3_extclass_d; + reg [0:1] entry3_extclass_q; + wire entry3_hv_d; + reg entry3_hv_q; + wire entry3_ds_d; + reg entry3_ds_q; + wire [0:7] entry3_pid_d; + reg [0:7] entry3_pid_q; + wire [0:8] entry3_cmpmask_d; + reg [0:8] entry3_cmpmask_q; + wire [0:9] entry3_parity_d; + reg [0:9] entry3_parity_q; + wire [0:1] wr_entry3_sel; + wire entry3_inval; + wire [0:1] entry3_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry3_cam_vec; + wire [0:51] entry4_epn_d; + reg [0:51] entry4_epn_q; + wire entry4_xbit_d; + reg entry4_xbit_q; + wire [0:2] entry4_size_d; + reg [0:2] entry4_size_q; + wire entry4_v_d; + reg entry4_v_q; + wire [0:3] entry4_thdid_d; + reg [0:3] entry4_thdid_q; + wire [0:1] entry4_class_d; + reg [0:1] entry4_class_q; + wire [0:1] entry4_extclass_d; + reg [0:1] entry4_extclass_q; + wire entry4_hv_d; + reg entry4_hv_q; + wire entry4_ds_d; + reg entry4_ds_q; + wire [0:7] entry4_pid_d; + reg [0:7] entry4_pid_q; + wire [0:8] entry4_cmpmask_d; + reg [0:8] entry4_cmpmask_q; + wire [0:9] entry4_parity_d; + reg [0:9] entry4_parity_q; + wire [0:1] wr_entry4_sel; + wire entry4_inval; + wire [0:1] entry4_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry4_cam_vec; + wire [0:51] entry5_epn_d; + reg [0:51] entry5_epn_q; + wire entry5_xbit_d; + reg entry5_xbit_q; + wire [0:2] entry5_size_d; + reg [0:2] entry5_size_q; + wire entry5_v_d; + reg entry5_v_q; + wire [0:3] entry5_thdid_d; + reg [0:3] entry5_thdid_q; + wire [0:1] entry5_class_d; + reg [0:1] entry5_class_q; + wire [0:1] entry5_extclass_d; + reg [0:1] entry5_extclass_q; + wire entry5_hv_d; + reg entry5_hv_q; + wire entry5_ds_d; + reg entry5_ds_q; + wire [0:7] entry5_pid_d; + reg [0:7] entry5_pid_q; + wire [0:8] entry5_cmpmask_d; + reg [0:8] entry5_cmpmask_q; + wire [0:9] entry5_parity_d; + reg [0:9] entry5_parity_q; + wire [0:1] wr_entry5_sel; + wire entry5_inval; + wire [0:1] entry5_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry5_cam_vec; + wire [0:51] entry6_epn_d; + reg [0:51] entry6_epn_q; + wire entry6_xbit_d; + reg entry6_xbit_q; + wire [0:2] entry6_size_d; + reg [0:2] entry6_size_q; + wire entry6_v_d; + reg entry6_v_q; + wire [0:3] entry6_thdid_d; + reg [0:3] entry6_thdid_q; + wire [0:1] entry6_class_d; + reg [0:1] entry6_class_q; + wire [0:1] entry6_extclass_d; + reg [0:1] entry6_extclass_q; + wire entry6_hv_d; + reg entry6_hv_q; + wire entry6_ds_d; + reg entry6_ds_q; + wire [0:7] entry6_pid_d; + reg [0:7] entry6_pid_q; + wire [0:8] entry6_cmpmask_d; + reg [0:8] entry6_cmpmask_q; + wire [0:9] entry6_parity_d; + reg [0:9] entry6_parity_q; + wire [0:1] wr_entry6_sel; + wire entry6_inval; + wire [0:1] entry6_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry6_cam_vec; + wire [0:51] entry7_epn_d; + reg [0:51] entry7_epn_q; + wire entry7_xbit_d; + reg entry7_xbit_q; + wire [0:2] entry7_size_d; + reg [0:2] entry7_size_q; + wire entry7_v_d; + reg entry7_v_q; + wire [0:3] entry7_thdid_d; + reg [0:3] entry7_thdid_q; + wire [0:1] entry7_class_d; + reg [0:1] entry7_class_q; + wire [0:1] entry7_extclass_d; + reg [0:1] entry7_extclass_q; + wire entry7_hv_d; + reg entry7_hv_q; + wire entry7_ds_d; + reg entry7_ds_q; + wire [0:7] entry7_pid_d; + reg [0:7] entry7_pid_q; + wire [0:8] entry7_cmpmask_d; + reg [0:8] entry7_cmpmask_q; + wire [0:9] entry7_parity_d; + reg [0:9] entry7_parity_q; + wire [0:1] wr_entry7_sel; + wire entry7_inval; + wire [0:1] entry7_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry7_cam_vec; + wire [0:51] entry8_epn_d; + reg [0:51] entry8_epn_q; + wire entry8_xbit_d; + reg entry8_xbit_q; + wire [0:2] entry8_size_d; + reg [0:2] entry8_size_q; + wire entry8_v_d; + reg entry8_v_q; + wire [0:3] entry8_thdid_d; + reg [0:3] entry8_thdid_q; + wire [0:1] entry8_class_d; + reg [0:1] entry8_class_q; + wire [0:1] entry8_extclass_d; + reg [0:1] entry8_extclass_q; + wire entry8_hv_d; + reg entry8_hv_q; + wire entry8_ds_d; + reg entry8_ds_q; + wire [0:7] entry8_pid_d; + reg [0:7] entry8_pid_q; + wire [0:8] entry8_cmpmask_d; + reg [0:8] entry8_cmpmask_q; + wire [0:9] entry8_parity_d; + reg [0:9] entry8_parity_q; + wire [0:1] wr_entry8_sel; + wire entry8_inval; + wire [0:1] entry8_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry8_cam_vec; + wire [0:51] entry9_epn_d; + reg [0:51] entry9_epn_q; + wire entry9_xbit_d; + reg entry9_xbit_q; + wire [0:2] entry9_size_d; + reg [0:2] entry9_size_q; + wire entry9_v_d; + reg entry9_v_q; + wire [0:3] entry9_thdid_d; + reg [0:3] entry9_thdid_q; + wire [0:1] entry9_class_d; + reg [0:1] entry9_class_q; + wire [0:1] entry9_extclass_d; + reg [0:1] entry9_extclass_q; + wire entry9_hv_d; + reg entry9_hv_q; + wire entry9_ds_d; + reg entry9_ds_q; + wire [0:7] entry9_pid_d; + reg [0:7] entry9_pid_q; + wire [0:8] entry9_cmpmask_d; + reg [0:8] entry9_cmpmask_q; + wire [0:9] entry9_parity_d; + reg [0:9] entry9_parity_q; + wire [0:1] wr_entry9_sel; + wire entry9_inval; + wire [0:1] entry9_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry9_cam_vec; + wire [0:51] entry10_epn_d; + reg [0:51] entry10_epn_q; + wire entry10_xbit_d; + reg entry10_xbit_q; + wire [0:2] entry10_size_d; + reg [0:2] entry10_size_q; + wire entry10_v_d; + reg entry10_v_q; + wire [0:3] entry10_thdid_d; + reg [0:3] entry10_thdid_q; + wire [0:1] entry10_class_d; + reg [0:1] entry10_class_q; + wire [0:1] entry10_extclass_d; + reg [0:1] entry10_extclass_q; + wire entry10_hv_d; + reg entry10_hv_q; + wire entry10_ds_d; + reg entry10_ds_q; + wire [0:7] entry10_pid_d; + reg [0:7] entry10_pid_q; + wire [0:8] entry10_cmpmask_d; + reg [0:8] entry10_cmpmask_q; + wire [0:9] entry10_parity_d; + reg [0:9] entry10_parity_q; + wire [0:1] wr_entry10_sel; + wire entry10_inval; + wire [0:1] entry10_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry10_cam_vec; + wire [0:51] entry11_epn_d; + reg [0:51] entry11_epn_q; + wire entry11_xbit_d; + reg entry11_xbit_q; + wire [0:2] entry11_size_d; + reg [0:2] entry11_size_q; + wire entry11_v_d; + reg entry11_v_q; + wire [0:3] entry11_thdid_d; + reg [0:3] entry11_thdid_q; + wire [0:1] entry11_class_d; + reg [0:1] entry11_class_q; + wire [0:1] entry11_extclass_d; + reg [0:1] entry11_extclass_q; + wire entry11_hv_d; + reg entry11_hv_q; + wire entry11_ds_d; + reg entry11_ds_q; + wire [0:7] entry11_pid_d; + reg [0:7] entry11_pid_q; + wire [0:8] entry11_cmpmask_d; + reg [0:8] entry11_cmpmask_q; + wire [0:9] entry11_parity_d; + reg [0:9] entry11_parity_q; + wire [0:1] wr_entry11_sel; + wire entry11_inval; + wire [0:1] entry11_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry11_cam_vec; + wire [0:51] entry12_epn_d; + reg [0:51] entry12_epn_q; + wire entry12_xbit_d; + reg entry12_xbit_q; + wire [0:2] entry12_size_d; + reg [0:2] entry12_size_q; + wire entry12_v_d; + reg entry12_v_q; + wire [0:3] entry12_thdid_d; + reg [0:3] entry12_thdid_q; + wire [0:1] entry12_class_d; + reg [0:1] entry12_class_q; + wire [0:1] entry12_extclass_d; + reg [0:1] entry12_extclass_q; + wire entry12_hv_d; + reg entry12_hv_q; + wire entry12_ds_d; + reg entry12_ds_q; + wire [0:7] entry12_pid_d; + reg [0:7] entry12_pid_q; + wire [0:8] entry12_cmpmask_d; + reg [0:8] entry12_cmpmask_q; + wire [0:9] entry12_parity_d; + reg [0:9] entry12_parity_q; + wire [0:1] wr_entry12_sel; + wire entry12_inval; + wire [0:1] entry12_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry12_cam_vec; + wire [0:51] entry13_epn_d; + reg [0:51] entry13_epn_q; + wire entry13_xbit_d; + reg entry13_xbit_q; + wire [0:2] entry13_size_d; + reg [0:2] entry13_size_q; + wire entry13_v_d; + reg entry13_v_q; + wire [0:3] entry13_thdid_d; + reg [0:3] entry13_thdid_q; + wire [0:1] entry13_class_d; + reg [0:1] entry13_class_q; + wire [0:1] entry13_extclass_d; + reg [0:1] entry13_extclass_q; + wire entry13_hv_d; + reg entry13_hv_q; + wire entry13_ds_d; + reg entry13_ds_q; + wire [0:7] entry13_pid_d; + reg [0:7] entry13_pid_q; + wire [0:8] entry13_cmpmask_d; + reg [0:8] entry13_cmpmask_q; + wire [0:9] entry13_parity_d; + reg [0:9] entry13_parity_q; + wire [0:1] wr_entry13_sel; + wire entry13_inval; + wire [0:1] entry13_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry13_cam_vec; + wire [0:51] entry14_epn_d; + reg [0:51] entry14_epn_q; + wire entry14_xbit_d; + reg entry14_xbit_q; + wire [0:2] entry14_size_d; + reg [0:2] entry14_size_q; + wire entry14_v_d; + reg entry14_v_q; + wire [0:3] entry14_thdid_d; + reg [0:3] entry14_thdid_q; + wire [0:1] entry14_class_d; + reg [0:1] entry14_class_q; + wire [0:1] entry14_extclass_d; + reg [0:1] entry14_extclass_q; + wire entry14_hv_d; + reg entry14_hv_q; + wire entry14_ds_d; + reg entry14_ds_q; + wire [0:7] entry14_pid_d; + reg [0:7] entry14_pid_q; + wire [0:8] entry14_cmpmask_d; + reg [0:8] entry14_cmpmask_q; + wire [0:9] entry14_parity_d; + reg [0:9] entry14_parity_q; + wire [0:1] wr_entry14_sel; + wire entry14_inval; + wire [0:1] entry14_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry14_cam_vec; + wire [0:51] entry15_epn_d; + reg [0:51] entry15_epn_q; + wire entry15_xbit_d; + reg entry15_xbit_q; + wire [0:2] entry15_size_d; + reg [0:2] entry15_size_q; + wire entry15_v_d; + reg entry15_v_q; + wire [0:3] entry15_thdid_d; + reg [0:3] entry15_thdid_q; + wire [0:1] entry15_class_d; + reg [0:1] entry15_class_q; + wire [0:1] entry15_extclass_d; + reg [0:1] entry15_extclass_q; + wire entry15_hv_d; + reg entry15_hv_q; + wire entry15_ds_d; + reg entry15_ds_q; + wire [0:7] entry15_pid_d; + reg [0:7] entry15_pid_q; + wire [0:8] entry15_cmpmask_d; + reg [0:8] entry15_cmpmask_q; + wire [0:9] entry15_parity_d; + reg [0:9] entry15_parity_q; + wire [0:1] wr_entry15_sel; + wire entry15_inval; + wire [0:1] entry15_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry15_cam_vec; + wire [0:4] cam_cmp_data_muxsel; + wire [0:4] rd_cam_data_muxsel; + wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_np1; + wire [0:ARRAY_DATA_WIDTH-1] array_cmp_data_np1; + wire [0:72] wr_array_data_bram; + wire [0:72] rd_array_data_d_std; + wire [0:55] array_cmp_data_bram_std; + wire [66:72] array_cmp_data_bramp_std; + + // latch signals + wire [0:ARRAY_DATA_WIDTH-1] rd_array_data_d; + reg [0:ARRAY_DATA_WIDTH-1] rd_array_data_q; + wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_d; + reg [0:CAM_DATA_WIDTH-1] cam_cmp_data_q; + wire [0:9] cam_cmp_parity_d; + reg [0:9] cam_cmp_parity_q; + wire [0:CAM_DATA_WIDTH-1] rd_cam_data_d; + reg [0:CAM_DATA_WIDTH-1] rd_cam_data_q; + wire [0:NUM_ENTRY-1] entry_match_d; + reg [0:NUM_ENTRY-1] entry_match_q; + wire [0:NUM_ENTRY-1] match_vec; + wire [0:NUM_ENTRY_LOG2-1] cam_hit_entry_d; + reg [0:NUM_ENTRY_LOG2-1] cam_hit_entry_q; + wire cam_hit_d; + reg cam_hit_q; + wire toggle_d; + reg toggle_q; + wire toggle2x_d; + reg toggle2x_q; + (* analysis_not_referenced="true" *) + wire unused; + + + + assign clk = (~nclk[0]); + assign clk2x = nclk[2]; + + always @(posedge clk) + begin: rlatch + sreset_q <= nclk[1]; + end + + // + // NEW clk2x gate logic start + // + + always @(posedge nclk[0]) + begin: tlatch + if (sreset_q == 1'b1) + toggle_q <= 1'b1; + else + toggle_q <= toggle_d; + end + + always @(posedge nclk[2]) + begin: flatch + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + end + + assign toggle_d = (~toggle_q); + assign toggle2x_d = toggle_q; + + // should force gate_fq to be on during odd 2x clock (second half of 1x clock). + assign gate_d = toggle_q ^ toggle2x_q; + // if you want the first half do the following + //assign gate_d <= ~(toggle_q ^ toggle2x_q); + + // + // NEW clk2x gate logic end + // + + // Slow Latches (nclk) + always @(posedge nclk[0]) + begin: slatch + if (sreset_q == 1'b1) + begin + cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; + cam_cmp_parity_q <= 10'b0; + rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; + rd_array_data_q <= {ARRAY_DATA_WIDTH{1'b0}}; + entry_match_q <= {NUM_ENTRY{1'b0}}; + cam_hit_entry_q <= {NUM_ENTRY_LOG2{1'b0}}; + cam_hit_q <= 1'b0; + comp_addr_np1_q <= {RPN_WIDTH{1'b0}}; + rpn_np2_q <= {RPN_WIDTH{1'b0}}; + attr_np2_q <= 21'b0; + entry0_size_q <= 3'b0; + entry0_xbit_q <= 1'b0; + entry0_epn_q <= 52'b0; + entry0_class_q <= 2'b0; + entry0_extclass_q <= 2'b0; + entry0_hv_q <= 1'b0; + entry0_ds_q <= 1'b0; + entry0_thdid_q <= 4'b0; + entry0_pid_q <= 8'b0; + entry0_v_q <= 1'b0; + entry0_parity_q <= 10'b0; + entry0_cmpmask_q <= 9'b0; + entry1_size_q <= 3'b0; + entry1_xbit_q <= 1'b0; + entry1_epn_q <= 52'b0; + entry1_class_q <= 2'b0; + entry1_extclass_q <= 2'b0; + entry1_hv_q <= 1'b0; + entry1_ds_q <= 1'b0; + entry1_thdid_q <= 4'b0; + entry1_pid_q <= 8'b0; + entry1_v_q <= 1'b0; + entry1_parity_q <= 10'b0; + entry1_cmpmask_q <= 9'b0; + entry2_size_q <= 3'b0; + entry2_xbit_q <= 1'b0; + entry2_epn_q <= 52'b0; + entry2_class_q <= 2'b0; + entry2_extclass_q <= 2'b0; + entry2_hv_q <= 1'b0; + entry2_ds_q <= 1'b0; + entry2_thdid_q <= 4'b0; + entry2_pid_q <= 8'b0; + entry2_v_q <= 1'b0; + entry2_parity_q <= 10'b0; + entry2_cmpmask_q <= 9'b0; + entry3_size_q <= 3'b0; + entry3_xbit_q <= 1'b0; + entry3_epn_q <= 52'b0; + entry3_class_q <= 2'b0; + entry3_extclass_q <= 2'b0; + entry3_hv_q <= 1'b0; + entry3_ds_q <= 1'b0; + entry3_thdid_q <= 4'b0; + entry3_pid_q <= 8'b0; + entry3_v_q <= 1'b0; + entry3_parity_q <= 10'b0; + entry3_cmpmask_q <= 9'b0; + entry4_size_q <= 3'b0; + entry4_xbit_q <= 1'b0; + entry4_epn_q <= 52'b0; + entry4_class_q <= 2'b0; + entry4_extclass_q <= 2'b0; + entry4_hv_q <= 1'b0; + entry4_ds_q <= 1'b0; + entry4_thdid_q <= 4'b0; + entry4_pid_q <= 8'b0; + entry4_v_q <= 1'b0; + entry4_parity_q <= 10'b0; + entry4_cmpmask_q <= 9'b0; + entry5_size_q <= 3'b0; + entry5_xbit_q <= 1'b0; + entry5_epn_q <= 52'b0; + entry5_class_q <= 2'b0; + entry5_extclass_q <= 2'b0; + entry5_hv_q <= 1'b0; + entry5_ds_q <= 1'b0; + entry5_thdid_q <= 4'b0; + entry5_pid_q <= 8'b0; + entry5_v_q <= 1'b0; + entry5_parity_q <= 10'b0; + entry5_cmpmask_q <= 9'b0; + entry6_size_q <= 3'b0; + entry6_xbit_q <= 1'b0; + entry6_epn_q <= 52'b0; + entry6_class_q <= 2'b0; + entry6_extclass_q <= 2'b0; + entry6_hv_q <= 1'b0; + entry6_ds_q <= 1'b0; + entry6_thdid_q <= 4'b0; + entry6_pid_q <= 8'b0; + entry6_v_q <= 1'b0; + entry6_parity_q <= 10'b0; + entry6_cmpmask_q <= 9'b0; + entry7_size_q <= 3'b0; + entry7_xbit_q <= 1'b0; + entry7_epn_q <= 52'b0; + entry7_class_q <= 2'b0; + entry7_extclass_q <= 2'b0; + entry7_hv_q <= 1'b0; + entry7_ds_q <= 1'b0; + entry7_thdid_q <= 4'b0; + entry7_pid_q <= 8'b0; + entry7_v_q <= 1'b0; + entry7_parity_q <= 10'b0; + entry7_cmpmask_q <= 9'b0; + entry8_size_q <= 3'b0; + entry8_xbit_q <= 1'b0; + entry8_epn_q <= 52'b0; + entry8_class_q <= 2'b0; + entry8_extclass_q <= 2'b0; + entry8_hv_q <= 1'b0; + entry8_ds_q <= 1'b0; + entry8_thdid_q <= 4'b0; + entry8_pid_q <= 8'b0; + entry8_v_q <= 1'b0; + entry8_parity_q <= 10'b0; + entry8_cmpmask_q <= 9'b0; + entry9_size_q <= 3'b0; + entry9_xbit_q <= 1'b0; + entry9_epn_q <= 52'b0; + entry9_class_q <= 2'b0; + entry9_extclass_q <= 2'b0; + entry9_hv_q <= 1'b0; + entry9_ds_q <= 1'b0; + entry9_thdid_q <= 4'b0; + entry9_pid_q <= 8'b0; + entry9_v_q <= 1'b0; + entry9_parity_q <= 10'b0; + entry9_cmpmask_q <= 9'b0; + entry10_size_q <= 3'b0; + entry10_xbit_q <= 1'b0; + entry10_epn_q <= 52'b0; + entry10_class_q <= 2'b0; + entry10_extclass_q <= 2'b0; + entry10_hv_q <= 1'b0; + entry10_ds_q <= 1'b0; + entry10_thdid_q <= 4'b0; + entry10_pid_q <= 8'b0; + entry10_v_q <= 1'b0; + entry10_parity_q <= 10'b0; + entry10_cmpmask_q <= 9'b0; + entry11_size_q <= 3'b0; + entry11_xbit_q <= 1'b0; + entry11_epn_q <= 52'b0; + entry11_class_q <= 2'b0; + entry11_extclass_q <= 2'b0; + entry11_hv_q <= 1'b0; + entry11_ds_q <= 1'b0; + entry11_thdid_q <= 4'b0; + entry11_pid_q <= 8'b0; + entry11_v_q <= 1'b0; + entry11_parity_q <= 10'b0; + entry11_cmpmask_q <= 9'b0; + entry12_size_q <= 3'b0; + entry12_xbit_q <= 1'b0; + entry12_epn_q <= 52'b0; + entry12_class_q <= 2'b0; + entry12_extclass_q <= 2'b0; + entry12_hv_q <= 1'b0; + entry12_ds_q <= 1'b0; + entry12_thdid_q <= 4'b0; + entry12_pid_q <= 8'b0; + entry12_v_q <= 1'b0; + entry12_parity_q <= 10'b0; + entry12_cmpmask_q <= 9'b0; + entry13_size_q <= 3'b0; + entry13_xbit_q <= 1'b0; + entry13_epn_q <= 52'b0; + entry13_class_q <= 2'b0; + entry13_extclass_q <= 2'b0; + entry13_hv_q <= 1'b0; + entry13_ds_q <= 1'b0; + entry13_thdid_q <= 4'b0; + entry13_pid_q <= 8'b0; + entry13_v_q <= 1'b0; + entry13_parity_q <= 10'b0; + entry13_cmpmask_q <= 9'b0; + entry14_size_q <= 3'b0; + entry14_xbit_q <= 1'b0; + entry14_epn_q <= 52'b0; + entry14_class_q <= 2'b0; + entry14_extclass_q <= 2'b0; + entry14_hv_q <= 1'b0; + entry14_ds_q <= 1'b0; + entry14_thdid_q <= 4'b0; + entry14_pid_q <= 8'b0; + entry14_v_q <= 1'b0; + entry14_parity_q <= 10'b0; + entry14_cmpmask_q <= 9'b0; + entry15_size_q <= 3'b0; + entry15_xbit_q <= 1'b0; + entry15_epn_q <= 52'b0; + entry15_class_q <= 2'b0; + entry15_extclass_q <= 2'b0; + entry15_hv_q <= 1'b0; + entry15_ds_q <= 1'b0; + entry15_thdid_q <= 4'b0; + entry15_pid_q <= 8'b0; + entry15_v_q <= 1'b0; + entry15_parity_q <= 10'b0; + entry15_cmpmask_q <= 9'b0; + end + else + begin + cam_cmp_data_q <= cam_cmp_data_d; + rd_cam_data_q <= rd_cam_data_d; + rd_array_data_q <= rd_array_data_d; + entry_match_q <= entry_match_d; + cam_hit_entry_q <= cam_hit_entry_d; + cam_hit_q <= cam_hit_d; + cam_cmp_parity_q <= cam_cmp_parity_d; + comp_addr_np1_q <= comp_addr_np1_d; + rpn_np2_q <= rpn_np2_d; + attr_np2_q <= attr_np2_d; + entry0_size_q <= entry0_size_d; + entry0_xbit_q <= entry0_xbit_d; + entry0_epn_q <= entry0_epn_d; + entry0_class_q <= entry0_class_d; + entry0_extclass_q <= entry0_extclass_d; + entry0_hv_q <= entry0_hv_d; + entry0_ds_q <= entry0_ds_d; + entry0_thdid_q <= entry0_thdid_d; + entry0_pid_q <= entry0_pid_d; + entry0_v_q <= entry0_v_d; + entry0_parity_q <= entry0_parity_d; + entry0_cmpmask_q <= entry0_cmpmask_d; + entry1_size_q <= entry1_size_d; + entry1_xbit_q <= entry1_xbit_d; + entry1_epn_q <= entry1_epn_d; + entry1_class_q <= entry1_class_d; + entry1_extclass_q <= entry1_extclass_d; + entry1_hv_q <= entry1_hv_d; + entry1_ds_q <= entry1_ds_d; + entry1_thdid_q <= entry1_thdid_d; + entry1_pid_q <= entry1_pid_d; + entry1_v_q <= entry1_v_d; + entry1_parity_q <= entry1_parity_d; + entry1_cmpmask_q <= entry1_cmpmask_d; + entry2_size_q <= entry2_size_d; + entry2_xbit_q <= entry2_xbit_d; + entry2_epn_q <= entry2_epn_d; + entry2_class_q <= entry2_class_d; + entry2_extclass_q <= entry2_extclass_d; + entry2_hv_q <= entry2_hv_d; + entry2_ds_q <= entry2_ds_d; + entry2_thdid_q <= entry2_thdid_d; + entry2_pid_q <= entry2_pid_d; + entry2_v_q <= entry2_v_d; + entry2_parity_q <= entry2_parity_d; + entry2_cmpmask_q <= entry2_cmpmask_d; + entry3_size_q <= entry3_size_d; + entry3_xbit_q <= entry3_xbit_d; + entry3_epn_q <= entry3_epn_d; + entry3_class_q <= entry3_class_d; + entry3_extclass_q <= entry3_extclass_d; + entry3_hv_q <= entry3_hv_d; + entry3_ds_q <= entry3_ds_d; + entry3_thdid_q <= entry3_thdid_d; + entry3_pid_q <= entry3_pid_d; + entry3_v_q <= entry3_v_d; + entry3_parity_q <= entry3_parity_d; + entry3_cmpmask_q <= entry3_cmpmask_d; + entry4_size_q <= entry4_size_d; + entry4_xbit_q <= entry4_xbit_d; + entry4_epn_q <= entry4_epn_d; + entry4_class_q <= entry4_class_d; + entry4_extclass_q <= entry4_extclass_d; + entry4_hv_q <= entry4_hv_d; + entry4_ds_q <= entry4_ds_d; + entry4_thdid_q <= entry4_thdid_d; + entry4_pid_q <= entry4_pid_d; + entry4_v_q <= entry4_v_d; + entry4_parity_q <= entry4_parity_d; + entry4_cmpmask_q <= entry4_cmpmask_d; + entry5_size_q <= entry5_size_d; + entry5_xbit_q <= entry5_xbit_d; + entry5_epn_q <= entry5_epn_d; + entry5_class_q <= entry5_class_d; + entry5_extclass_q <= entry5_extclass_d; + entry5_hv_q <= entry5_hv_d; + entry5_ds_q <= entry5_ds_d; + entry5_thdid_q <= entry5_thdid_d; + entry5_pid_q <= entry5_pid_d; + entry5_v_q <= entry5_v_d; + entry5_parity_q <= entry5_parity_d; + entry5_cmpmask_q <= entry5_cmpmask_d; + entry6_size_q <= entry6_size_d; + entry6_xbit_q <= entry6_xbit_d; + entry6_epn_q <= entry6_epn_d; + entry6_class_q <= entry6_class_d; + entry6_extclass_q <= entry6_extclass_d; + entry6_hv_q <= entry6_hv_d; + entry6_ds_q <= entry6_ds_d; + entry6_thdid_q <= entry6_thdid_d; + entry6_pid_q <= entry6_pid_d; + entry6_v_q <= entry6_v_d; + entry6_parity_q <= entry6_parity_d; + entry6_cmpmask_q <= entry6_cmpmask_d; + entry7_size_q <= entry7_size_d; + entry7_xbit_q <= entry7_xbit_d; + entry7_epn_q <= entry7_epn_d; + entry7_class_q <= entry7_class_d; + entry7_extclass_q <= entry7_extclass_d; + entry7_hv_q <= entry7_hv_d; + entry7_ds_q <= entry7_ds_d; + entry7_thdid_q <= entry7_thdid_d; + entry7_pid_q <= entry7_pid_d; + entry7_v_q <= entry7_v_d; + entry7_parity_q <= entry7_parity_d; + entry7_cmpmask_q <= entry7_cmpmask_d; + entry8_size_q <= entry8_size_d; + entry8_xbit_q <= entry8_xbit_d; + entry8_epn_q <= entry8_epn_d; + entry8_class_q <= entry8_class_d; + entry8_extclass_q <= entry8_extclass_d; + entry8_hv_q <= entry8_hv_d; + entry8_ds_q <= entry8_ds_d; + entry8_thdid_q <= entry8_thdid_d; + entry8_pid_q <= entry8_pid_d; + entry8_v_q <= entry8_v_d; + entry8_parity_q <= entry8_parity_d; + entry8_cmpmask_q <= entry8_cmpmask_d; + entry9_size_q <= entry9_size_d; + entry9_xbit_q <= entry9_xbit_d; + entry9_epn_q <= entry9_epn_d; + entry9_class_q <= entry9_class_d; + entry9_extclass_q <= entry9_extclass_d; + entry9_hv_q <= entry9_hv_d; + entry9_ds_q <= entry9_ds_d; + entry9_thdid_q <= entry9_thdid_d; + entry9_pid_q <= entry9_pid_d; + entry9_v_q <= entry9_v_d; + entry9_parity_q <= entry9_parity_d; + entry9_cmpmask_q <= entry9_cmpmask_d; + entry10_size_q <= entry10_size_d; + entry10_xbit_q <= entry10_xbit_d; + entry10_epn_q <= entry10_epn_d; + entry10_class_q <= entry10_class_d; + entry10_extclass_q <= entry10_extclass_d; + entry10_hv_q <= entry10_hv_d; + entry10_ds_q <= entry10_ds_d; + entry10_thdid_q <= entry10_thdid_d; + entry10_pid_q <= entry10_pid_d; + entry10_v_q <= entry10_v_d; + entry10_parity_q <= entry10_parity_d; + entry10_cmpmask_q <= entry10_cmpmask_d; + entry11_size_q <= entry11_size_d; + entry11_xbit_q <= entry11_xbit_d; + entry11_epn_q <= entry11_epn_d; + entry11_class_q <= entry11_class_d; + entry11_extclass_q <= entry11_extclass_d; + entry11_hv_q <= entry11_hv_d; + entry11_ds_q <= entry11_ds_d; + entry11_thdid_q <= entry11_thdid_d; + entry11_pid_q <= entry11_pid_d; + entry11_v_q <= entry11_v_d; + entry11_parity_q <= entry11_parity_d; + entry11_cmpmask_q <= entry11_cmpmask_d; + entry12_size_q <= entry12_size_d; + entry12_xbit_q <= entry12_xbit_d; + entry12_epn_q <= entry12_epn_d; + entry12_class_q <= entry12_class_d; + entry12_extclass_q <= entry12_extclass_d; + entry12_hv_q <= entry12_hv_d; + entry12_ds_q <= entry12_ds_d; + entry12_thdid_q <= entry12_thdid_d; + entry12_pid_q <= entry12_pid_d; + entry12_v_q <= entry12_v_d; + entry12_parity_q <= entry12_parity_d; + entry12_cmpmask_q <= entry12_cmpmask_d; + entry13_size_q <= entry13_size_d; + entry13_xbit_q <= entry13_xbit_d; + entry13_epn_q <= entry13_epn_d; + entry13_class_q <= entry13_class_d; + entry13_extclass_q <= entry13_extclass_d; + entry13_hv_q <= entry13_hv_d; + entry13_ds_q <= entry13_ds_d; + entry13_thdid_q <= entry13_thdid_d; + entry13_pid_q <= entry13_pid_d; + entry13_v_q <= entry13_v_d; + entry13_parity_q <= entry13_parity_d; + entry13_cmpmask_q <= entry13_cmpmask_d; + entry14_size_q <= entry14_size_d; + entry14_xbit_q <= entry14_xbit_d; + entry14_epn_q <= entry14_epn_d; + entry14_class_q <= entry14_class_d; + entry14_extclass_q <= entry14_extclass_d; + entry14_hv_q <= entry14_hv_d; + entry14_ds_q <= entry14_ds_d; + entry14_thdid_q <= entry14_thdid_d; + entry14_pid_q <= entry14_pid_d; + entry14_v_q <= entry14_v_d; + entry14_parity_q <= entry14_parity_d; + entry14_cmpmask_q <= entry14_cmpmask_d; + entry15_size_q <= entry15_size_d; + entry15_xbit_q <= entry15_xbit_d; + entry15_epn_q <= entry15_epn_d; + entry15_class_q <= entry15_class_d; + entry15_extclass_q <= entry15_extclass_d; + entry15_hv_q <= entry15_hv_d; + entry15_ds_q <= entry15_ds_d; + entry15_thdid_q <= entry15_thdid_d; + entry15_pid_q <= entry15_pid_d; + entry15_v_q <= entry15_v_d; + entry15_parity_q <= entry15_parity_d; + entry15_cmpmask_q <= entry15_cmpmask_d; + end + end + + //--------------------------------------------------------------------- + // latch input logic + //--------------------------------------------------------------------- + assign comp_addr_np1_d = comp_addr[52 - RPN_WIDTH:51]; + + assign cam_hit_d = ((match_vec != 16'b0000000000000000) & (comp_request == 1'b1)) ? 1'b1 : + 1'b0; + + assign cam_hit_entry_d = (match_vec[0:1] == 2'b01) ? 4'b0001 : + (match_vec[0:2] == 3'b001) ? 4'b0010 : + (match_vec[0:3] == 4'b0001) ? 4'b0011 : + (match_vec[0:4] == 5'b00001) ? 4'b0100 : + (match_vec[0:5] == 6'b000001) ? 4'b0101 : + (match_vec[0:6] == 7'b0000001) ? 4'b0110 : + (match_vec[0:7] == 8'b00000001) ? 4'b0111 : + (match_vec[0:8] == 9'b000000001) ? 4'b1000 : + (match_vec[0:9] == 10'b0000000001) ? 4'b1001 : + (match_vec[0:10] == 11'b00000000001) ? 4'b1010 : + (match_vec[0:11] == 12'b000000000001) ? 4'b1011 : + (match_vec[0:12] == 13'b0000000000001) ? 4'b1100 : + (match_vec[0:13] == 14'b00000000000001) ? 4'b1101 : + (match_vec[0:14] == 15'b000000000000001) ? 4'b1110 : + (match_vec[0:15] == 16'b0000000000000001) ? 4'b1111 : + 4'b0000; + + assign entry_match_d = ((comp_request == 1'b1)) ? match_vec : + {NUM_ENTRY{1'b0}}; + + // entry write next state logic + assign wr_entry0_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0000)) ? 1'b1 : + 1'b0; + assign wr_entry0_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0000)) ? 1'b1 : + 1'b0; + assign entry0_epn_d[0:31] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry0_epn_q[0:31]; + assign entry0_epn_d[32:51] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry0_epn_q[32:51]; + assign entry0_xbit_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[52] : + entry0_xbit_q; + assign entry0_size_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry0_size_q[0:2]; + assign entry0_class_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry0_class_q[0:1]; + assign entry0_extclass_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry0_extclass_q[0:1]; + assign entry0_hv_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[65] : + entry0_hv_q; + assign entry0_ds_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[66] : + entry0_ds_q; + assign entry0_pid_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry0_pid_q[0:7]; + assign entry0_cmpmask_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry0_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry0_parity_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry0_parity_q[0:3]; + assign entry0_parity_d[4:6] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry0_parity_q[4:6]; + assign entry0_parity_d[7] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry0_parity_q[7]; + assign entry0_parity_d[8] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry0_parity_q[8]; + assign entry0_parity_d[9] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry0_parity_q[9]; + assign wr_entry1_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0001)) ? 1'b1 : + 1'b0; + assign wr_entry1_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0001)) ? 1'b1 : + 1'b0; + assign entry1_epn_d[0:31] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry1_epn_q[0:31]; + assign entry1_epn_d[32:51] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry1_epn_q[32:51]; + assign entry1_xbit_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[52] : + entry1_xbit_q; + assign entry1_size_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry1_size_q[0:2]; + assign entry1_class_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry1_class_q[0:1]; + assign entry1_extclass_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry1_extclass_q[0:1]; + assign entry1_hv_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[65] : + entry1_hv_q; + assign entry1_ds_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[66] : + entry1_ds_q; + assign entry1_pid_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry1_pid_q[0:7]; + assign entry1_cmpmask_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry1_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry1_parity_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry1_parity_q[0:3]; + assign entry1_parity_d[4:6] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry1_parity_q[4:6]; + assign entry1_parity_d[7] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry1_parity_q[7]; + assign entry1_parity_d[8] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry1_parity_q[8]; + assign entry1_parity_d[9] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry1_parity_q[9]; + assign wr_entry2_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0010)) ? 1'b1 : + 1'b0; + assign wr_entry2_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0010)) ? 1'b1 : + 1'b0; + assign entry2_epn_d[0:31] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry2_epn_q[0:31]; + assign entry2_epn_d[32:51] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry2_epn_q[32:51]; + assign entry2_xbit_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[52] : + entry2_xbit_q; + assign entry2_size_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry2_size_q[0:2]; + assign entry2_class_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry2_class_q[0:1]; + assign entry2_extclass_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry2_extclass_q[0:1]; + assign entry2_hv_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[65] : + entry2_hv_q; + assign entry2_ds_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[66] : + entry2_ds_q; + assign entry2_pid_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry2_pid_q[0:7]; + assign entry2_cmpmask_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry2_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry2_parity_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry2_parity_q[0:3]; + assign entry2_parity_d[4:6] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry2_parity_q[4:6]; + assign entry2_parity_d[7] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry2_parity_q[7]; + assign entry2_parity_d[8] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry2_parity_q[8]; + assign entry2_parity_d[9] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry2_parity_q[9]; + assign wr_entry3_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0011)) ? 1'b1 : + 1'b0; + assign wr_entry3_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0011)) ? 1'b1 : + 1'b0; + assign entry3_epn_d[0:31] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry3_epn_q[0:31]; + assign entry3_epn_d[32:51] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry3_epn_q[32:51]; + assign entry3_xbit_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[52] : + entry3_xbit_q; + assign entry3_size_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry3_size_q[0:2]; + assign entry3_class_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry3_class_q[0:1]; + assign entry3_extclass_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry3_extclass_q[0:1]; + assign entry3_hv_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[65] : + entry3_hv_q; + assign entry3_ds_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[66] : + entry3_ds_q; + assign entry3_pid_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry3_pid_q[0:7]; + assign entry3_cmpmask_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry3_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry3_parity_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry3_parity_q[0:3]; + assign entry3_parity_d[4:6] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry3_parity_q[4:6]; + assign entry3_parity_d[7] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry3_parity_q[7]; + assign entry3_parity_d[8] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry3_parity_q[8]; + assign entry3_parity_d[9] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry3_parity_q[9]; + assign wr_entry4_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0100)) ? 1'b1 : + 1'b0; + assign wr_entry4_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0100)) ? 1'b1 : + 1'b0; + assign entry4_epn_d[0:31] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry4_epn_q[0:31]; + assign entry4_epn_d[32:51] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry4_epn_q[32:51]; + assign entry4_xbit_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[52] : + entry4_xbit_q; + assign entry4_size_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry4_size_q[0:2]; + assign entry4_class_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry4_class_q[0:1]; + assign entry4_extclass_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry4_extclass_q[0:1]; + assign entry4_hv_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[65] : + entry4_hv_q; + assign entry4_ds_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[66] : + entry4_ds_q; + assign entry4_pid_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry4_pid_q[0:7]; + assign entry4_cmpmask_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry4_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry4_parity_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry4_parity_q[0:3]; + assign entry4_parity_d[4:6] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry4_parity_q[4:6]; + assign entry4_parity_d[7] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry4_parity_q[7]; + assign entry4_parity_d[8] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry4_parity_q[8]; + assign entry4_parity_d[9] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry4_parity_q[9]; + assign wr_entry5_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0101)) ? 1'b1 : + 1'b0; + assign wr_entry5_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0101)) ? 1'b1 : + 1'b0; + assign entry5_epn_d[0:31] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry5_epn_q[0:31]; + assign entry5_epn_d[32:51] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry5_epn_q[32:51]; + assign entry5_xbit_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[52] : + entry5_xbit_q; + assign entry5_size_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry5_size_q[0:2]; + assign entry5_class_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry5_class_q[0:1]; + assign entry5_extclass_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry5_extclass_q[0:1]; + assign entry5_hv_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[65] : + entry5_hv_q; + assign entry5_ds_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[66] : + entry5_ds_q; + assign entry5_pid_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry5_pid_q[0:7]; + assign entry5_cmpmask_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry5_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry5_parity_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry5_parity_q[0:3]; + assign entry5_parity_d[4:6] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry5_parity_q[4:6]; + assign entry5_parity_d[7] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry5_parity_q[7]; + assign entry5_parity_d[8] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry5_parity_q[8]; + assign entry5_parity_d[9] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry5_parity_q[9]; + assign wr_entry6_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0110)) ? 1'b1 : + 1'b0; + assign wr_entry6_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0110)) ? 1'b1 : + 1'b0; + assign entry6_epn_d[0:31] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry6_epn_q[0:31]; + assign entry6_epn_d[32:51] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry6_epn_q[32:51]; + assign entry6_xbit_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[52] : + entry6_xbit_q; + assign entry6_size_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry6_size_q[0:2]; + assign entry6_class_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry6_class_q[0:1]; + assign entry6_extclass_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry6_extclass_q[0:1]; + assign entry6_hv_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[65] : + entry6_hv_q; + assign entry6_ds_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[66] : + entry6_ds_q; + assign entry6_pid_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry6_pid_q[0:7]; + assign entry6_cmpmask_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry6_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry6_parity_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry6_parity_q[0:3]; + assign entry6_parity_d[4:6] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry6_parity_q[4:6]; + assign entry6_parity_d[7] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry6_parity_q[7]; + assign entry6_parity_d[8] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry6_parity_q[8]; + assign entry6_parity_d[9] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry6_parity_q[9]; + assign wr_entry7_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0111)) ? 1'b1 : + 1'b0; + assign wr_entry7_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0111)) ? 1'b1 : + 1'b0; + assign entry7_epn_d[0:31] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry7_epn_q[0:31]; + assign entry7_epn_d[32:51] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry7_epn_q[32:51]; + assign entry7_xbit_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[52] : + entry7_xbit_q; + assign entry7_size_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry7_size_q[0:2]; + assign entry7_class_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry7_class_q[0:1]; + assign entry7_extclass_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry7_extclass_q[0:1]; + assign entry7_hv_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[65] : + entry7_hv_q; + assign entry7_ds_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[66] : + entry7_ds_q; + assign entry7_pid_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry7_pid_q[0:7]; + assign entry7_cmpmask_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry7_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry7_parity_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry7_parity_q[0:3]; + assign entry7_parity_d[4:6] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry7_parity_q[4:6]; + assign entry7_parity_d[7] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry7_parity_q[7]; + assign entry7_parity_d[8] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry7_parity_q[8]; + assign entry7_parity_d[9] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry7_parity_q[9]; + assign wr_entry8_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1000)) ? 1'b1 : + 1'b0; + assign wr_entry8_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1000)) ? 1'b1 : + 1'b0; + assign entry8_epn_d[0:31] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry8_epn_q[0:31]; + assign entry8_epn_d[32:51] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry8_epn_q[32:51]; + assign entry8_xbit_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[52] : + entry8_xbit_q; + assign entry8_size_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry8_size_q[0:2]; + assign entry8_class_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry8_class_q[0:1]; + assign entry8_extclass_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry8_extclass_q[0:1]; + assign entry8_hv_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[65] : + entry8_hv_q; + assign entry8_ds_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[66] : + entry8_ds_q; + assign entry8_pid_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry8_pid_q[0:7]; + assign entry8_cmpmask_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry8_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry8_parity_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry8_parity_q[0:3]; + assign entry8_parity_d[4:6] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry8_parity_q[4:6]; + assign entry8_parity_d[7] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry8_parity_q[7]; + assign entry8_parity_d[8] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry8_parity_q[8]; + assign entry8_parity_d[9] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry8_parity_q[9]; + assign wr_entry9_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1001)) ? 1'b1 : + 1'b0; + assign wr_entry9_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1001)) ? 1'b1 : + 1'b0; + assign entry9_epn_d[0:31] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry9_epn_q[0:31]; + assign entry9_epn_d[32:51] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry9_epn_q[32:51]; + assign entry9_xbit_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[52] : + entry9_xbit_q; + assign entry9_size_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry9_size_q[0:2]; + assign entry9_class_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry9_class_q[0:1]; + assign entry9_extclass_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry9_extclass_q[0:1]; + assign entry9_hv_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[65] : + entry9_hv_q; + assign entry9_ds_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[66] : + entry9_ds_q; + assign entry9_pid_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry9_pid_q[0:7]; + assign entry9_cmpmask_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry9_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry9_parity_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry9_parity_q[0:3]; + assign entry9_parity_d[4:6] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry9_parity_q[4:6]; + assign entry9_parity_d[7] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry9_parity_q[7]; + assign entry9_parity_d[8] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry9_parity_q[8]; + assign entry9_parity_d[9] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry9_parity_q[9]; + assign wr_entry10_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1010)) ? 1'b1 : + 1'b0; + assign wr_entry10_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1010)) ? 1'b1 : + 1'b0; + assign entry10_epn_d[0:31] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry10_epn_q[0:31]; + assign entry10_epn_d[32:51] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry10_epn_q[32:51]; + assign entry10_xbit_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[52] : + entry10_xbit_q; + assign entry10_size_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry10_size_q[0:2]; + assign entry10_class_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry10_class_q[0:1]; + assign entry10_extclass_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry10_extclass_q[0:1]; + assign entry10_hv_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[65] : + entry10_hv_q; + assign entry10_ds_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[66] : + entry10_ds_q; + assign entry10_pid_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry10_pid_q[0:7]; + assign entry10_cmpmask_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry10_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry10_parity_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry10_parity_q[0:3]; + assign entry10_parity_d[4:6] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry10_parity_q[4:6]; + assign entry10_parity_d[7] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry10_parity_q[7]; + assign entry10_parity_d[8] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry10_parity_q[8]; + assign entry10_parity_d[9] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry10_parity_q[9]; + assign wr_entry11_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1011)) ? 1'b1 : + 1'b0; + assign wr_entry11_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1011)) ? 1'b1 : + 1'b0; + assign entry11_epn_d[0:31] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry11_epn_q[0:31]; + assign entry11_epn_d[32:51] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry11_epn_q[32:51]; + assign entry11_xbit_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[52] : + entry11_xbit_q; + assign entry11_size_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry11_size_q[0:2]; + assign entry11_class_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry11_class_q[0:1]; + assign entry11_extclass_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry11_extclass_q[0:1]; + assign entry11_hv_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[65] : + entry11_hv_q; + assign entry11_ds_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[66] : + entry11_ds_q; + assign entry11_pid_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry11_pid_q[0:7]; + assign entry11_cmpmask_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry11_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry11_parity_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry11_parity_q[0:3]; + assign entry11_parity_d[4:6] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry11_parity_q[4:6]; + assign entry11_parity_d[7] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry11_parity_q[7]; + assign entry11_parity_d[8] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry11_parity_q[8]; + assign entry11_parity_d[9] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry11_parity_q[9]; + assign wr_entry12_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1100)) ? 1'b1 : + 1'b0; + assign wr_entry12_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1100)) ? 1'b1 : + 1'b0; + assign entry12_epn_d[0:31] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry12_epn_q[0:31]; + assign entry12_epn_d[32:51] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry12_epn_q[32:51]; + assign entry12_xbit_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[52] : + entry12_xbit_q; + assign entry12_size_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry12_size_q[0:2]; + assign entry12_class_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry12_class_q[0:1]; + assign entry12_extclass_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry12_extclass_q[0:1]; + assign entry12_hv_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[65] : + entry12_hv_q; + assign entry12_ds_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[66] : + entry12_ds_q; + assign entry12_pid_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry12_pid_q[0:7]; + assign entry12_cmpmask_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry12_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry12_parity_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry12_parity_q[0:3]; + assign entry12_parity_d[4:6] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry12_parity_q[4:6]; + assign entry12_parity_d[7] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry12_parity_q[7]; + assign entry12_parity_d[8] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry12_parity_q[8]; + assign entry12_parity_d[9] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry12_parity_q[9]; + assign wr_entry13_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1101)) ? 1'b1 : + 1'b0; + assign wr_entry13_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1101)) ? 1'b1 : + 1'b0; + assign entry13_epn_d[0:31] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry13_epn_q[0:31]; + assign entry13_epn_d[32:51] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry13_epn_q[32:51]; + assign entry13_xbit_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[52] : + entry13_xbit_q; + assign entry13_size_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry13_size_q[0:2]; + assign entry13_class_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry13_class_q[0:1]; + assign entry13_extclass_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry13_extclass_q[0:1]; + assign entry13_hv_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[65] : + entry13_hv_q; + assign entry13_ds_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[66] : + entry13_ds_q; + assign entry13_pid_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry13_pid_q[0:7]; + assign entry13_cmpmask_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry13_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry13_parity_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry13_parity_q[0:3]; + assign entry13_parity_d[4:6] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry13_parity_q[4:6]; + assign entry13_parity_d[7] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry13_parity_q[7]; + assign entry13_parity_d[8] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry13_parity_q[8]; + assign entry13_parity_d[9] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry13_parity_q[9]; + assign wr_entry14_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1110)) ? 1'b1 : + 1'b0; + assign wr_entry14_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1110)) ? 1'b1 : + 1'b0; + assign entry14_epn_d[0:31] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry14_epn_q[0:31]; + assign entry14_epn_d[32:51] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry14_epn_q[32:51]; + assign entry14_xbit_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[52] : + entry14_xbit_q; + assign entry14_size_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry14_size_q[0:2]; + assign entry14_class_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry14_class_q[0:1]; + assign entry14_extclass_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry14_extclass_q[0:1]; + assign entry14_hv_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[65] : + entry14_hv_q; + assign entry14_ds_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[66] : + entry14_ds_q; + assign entry14_pid_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry14_pid_q[0:7]; + assign entry14_cmpmask_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry14_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry14_parity_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry14_parity_q[0:3]; + assign entry14_parity_d[4:6] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry14_parity_q[4:6]; + assign entry14_parity_d[7] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry14_parity_q[7]; + assign entry14_parity_d[8] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry14_parity_q[8]; + assign entry14_parity_d[9] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry14_parity_q[9]; + assign wr_entry15_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1111)) ? 1'b1 : + 1'b0; + assign wr_entry15_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1111)) ? 1'b1 : + 1'b0; + assign entry15_epn_d[0:31] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry15_epn_q[0:31]; + assign entry15_epn_d[32:51] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry15_epn_q[32:51]; + assign entry15_xbit_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[52] : + entry15_xbit_q; + assign entry15_size_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry15_size_q[0:2]; + assign entry15_class_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry15_class_q[0:1]; + assign entry15_extclass_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry15_extclass_q[0:1]; + assign entry15_hv_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[65] : + entry15_hv_q; + assign entry15_ds_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[66] : + entry15_ds_q; + assign entry15_pid_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry15_pid_q[0:7]; + assign entry15_cmpmask_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry15_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry15_parity_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry15_parity_q[0:3]; + assign entry15_parity_d[4:6] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry15_parity_q[4:6]; + assign entry15_parity_d[7] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry15_parity_q[7]; + assign entry15_parity_d[8] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry15_parity_q[8]; + assign entry15_parity_d[9] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry15_parity_q[9]; + + + // entry valid and thdid next state logic + assign entry0_inval = (comp_invalidate & match_vec[0]) | flash_invalidate; + assign entry0_v_muxsel[0:1] = ({entry0_inval, wr_entry0_sel[0]}); + assign entry0_v_d = (entry0_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry0_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry0_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry0_v_q; + assign entry0_thdid_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry0_thdid_q[0:3]; + assign entry1_inval = (comp_invalidate & match_vec[1]) | flash_invalidate; + assign entry1_v_muxsel[0:1] = ({entry1_inval, wr_entry1_sel[0]}); + assign entry1_v_d = (entry1_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry1_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry1_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry1_v_q; + assign entry1_thdid_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry1_thdid_q[0:3]; + assign entry2_inval = (comp_invalidate & match_vec[2]) | flash_invalidate; + assign entry2_v_muxsel[0:1] = ({entry2_inval, wr_entry2_sel[0]}); + assign entry2_v_d = (entry2_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry2_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry2_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry2_v_q; + assign entry2_thdid_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry2_thdid_q[0:3]; + assign entry3_inval = (comp_invalidate & match_vec[3]) | flash_invalidate; + assign entry3_v_muxsel[0:1] = ({entry3_inval, wr_entry3_sel[0]}); + assign entry3_v_d = (entry3_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry3_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry3_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry3_v_q; + assign entry3_thdid_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry3_thdid_q[0:3]; + assign entry4_inval = (comp_invalidate & match_vec[4]) | flash_invalidate; + assign entry4_v_muxsel[0:1] = ({entry4_inval, wr_entry4_sel[0]}); + assign entry4_v_d = (entry4_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry4_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry4_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry4_v_q; + assign entry4_thdid_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry4_thdid_q[0:3]; + assign entry5_inval = (comp_invalidate & match_vec[5]) | flash_invalidate; + assign entry5_v_muxsel[0:1] = ({entry5_inval, wr_entry5_sel[0]}); + assign entry5_v_d = (entry5_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry5_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry5_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry5_v_q; + assign entry5_thdid_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry5_thdid_q[0:3]; + assign entry6_inval = (comp_invalidate & match_vec[6]) | flash_invalidate; + assign entry6_v_muxsel[0:1] = ({entry6_inval, wr_entry6_sel[0]}); + assign entry6_v_d = (entry6_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry6_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry6_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry6_v_q; + assign entry6_thdid_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry6_thdid_q[0:3]; + assign entry7_inval = (comp_invalidate & match_vec[7]) | flash_invalidate; + assign entry7_v_muxsel[0:1] = ({entry7_inval, wr_entry7_sel[0]}); + assign entry7_v_d = (entry7_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry7_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry7_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry7_v_q; + assign entry7_thdid_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry7_thdid_q[0:3]; + assign entry8_inval = (comp_invalidate & match_vec[8]) | flash_invalidate; + assign entry8_v_muxsel[0:1] = ({entry8_inval, wr_entry8_sel[0]}); + assign entry8_v_d = (entry8_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry8_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry8_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry8_v_q; + assign entry8_thdid_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry8_thdid_q[0:3]; + assign entry9_inval = (comp_invalidate & match_vec[9]) | flash_invalidate; + assign entry9_v_muxsel[0:1] = ({entry9_inval, wr_entry9_sel[0]}); + assign entry9_v_d = (entry9_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry9_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry9_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry9_v_q; + assign entry9_thdid_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry9_thdid_q[0:3]; + assign entry10_inval = (comp_invalidate & match_vec[10]) | flash_invalidate; + assign entry10_v_muxsel[0:1] = ({entry10_inval, wr_entry10_sel[0]}); + assign entry10_v_d = (entry10_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry10_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry10_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry10_v_q; + assign entry10_thdid_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry10_thdid_q[0:3]; + assign entry11_inval = (comp_invalidate & match_vec[11]) | flash_invalidate; + assign entry11_v_muxsel[0:1] = ({entry11_inval, wr_entry11_sel[0]}); + assign entry11_v_d = (entry11_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry11_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry11_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry11_v_q; + assign entry11_thdid_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry11_thdid_q[0:3]; + assign entry12_inval = (comp_invalidate & match_vec[12]) | flash_invalidate; + assign entry12_v_muxsel[0:1] = ({entry12_inval, wr_entry12_sel[0]}); + assign entry12_v_d = (entry12_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry12_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry12_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry12_v_q; + assign entry12_thdid_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry12_thdid_q[0:3]; + assign entry13_inval = (comp_invalidate & match_vec[13]) | flash_invalidate; + assign entry13_v_muxsel[0:1] = ({entry13_inval, wr_entry13_sel[0]}); + assign entry13_v_d = (entry13_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry13_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry13_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry13_v_q; + assign entry13_thdid_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry13_thdid_q[0:3]; + assign entry14_inval = (comp_invalidate & match_vec[14]) | flash_invalidate; + assign entry14_v_muxsel[0:1] = ({entry14_inval, wr_entry14_sel[0]}); + assign entry14_v_d = (entry14_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry14_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry14_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry14_v_q; + assign entry14_thdid_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry14_thdid_q[0:3]; + assign entry15_inval = (comp_invalidate & match_vec[15]) | flash_invalidate; + assign entry15_v_muxsel[0:1] = ({entry15_inval, wr_entry15_sel[0]}); + assign entry15_v_d = (entry15_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry15_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry15_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry15_v_q; + assign entry15_thdid_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry15_thdid_q[0:3]; + + + // CAM compare data out mux + assign entry0_cam_vec = {entry0_epn_q, entry0_xbit_q, entry0_size_q, entry0_v_q, entry0_thdid_q, entry0_class_q, entry0_extclass_q, entry0_hv_q, entry0_ds_q, entry0_pid_q, entry0_cmpmask_q}; + assign entry1_cam_vec = {entry1_epn_q, entry1_xbit_q, entry1_size_q, entry1_v_q, entry1_thdid_q, entry1_class_q, entry1_extclass_q, entry1_hv_q, entry1_ds_q, entry1_pid_q, entry1_cmpmask_q}; + assign entry2_cam_vec = {entry2_epn_q, entry2_xbit_q, entry2_size_q, entry2_v_q, entry2_thdid_q, entry2_class_q, entry2_extclass_q, entry2_hv_q, entry2_ds_q, entry2_pid_q, entry2_cmpmask_q}; + assign entry3_cam_vec = {entry3_epn_q, entry3_xbit_q, entry3_size_q, entry3_v_q, entry3_thdid_q, entry3_class_q, entry3_extclass_q, entry3_hv_q, entry3_ds_q, entry3_pid_q, entry3_cmpmask_q}; + assign entry4_cam_vec = {entry4_epn_q, entry4_xbit_q, entry4_size_q, entry4_v_q, entry4_thdid_q, entry4_class_q, entry4_extclass_q, entry4_hv_q, entry4_ds_q, entry4_pid_q, entry4_cmpmask_q}; + assign entry5_cam_vec = {entry5_epn_q, entry5_xbit_q, entry5_size_q, entry5_v_q, entry5_thdid_q, entry5_class_q, entry5_extclass_q, entry5_hv_q, entry5_ds_q, entry5_pid_q, entry5_cmpmask_q}; + assign entry6_cam_vec = {entry6_epn_q, entry6_xbit_q, entry6_size_q, entry6_v_q, entry6_thdid_q, entry6_class_q, entry6_extclass_q, entry6_hv_q, entry6_ds_q, entry6_pid_q, entry6_cmpmask_q}; + assign entry7_cam_vec = {entry7_epn_q, entry7_xbit_q, entry7_size_q, entry7_v_q, entry7_thdid_q, entry7_class_q, entry7_extclass_q, entry7_hv_q, entry7_ds_q, entry7_pid_q, entry7_cmpmask_q}; + assign entry8_cam_vec = {entry8_epn_q, entry8_xbit_q, entry8_size_q, entry8_v_q, entry8_thdid_q, entry8_class_q, entry8_extclass_q, entry8_hv_q, entry8_ds_q, entry8_pid_q, entry8_cmpmask_q}; + assign entry9_cam_vec = {entry9_epn_q, entry9_xbit_q, entry9_size_q, entry9_v_q, entry9_thdid_q, entry9_class_q, entry9_extclass_q, entry9_hv_q, entry9_ds_q, entry9_pid_q, entry9_cmpmask_q}; + assign entry10_cam_vec = {entry10_epn_q, entry10_xbit_q, entry10_size_q, entry10_v_q, entry10_thdid_q, entry10_class_q, entry10_extclass_q, entry10_hv_q, entry10_ds_q, entry10_pid_q, entry10_cmpmask_q}; + assign entry11_cam_vec = {entry11_epn_q, entry11_xbit_q, entry11_size_q, entry11_v_q, entry11_thdid_q, entry11_class_q, entry11_extclass_q, entry11_hv_q, entry11_ds_q, entry11_pid_q, entry11_cmpmask_q}; + assign entry12_cam_vec = {entry12_epn_q, entry12_xbit_q, entry12_size_q, entry12_v_q, entry12_thdid_q, entry12_class_q, entry12_extclass_q, entry12_hv_q, entry12_ds_q, entry12_pid_q, entry12_cmpmask_q}; + assign entry13_cam_vec = {entry13_epn_q, entry13_xbit_q, entry13_size_q, entry13_v_q, entry13_thdid_q, entry13_class_q, entry13_extclass_q, entry13_hv_q, entry13_ds_q, entry13_pid_q, entry13_cmpmask_q}; + assign entry14_cam_vec = {entry14_epn_q, entry14_xbit_q, entry14_size_q, entry14_v_q, entry14_thdid_q, entry14_class_q, entry14_extclass_q, entry14_hv_q, entry14_ds_q, entry14_pid_q, entry14_cmpmask_q}; + assign entry15_cam_vec = {entry15_epn_q, entry15_xbit_q, entry15_size_q, entry15_v_q, entry15_thdid_q, entry15_class_q, entry15_extclass_q, entry15_hv_q, entry15_ds_q, entry15_pid_q, entry15_cmpmask_q}; + + + assign cam_cmp_data_muxsel = {(~(comp_request)), cam_hit_entry_d}; + assign cam_cmp_data_d = (cam_cmp_data_muxsel == 5'b00000) ? entry0_cam_vec : + (cam_cmp_data_muxsel == 5'b00001) ? entry1_cam_vec : + (cam_cmp_data_muxsel == 5'b00010) ? entry2_cam_vec : + (cam_cmp_data_muxsel == 5'b00011) ? entry3_cam_vec : + (cam_cmp_data_muxsel == 5'b00100) ? entry4_cam_vec : + (cam_cmp_data_muxsel == 5'b00101) ? entry5_cam_vec : + (cam_cmp_data_muxsel == 5'b00110) ? entry6_cam_vec : + (cam_cmp_data_muxsel == 5'b00111) ? entry7_cam_vec : + (cam_cmp_data_muxsel == 5'b01000) ? entry8_cam_vec : + (cam_cmp_data_muxsel == 5'b01001) ? entry9_cam_vec : + (cam_cmp_data_muxsel == 5'b01010) ? entry10_cam_vec : + (cam_cmp_data_muxsel == 5'b01011) ? entry11_cam_vec : + (cam_cmp_data_muxsel == 5'b01100) ? entry12_cam_vec : + (cam_cmp_data_muxsel == 5'b01101) ? entry13_cam_vec : + (cam_cmp_data_muxsel == 5'b01110) ? entry14_cam_vec : + (cam_cmp_data_muxsel == 5'b01111) ? entry15_cam_vec : + cam_cmp_data_q; + + assign cam_cmp_data_np1 = cam_cmp_data_q; + + // CAM read data out mux + assign rd_cam_data_muxsel = {(~(rd_val)), rw_entry}; + + assign rd_cam_data_d = (rd_cam_data_muxsel == 5'b00000) ? entry0_cam_vec : + (rd_cam_data_muxsel == 5'b00001) ? entry1_cam_vec : + (rd_cam_data_muxsel == 5'b00010) ? entry2_cam_vec : + (rd_cam_data_muxsel == 5'b00011) ? entry3_cam_vec : + (rd_cam_data_muxsel == 5'b00100) ? entry4_cam_vec : + (rd_cam_data_muxsel == 5'b00101) ? entry5_cam_vec : + (rd_cam_data_muxsel == 5'b00110) ? entry6_cam_vec : + (rd_cam_data_muxsel == 5'b00111) ? entry7_cam_vec : + (rd_cam_data_muxsel == 5'b01000) ? entry8_cam_vec : + (rd_cam_data_muxsel == 5'b01001) ? entry9_cam_vec : + (rd_cam_data_muxsel == 5'b01010) ? entry10_cam_vec : + (rd_cam_data_muxsel == 5'b01011) ? entry11_cam_vec : + (rd_cam_data_muxsel == 5'b01100) ? entry12_cam_vec : + (rd_cam_data_muxsel == 5'b01101) ? entry13_cam_vec : + (rd_cam_data_muxsel == 5'b01110) ? entry14_cam_vec : + (rd_cam_data_muxsel == 5'b01111) ? entry15_cam_vec : + rd_cam_data_q; + + // CAM compare parity out mux + assign cam_cmp_parity_d = (cam_cmp_data_muxsel == 5'b00000) ? entry0_parity_q : + (cam_cmp_data_muxsel == 5'b00001) ? entry1_parity_q : + (cam_cmp_data_muxsel == 5'b00010) ? entry2_parity_q : + (cam_cmp_data_muxsel == 5'b00011) ? entry3_parity_q : + (cam_cmp_data_muxsel == 5'b00100) ? entry4_parity_q : + (cam_cmp_data_muxsel == 5'b00101) ? entry5_parity_q : + (cam_cmp_data_muxsel == 5'b00110) ? entry6_parity_q : + (cam_cmp_data_muxsel == 5'b00111) ? entry7_parity_q : + (cam_cmp_data_muxsel == 5'b01000) ? entry8_parity_q : + (cam_cmp_data_muxsel == 5'b01001) ? entry9_parity_q : + (cam_cmp_data_muxsel == 5'b01010) ? entry10_parity_q : + (cam_cmp_data_muxsel == 5'b01011) ? entry11_parity_q : + (cam_cmp_data_muxsel == 5'b01100) ? entry12_parity_q : + (cam_cmp_data_muxsel == 5'b01101) ? entry13_parity_q : + (cam_cmp_data_muxsel == 5'b01110) ? entry14_parity_q : + (cam_cmp_data_muxsel == 5'b01111) ? entry15_parity_q : + cam_cmp_parity_q; + + assign array_cmp_data_np1[0:50] = {array_cmp_data_bram[2:31], array_cmp_data_bram[34:39], array_cmp_data_bram[41:55]}; + assign array_cmp_data_np1[51:60] = cam_cmp_parity_q; + assign array_cmp_data_np1[61:67] = array_cmp_data_bramp[66:72]; + + assign array_cmp_data = array_cmp_data_np1; + + // CAM read parity out mux + assign rd_array_data_d[51:60] = (rd_cam_data_muxsel == 5'b00000) ? entry0_parity_q : + (rd_cam_data_muxsel == 5'b00001) ? entry1_parity_q : + (rd_cam_data_muxsel == 5'b00010) ? entry2_parity_q : + (rd_cam_data_muxsel == 5'b00011) ? entry3_parity_q : + (rd_cam_data_muxsel == 5'b00100) ? entry4_parity_q : + (rd_cam_data_muxsel == 5'b00101) ? entry5_parity_q : + (rd_cam_data_muxsel == 5'b00110) ? entry6_parity_q : + (rd_cam_data_muxsel == 5'b00111) ? entry7_parity_q : + (rd_cam_data_muxsel == 5'b01000) ? entry8_parity_q : + (rd_cam_data_muxsel == 5'b01001) ? entry9_parity_q : + (rd_cam_data_muxsel == 5'b01010) ? entry10_parity_q : + (rd_cam_data_muxsel == 5'b01011) ? entry11_parity_q : + (rd_cam_data_muxsel == 5'b01100) ? entry12_parity_q : + (rd_cam_data_muxsel == 5'b01101) ? entry13_parity_q : + (rd_cam_data_muxsel == 5'b01110) ? entry14_parity_q : + (rd_cam_data_muxsel == 5'b01111) ? entry15_parity_q : + rd_array_data_q[51:60]; + + // internal bypass latch input for rpn + // using cam_cmp_data(75:78) cmpmask bits for mux selects + assign rpn_np2_d[22:33] = (comp_addr_np1_q[22:33] & {12{bypass_mux_enab_np1}}) | + (array_cmp_data_np1[0:11] & {12{~(bypass_mux_enab_np1)}}); // real page from cam-array + + //CAM_PgSize_1GB + assign rpn_np2_d[34:39] = (comp_addr_np1_q[34:39] & {6{(~(cam_cmp_data_np1[75])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[12:17] & {6{cam_cmp_data_np1[75] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_1GB or CAM_PgSize_16MB + assign rpn_np2_d[40:43] = (comp_addr_np1_q[40:43] & {4{(~(cam_cmp_data_np1[76])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[18:21] & {4{cam_cmp_data_np1[76] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_1GB or CAM_PgSize_16MB or CAM_PgSize_1MB + assign rpn_np2_d[44:47] = (comp_addr_np1_q[44:47] & {4{(~(cam_cmp_data_np1[77])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[22:25] & {4{cam_cmp_data_np1[77] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_Larger_than_4K + assign rpn_np2_d[48:51] = (comp_addr_np1_q[48:51] & {4{(~(cam_cmp_data_np1[78])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[26:29] & {4{cam_cmp_data_np1[78] & (~bypass_mux_enab_np1)}}); + + // internal bypass latch input for attributes + assign attr_np2_d[0:20] = (bypass_attr_np1[0:20] & {21{bypass_mux_enab_np1}}) | + (array_cmp_data_np1[30:50] & {21{~bypass_mux_enab_np1}}); + + // new port output assignments + assign rpn_np2[22:51] = rpn_np2_q[22:51]; + assign attr_np2[0:20] = attr_np2_q[0:20]; + + //--------------------------------------------------------------------- + // matchline component instantiations + //--------------------------------------------------------------------- + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb0( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry0_size_q), + .entry_cmpmask(entry0_cmpmask_q[0:3]), + .entry_xbit(entry0_xbit_q), + .entry_xbitmask(entry0_cmpmask_q[4:7]), + .entry_epn(entry0_epn_q), + .comp_class(comp_class), + .entry_class(entry0_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry0_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry0_hv_q), + .entry_ds(entry0_ds_q), + .state_enable(state_enable), + .entry_thdid(entry0_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry0_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry0_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[0]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb1( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry1_size_q), + .entry_cmpmask(entry1_cmpmask_q[0:3]), + .entry_xbit(entry1_xbit_q), + .entry_xbitmask(entry1_cmpmask_q[4:7]), + .entry_epn(entry1_epn_q), + .comp_class(comp_class), + .entry_class(entry1_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry1_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry1_hv_q), + .entry_ds(entry1_ds_q), + .state_enable(state_enable), + .entry_thdid(entry1_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry1_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry1_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[1]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb2( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry2_size_q), + .entry_cmpmask(entry2_cmpmask_q[0:3]), + .entry_xbit(entry2_xbit_q), + .entry_xbitmask(entry2_cmpmask_q[4:7]), + .entry_epn(entry2_epn_q), + .comp_class(comp_class), + .entry_class(entry2_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry2_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry2_hv_q), + .entry_ds(entry2_ds_q), + .state_enable(state_enable), + .entry_thdid(entry2_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry2_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry2_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[2]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb3( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry3_size_q), + .entry_cmpmask(entry3_cmpmask_q[0:3]), + .entry_xbit(entry3_xbit_q), + .entry_xbitmask(entry3_cmpmask_q[4:7]), + .entry_epn(entry3_epn_q), + .comp_class(comp_class), + .entry_class(entry3_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry3_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry3_hv_q), + .entry_ds(entry3_ds_q), + .state_enable(state_enable), + .entry_thdid(entry3_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry3_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry3_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[3]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb4( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry4_size_q), + .entry_cmpmask(entry4_cmpmask_q[0:3]), + .entry_xbit(entry4_xbit_q), + .entry_xbitmask(entry4_cmpmask_q[4:7]), + .entry_epn(entry4_epn_q), + .comp_class(comp_class), + .entry_class(entry4_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry4_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry4_hv_q), + .entry_ds(entry4_ds_q), + .state_enable(state_enable), + .entry_thdid(entry4_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry4_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry4_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[4]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb5( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry5_size_q), + .entry_cmpmask(entry5_cmpmask_q[0:3]), + .entry_xbit(entry5_xbit_q), + .entry_xbitmask(entry5_cmpmask_q[4:7]), + .entry_epn(entry5_epn_q), + .comp_class(comp_class), + .entry_class(entry5_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry5_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry5_hv_q), + .entry_ds(entry5_ds_q), + .state_enable(state_enable), + .entry_thdid(entry5_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry5_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry5_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[5]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb6( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry6_size_q), + .entry_cmpmask(entry6_cmpmask_q[0:3]), + .entry_xbit(entry6_xbit_q), + .entry_xbitmask(entry6_cmpmask_q[4:7]), + .entry_epn(entry6_epn_q), + .comp_class(comp_class), + .entry_class(entry6_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry6_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry6_hv_q), + .entry_ds(entry6_ds_q), + .state_enable(state_enable), + .entry_thdid(entry6_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry6_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry6_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[6]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb7( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry7_size_q), + .entry_cmpmask(entry7_cmpmask_q[0:3]), + .entry_xbit(entry7_xbit_q), + .entry_xbitmask(entry7_cmpmask_q[4:7]), + .entry_epn(entry7_epn_q), + .comp_class(comp_class), + .entry_class(entry7_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry7_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry7_hv_q), + .entry_ds(entry7_ds_q), + .state_enable(state_enable), + .entry_thdid(entry7_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry7_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry7_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[7]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb8( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry8_size_q), + .entry_cmpmask(entry8_cmpmask_q[0:3]), + .entry_xbit(entry8_xbit_q), + .entry_xbitmask(entry8_cmpmask_q[4:7]), + .entry_epn(entry8_epn_q), + .comp_class(comp_class), + .entry_class(entry8_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry8_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry8_hv_q), + .entry_ds(entry8_ds_q), + .state_enable(state_enable), + .entry_thdid(entry8_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry8_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry8_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[8]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb9( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry9_size_q), + .entry_cmpmask(entry9_cmpmask_q[0:3]), + .entry_xbit(entry9_xbit_q), + .entry_xbitmask(entry9_cmpmask_q[4:7]), + .entry_epn(entry9_epn_q), + .comp_class(comp_class), + .entry_class(entry9_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry9_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry9_hv_q), + .entry_ds(entry9_ds_q), + .state_enable(state_enable), + .entry_thdid(entry9_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry9_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry9_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[9]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb10( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry10_size_q), + .entry_cmpmask(entry10_cmpmask_q[0:3]), + .entry_xbit(entry10_xbit_q), + .entry_xbitmask(entry10_cmpmask_q[4:7]), + .entry_epn(entry10_epn_q), + .comp_class(comp_class), + .entry_class(entry10_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry10_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry10_hv_q), + .entry_ds(entry10_ds_q), + .state_enable(state_enable), + .entry_thdid(entry10_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry10_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry10_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[10]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb11( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry11_size_q), + .entry_cmpmask(entry11_cmpmask_q[0:3]), + .entry_xbit(entry11_xbit_q), + .entry_xbitmask(entry11_cmpmask_q[4:7]), + .entry_epn(entry11_epn_q), + .comp_class(comp_class), + .entry_class(entry11_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry11_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry11_hv_q), + .entry_ds(entry11_ds_q), + .state_enable(state_enable), + .entry_thdid(entry11_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry11_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry11_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[11]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb12( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry12_size_q), + .entry_cmpmask(entry12_cmpmask_q[0:3]), + .entry_xbit(entry12_xbit_q), + .entry_xbitmask(entry12_cmpmask_q[4:7]), + .entry_epn(entry12_epn_q), + .comp_class(comp_class), + .entry_class(entry12_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry12_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry12_hv_q), + .entry_ds(entry12_ds_q), + .state_enable(state_enable), + .entry_thdid(entry12_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry12_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry12_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[12]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb13( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry13_size_q), + .entry_cmpmask(entry13_cmpmask_q[0:3]), + .entry_xbit(entry13_xbit_q), + .entry_xbitmask(entry13_cmpmask_q[4:7]), + .entry_epn(entry13_epn_q), + .comp_class(comp_class), + .entry_class(entry13_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry13_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry13_hv_q), + .entry_ds(entry13_ds_q), + .state_enable(state_enable), + .entry_thdid(entry13_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry13_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry13_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[13]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb14( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry14_size_q), + .entry_cmpmask(entry14_cmpmask_q[0:3]), + .entry_xbit(entry14_xbit_q), + .entry_xbitmask(entry14_cmpmask_q[4:7]), + .entry_epn(entry14_epn_q), + .comp_class(comp_class), + .entry_class(entry14_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry14_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry14_hv_q), + .entry_ds(entry14_ds_q), + .state_enable(state_enable), + .entry_thdid(entry14_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry14_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry14_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[14]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb15( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry15_size_q), + .entry_cmpmask(entry15_cmpmask_q[0:3]), + .entry_xbit(entry15_xbit_q), + .entry_xbitmask(entry15_cmpmask_q[4:7]), + .entry_epn(entry15_epn_q), + .comp_class(comp_class), + .entry_class(entry15_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry15_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry15_hv_q), + .entry_ds(entry15_ds_q), + .state_enable(state_enable), + .entry_thdid(entry15_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry15_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry15_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[15]) + ); + + + //--------------------------------------------------------------------- + // BRAM signal assignments + //--------------------------------------------------------------------- + assign bram0_wea = wr_array_val[0] & gate_fq; + assign bram1_wea = wr_array_val[1] & gate_fq; + assign bram2_wea = wr_array_val[1] & gate_fq; + + assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + assign bram2_addra[10 - NUM_ENTRY_LOG2:9] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + + assign bram0_addrb[9 - NUM_ENTRY_LOG2:8] = cam_hit_entry_q; + assign bram1_addrb[11 - NUM_ENTRY_LOG2:10] = cam_hit_entry_q; + assign bram2_addrb[10 - NUM_ENTRY_LOG2:9] = cam_hit_entry_q; + + // Unused Address Bits + assign bram0_addra[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; + assign bram0_addrb[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; + assign bram1_addra[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; + assign bram1_addrb[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; + assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; + assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; + + // This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) + // uses wr_array_val(0), parity is wr_array_data_bram(66:69) + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram0( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram0_addra), + .ADDRB(bram0_addrb), + .DIA(wr_array_data_bram[0:31]), + .DIB(32'b0), + .DOA(rd_array_data_d_std[0:31]), + .DOB(array_cmp_data_bram_std[0:31]), + .DOPA(rd_array_data_d_std[66:69]), + .DOPB(array_cmp_data_bramp_std[66:69]), + .DIPA(wr_array_data_bram[66:69]), + .DIPB(4'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram0_wea), + .WEB(1'b0) + ); + + // This ram houses the RPN(18:19),R,C,4xResv bits, wr_array_data_bram(32:39) + // uses wr_array_val(1), parity is wr_array_data_bram(70) + RAMB16_S9_S9 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram1( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram1_addra), + .ADDRB(bram1_addrb), + .DIA(wr_array_data_bram[32:39]), + .DIB(8'b0), + .DOA(rd_array_data_d_std[32:39]), + .DOB(array_cmp_data_bram_std[32:39]), + .DOPA(rd_array_data_d_std[70:70]), + .DOPB(array_cmp_data_bramp_std[70:70]), + .DIPA(wr_array_data_bram[70:70]), + .DIPB(1'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram1_wea), + .WEB(1'b0) + ); + + // This ram houses the 1xResv,U0-U3,WIMGE,UX,UW,UR,SX,SW,SR bits, wr_array_data_bram(40:55) + // uses wr_array_val(1), parity is wr_array_data_bram(71:72) + RAMB16_S18_S18 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram2( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram2_addra), + .ADDRB(bram2_addrb), + .DIA(wr_array_data_bram[40:55]), + .DIB(16'b0), + .DOA(rd_array_data_d_std[40:55]), + .DOB(array_cmp_data_bram_std[40:55]), + .DOPA(rd_array_data_d_std[71:72]), + .DOPB(array_cmp_data_bramp_std[71:72]), + .DIPA(wr_array_data_bram[71:72]), + .DIPB(2'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram2_wea), + .WEB(1'b0) + ); + + // array write data swizzle -> convert 68-bit data to 73-bit bram data + // 32x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:47 - UX,UW,UR + // 48:50 - SX,SW,SR + // 51:60 - CAM parity + // 61:67 - Array parity + // + // RTX layout in A2_AvpEratHelper.C + // ram0(0:31): 00 & RPN(0:29) + // ram1(0:7) : 00 & R,C,ResvAttr(0:3) + // ram2(0:15): '0' & U(0:3),WIMGE,UX,UW,UR,SX,SW,SR + assign wr_array_data_bram[0:72] = {2'b00, wr_array_data[0:29], 2'b00, wr_array_data[30:35], 1'b0, wr_array_data[36:50], wr_array_data[51:60], wr_array_data[61:67]}; + + assign rd_array_data_d_std[56:65] = 10'b0; // tie off unused bits + + assign rd_array_data_d[0:29] = rd_array_data_d_std[2:31]; + assign rd_array_data_d[30:35] = rd_array_data_d_std[34:39]; + assign rd_array_data_d[36:50] = rd_array_data_d_std[41:55]; + assign rd_array_data_d[61:67] = rd_array_data_d_std[66:72]; + assign array_cmp_data_bram = array_cmp_data_bram_std; + assign array_cmp_data_bramp = array_cmp_data_bramp_std; + + //--------------------------------------------------------------------- + // entity output assignments + //--------------------------------------------------------------------- + assign rd_array_data = rd_array_data_q; + assign cam_cmp_data = cam_cmp_data_q; + assign rd_cam_data = rd_cam_data_q; + + assign entry_valid[0] = entry0_v_q; + assign entry_valid[1] = entry1_v_q; + assign entry_valid[2] = entry2_v_q; + assign entry_valid[3] = entry3_v_q; + assign entry_valid[4] = entry4_v_q; + assign entry_valid[5] = entry5_v_q; + assign entry_valid[6] = entry6_v_q; + assign entry_valid[7] = entry7_v_q; + assign entry_valid[8] = entry8_v_q; + assign entry_valid[9] = entry9_v_q; + assign entry_valid[10] = entry10_v_q; + assign entry_valid[11] = entry11_v_q; + assign entry_valid[12] = entry12_v_q; + assign entry_valid[13] = entry13_v_q; + assign entry_valid[14] = entry14_v_q; + assign entry_valid[15] = entry15_v_q; + + assign entry_match = entry_match_q; + + assign cam_hit_entry = cam_hit_entry_q; + assign cam_hit = cam_hit_q; + + assign func_scan_out = func_scan_in; + assign regfile_scan_out = regfile_scan_in; + assign time_scan_out = time_scan_in; + + assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, + tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, + lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, + pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, pc_fce_2, array_cmp_data_bram[0:1], array_cmp_data_bram[32:33], + array_cmp_data_bram[40], wr_array_data_bram[56:65], + cam_cmp_data_np1[0:74], cam_cmp_data_np1[79:CAM_DATA_WIDTH-1], + rd_array_data_d_std[0:1], rd_array_data_d_std[32:33], + rd_array_data_d_std[40], rd_array_data_d_std[56:65], rd_val_late, wr_val_early}; +endmodule diff --git a/rel/src/verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v b/rel/src/verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v new file mode 100644 index 0000000..f2a7fe6 --- /dev/null +++ b/rel/src/verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v @@ -0,0 +1,471 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: I-ERAT CAM Match Line Logic for Functional Model +//* +//* NAME: tri_cam_16x143_1r1w1c_matchline +//* +//********************************************************************* + +module tri_cam_16x143_1r1w1c_matchline( + addr_in, + addr_enable, + comp_pgsize, + pgsize_enable, + entry_size, + entry_cmpmask, + entry_xbit, + entry_xbitmask, + entry_epn, + comp_class, + entry_class, + class_enable, + comp_extclass, + entry_extclass, + extclass_enable, + comp_state, + entry_hv, + entry_ds, + state_enable, + entry_thdid, + comp_thdid, + thdid_enable, + entry_pid, + comp_pid, + pid_enable, + entry_v, + comp_invalidate, + match +); + parameter HAVE_XBIT = 1; + parameter NUM_PGSIZES = 5; + parameter HAVE_CMPMASK = 1; + parameter CMPMASK_WIDTH = 4; + + // @{default:nclk}@ + input [0:51] addr_in; + input [0:1] addr_enable; + input [0:2] comp_pgsize; + input pgsize_enable; + input [0:2] entry_size; + input [0:CMPMASK_WIDTH-1] entry_cmpmask; + input entry_xbit; + input [0:CMPMASK_WIDTH-1] entry_xbitmask; + input [0:51] entry_epn; + input [0:1] comp_class; + input [0:1] entry_class; + input [0:2] class_enable; + input [0:1] comp_extclass; + input [0:1] entry_extclass; + input [0:1] extclass_enable; + input [0:1] comp_state; + input entry_hv; + input entry_ds; + input [0:1] state_enable; + input [0:3] entry_thdid; + input [0:3] comp_thdid; + input [0:1] thdid_enable; + input [0:7] entry_pid; + input [0:7] comp_pid; + input pid_enable; + input entry_v; + input comp_invalidate; + + output match; + + // tri_cam_16x143_1r1w1c_matchline + + //---------------------------------------------------------------------- + // Signals + //---------------------------------------------------------------------- + + wire [34:51] entry_epn_b; + wire function_50_51; + wire function_48_51; + wire function_46_51; + wire function_44_51; + wire function_40_51; + wire function_36_51; + wire function_34_51; + wire pgsize_eq_16K; + wire pgsize_eq_64K; + wire pgsize_eq_256K; + wire pgsize_eq_1M; + wire pgsize_eq_16M; + wire pgsize_eq_256M; + wire pgsize_eq_1G; + wire pgsize_gte_16K; + wire pgsize_gte_64K; + wire pgsize_gte_256K; + wire pgsize_gte_1M; + wire pgsize_gte_16M; + wire pgsize_gte_256M; + wire pgsize_gte_1G; + wire comp_or_34_35; + wire comp_or_34_39; + wire comp_or_36_39; + wire comp_or_40_43; + wire comp_or_44_45; + wire comp_or_44_47; + wire comp_or_46_47; + wire comp_or_48_49; + wire comp_or_48_51; + wire comp_or_50_51; + wire [0:72] match_line; + wire pgsize_match; + wire addr_match; + wire class_match; + wire extclass_match; + wire state_match; + wire thdid_match; + wire pid_match; + (* analysis_not_referenced="true" *) + wire [0:2] unused; + + assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^ + {addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]})); + + generate + begin + if (NUM_PGSIZES == 8) + begin : numpgsz8 + // tie off unused signals + assign comp_or_34_39 = 1'b0; + assign comp_or_44_47 = 1'b0; + assign comp_or_48_51 = 1'b0; + assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51}; + + assign entry_epn_b[34:51] = (~(entry_epn[34:51])); + + if (HAVE_CMPMASK == 0) + begin + assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & entry_size[2]); + assign pgsize_eq_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + assign pgsize_eq_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]); + assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))); + assign pgsize_eq_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]); + assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))); + assign pgsize_eq_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]); + + assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & entry_size[2]); + assign pgsize_gte_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_1G; + assign pgsize_gte_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_256M; + assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M; + assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M; + assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_256K; + assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_64K; + + assign unused[1] = |{entry_cmpmask, entry_xbitmask}; + end + + if (HAVE_CMPMASK == 1) + begin + // size entry_cmpmask: 0123456 + // 1GB 0000000 + // 256MB 1000000 + // 16MB 1100000 + // 1MB 1110000 + // 256KB 1111000 + // 64KB 1111100 + // 16KB 1111110 + // 4KB 1111111 + assign pgsize_gte_1G = (~entry_cmpmask[0]); + assign pgsize_gte_256M = (~entry_cmpmask[1]); + assign pgsize_gte_16M = (~entry_cmpmask[2]); + assign pgsize_gte_1M = (~entry_cmpmask[3]); + assign pgsize_gte_256K = (~entry_cmpmask[4]); + assign pgsize_gte_64K = (~entry_cmpmask[5]); + assign pgsize_gte_16K = (~entry_cmpmask[6]); + + // size entry_xbitmask: 0123456 + // 1GB 1000000 + // 256MB 0100000 + // 16MB 0010000 + // 1MB 0001000 + // 256KB 0000100 + // 64KB 0000010 + // 16KB 0000001 + // 4KB 0000000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_256M = entry_xbitmask[1]; + assign pgsize_eq_16M = entry_xbitmask[2]; + assign pgsize_eq_1M = entry_xbitmask[3]; + assign pgsize_eq_256K = entry_xbitmask[4]; + assign pgsize_eq_64K = entry_xbitmask[5]; + assign pgsize_eq_16K = entry_xbitmask[6]; + + assign unused[1] = 1'b0; + end + + if (HAVE_XBIT == 0) + begin + assign function_34_51 = 1'b0; + assign function_36_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_48_51 = 1'b0; + assign function_50_51 = 1'b0; + assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51, + function_46_51, function_48_51, function_50_51, entry_xbit, + entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M, + pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K}; + end + + if (HAVE_XBIT != 0) + begin + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51])); + assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51])); + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51])); + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51])); + assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51])); + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51])); + assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | (|(entry_epn_b[50:51] & addr_in[50:51])); + assign unused[2] = 1'b0; + end + + assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K; + assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K; + assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K; + assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M; + assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M; + assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M; + assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G; + + if (HAVE_XBIT == 0) + begin + assign addr_match = (comp_or_34_35 & // Ignore functions based on page size + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + + if (HAVE_XBIT != 0) + begin + assign addr_match = (function_50_51 & // Exclusion functions + function_48_51 & + function_46_51 & + function_44_51 & + function_40_51 & + function_36_51 & + function_34_51 & + comp_or_34_35 & // Ignore functions based on page size + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[31:33])) & // Regular compare largest page size + (&(match_line[0:30]) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + end // numpgsz8: NUM_PGSIZES = 8 + + + if (NUM_PGSIZES == 5) + begin : numpgsz5 + // tie off unused signals + assign function_50_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_36_51 = 1'b0; + assign pgsize_eq_16K = 1'b0; + assign pgsize_eq_256K = 1'b0; + assign pgsize_eq_256M = 1'b0; + assign pgsize_gte_16K = 1'b0; + assign pgsize_gte_256K = 1'b0; + assign pgsize_gte_256M = 1'b0; + assign comp_or_34_35 = 1'b0; + assign comp_or_36_39 = 1'b0; + assign comp_or_44_45 = 1'b0; + assign comp_or_46_47 = 1'b0; + assign comp_or_48_49 = 1'b0; + assign comp_or_50_51 = 1'b0; + assign unused[0] = |{function_50_51, function_46_51, function_36_51, + pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M, + pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M, + comp_or_34_35, comp_or_36_39, comp_or_44_45, + comp_or_46_47, comp_or_48_49, comp_or_50_51}; + + assign entry_epn_b[34:51] = (~(entry_epn[34:51])); + + if (HAVE_CMPMASK == 0) + begin + // 110 + assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + // 111 + assign pgsize_eq_16M = ( entry_size[0] & entry_size[1] & entry_size[2]); + // 101 + assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]); + // 011 + assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]); + + assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + assign pgsize_gte_16M = ( entry_size[0] & entry_size[1] & entry_size[2]) | pgsize_gte_1G; + assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M; + assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M; + + assign unused[1] = |{entry_cmpmask, entry_xbitmask}; + end + + if (HAVE_CMPMASK == 1) + begin + // size entry_cmpmask: 0123 + // 1GB 0000 + // 16MB 1000 + // 1MB 1100 + // 64KB 1110 + // 4KB 1111 + assign pgsize_gte_1G = (~entry_cmpmask[0]); + assign pgsize_gte_16M = (~entry_cmpmask[1]); + assign pgsize_gte_1M = (~entry_cmpmask[2]); + assign pgsize_gte_64K = (~entry_cmpmask[3]); + + // size entry_xbitmask: 0123 + // 1GB 1000 + // 16MB 0100 + // 1MB 0010 + // 64KB 0001 + // 4KB 0000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_16M = entry_xbitmask[1]; + assign pgsize_eq_1M = entry_xbitmask[2]; + assign pgsize_eq_64K = entry_xbitmask[3]; + + assign unused[1] = 1'b0; + end + + if (HAVE_XBIT == 0) + begin + assign function_34_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_48_51 = 1'b0; + assign unused[2] = |{function_34_51, function_40_51, function_44_51, + function_48_51, entry_xbit, entry_epn_b, + pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K}; + end + + if (HAVE_XBIT != 0) + begin + // 1G + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51])); + // 16M + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51])); + // 1M + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51])); + // 64K + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51])); + assign unused[2] = 1'b0; + end + + assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K; + assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M; + assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M; + assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G; + + if (HAVE_XBIT == 0) + begin + assign addr_match = (comp_or_34_39 & // Ignore functions based on page size + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + + if (HAVE_XBIT != 0) + begin + assign addr_match = (function_48_51 & + function_44_51 & + function_40_51 & + function_34_51 & + comp_or_34_39 & // Ignore functions based on page size + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + end // numpgsz5: NUM_PGSIZES = 5 + + + assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable)); + + assign class_match = (match_line[55] | (~(class_enable[0]))) & + (match_line[56] | (~(class_enable[1]))) & + ((&(match_line[55:56])) | (~(class_enable[2])) | + ((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit + + assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) & // iprot bit + (match_line[58] | (~(extclass_enable[1]))); // pid_nz bit + + assign state_match = (match_line[59] | (~(state_enable[0]))) & + (match_line[60] | (~(state_enable[1]))); + + assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) & + (&(match_line[69:72]) | (~(thdid_enable[1])) | + ((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit + + assign pid_match = (&(match_line[61:68])) | + // entry_pid=0 ignores pid match for compares, + // but not for invalidates. + ((~(entry_extclass[1])) & (~comp_invalidate)) | // pid_nz bit + (~(pid_enable)); + + assign match = addr_match & // Address compare + pgsize_match & // Size compare + class_match & // Class compare + extclass_match & // ExtClass compare + state_match & // State compare + thdid_match & // ThdID compare + pid_match & // PID compare + entry_v; // Valid + end + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_cam_32x143_1r1w1c.v b/rel/src/verilog/trilib/tri_cam_32x143_1r1w1c.v new file mode 100644 index 0000000..2046087 --- /dev/null +++ b/rel/src/verilog/trilib/tri_cam_32x143_1r1w1c.v @@ -0,0 +1,4851 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Mon Nov 8 10:36:46 2010 + +//******************************************************************** +//* TITLE: I-ERAT CAM Tri-Library Model +//* NAME: tri_cam_32x143_1r1w1c +//******************************************************************** + +`include "tri_a2o.vh" + +module tri_cam_32x143_1r1w1c( + gnd, + vdd, + vcs, + nclk, + tc_ccflush_dc, + tc_scan_dis_dc_b, + tc_scan_diag_dc, + tc_lbist_en_dc, + an_ac_atpg_en_dc, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_act_dis_dc, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + pc_sg_2, + pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2, + pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, + pc_fce_2, + func_scan_in, + func_scan_out, + regfile_scan_in, + regfile_scan_out, + time_scan_in, + time_scan_out, + rd_val, + rd_val_late, + rw_entry, + wr_array_data, + wr_cam_data, + wr_array_val, + wr_cam_val, + wr_val_early, + comp_request, + comp_addr, + addr_enable, + comp_pgsize, + pgsize_enable, + comp_class, + class_enable, + comp_extclass, + extclass_enable, + comp_state, + state_enable, + comp_thdid, + thdid_enable, + comp_pid, + pid_enable, + comp_invalidate, + flash_invalidate, + array_cmp_data, + rd_array_data, + cam_cmp_data, + cam_hit, + cam_hit_entry, + entry_match, + entry_valid, + rd_cam_data, + bypass_mux_enab_np1, + bypass_attr_np1, + attr_np2, + rpn_np2 +); + parameter CAM_DATA_WIDTH = 84; + parameter ARRAY_DATA_WIDTH = 68; + parameter RPN_WIDTH = 30; + parameter NUM_ENTRY = 32; + parameter NUM_ENTRY_LOG2 = 5; + + // Power Pins + inout gnd; + inout vdd; + inout vcs; + + // Clocks and Scan Cntls + input [0:`NCLK_WIDTH-1] nclk; + input tc_ccflush_dc; + input tc_scan_dis_dc_b; + input tc_scan_diag_dc; + input tc_lbist_en_dc; + input an_ac_atpg_en_dc; + + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input lcb_act_dis_dc; + input [0:3] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:3] lcb_delay_lclkr_dc; + + input pc_sg_2; + input pc_func_slp_sl_thold_2; + input pc_func_slp_nsl_thold_2; + input pc_regf_slp_sl_thold_2; + input pc_time_sl_thold_2; + input pc_fce_2; + + input func_scan_in; + output func_scan_out; + input [0:6] regfile_scan_in; // 0:2 -> CAM, 3:6 -> RAM + output [0:6] regfile_scan_out; + input time_scan_in; + output time_scan_out; + + // Read Port + input rd_val; + input rd_val_late; + input [0:NUM_ENTRY_LOG2-1] rw_entry; + + // Write Port + input [0:ARRAY_DATA_WIDTH-1] wr_array_data; + input [0:CAM_DATA_WIDTH-1] wr_cam_data; + input [0:1] wr_array_val; + input [0:1] wr_cam_val; + input wr_val_early; + + // CAM Port + input comp_request; + input [0:51] comp_addr; + input [0:1] addr_enable; + input [0:2] comp_pgsize; + input pgsize_enable; + input [0:1] comp_class; + input [0:2] class_enable; + input [0:1] comp_extclass; + input [0:1] extclass_enable; + input [0:1] comp_state; + input [0:1] state_enable; + input [0:3] comp_thdid; + input [0:1] thdid_enable; + input [0:7] comp_pid; + input pid_enable; + input comp_invalidate; + input flash_invalidate; + + // Outputs + // Data Out + output [0:ARRAY_DATA_WIDTH-1] array_cmp_data; + output [0:ARRAY_DATA_WIDTH-1] rd_array_data; + + // CAM Output + output [0:CAM_DATA_WIDTH-1] cam_cmp_data; + output cam_hit; + output [0:NUM_ENTRY_LOG2-1] cam_hit_entry; + output [0:NUM_ENTRY-1] entry_match; + output [0:NUM_ENTRY-1] entry_valid; + output [0:CAM_DATA_WIDTH-1] rd_cam_data; + + //--- new ports for IO plus ----------------------- + input bypass_mux_enab_np1; + input [0:20] bypass_attr_np1; + output [0:20] attr_np2; + + output [22:51] rpn_np2; + + // tri_cam_32x143_1r1w1c + + // Configuration Statement for NCsim + //for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9; + //for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18; + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire clk; + wire clk2x; + wire [0:8] bram0_addra; + wire [0:8] bram0_addrb; + wire [0:10] bram1_addra; + wire [0:10] bram1_addrb; + wire [0:9] bram2_addra; + wire [0:9] bram2_addrb; + wire bram0_wea; + wire bram1_wea; + wire bram2_wea; + wire [0:55] array_cmp_data_bram; + wire [66:72] array_cmp_data_bramp; + + // Latches + reg sreset_q; + reg gate_fq; + wire gate_d; + wire [52-RPN_WIDTH:51] comp_addr_np1_d; + reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input + wire [52-RPN_WIDTH:51] rpn_np2_d; + reg [52-RPN_WIDTH:51] rpn_np2_q; + wire [0:20] attr_np2_d; + reg [0:20] attr_np2_q; + + // CAM entry signals + wire [0:51] entry0_epn_d; + reg [0:51] entry0_epn_q; + wire entry0_xbit_d; + reg entry0_xbit_q; + wire [0:2] entry0_size_d; + reg [0:2] entry0_size_q; + wire entry0_v_d; + reg entry0_v_q; + wire [0:3] entry0_thdid_d; + reg [0:3] entry0_thdid_q; + wire [0:1] entry0_class_d; + reg [0:1] entry0_class_q; + wire [0:1] entry0_extclass_d; + reg [0:1] entry0_extclass_q; + wire entry0_hv_d; + reg entry0_hv_q; + wire entry0_ds_d; + reg entry0_ds_q; + wire [0:7] entry0_pid_d; + reg [0:7] entry0_pid_q; + wire [0:8] entry0_cmpmask_d; + reg [0:8] entry0_cmpmask_q; + wire [0:9] entry0_parity_d; + reg [0:9] entry0_parity_q; + wire [0:1] wr_entry0_sel; + wire entry0_inval; + wire [0:1] entry0_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry0_cam_vec; + wire [0:51] entry1_epn_d; + reg [0:51] entry1_epn_q; + wire entry1_xbit_d; + reg entry1_xbit_q; + wire [0:2] entry1_size_d; + reg [0:2] entry1_size_q; + wire entry1_v_d; + reg entry1_v_q; + wire [0:3] entry1_thdid_d; + reg [0:3] entry1_thdid_q; + wire [0:1] entry1_class_d; + reg [0:1] entry1_class_q; + wire [0:1] entry1_extclass_d; + reg [0:1] entry1_extclass_q; + wire entry1_hv_d; + reg entry1_hv_q; + wire entry1_ds_d; + reg entry1_ds_q; + wire [0:7] entry1_pid_d; + reg [0:7] entry1_pid_q; + wire [0:8] entry1_cmpmask_d; + reg [0:8] entry1_cmpmask_q; + wire [0:9] entry1_parity_d; + reg [0:9] entry1_parity_q; + wire [0:1] wr_entry1_sel; + wire entry1_inval; + wire [0:1] entry1_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry1_cam_vec; + wire [0:51] entry2_epn_d; + reg [0:51] entry2_epn_q; + wire entry2_xbit_d; + reg entry2_xbit_q; + wire [0:2] entry2_size_d; + reg [0:2] entry2_size_q; + wire entry2_v_d; + reg entry2_v_q; + wire [0:3] entry2_thdid_d; + reg [0:3] entry2_thdid_q; + wire [0:1] entry2_class_d; + reg [0:1] entry2_class_q; + wire [0:1] entry2_extclass_d; + reg [0:1] entry2_extclass_q; + wire entry2_hv_d; + reg entry2_hv_q; + wire entry2_ds_d; + reg entry2_ds_q; + wire [0:7] entry2_pid_d; + reg [0:7] entry2_pid_q; + wire [0:8] entry2_cmpmask_d; + reg [0:8] entry2_cmpmask_q; + wire [0:9] entry2_parity_d; + reg [0:9] entry2_parity_q; + wire [0:1] wr_entry2_sel; + wire entry2_inval; + wire [0:1] entry2_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry2_cam_vec; + wire [0:51] entry3_epn_d; + reg [0:51] entry3_epn_q; + wire entry3_xbit_d; + reg entry3_xbit_q; + wire [0:2] entry3_size_d; + reg [0:2] entry3_size_q; + wire entry3_v_d; + reg entry3_v_q; + wire [0:3] entry3_thdid_d; + reg [0:3] entry3_thdid_q; + wire [0:1] entry3_class_d; + reg [0:1] entry3_class_q; + wire [0:1] entry3_extclass_d; + reg [0:1] entry3_extclass_q; + wire entry3_hv_d; + reg entry3_hv_q; + wire entry3_ds_d; + reg entry3_ds_q; + wire [0:7] entry3_pid_d; + reg [0:7] entry3_pid_q; + wire [0:8] entry3_cmpmask_d; + reg [0:8] entry3_cmpmask_q; + wire [0:9] entry3_parity_d; + reg [0:9] entry3_parity_q; + wire [0:1] wr_entry3_sel; + wire entry3_inval; + wire [0:1] entry3_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry3_cam_vec; + wire [0:51] entry4_epn_d; + reg [0:51] entry4_epn_q; + wire entry4_xbit_d; + reg entry4_xbit_q; + wire [0:2] entry4_size_d; + reg [0:2] entry4_size_q; + wire entry4_v_d; + reg entry4_v_q; + wire [0:3] entry4_thdid_d; + reg [0:3] entry4_thdid_q; + wire [0:1] entry4_class_d; + reg [0:1] entry4_class_q; + wire [0:1] entry4_extclass_d; + reg [0:1] entry4_extclass_q; + wire entry4_hv_d; + reg entry4_hv_q; + wire entry4_ds_d; + reg entry4_ds_q; + wire [0:7] entry4_pid_d; + reg [0:7] entry4_pid_q; + wire [0:8] entry4_cmpmask_d; + reg [0:8] entry4_cmpmask_q; + wire [0:9] entry4_parity_d; + reg [0:9] entry4_parity_q; + wire [0:1] wr_entry4_sel; + wire entry4_inval; + wire [0:1] entry4_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry4_cam_vec; + wire [0:51] entry5_epn_d; + reg [0:51] entry5_epn_q; + wire entry5_xbit_d; + reg entry5_xbit_q; + wire [0:2] entry5_size_d; + reg [0:2] entry5_size_q; + wire entry5_v_d; + reg entry5_v_q; + wire [0:3] entry5_thdid_d; + reg [0:3] entry5_thdid_q; + wire [0:1] entry5_class_d; + reg [0:1] entry5_class_q; + wire [0:1] entry5_extclass_d; + reg [0:1] entry5_extclass_q; + wire entry5_hv_d; + reg entry5_hv_q; + wire entry5_ds_d; + reg entry5_ds_q; + wire [0:7] entry5_pid_d; + reg [0:7] entry5_pid_q; + wire [0:8] entry5_cmpmask_d; + reg [0:8] entry5_cmpmask_q; + wire [0:9] entry5_parity_d; + reg [0:9] entry5_parity_q; + wire [0:1] wr_entry5_sel; + wire entry5_inval; + wire [0:1] entry5_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry5_cam_vec; + wire [0:51] entry6_epn_d; + reg [0:51] entry6_epn_q; + wire entry6_xbit_d; + reg entry6_xbit_q; + wire [0:2] entry6_size_d; + reg [0:2] entry6_size_q; + wire entry6_v_d; + reg entry6_v_q; + wire [0:3] entry6_thdid_d; + reg [0:3] entry6_thdid_q; + wire [0:1] entry6_class_d; + reg [0:1] entry6_class_q; + wire [0:1] entry6_extclass_d; + reg [0:1] entry6_extclass_q; + wire entry6_hv_d; + reg entry6_hv_q; + wire entry6_ds_d; + reg entry6_ds_q; + wire [0:7] entry6_pid_d; + reg [0:7] entry6_pid_q; + wire [0:8] entry6_cmpmask_d; + reg [0:8] entry6_cmpmask_q; + wire [0:9] entry6_parity_d; + reg [0:9] entry6_parity_q; + wire [0:1] wr_entry6_sel; + wire entry6_inval; + wire [0:1] entry6_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry6_cam_vec; + wire [0:51] entry7_epn_d; + reg [0:51] entry7_epn_q; + wire entry7_xbit_d; + reg entry7_xbit_q; + wire [0:2] entry7_size_d; + reg [0:2] entry7_size_q; + wire entry7_v_d; + reg entry7_v_q; + wire [0:3] entry7_thdid_d; + reg [0:3] entry7_thdid_q; + wire [0:1] entry7_class_d; + reg [0:1] entry7_class_q; + wire [0:1] entry7_extclass_d; + reg [0:1] entry7_extclass_q; + wire entry7_hv_d; + reg entry7_hv_q; + wire entry7_ds_d; + reg entry7_ds_q; + wire [0:7] entry7_pid_d; + reg [0:7] entry7_pid_q; + wire [0:8] entry7_cmpmask_d; + reg [0:8] entry7_cmpmask_q; + wire [0:9] entry7_parity_d; + reg [0:9] entry7_parity_q; + wire [0:1] wr_entry7_sel; + wire entry7_inval; + wire [0:1] entry7_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry7_cam_vec; + wire [0:51] entry8_epn_d; + reg [0:51] entry8_epn_q; + wire entry8_xbit_d; + reg entry8_xbit_q; + wire [0:2] entry8_size_d; + reg [0:2] entry8_size_q; + wire entry8_v_d; + reg entry8_v_q; + wire [0:3] entry8_thdid_d; + reg [0:3] entry8_thdid_q; + wire [0:1] entry8_class_d; + reg [0:1] entry8_class_q; + wire [0:1] entry8_extclass_d; + reg [0:1] entry8_extclass_q; + wire entry8_hv_d; + reg entry8_hv_q; + wire entry8_ds_d; + reg entry8_ds_q; + wire [0:7] entry8_pid_d; + reg [0:7] entry8_pid_q; + wire [0:8] entry8_cmpmask_d; + reg [0:8] entry8_cmpmask_q; + wire [0:9] entry8_parity_d; + reg [0:9] entry8_parity_q; + wire [0:1] wr_entry8_sel; + wire entry8_inval; + wire [0:1] entry8_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry8_cam_vec; + wire [0:51] entry9_epn_d; + reg [0:51] entry9_epn_q; + wire entry9_xbit_d; + reg entry9_xbit_q; + wire [0:2] entry9_size_d; + reg [0:2] entry9_size_q; + wire entry9_v_d; + reg entry9_v_q; + wire [0:3] entry9_thdid_d; + reg [0:3] entry9_thdid_q; + wire [0:1] entry9_class_d; + reg [0:1] entry9_class_q; + wire [0:1] entry9_extclass_d; + reg [0:1] entry9_extclass_q; + wire entry9_hv_d; + reg entry9_hv_q; + wire entry9_ds_d; + reg entry9_ds_q; + wire [0:7] entry9_pid_d; + reg [0:7] entry9_pid_q; + wire [0:8] entry9_cmpmask_d; + reg [0:8] entry9_cmpmask_q; + wire [0:9] entry9_parity_d; + reg [0:9] entry9_parity_q; + wire [0:1] wr_entry9_sel; + wire entry9_inval; + wire [0:1] entry9_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry9_cam_vec; + wire [0:51] entry10_epn_d; + reg [0:51] entry10_epn_q; + wire entry10_xbit_d; + reg entry10_xbit_q; + wire [0:2] entry10_size_d; + reg [0:2] entry10_size_q; + wire entry10_v_d; + reg entry10_v_q; + wire [0:3] entry10_thdid_d; + reg [0:3] entry10_thdid_q; + wire [0:1] entry10_class_d; + reg [0:1] entry10_class_q; + wire [0:1] entry10_extclass_d; + reg [0:1] entry10_extclass_q; + wire entry10_hv_d; + reg entry10_hv_q; + wire entry10_ds_d; + reg entry10_ds_q; + wire [0:7] entry10_pid_d; + reg [0:7] entry10_pid_q; + wire [0:8] entry10_cmpmask_d; + reg [0:8] entry10_cmpmask_q; + wire [0:9] entry10_parity_d; + reg [0:9] entry10_parity_q; + wire [0:1] wr_entry10_sel; + wire entry10_inval; + wire [0:1] entry10_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry10_cam_vec; + wire [0:51] entry11_epn_d; + reg [0:51] entry11_epn_q; + wire entry11_xbit_d; + reg entry11_xbit_q; + wire [0:2] entry11_size_d; + reg [0:2] entry11_size_q; + wire entry11_v_d; + reg entry11_v_q; + wire [0:3] entry11_thdid_d; + reg [0:3] entry11_thdid_q; + wire [0:1] entry11_class_d; + reg [0:1] entry11_class_q; + wire [0:1] entry11_extclass_d; + reg [0:1] entry11_extclass_q; + wire entry11_hv_d; + reg entry11_hv_q; + wire entry11_ds_d; + reg entry11_ds_q; + wire [0:7] entry11_pid_d; + reg [0:7] entry11_pid_q; + wire [0:8] entry11_cmpmask_d; + reg [0:8] entry11_cmpmask_q; + wire [0:9] entry11_parity_d; + reg [0:9] entry11_parity_q; + wire [0:1] wr_entry11_sel; + wire entry11_inval; + wire [0:1] entry11_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry11_cam_vec; + wire [0:51] entry12_epn_d; + reg [0:51] entry12_epn_q; + wire entry12_xbit_d; + reg entry12_xbit_q; + wire [0:2] entry12_size_d; + reg [0:2] entry12_size_q; + wire entry12_v_d; + reg entry12_v_q; + wire [0:3] entry12_thdid_d; + reg [0:3] entry12_thdid_q; + wire [0:1] entry12_class_d; + reg [0:1] entry12_class_q; + wire [0:1] entry12_extclass_d; + reg [0:1] entry12_extclass_q; + wire entry12_hv_d; + reg entry12_hv_q; + wire entry12_ds_d; + reg entry12_ds_q; + wire [0:7] entry12_pid_d; + reg [0:7] entry12_pid_q; + wire [0:8] entry12_cmpmask_d; + reg [0:8] entry12_cmpmask_q; + wire [0:9] entry12_parity_d; + reg [0:9] entry12_parity_q; + wire [0:1] wr_entry12_sel; + wire entry12_inval; + wire [0:1] entry12_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry12_cam_vec; + wire [0:51] entry13_epn_d; + reg [0:51] entry13_epn_q; + wire entry13_xbit_d; + reg entry13_xbit_q; + wire [0:2] entry13_size_d; + reg [0:2] entry13_size_q; + wire entry13_v_d; + reg entry13_v_q; + wire [0:3] entry13_thdid_d; + reg [0:3] entry13_thdid_q; + wire [0:1] entry13_class_d; + reg [0:1] entry13_class_q; + wire [0:1] entry13_extclass_d; + reg [0:1] entry13_extclass_q; + wire entry13_hv_d; + reg entry13_hv_q; + wire entry13_ds_d; + reg entry13_ds_q; + wire [0:7] entry13_pid_d; + reg [0:7] entry13_pid_q; + wire [0:8] entry13_cmpmask_d; + reg [0:8] entry13_cmpmask_q; + wire [0:9] entry13_parity_d; + reg [0:9] entry13_parity_q; + wire [0:1] wr_entry13_sel; + wire entry13_inval; + wire [0:1] entry13_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry13_cam_vec; + wire [0:51] entry14_epn_d; + reg [0:51] entry14_epn_q; + wire entry14_xbit_d; + reg entry14_xbit_q; + wire [0:2] entry14_size_d; + reg [0:2] entry14_size_q; + wire entry14_v_d; + reg entry14_v_q; + wire [0:3] entry14_thdid_d; + reg [0:3] entry14_thdid_q; + wire [0:1] entry14_class_d; + reg [0:1] entry14_class_q; + wire [0:1] entry14_extclass_d; + reg [0:1] entry14_extclass_q; + wire entry14_hv_d; + reg entry14_hv_q; + wire entry14_ds_d; + reg entry14_ds_q; + wire [0:7] entry14_pid_d; + reg [0:7] entry14_pid_q; + wire [0:8] entry14_cmpmask_d; + reg [0:8] entry14_cmpmask_q; + wire [0:9] entry14_parity_d; + reg [0:9] entry14_parity_q; + wire [0:1] wr_entry14_sel; + wire entry14_inval; + wire [0:1] entry14_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry14_cam_vec; + wire [0:51] entry15_epn_d; + reg [0:51] entry15_epn_q; + wire entry15_xbit_d; + reg entry15_xbit_q; + wire [0:2] entry15_size_d; + reg [0:2] entry15_size_q; + wire entry15_v_d; + reg entry15_v_q; + wire [0:3] entry15_thdid_d; + reg [0:3] entry15_thdid_q; + wire [0:1] entry15_class_d; + reg [0:1] entry15_class_q; + wire [0:1] entry15_extclass_d; + reg [0:1] entry15_extclass_q; + wire entry15_hv_d; + reg entry15_hv_q; + wire entry15_ds_d; + reg entry15_ds_q; + wire [0:7] entry15_pid_d; + reg [0:7] entry15_pid_q; + wire [0:8] entry15_cmpmask_d; + reg [0:8] entry15_cmpmask_q; + wire [0:9] entry15_parity_d; + reg [0:9] entry15_parity_q; + wire [0:1] wr_entry15_sel; + wire entry15_inval; + wire [0:1] entry15_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry15_cam_vec; + wire [0:51] entry16_epn_d; + reg [0:51] entry16_epn_q; + wire entry16_xbit_d; + reg entry16_xbit_q; + wire [0:2] entry16_size_d; + reg [0:2] entry16_size_q; + wire entry16_v_d; + reg entry16_v_q; + wire [0:3] entry16_thdid_d; + reg [0:3] entry16_thdid_q; + wire [0:1] entry16_class_d; + reg [0:1] entry16_class_q; + wire [0:1] entry16_extclass_d; + reg [0:1] entry16_extclass_q; + wire entry16_hv_d; + reg entry16_hv_q; + wire entry16_ds_d; + reg entry16_ds_q; + wire [0:7] entry16_pid_d; + reg [0:7] entry16_pid_q; + wire [0:8] entry16_cmpmask_d; + reg [0:8] entry16_cmpmask_q; + wire [0:9] entry16_parity_d; + reg [0:9] entry16_parity_q; + wire [0:1] wr_entry16_sel; + wire entry16_inval; + wire [0:1] entry16_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry16_cam_vec; + wire [0:51] entry17_epn_d; + reg [0:51] entry17_epn_q; + wire entry17_xbit_d; + reg entry17_xbit_q; + wire [0:2] entry17_size_d; + reg [0:2] entry17_size_q; + wire entry17_v_d; + reg entry17_v_q; + wire [0:3] entry17_thdid_d; + reg [0:3] entry17_thdid_q; + wire [0:1] entry17_class_d; + reg [0:1] entry17_class_q; + wire [0:1] entry17_extclass_d; + reg [0:1] entry17_extclass_q; + wire entry17_hv_d; + reg entry17_hv_q; + wire entry17_ds_d; + reg entry17_ds_q; + wire [0:7] entry17_pid_d; + reg [0:7] entry17_pid_q; + wire [0:8] entry17_cmpmask_d; + reg [0:8] entry17_cmpmask_q; + wire [0:9] entry17_parity_d; + reg [0:9] entry17_parity_q; + wire [0:1] wr_entry17_sel; + wire entry17_inval; + wire [0:1] entry17_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry17_cam_vec; + wire [0:51] entry18_epn_d; + reg [0:51] entry18_epn_q; + wire entry18_xbit_d; + reg entry18_xbit_q; + wire [0:2] entry18_size_d; + reg [0:2] entry18_size_q; + wire entry18_v_d; + reg entry18_v_q; + wire [0:3] entry18_thdid_d; + reg [0:3] entry18_thdid_q; + wire [0:1] entry18_class_d; + reg [0:1] entry18_class_q; + wire [0:1] entry18_extclass_d; + reg [0:1] entry18_extclass_q; + wire entry18_hv_d; + reg entry18_hv_q; + wire entry18_ds_d; + reg entry18_ds_q; + wire [0:7] entry18_pid_d; + reg [0:7] entry18_pid_q; + wire [0:8] entry18_cmpmask_d; + reg [0:8] entry18_cmpmask_q; + wire [0:9] entry18_parity_d; + reg [0:9] entry18_parity_q; + wire [0:1] wr_entry18_sel; + wire entry18_inval; + wire [0:1] entry18_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry18_cam_vec; + wire [0:51] entry19_epn_d; + reg [0:51] entry19_epn_q; + wire entry19_xbit_d; + reg entry19_xbit_q; + wire [0:2] entry19_size_d; + reg [0:2] entry19_size_q; + wire entry19_v_d; + reg entry19_v_q; + wire [0:3] entry19_thdid_d; + reg [0:3] entry19_thdid_q; + wire [0:1] entry19_class_d; + reg [0:1] entry19_class_q; + wire [0:1] entry19_extclass_d; + reg [0:1] entry19_extclass_q; + wire entry19_hv_d; + reg entry19_hv_q; + wire entry19_ds_d; + reg entry19_ds_q; + wire [0:7] entry19_pid_d; + reg [0:7] entry19_pid_q; + wire [0:8] entry19_cmpmask_d; + reg [0:8] entry19_cmpmask_q; + wire [0:9] entry19_parity_d; + reg [0:9] entry19_parity_q; + wire [0:1] wr_entry19_sel; + wire entry19_inval; + wire [0:1] entry19_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry19_cam_vec; + wire [0:51] entry20_epn_d; + reg [0:51] entry20_epn_q; + wire entry20_xbit_d; + reg entry20_xbit_q; + wire [0:2] entry20_size_d; + reg [0:2] entry20_size_q; + wire entry20_v_d; + reg entry20_v_q; + wire [0:3] entry20_thdid_d; + reg [0:3] entry20_thdid_q; + wire [0:1] entry20_class_d; + reg [0:1] entry20_class_q; + wire [0:1] entry20_extclass_d; + reg [0:1] entry20_extclass_q; + wire entry20_hv_d; + reg entry20_hv_q; + wire entry20_ds_d; + reg entry20_ds_q; + wire [0:7] entry20_pid_d; + reg [0:7] entry20_pid_q; + wire [0:8] entry20_cmpmask_d; + reg [0:8] entry20_cmpmask_q; + wire [0:9] entry20_parity_d; + reg [0:9] entry20_parity_q; + wire [0:1] wr_entry20_sel; + wire entry20_inval; + wire [0:1] entry20_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry20_cam_vec; + wire [0:51] entry21_epn_d; + reg [0:51] entry21_epn_q; + wire entry21_xbit_d; + reg entry21_xbit_q; + wire [0:2] entry21_size_d; + reg [0:2] entry21_size_q; + wire entry21_v_d; + reg entry21_v_q; + wire [0:3] entry21_thdid_d; + reg [0:3] entry21_thdid_q; + wire [0:1] entry21_class_d; + reg [0:1] entry21_class_q; + wire [0:1] entry21_extclass_d; + reg [0:1] entry21_extclass_q; + wire entry21_hv_d; + reg entry21_hv_q; + wire entry21_ds_d; + reg entry21_ds_q; + wire [0:7] entry21_pid_d; + reg [0:7] entry21_pid_q; + wire [0:8] entry21_cmpmask_d; + reg [0:8] entry21_cmpmask_q; + wire [0:9] entry21_parity_d; + reg [0:9] entry21_parity_q; + wire [0:1] wr_entry21_sel; + wire entry21_inval; + wire [0:1] entry21_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry21_cam_vec; + wire [0:51] entry22_epn_d; + reg [0:51] entry22_epn_q; + wire entry22_xbit_d; + reg entry22_xbit_q; + wire [0:2] entry22_size_d; + reg [0:2] entry22_size_q; + wire entry22_v_d; + reg entry22_v_q; + wire [0:3] entry22_thdid_d; + reg [0:3] entry22_thdid_q; + wire [0:1] entry22_class_d; + reg [0:1] entry22_class_q; + wire [0:1] entry22_extclass_d; + reg [0:1] entry22_extclass_q; + wire entry22_hv_d; + reg entry22_hv_q; + wire entry22_ds_d; + reg entry22_ds_q; + wire [0:7] entry22_pid_d; + reg [0:7] entry22_pid_q; + wire [0:8] entry22_cmpmask_d; + reg [0:8] entry22_cmpmask_q; + wire [0:9] entry22_parity_d; + reg [0:9] entry22_parity_q; + wire [0:1] wr_entry22_sel; + wire entry22_inval; + wire [0:1] entry22_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry22_cam_vec; + wire [0:51] entry23_epn_d; + reg [0:51] entry23_epn_q; + wire entry23_xbit_d; + reg entry23_xbit_q; + wire [0:2] entry23_size_d; + reg [0:2] entry23_size_q; + wire entry23_v_d; + reg entry23_v_q; + wire [0:3] entry23_thdid_d; + reg [0:3] entry23_thdid_q; + wire [0:1] entry23_class_d; + reg [0:1] entry23_class_q; + wire [0:1] entry23_extclass_d; + reg [0:1] entry23_extclass_q; + wire entry23_hv_d; + reg entry23_hv_q; + wire entry23_ds_d; + reg entry23_ds_q; + wire [0:7] entry23_pid_d; + reg [0:7] entry23_pid_q; + wire [0:8] entry23_cmpmask_d; + reg [0:8] entry23_cmpmask_q; + wire [0:9] entry23_parity_d; + reg [0:9] entry23_parity_q; + wire [0:1] wr_entry23_sel; + wire entry23_inval; + wire [0:1] entry23_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry23_cam_vec; + wire [0:51] entry24_epn_d; + reg [0:51] entry24_epn_q; + wire entry24_xbit_d; + reg entry24_xbit_q; + wire [0:2] entry24_size_d; + reg [0:2] entry24_size_q; + wire entry24_v_d; + reg entry24_v_q; + wire [0:3] entry24_thdid_d; + reg [0:3] entry24_thdid_q; + wire [0:1] entry24_class_d; + reg [0:1] entry24_class_q; + wire [0:1] entry24_extclass_d; + reg [0:1] entry24_extclass_q; + wire entry24_hv_d; + reg entry24_hv_q; + wire entry24_ds_d; + reg entry24_ds_q; + wire [0:7] entry24_pid_d; + reg [0:7] entry24_pid_q; + wire [0:8] entry24_cmpmask_d; + reg [0:8] entry24_cmpmask_q; + wire [0:9] entry24_parity_d; + reg [0:9] entry24_parity_q; + wire [0:1] wr_entry24_sel; + wire entry24_inval; + wire [0:1] entry24_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry24_cam_vec; + wire [0:51] entry25_epn_d; + reg [0:51] entry25_epn_q; + wire entry25_xbit_d; + reg entry25_xbit_q; + wire [0:2] entry25_size_d; + reg [0:2] entry25_size_q; + wire entry25_v_d; + reg entry25_v_q; + wire [0:3] entry25_thdid_d; + reg [0:3] entry25_thdid_q; + wire [0:1] entry25_class_d; + reg [0:1] entry25_class_q; + wire [0:1] entry25_extclass_d; + reg [0:1] entry25_extclass_q; + wire entry25_hv_d; + reg entry25_hv_q; + wire entry25_ds_d; + reg entry25_ds_q; + wire [0:7] entry25_pid_d; + reg [0:7] entry25_pid_q; + wire [0:8] entry25_cmpmask_d; + reg [0:8] entry25_cmpmask_q; + wire [0:9] entry25_parity_d; + reg [0:9] entry25_parity_q; + wire [0:1] wr_entry25_sel; + wire entry25_inval; + wire [0:1] entry25_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry25_cam_vec; + wire [0:51] entry26_epn_d; + reg [0:51] entry26_epn_q; + wire entry26_xbit_d; + reg entry26_xbit_q; + wire [0:2] entry26_size_d; + reg [0:2] entry26_size_q; + wire entry26_v_d; + reg entry26_v_q; + wire [0:3] entry26_thdid_d; + reg [0:3] entry26_thdid_q; + wire [0:1] entry26_class_d; + reg [0:1] entry26_class_q; + wire [0:1] entry26_extclass_d; + reg [0:1] entry26_extclass_q; + wire entry26_hv_d; + reg entry26_hv_q; + wire entry26_ds_d; + reg entry26_ds_q; + wire [0:7] entry26_pid_d; + reg [0:7] entry26_pid_q; + wire [0:8] entry26_cmpmask_d; + reg [0:8] entry26_cmpmask_q; + wire [0:9] entry26_parity_d; + reg [0:9] entry26_parity_q; + wire [0:1] wr_entry26_sel; + wire entry26_inval; + wire [0:1] entry26_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry26_cam_vec; + wire [0:51] entry27_epn_d; + reg [0:51] entry27_epn_q; + wire entry27_xbit_d; + reg entry27_xbit_q; + wire [0:2] entry27_size_d; + reg [0:2] entry27_size_q; + wire entry27_v_d; + reg entry27_v_q; + wire [0:3] entry27_thdid_d; + reg [0:3] entry27_thdid_q; + wire [0:1] entry27_class_d; + reg [0:1] entry27_class_q; + wire [0:1] entry27_extclass_d; + reg [0:1] entry27_extclass_q; + wire entry27_hv_d; + reg entry27_hv_q; + wire entry27_ds_d; + reg entry27_ds_q; + wire [0:7] entry27_pid_d; + reg [0:7] entry27_pid_q; + wire [0:8] entry27_cmpmask_d; + reg [0:8] entry27_cmpmask_q; + wire [0:9] entry27_parity_d; + reg [0:9] entry27_parity_q; + wire [0:1] wr_entry27_sel; + wire entry27_inval; + wire [0:1] entry27_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry27_cam_vec; + wire [0:51] entry28_epn_d; + reg [0:51] entry28_epn_q; + wire entry28_xbit_d; + reg entry28_xbit_q; + wire [0:2] entry28_size_d; + reg [0:2] entry28_size_q; + wire entry28_v_d; + reg entry28_v_q; + wire [0:3] entry28_thdid_d; + reg [0:3] entry28_thdid_q; + wire [0:1] entry28_class_d; + reg [0:1] entry28_class_q; + wire [0:1] entry28_extclass_d; + reg [0:1] entry28_extclass_q; + wire entry28_hv_d; + reg entry28_hv_q; + wire entry28_ds_d; + reg entry28_ds_q; + wire [0:7] entry28_pid_d; + reg [0:7] entry28_pid_q; + wire [0:8] entry28_cmpmask_d; + reg [0:8] entry28_cmpmask_q; + wire [0:9] entry28_parity_d; + reg [0:9] entry28_parity_q; + wire [0:1] wr_entry28_sel; + wire entry28_inval; + wire [0:1] entry28_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry28_cam_vec; + wire [0:51] entry29_epn_d; + reg [0:51] entry29_epn_q; + wire entry29_xbit_d; + reg entry29_xbit_q; + wire [0:2] entry29_size_d; + reg [0:2] entry29_size_q; + wire entry29_v_d; + reg entry29_v_q; + wire [0:3] entry29_thdid_d; + reg [0:3] entry29_thdid_q; + wire [0:1] entry29_class_d; + reg [0:1] entry29_class_q; + wire [0:1] entry29_extclass_d; + reg [0:1] entry29_extclass_q; + wire entry29_hv_d; + reg entry29_hv_q; + wire entry29_ds_d; + reg entry29_ds_q; + wire [0:7] entry29_pid_d; + reg [0:7] entry29_pid_q; + wire [0:8] entry29_cmpmask_d; + reg [0:8] entry29_cmpmask_q; + wire [0:9] entry29_parity_d; + reg [0:9] entry29_parity_q; + wire [0:1] wr_entry29_sel; + wire entry29_inval; + wire [0:1] entry29_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry29_cam_vec; + wire [0:51] entry30_epn_d; + reg [0:51] entry30_epn_q; + wire entry30_xbit_d; + reg entry30_xbit_q; + wire [0:2] entry30_size_d; + reg [0:2] entry30_size_q; + wire entry30_v_d; + reg entry30_v_q; + wire [0:3] entry30_thdid_d; + reg [0:3] entry30_thdid_q; + wire [0:1] entry30_class_d; + reg [0:1] entry30_class_q; + wire [0:1] entry30_extclass_d; + reg [0:1] entry30_extclass_q; + wire entry30_hv_d; + reg entry30_hv_q; + wire entry30_ds_d; + reg entry30_ds_q; + wire [0:7] entry30_pid_d; + reg [0:7] entry30_pid_q; + wire [0:8] entry30_cmpmask_d; + reg [0:8] entry30_cmpmask_q; + wire [0:9] entry30_parity_d; + reg [0:9] entry30_parity_q; + wire [0:1] wr_entry30_sel; + wire entry30_inval; + wire [0:1] entry30_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry30_cam_vec; + wire [0:51] entry31_epn_d; + reg [0:51] entry31_epn_q; + wire entry31_xbit_d; + reg entry31_xbit_q; + wire [0:2] entry31_size_d; + reg [0:2] entry31_size_q; + wire entry31_v_d; + reg entry31_v_q; + wire [0:3] entry31_thdid_d; + reg [0:3] entry31_thdid_q; + wire [0:1] entry31_class_d; + reg [0:1] entry31_class_q; + wire [0:1] entry31_extclass_d; + reg [0:1] entry31_extclass_q; + wire entry31_hv_d; + reg entry31_hv_q; + wire entry31_ds_d; + reg entry31_ds_q; + wire [0:7] entry31_pid_d; + reg [0:7] entry31_pid_q; + wire [0:8] entry31_cmpmask_d; + reg [0:8] entry31_cmpmask_q; + wire [0:9] entry31_parity_d; + reg [0:9] entry31_parity_q; + wire [0:1] wr_entry31_sel; + wire entry31_inval; + wire [0:1] entry31_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry31_cam_vec; + wire [0:5] cam_cmp_data_muxsel; + wire [0:5] rd_cam_data_muxsel; + wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_np1; + wire [0:ARRAY_DATA_WIDTH-1] array_cmp_data_np1; + wire [0:72] wr_array_data_bram; + wire [0:72] rd_array_data_d_std; + wire [0:55] array_cmp_data_bram_std; + wire [66:72] array_cmp_data_bramp_std; + + // latch signals + wire [0:ARRAY_DATA_WIDTH-1] rd_array_data_d; + reg [0:ARRAY_DATA_WIDTH-1] rd_array_data_q; + wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_d; + reg [0:CAM_DATA_WIDTH-1] cam_cmp_data_q; + wire [0:9] cam_cmp_parity_d; + reg [0:9] cam_cmp_parity_q; + wire [0:CAM_DATA_WIDTH-1] rd_cam_data_d; + reg [0:CAM_DATA_WIDTH-1] rd_cam_data_q; + wire [0:NUM_ENTRY-1] entry_match_d; + reg [0:NUM_ENTRY-1] entry_match_q; + wire [0:NUM_ENTRY-1] match_vec; + wire [0:NUM_ENTRY_LOG2-1] cam_hit_entry_d; + reg [0:NUM_ENTRY_LOG2-1] cam_hit_entry_q; + wire cam_hit_d; + reg cam_hit_q; + wire toggle_d; + reg toggle_q; + wire toggle2x_d; + reg toggle2x_q; + (* analysis_not_referenced="true" *) + wire unused; + + + + assign clk = (~nclk[0]); + assign clk2x = nclk[2]; + + always @(posedge clk) + begin: rlatch + sreset_q <= nclk[1]; + end + + // + // NEW clk2x gate logic start + // + + always @(posedge nclk[0]) + begin: tlatch + if (sreset_q == 1'b1) + toggle_q <= 1'b1; + else + toggle_q <= toggle_d; + end + + always @(posedge nclk[2]) + begin: flatch + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + end + + assign toggle_d = (~toggle_q); + assign toggle2x_d = toggle_q; + + // should force gate_fq to be on during odd 2x clock (second half of 1x clock). + assign gate_d = toggle_q ^ toggle2x_q; + // if you want the first half do the following + //assign gate_d <= ~(toggle_q ^ toggle2x_q); + + // + // NEW clk2x gate logic end + // + + // Slow Latches (nclk) + always @(posedge nclk[0]) + begin: slatch + if (sreset_q == 1'b1) + begin + cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; + cam_cmp_parity_q <= 10'b0; + rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; + rd_array_data_q <= {ARRAY_DATA_WIDTH{1'b0}}; + entry_match_q <= {NUM_ENTRY{1'b0}}; + cam_hit_entry_q <= {NUM_ENTRY_LOG2{1'b0}}; + cam_hit_q <= 1'b0; + comp_addr_np1_q <= {RPN_WIDTH{1'b0}}; + rpn_np2_q <= {RPN_WIDTH{1'b0}}; + attr_np2_q <= 21'b0; + entry0_size_q <= 3'b0; + entry0_xbit_q <= 1'b0; + entry0_epn_q <= 52'b0; + entry0_class_q <= 2'b0; + entry0_extclass_q <= 2'b0; + entry0_hv_q <= 1'b0; + entry0_ds_q <= 1'b0; + entry0_thdid_q <= 4'b0; + entry0_pid_q <= 8'b0; + entry0_v_q <= 1'b0; + entry0_parity_q <= 10'b0; + entry0_cmpmask_q <= 9'b0; + entry1_size_q <= 3'b0; + entry1_xbit_q <= 1'b0; + entry1_epn_q <= 52'b0; + entry1_class_q <= 2'b0; + entry1_extclass_q <= 2'b0; + entry1_hv_q <= 1'b0; + entry1_ds_q <= 1'b0; + entry1_thdid_q <= 4'b0; + entry1_pid_q <= 8'b0; + entry1_v_q <= 1'b0; + entry1_parity_q <= 10'b0; + entry1_cmpmask_q <= 9'b0; + entry2_size_q <= 3'b0; + entry2_xbit_q <= 1'b0; + entry2_epn_q <= 52'b0; + entry2_class_q <= 2'b0; + entry2_extclass_q <= 2'b0; + entry2_hv_q <= 1'b0; + entry2_ds_q <= 1'b0; + entry2_thdid_q <= 4'b0; + entry2_pid_q <= 8'b0; + entry2_v_q <= 1'b0; + entry2_parity_q <= 10'b0; + entry2_cmpmask_q <= 9'b0; + entry3_size_q <= 3'b0; + entry3_xbit_q <= 1'b0; + entry3_epn_q <= 52'b0; + entry3_class_q <= 2'b0; + entry3_extclass_q <= 2'b0; + entry3_hv_q <= 1'b0; + entry3_ds_q <= 1'b0; + entry3_thdid_q <= 4'b0; + entry3_pid_q <= 8'b0; + entry3_v_q <= 1'b0; + entry3_parity_q <= 10'b0; + entry3_cmpmask_q <= 9'b0; + entry4_size_q <= 3'b0; + entry4_xbit_q <= 1'b0; + entry4_epn_q <= 52'b0; + entry4_class_q <= 2'b0; + entry4_extclass_q <= 2'b0; + entry4_hv_q <= 1'b0; + entry4_ds_q <= 1'b0; + entry4_thdid_q <= 4'b0; + entry4_pid_q <= 8'b0; + entry4_v_q <= 1'b0; + entry4_parity_q <= 10'b0; + entry4_cmpmask_q <= 9'b0; + entry5_size_q <= 3'b0; + entry5_xbit_q <= 1'b0; + entry5_epn_q <= 52'b0; + entry5_class_q <= 2'b0; + entry5_extclass_q <= 2'b0; + entry5_hv_q <= 1'b0; + entry5_ds_q <= 1'b0; + entry5_thdid_q <= 4'b0; + entry5_pid_q <= 8'b0; + entry5_v_q <= 1'b0; + entry5_parity_q <= 10'b0; + entry5_cmpmask_q <= 9'b0; + entry6_size_q <= 3'b0; + entry6_xbit_q <= 1'b0; + entry6_epn_q <= 52'b0; + entry6_class_q <= 2'b0; + entry6_extclass_q <= 2'b0; + entry6_hv_q <= 1'b0; + entry6_ds_q <= 1'b0; + entry6_thdid_q <= 4'b0; + entry6_pid_q <= 8'b0; + entry6_v_q <= 1'b0; + entry6_parity_q <= 10'b0; + entry6_cmpmask_q <= 9'b0; + entry7_size_q <= 3'b0; + entry7_xbit_q <= 1'b0; + entry7_epn_q <= 52'b0; + entry7_class_q <= 2'b0; + entry7_extclass_q <= 2'b0; + entry7_hv_q <= 1'b0; + entry7_ds_q <= 1'b0; + entry7_thdid_q <= 4'b0; + entry7_pid_q <= 8'b0; + entry7_v_q <= 1'b0; + entry7_parity_q <= 10'b0; + entry7_cmpmask_q <= 9'b0; + entry8_size_q <= 3'b0; + entry8_xbit_q <= 1'b0; + entry8_epn_q <= 52'b0; + entry8_class_q <= 2'b0; + entry8_extclass_q <= 2'b0; + entry8_hv_q <= 1'b0; + entry8_ds_q <= 1'b0; + entry8_thdid_q <= 4'b0; + entry8_pid_q <= 8'b0; + entry8_v_q <= 1'b0; + entry8_parity_q <= 10'b0; + entry8_cmpmask_q <= 9'b0; + entry9_size_q <= 3'b0; + entry9_xbit_q <= 1'b0; + entry9_epn_q <= 52'b0; + entry9_class_q <= 2'b0; + entry9_extclass_q <= 2'b0; + entry9_hv_q <= 1'b0; + entry9_ds_q <= 1'b0; + entry9_thdid_q <= 4'b0; + entry9_pid_q <= 8'b0; + entry9_v_q <= 1'b0; + entry9_parity_q <= 10'b0; + entry9_cmpmask_q <= 9'b0; + entry10_size_q <= 3'b0; + entry10_xbit_q <= 1'b0; + entry10_epn_q <= 52'b0; + entry10_class_q <= 2'b0; + entry10_extclass_q <= 2'b0; + entry10_hv_q <= 1'b0; + entry10_ds_q <= 1'b0; + entry10_thdid_q <= 4'b0; + entry10_pid_q <= 8'b0; + entry10_v_q <= 1'b0; + entry10_parity_q <= 10'b0; + entry10_cmpmask_q <= 9'b0; + entry11_size_q <= 3'b0; + entry11_xbit_q <= 1'b0; + entry11_epn_q <= 52'b0; + entry11_class_q <= 2'b0; + entry11_extclass_q <= 2'b0; + entry11_hv_q <= 1'b0; + entry11_ds_q <= 1'b0; + entry11_thdid_q <= 4'b0; + entry11_pid_q <= 8'b0; + entry11_v_q <= 1'b0; + entry11_parity_q <= 10'b0; + entry11_cmpmask_q <= 9'b0; + entry12_size_q <= 3'b0; + entry12_xbit_q <= 1'b0; + entry12_epn_q <= 52'b0; + entry12_class_q <= 2'b0; + entry12_extclass_q <= 2'b0; + entry12_hv_q <= 1'b0; + entry12_ds_q <= 1'b0; + entry12_thdid_q <= 4'b0; + entry12_pid_q <= 8'b0; + entry12_v_q <= 1'b0; + entry12_parity_q <= 10'b0; + entry12_cmpmask_q <= 9'b0; + entry13_size_q <= 3'b0; + entry13_xbit_q <= 1'b0; + entry13_epn_q <= 52'b0; + entry13_class_q <= 2'b0; + entry13_extclass_q <= 2'b0; + entry13_hv_q <= 1'b0; + entry13_ds_q <= 1'b0; + entry13_thdid_q <= 4'b0; + entry13_pid_q <= 8'b0; + entry13_v_q <= 1'b0; + entry13_parity_q <= 10'b0; + entry13_cmpmask_q <= 9'b0; + entry14_size_q <= 3'b0; + entry14_xbit_q <= 1'b0; + entry14_epn_q <= 52'b0; + entry14_class_q <= 2'b0; + entry14_extclass_q <= 2'b0; + entry14_hv_q <= 1'b0; + entry14_ds_q <= 1'b0; + entry14_thdid_q <= 4'b0; + entry14_pid_q <= 8'b0; + entry14_v_q <= 1'b0; + entry14_parity_q <= 10'b0; + entry14_cmpmask_q <= 9'b0; + entry15_size_q <= 3'b0; + entry15_xbit_q <= 1'b0; + entry15_epn_q <= 52'b0; + entry15_class_q <= 2'b0; + entry15_extclass_q <= 2'b0; + entry15_hv_q <= 1'b0; + entry15_ds_q <= 1'b0; + entry15_thdid_q <= 4'b0; + entry15_pid_q <= 8'b0; + entry15_v_q <= 1'b0; + entry15_parity_q <= 10'b0; + entry15_cmpmask_q <= 9'b0; + entry16_size_q <= 3'b0; + entry16_xbit_q <= 1'b0; + entry16_epn_q <= 52'b0; + entry16_class_q <= 2'b0; + entry16_extclass_q <= 2'b0; + entry16_hv_q <= 1'b0; + entry16_ds_q <= 1'b0; + entry16_thdid_q <= 4'b0; + entry16_pid_q <= 8'b0; + entry16_v_q <= 1'b0; + entry16_parity_q <= 10'b0; + entry16_cmpmask_q <= 9'b0; + entry17_size_q <= 3'b0; + entry17_xbit_q <= 1'b0; + entry17_epn_q <= 52'b0; + entry17_class_q <= 2'b0; + entry17_extclass_q <= 2'b0; + entry17_hv_q <= 1'b0; + entry17_ds_q <= 1'b0; + entry17_thdid_q <= 4'b0; + entry17_pid_q <= 8'b0; + entry17_v_q <= 1'b0; + entry17_parity_q <= 10'b0; + entry17_cmpmask_q <= 9'b0; + entry18_size_q <= 3'b0; + entry18_xbit_q <= 1'b0; + entry18_epn_q <= 52'b0; + entry18_class_q <= 2'b0; + entry18_extclass_q <= 2'b0; + entry18_hv_q <= 1'b0; + entry18_ds_q <= 1'b0; + entry18_thdid_q <= 4'b0; + entry18_pid_q <= 8'b0; + entry18_v_q <= 1'b0; + entry18_parity_q <= 10'b0; + entry18_cmpmask_q <= 9'b0; + entry19_size_q <= 3'b0; + entry19_xbit_q <= 1'b0; + entry19_epn_q <= 52'b0; + entry19_class_q <= 2'b0; + entry19_extclass_q <= 2'b0; + entry19_hv_q <= 1'b0; + entry19_ds_q <= 1'b0; + entry19_thdid_q <= 4'b0; + entry19_pid_q <= 8'b0; + entry19_v_q <= 1'b0; + entry19_parity_q <= 10'b0; + entry19_cmpmask_q <= 9'b0; + entry20_size_q <= 3'b0; + entry20_xbit_q <= 1'b0; + entry20_epn_q <= 52'b0; + entry20_class_q <= 2'b0; + entry20_extclass_q <= 2'b0; + entry20_hv_q <= 1'b0; + entry20_ds_q <= 1'b0; + entry20_thdid_q <= 4'b0; + entry20_pid_q <= 8'b0; + entry20_v_q <= 1'b0; + entry20_parity_q <= 10'b0; + entry20_cmpmask_q <= 9'b0; + entry21_size_q <= 3'b0; + entry21_xbit_q <= 1'b0; + entry21_epn_q <= 52'b0; + entry21_class_q <= 2'b0; + entry21_extclass_q <= 2'b0; + entry21_hv_q <= 1'b0; + entry21_ds_q <= 1'b0; + entry21_thdid_q <= 4'b0; + entry21_pid_q <= 8'b0; + entry21_v_q <= 1'b0; + entry21_parity_q <= 10'b0; + entry21_cmpmask_q <= 9'b0; + entry22_size_q <= 3'b0; + entry22_xbit_q <= 1'b0; + entry22_epn_q <= 52'b0; + entry22_class_q <= 2'b0; + entry22_extclass_q <= 2'b0; + entry22_hv_q <= 1'b0; + entry22_ds_q <= 1'b0; + entry22_thdid_q <= 4'b0; + entry22_pid_q <= 8'b0; + entry22_v_q <= 1'b0; + entry22_parity_q <= 10'b0; + entry22_cmpmask_q <= 9'b0; + entry23_size_q <= 3'b0; + entry23_xbit_q <= 1'b0; + entry23_epn_q <= 52'b0; + entry23_class_q <= 2'b0; + entry23_extclass_q <= 2'b0; + entry23_hv_q <= 1'b0; + entry23_ds_q <= 1'b0; + entry23_thdid_q <= 4'b0; + entry23_pid_q <= 8'b0; + entry23_v_q <= 1'b0; + entry23_parity_q <= 10'b0; + entry23_cmpmask_q <= 9'b0; + entry24_size_q <= 3'b0; + entry24_xbit_q <= 1'b0; + entry24_epn_q <= 52'b0; + entry24_class_q <= 2'b0; + entry24_extclass_q <= 2'b0; + entry24_hv_q <= 1'b0; + entry24_ds_q <= 1'b0; + entry24_thdid_q <= 4'b0; + entry24_pid_q <= 8'b0; + entry24_v_q <= 1'b0; + entry24_parity_q <= 10'b0; + entry24_cmpmask_q <= 9'b0; + entry25_size_q <= 3'b0; + entry25_xbit_q <= 1'b0; + entry25_epn_q <= 52'b0; + entry25_class_q <= 2'b0; + entry25_extclass_q <= 2'b0; + entry25_hv_q <= 1'b0; + entry25_ds_q <= 1'b0; + entry25_thdid_q <= 4'b0; + entry25_pid_q <= 8'b0; + entry25_v_q <= 1'b0; + entry25_parity_q <= 10'b0; + entry25_cmpmask_q <= 9'b0; + entry26_size_q <= 3'b0; + entry26_xbit_q <= 1'b0; + entry26_epn_q <= 52'b0; + entry26_class_q <= 2'b0; + entry26_extclass_q <= 2'b0; + entry26_hv_q <= 1'b0; + entry26_ds_q <= 1'b0; + entry26_thdid_q <= 4'b0; + entry26_pid_q <= 8'b0; + entry26_v_q <= 1'b0; + entry26_parity_q <= 10'b0; + entry26_cmpmask_q <= 9'b0; + entry27_size_q <= 3'b0; + entry27_xbit_q <= 1'b0; + entry27_epn_q <= 52'b0; + entry27_class_q <= 2'b0; + entry27_extclass_q <= 2'b0; + entry27_hv_q <= 1'b0; + entry27_ds_q <= 1'b0; + entry27_thdid_q <= 4'b0; + entry27_pid_q <= 8'b0; + entry27_v_q <= 1'b0; + entry27_parity_q <= 10'b0; + entry27_cmpmask_q <= 9'b0; + entry28_size_q <= 3'b0; + entry28_xbit_q <= 1'b0; + entry28_epn_q <= 52'b0; + entry28_class_q <= 2'b0; + entry28_extclass_q <= 2'b0; + entry28_hv_q <= 1'b0; + entry28_ds_q <= 1'b0; + entry28_thdid_q <= 4'b0; + entry28_pid_q <= 8'b0; + entry28_v_q <= 1'b0; + entry28_parity_q <= 10'b0; + entry28_cmpmask_q <= 9'b0; + entry29_size_q <= 3'b0; + entry29_xbit_q <= 1'b0; + entry29_epn_q <= 52'b0; + entry29_class_q <= 2'b0; + entry29_extclass_q <= 2'b0; + entry29_hv_q <= 1'b0; + entry29_ds_q <= 1'b0; + entry29_thdid_q <= 4'b0; + entry29_pid_q <= 8'b0; + entry29_v_q <= 1'b0; + entry29_parity_q <= 10'b0; + entry29_cmpmask_q <= 9'b0; + entry30_size_q <= 3'b0; + entry30_xbit_q <= 1'b0; + entry30_epn_q <= 52'b0; + entry30_class_q <= 2'b0; + entry30_extclass_q <= 2'b0; + entry30_hv_q <= 1'b0; + entry30_ds_q <= 1'b0; + entry30_thdid_q <= 4'b0; + entry30_pid_q <= 8'b0; + entry30_v_q <= 1'b0; + entry30_parity_q <= 10'b0; + entry30_cmpmask_q <= 9'b0; + entry31_size_q <= 3'b0; + entry31_xbit_q <= 1'b0; + entry31_epn_q <= 52'b0; + entry31_class_q <= 2'b0; + entry31_extclass_q <= 2'b0; + entry31_hv_q <= 1'b0; + entry31_ds_q <= 1'b0; + entry31_thdid_q <= 4'b0; + entry31_pid_q <= 8'b0; + entry31_v_q <= 1'b0; + entry31_parity_q <= 10'b0; + entry31_cmpmask_q <= 9'b0; + end + else + begin + cam_cmp_data_q <= cam_cmp_data_d; + rd_cam_data_q <= rd_cam_data_d; + rd_array_data_q <= rd_array_data_d; + entry_match_q <= entry_match_d; + cam_hit_entry_q <= cam_hit_entry_d; + cam_hit_q <= cam_hit_d; + cam_cmp_parity_q <= cam_cmp_parity_d; + comp_addr_np1_q <= comp_addr_np1_d; + rpn_np2_q <= rpn_np2_d; + attr_np2_q <= attr_np2_d; + entry0_size_q <= entry0_size_d; + entry0_xbit_q <= entry0_xbit_d; + entry0_epn_q <= entry0_epn_d; + entry0_class_q <= entry0_class_d; + entry0_extclass_q <= entry0_extclass_d; + entry0_hv_q <= entry0_hv_d; + entry0_ds_q <= entry0_ds_d; + entry0_thdid_q <= entry0_thdid_d; + entry0_pid_q <= entry0_pid_d; + entry0_v_q <= entry0_v_d; + entry0_parity_q <= entry0_parity_d; + entry0_cmpmask_q <= entry0_cmpmask_d; + entry1_size_q <= entry1_size_d; + entry1_xbit_q <= entry1_xbit_d; + entry1_epn_q <= entry1_epn_d; + entry1_class_q <= entry1_class_d; + entry1_extclass_q <= entry1_extclass_d; + entry1_hv_q <= entry1_hv_d; + entry1_ds_q <= entry1_ds_d; + entry1_thdid_q <= entry1_thdid_d; + entry1_pid_q <= entry1_pid_d; + entry1_v_q <= entry1_v_d; + entry1_parity_q <= entry1_parity_d; + entry1_cmpmask_q <= entry1_cmpmask_d; + entry2_size_q <= entry2_size_d; + entry2_xbit_q <= entry2_xbit_d; + entry2_epn_q <= entry2_epn_d; + entry2_class_q <= entry2_class_d; + entry2_extclass_q <= entry2_extclass_d; + entry2_hv_q <= entry2_hv_d; + entry2_ds_q <= entry2_ds_d; + entry2_thdid_q <= entry2_thdid_d; + entry2_pid_q <= entry2_pid_d; + entry2_v_q <= entry2_v_d; + entry2_parity_q <= entry2_parity_d; + entry2_cmpmask_q <= entry2_cmpmask_d; + entry3_size_q <= entry3_size_d; + entry3_xbit_q <= entry3_xbit_d; + entry3_epn_q <= entry3_epn_d; + entry3_class_q <= entry3_class_d; + entry3_extclass_q <= entry3_extclass_d; + entry3_hv_q <= entry3_hv_d; + entry3_ds_q <= entry3_ds_d; + entry3_thdid_q <= entry3_thdid_d; + entry3_pid_q <= entry3_pid_d; + entry3_v_q <= entry3_v_d; + entry3_parity_q <= entry3_parity_d; + entry3_cmpmask_q <= entry3_cmpmask_d; + entry4_size_q <= entry4_size_d; + entry4_xbit_q <= entry4_xbit_d; + entry4_epn_q <= entry4_epn_d; + entry4_class_q <= entry4_class_d; + entry4_extclass_q <= entry4_extclass_d; + entry4_hv_q <= entry4_hv_d; + entry4_ds_q <= entry4_ds_d; + entry4_thdid_q <= entry4_thdid_d; + entry4_pid_q <= entry4_pid_d; + entry4_v_q <= entry4_v_d; + entry4_parity_q <= entry4_parity_d; + entry4_cmpmask_q <= entry4_cmpmask_d; + entry5_size_q <= entry5_size_d; + entry5_xbit_q <= entry5_xbit_d; + entry5_epn_q <= entry5_epn_d; + entry5_class_q <= entry5_class_d; + entry5_extclass_q <= entry5_extclass_d; + entry5_hv_q <= entry5_hv_d; + entry5_ds_q <= entry5_ds_d; + entry5_thdid_q <= entry5_thdid_d; + entry5_pid_q <= entry5_pid_d; + entry5_v_q <= entry5_v_d; + entry5_parity_q <= entry5_parity_d; + entry5_cmpmask_q <= entry5_cmpmask_d; + entry6_size_q <= entry6_size_d; + entry6_xbit_q <= entry6_xbit_d; + entry6_epn_q <= entry6_epn_d; + entry6_class_q <= entry6_class_d; + entry6_extclass_q <= entry6_extclass_d; + entry6_hv_q <= entry6_hv_d; + entry6_ds_q <= entry6_ds_d; + entry6_thdid_q <= entry6_thdid_d; + entry6_pid_q <= entry6_pid_d; + entry6_v_q <= entry6_v_d; + entry6_parity_q <= entry6_parity_d; + entry6_cmpmask_q <= entry6_cmpmask_d; + entry7_size_q <= entry7_size_d; + entry7_xbit_q <= entry7_xbit_d; + entry7_epn_q <= entry7_epn_d; + entry7_class_q <= entry7_class_d; + entry7_extclass_q <= entry7_extclass_d; + entry7_hv_q <= entry7_hv_d; + entry7_ds_q <= entry7_ds_d; + entry7_thdid_q <= entry7_thdid_d; + entry7_pid_q <= entry7_pid_d; + entry7_v_q <= entry7_v_d; + entry7_parity_q <= entry7_parity_d; + entry7_cmpmask_q <= entry7_cmpmask_d; + entry8_size_q <= entry8_size_d; + entry8_xbit_q <= entry8_xbit_d; + entry8_epn_q <= entry8_epn_d; + entry8_class_q <= entry8_class_d; + entry8_extclass_q <= entry8_extclass_d; + entry8_hv_q <= entry8_hv_d; + entry8_ds_q <= entry8_ds_d; + entry8_thdid_q <= entry8_thdid_d; + entry8_pid_q <= entry8_pid_d; + entry8_v_q <= entry8_v_d; + entry8_parity_q <= entry8_parity_d; + entry8_cmpmask_q <= entry8_cmpmask_d; + entry9_size_q <= entry9_size_d; + entry9_xbit_q <= entry9_xbit_d; + entry9_epn_q <= entry9_epn_d; + entry9_class_q <= entry9_class_d; + entry9_extclass_q <= entry9_extclass_d; + entry9_hv_q <= entry9_hv_d; + entry9_ds_q <= entry9_ds_d; + entry9_thdid_q <= entry9_thdid_d; + entry9_pid_q <= entry9_pid_d; + entry9_v_q <= entry9_v_d; + entry9_parity_q <= entry9_parity_d; + entry9_cmpmask_q <= entry9_cmpmask_d; + entry10_size_q <= entry10_size_d; + entry10_xbit_q <= entry10_xbit_d; + entry10_epn_q <= entry10_epn_d; + entry10_class_q <= entry10_class_d; + entry10_extclass_q <= entry10_extclass_d; + entry10_hv_q <= entry10_hv_d; + entry10_ds_q <= entry10_ds_d; + entry10_thdid_q <= entry10_thdid_d; + entry10_pid_q <= entry10_pid_d; + entry10_v_q <= entry10_v_d; + entry10_parity_q <= entry10_parity_d; + entry10_cmpmask_q <= entry10_cmpmask_d; + entry11_size_q <= entry11_size_d; + entry11_xbit_q <= entry11_xbit_d; + entry11_epn_q <= entry11_epn_d; + entry11_class_q <= entry11_class_d; + entry11_extclass_q <= entry11_extclass_d; + entry11_hv_q <= entry11_hv_d; + entry11_ds_q <= entry11_ds_d; + entry11_thdid_q <= entry11_thdid_d; + entry11_pid_q <= entry11_pid_d; + entry11_v_q <= entry11_v_d; + entry11_parity_q <= entry11_parity_d; + entry11_cmpmask_q <= entry11_cmpmask_d; + entry12_size_q <= entry12_size_d; + entry12_xbit_q <= entry12_xbit_d; + entry12_epn_q <= entry12_epn_d; + entry12_class_q <= entry12_class_d; + entry12_extclass_q <= entry12_extclass_d; + entry12_hv_q <= entry12_hv_d; + entry12_ds_q <= entry12_ds_d; + entry12_thdid_q <= entry12_thdid_d; + entry12_pid_q <= entry12_pid_d; + entry12_v_q <= entry12_v_d; + entry12_parity_q <= entry12_parity_d; + entry12_cmpmask_q <= entry12_cmpmask_d; + entry13_size_q <= entry13_size_d; + entry13_xbit_q <= entry13_xbit_d; + entry13_epn_q <= entry13_epn_d; + entry13_class_q <= entry13_class_d; + entry13_extclass_q <= entry13_extclass_d; + entry13_hv_q <= entry13_hv_d; + entry13_ds_q <= entry13_ds_d; + entry13_thdid_q <= entry13_thdid_d; + entry13_pid_q <= entry13_pid_d; + entry13_v_q <= entry13_v_d; + entry13_parity_q <= entry13_parity_d; + entry13_cmpmask_q <= entry13_cmpmask_d; + entry14_size_q <= entry14_size_d; + entry14_xbit_q <= entry14_xbit_d; + entry14_epn_q <= entry14_epn_d; + entry14_class_q <= entry14_class_d; + entry14_extclass_q <= entry14_extclass_d; + entry14_hv_q <= entry14_hv_d; + entry14_ds_q <= entry14_ds_d; + entry14_thdid_q <= entry14_thdid_d; + entry14_pid_q <= entry14_pid_d; + entry14_v_q <= entry14_v_d; + entry14_parity_q <= entry14_parity_d; + entry14_cmpmask_q <= entry14_cmpmask_d; + entry15_size_q <= entry15_size_d; + entry15_xbit_q <= entry15_xbit_d; + entry15_epn_q <= entry15_epn_d; + entry15_class_q <= entry15_class_d; + entry15_extclass_q <= entry15_extclass_d; + entry15_hv_q <= entry15_hv_d; + entry15_ds_q <= entry15_ds_d; + entry15_thdid_q <= entry15_thdid_d; + entry15_pid_q <= entry15_pid_d; + entry15_v_q <= entry15_v_d; + entry15_parity_q <= entry15_parity_d; + entry15_cmpmask_q <= entry15_cmpmask_d; + entry16_size_q <= entry16_size_d; + entry16_xbit_q <= entry16_xbit_d; + entry16_epn_q <= entry16_epn_d; + entry16_class_q <= entry16_class_d; + entry16_extclass_q <= entry16_extclass_d; + entry16_hv_q <= entry16_hv_d; + entry16_ds_q <= entry16_ds_d; + entry16_thdid_q <= entry16_thdid_d; + entry16_pid_q <= entry16_pid_d; + entry16_v_q <= entry16_v_d; + entry16_parity_q <= entry16_parity_d; + entry16_cmpmask_q <= entry16_cmpmask_d; + entry17_size_q <= entry17_size_d; + entry17_xbit_q <= entry17_xbit_d; + entry17_epn_q <= entry17_epn_d; + entry17_class_q <= entry17_class_d; + entry17_extclass_q <= entry17_extclass_d; + entry17_hv_q <= entry17_hv_d; + entry17_ds_q <= entry17_ds_d; + entry17_thdid_q <= entry17_thdid_d; + entry17_pid_q <= entry17_pid_d; + entry17_v_q <= entry17_v_d; + entry17_parity_q <= entry17_parity_d; + entry17_cmpmask_q <= entry17_cmpmask_d; + entry18_size_q <= entry18_size_d; + entry18_xbit_q <= entry18_xbit_d; + entry18_epn_q <= entry18_epn_d; + entry18_class_q <= entry18_class_d; + entry18_extclass_q <= entry18_extclass_d; + entry18_hv_q <= entry18_hv_d; + entry18_ds_q <= entry18_ds_d; + entry18_thdid_q <= entry18_thdid_d; + entry18_pid_q <= entry18_pid_d; + entry18_v_q <= entry18_v_d; + entry18_parity_q <= entry18_parity_d; + entry18_cmpmask_q <= entry18_cmpmask_d; + entry19_size_q <= entry19_size_d; + entry19_xbit_q <= entry19_xbit_d; + entry19_epn_q <= entry19_epn_d; + entry19_class_q <= entry19_class_d; + entry19_extclass_q <= entry19_extclass_d; + entry19_hv_q <= entry19_hv_d; + entry19_ds_q <= entry19_ds_d; + entry19_thdid_q <= entry19_thdid_d; + entry19_pid_q <= entry19_pid_d; + entry19_v_q <= entry19_v_d; + entry19_parity_q <= entry19_parity_d; + entry19_cmpmask_q <= entry19_cmpmask_d; + entry20_size_q <= entry20_size_d; + entry20_xbit_q <= entry20_xbit_d; + entry20_epn_q <= entry20_epn_d; + entry20_class_q <= entry20_class_d; + entry20_extclass_q <= entry20_extclass_d; + entry20_hv_q <= entry20_hv_d; + entry20_ds_q <= entry20_ds_d; + entry20_thdid_q <= entry20_thdid_d; + entry20_pid_q <= entry20_pid_d; + entry20_v_q <= entry20_v_d; + entry20_parity_q <= entry20_parity_d; + entry20_cmpmask_q <= entry20_cmpmask_d; + entry21_size_q <= entry21_size_d; + entry21_xbit_q <= entry21_xbit_d; + entry21_epn_q <= entry21_epn_d; + entry21_class_q <= entry21_class_d; + entry21_extclass_q <= entry21_extclass_d; + entry21_hv_q <= entry21_hv_d; + entry21_ds_q <= entry21_ds_d; + entry21_thdid_q <= entry21_thdid_d; + entry21_pid_q <= entry21_pid_d; + entry21_v_q <= entry21_v_d; + entry21_parity_q <= entry21_parity_d; + entry21_cmpmask_q <= entry21_cmpmask_d; + entry22_size_q <= entry22_size_d; + entry22_xbit_q <= entry22_xbit_d; + entry22_epn_q <= entry22_epn_d; + entry22_class_q <= entry22_class_d; + entry22_extclass_q <= entry22_extclass_d; + entry22_hv_q <= entry22_hv_d; + entry22_ds_q <= entry22_ds_d; + entry22_thdid_q <= entry22_thdid_d; + entry22_pid_q <= entry22_pid_d; + entry22_v_q <= entry22_v_d; + entry22_parity_q <= entry22_parity_d; + entry22_cmpmask_q <= entry22_cmpmask_d; + entry23_size_q <= entry23_size_d; + entry23_xbit_q <= entry23_xbit_d; + entry23_epn_q <= entry23_epn_d; + entry23_class_q <= entry23_class_d; + entry23_extclass_q <= entry23_extclass_d; + entry23_hv_q <= entry23_hv_d; + entry23_ds_q <= entry23_ds_d; + entry23_thdid_q <= entry23_thdid_d; + entry23_pid_q <= entry23_pid_d; + entry23_v_q <= entry23_v_d; + entry23_parity_q <= entry23_parity_d; + entry23_cmpmask_q <= entry23_cmpmask_d; + entry24_size_q <= entry24_size_d; + entry24_xbit_q <= entry24_xbit_d; + entry24_epn_q <= entry24_epn_d; + entry24_class_q <= entry24_class_d; + entry24_extclass_q <= entry24_extclass_d; + entry24_hv_q <= entry24_hv_d; + entry24_ds_q <= entry24_ds_d; + entry24_thdid_q <= entry24_thdid_d; + entry24_pid_q <= entry24_pid_d; + entry24_v_q <= entry24_v_d; + entry24_parity_q <= entry24_parity_d; + entry24_cmpmask_q <= entry24_cmpmask_d; + entry25_size_q <= entry25_size_d; + entry25_xbit_q <= entry25_xbit_d; + entry25_epn_q <= entry25_epn_d; + entry25_class_q <= entry25_class_d; + entry25_extclass_q <= entry25_extclass_d; + entry25_hv_q <= entry25_hv_d; + entry25_ds_q <= entry25_ds_d; + entry25_thdid_q <= entry25_thdid_d; + entry25_pid_q <= entry25_pid_d; + entry25_v_q <= entry25_v_d; + entry25_parity_q <= entry25_parity_d; + entry25_cmpmask_q <= entry25_cmpmask_d; + entry26_size_q <= entry26_size_d; + entry26_xbit_q <= entry26_xbit_d; + entry26_epn_q <= entry26_epn_d; + entry26_class_q <= entry26_class_d; + entry26_extclass_q <= entry26_extclass_d; + entry26_hv_q <= entry26_hv_d; + entry26_ds_q <= entry26_ds_d; + entry26_thdid_q <= entry26_thdid_d; + entry26_pid_q <= entry26_pid_d; + entry26_v_q <= entry26_v_d; + entry26_parity_q <= entry26_parity_d; + entry26_cmpmask_q <= entry26_cmpmask_d; + entry27_size_q <= entry27_size_d; + entry27_xbit_q <= entry27_xbit_d; + entry27_epn_q <= entry27_epn_d; + entry27_class_q <= entry27_class_d; + entry27_extclass_q <= entry27_extclass_d; + entry27_hv_q <= entry27_hv_d; + entry27_ds_q <= entry27_ds_d; + entry27_thdid_q <= entry27_thdid_d; + entry27_pid_q <= entry27_pid_d; + entry27_v_q <= entry27_v_d; + entry27_parity_q <= entry27_parity_d; + entry27_cmpmask_q <= entry27_cmpmask_d; + entry28_size_q <= entry28_size_d; + entry28_xbit_q <= entry28_xbit_d; + entry28_epn_q <= entry28_epn_d; + entry28_class_q <= entry28_class_d; + entry28_extclass_q <= entry28_extclass_d; + entry28_hv_q <= entry28_hv_d; + entry28_ds_q <= entry28_ds_d; + entry28_thdid_q <= entry28_thdid_d; + entry28_pid_q <= entry28_pid_d; + entry28_v_q <= entry28_v_d; + entry28_parity_q <= entry28_parity_d; + entry28_cmpmask_q <= entry28_cmpmask_d; + entry29_size_q <= entry29_size_d; + entry29_xbit_q <= entry29_xbit_d; + entry29_epn_q <= entry29_epn_d; + entry29_class_q <= entry29_class_d; + entry29_extclass_q <= entry29_extclass_d; + entry29_hv_q <= entry29_hv_d; + entry29_ds_q <= entry29_ds_d; + entry29_thdid_q <= entry29_thdid_d; + entry29_pid_q <= entry29_pid_d; + entry29_v_q <= entry29_v_d; + entry29_parity_q <= entry29_parity_d; + entry29_cmpmask_q <= entry29_cmpmask_d; + entry30_size_q <= entry30_size_d; + entry30_xbit_q <= entry30_xbit_d; + entry30_epn_q <= entry30_epn_d; + entry30_class_q <= entry30_class_d; + entry30_extclass_q <= entry30_extclass_d; + entry30_hv_q <= entry30_hv_d; + entry30_ds_q <= entry30_ds_d; + entry30_thdid_q <= entry30_thdid_d; + entry30_pid_q <= entry30_pid_d; + entry30_v_q <= entry30_v_d; + entry30_parity_q <= entry30_parity_d; + entry30_cmpmask_q <= entry30_cmpmask_d; + entry31_size_q <= entry31_size_d; + entry31_xbit_q <= entry31_xbit_d; + entry31_epn_q <= entry31_epn_d; + entry31_class_q <= entry31_class_d; + entry31_extclass_q <= entry31_extclass_d; + entry31_hv_q <= entry31_hv_d; + entry31_ds_q <= entry31_ds_d; + entry31_thdid_q <= entry31_thdid_d; + entry31_pid_q <= entry31_pid_d; + entry31_v_q <= entry31_v_d; + entry31_parity_q <= entry31_parity_d; + entry31_cmpmask_q <= entry31_cmpmask_d; + end + end + + //--------------------------------------------------------------------- + // latch input logic + //--------------------------------------------------------------------- + assign comp_addr_np1_d = comp_addr[52 - RPN_WIDTH:51]; + + assign cam_hit_d = ((match_vec != 32'b00000000000000000000000000000000) & (comp_request == 1'b1)) ? 1'b1 : + 1'b0; + + assign cam_hit_entry_d = (match_vec[0:1] == 2'b01) ? 5'b00001 : + (match_vec[0:2] == 3'b001) ? 5'b00010 : + (match_vec[0:3] == 4'b0001) ? 5'b00011 : + (match_vec[0:4] == 5'b00001) ? 5'b00100 : + (match_vec[0:5] == 6'b000001) ? 5'b00101 : + (match_vec[0:6] == 7'b0000001) ? 5'b00110 : + (match_vec[0:7] == 8'b00000001) ? 5'b00111 : + (match_vec[0:8] == 9'b000000001) ? 5'b01000 : + (match_vec[0:9] == 10'b0000000001) ? 5'b01001 : + (match_vec[0:10] == 11'b00000000001) ? 5'b01010 : + (match_vec[0:11] == 12'b000000000001) ? 5'b01011 : + (match_vec[0:12] == 13'b0000000000001) ? 5'b01100 : + (match_vec[0:13] == 14'b00000000000001) ? 5'b01101 : + (match_vec[0:14] == 15'b000000000000001) ? 5'b01110 : + (match_vec[0:15] == 16'b0000000000000001) ? 5'b01111 : + (match_vec[0:16] == 17'b00000000000000001) ? 5'b10000 : + (match_vec[0:17] == 18'b000000000000000001) ? 5'b10001 : + (match_vec[0:18] == 19'b0000000000000000001) ? 5'b10010 : + (match_vec[0:19] == 20'b00000000000000000001) ? 5'b10011 : + (match_vec[0:20] == 21'b000000000000000000001) ? 5'b10100 : + (match_vec[0:21] == 22'b0000000000000000000001) ? 5'b10101 : + (match_vec[0:22] == 23'b00000000000000000000001) ? 5'b10110 : + (match_vec[0:23] == 24'b000000000000000000000001) ? 5'b10111 : + (match_vec[0:24] == 25'b0000000000000000000000001) ? 5'b11000 : + (match_vec[0:25] == 26'b00000000000000000000000001) ? 5'b11001 : + (match_vec[0:26] == 27'b000000000000000000000000001) ? 5'b11010 : + (match_vec[0:27] == 28'b0000000000000000000000000001) ? 5'b11011 : + (match_vec[0:28] == 29'b00000000000000000000000000001) ? 5'b11100 : + (match_vec[0:29] == 30'b000000000000000000000000000001) ? 5'b11101 : + (match_vec[0:30] == 31'b0000000000000000000000000000001) ? 5'b11110 : + (match_vec[0:31] == 32'b00000000000000000000000000000001) ? 5'b11111 : + 5'b00000; + + assign entry_match_d = ((comp_request == 1'b1)) ? match_vec : + {NUM_ENTRY{1'b0}}; + + // entry write next state logic + assign wr_entry0_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00000)) ? 1'b1 : + 1'b0; + assign wr_entry0_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00000)) ? 1'b1 : + 1'b0; + assign entry0_epn_d[0:31] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry0_epn_q[0:31]; + assign entry0_epn_d[32:51] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry0_epn_q[32:51]; + assign entry0_xbit_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[52] : + entry0_xbit_q; + assign entry0_size_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry0_size_q[0:2]; + assign entry0_class_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry0_class_q[0:1]; + assign entry0_extclass_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry0_extclass_q[0:1]; + assign entry0_hv_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[65] : + entry0_hv_q; + assign entry0_ds_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[66] : + entry0_ds_q; + assign entry0_pid_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry0_pid_q[0:7]; + assign entry0_cmpmask_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry0_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry0_parity_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry0_parity_q[0:3]; + assign entry0_parity_d[4:6] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry0_parity_q[4:6]; + assign entry0_parity_d[7] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry0_parity_q[7]; + assign entry0_parity_d[8] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry0_parity_q[8]; + assign entry0_parity_d[9] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry0_parity_q[9]; + assign wr_entry1_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00001)) ? 1'b1 : + 1'b0; + assign wr_entry1_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00001)) ? 1'b1 : + 1'b0; + assign entry1_epn_d[0:31] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry1_epn_q[0:31]; + assign entry1_epn_d[32:51] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry1_epn_q[32:51]; + assign entry1_xbit_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[52] : + entry1_xbit_q; + assign entry1_size_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry1_size_q[0:2]; + assign entry1_class_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry1_class_q[0:1]; + assign entry1_extclass_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry1_extclass_q[0:1]; + assign entry1_hv_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[65] : + entry1_hv_q; + assign entry1_ds_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[66] : + entry1_ds_q; + assign entry1_pid_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry1_pid_q[0:7]; + assign entry1_cmpmask_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry1_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry1_parity_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry1_parity_q[0:3]; + assign entry1_parity_d[4:6] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry1_parity_q[4:6]; + assign entry1_parity_d[7] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry1_parity_q[7]; + assign entry1_parity_d[8] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry1_parity_q[8]; + assign entry1_parity_d[9] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry1_parity_q[9]; + assign wr_entry2_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00010)) ? 1'b1 : + 1'b0; + assign wr_entry2_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00010)) ? 1'b1 : + 1'b0; + assign entry2_epn_d[0:31] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry2_epn_q[0:31]; + assign entry2_epn_d[32:51] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry2_epn_q[32:51]; + assign entry2_xbit_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[52] : + entry2_xbit_q; + assign entry2_size_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry2_size_q[0:2]; + assign entry2_class_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry2_class_q[0:1]; + assign entry2_extclass_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry2_extclass_q[0:1]; + assign entry2_hv_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[65] : + entry2_hv_q; + assign entry2_ds_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[66] : + entry2_ds_q; + assign entry2_pid_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry2_pid_q[0:7]; + assign entry2_cmpmask_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry2_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry2_parity_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry2_parity_q[0:3]; + assign entry2_parity_d[4:6] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry2_parity_q[4:6]; + assign entry2_parity_d[7] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry2_parity_q[7]; + assign entry2_parity_d[8] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry2_parity_q[8]; + assign entry2_parity_d[9] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry2_parity_q[9]; + assign wr_entry3_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00011)) ? 1'b1 : + 1'b0; + assign wr_entry3_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00011)) ? 1'b1 : + 1'b0; + assign entry3_epn_d[0:31] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry3_epn_q[0:31]; + assign entry3_epn_d[32:51] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry3_epn_q[32:51]; + assign entry3_xbit_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[52] : + entry3_xbit_q; + assign entry3_size_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry3_size_q[0:2]; + assign entry3_class_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry3_class_q[0:1]; + assign entry3_extclass_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry3_extclass_q[0:1]; + assign entry3_hv_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[65] : + entry3_hv_q; + assign entry3_ds_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[66] : + entry3_ds_q; + assign entry3_pid_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry3_pid_q[0:7]; + assign entry3_cmpmask_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry3_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry3_parity_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry3_parity_q[0:3]; + assign entry3_parity_d[4:6] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry3_parity_q[4:6]; + assign entry3_parity_d[7] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry3_parity_q[7]; + assign entry3_parity_d[8] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry3_parity_q[8]; + assign entry3_parity_d[9] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry3_parity_q[9]; + assign wr_entry4_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00100)) ? 1'b1 : + 1'b0; + assign wr_entry4_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00100)) ? 1'b1 : + 1'b0; + assign entry4_epn_d[0:31] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry4_epn_q[0:31]; + assign entry4_epn_d[32:51] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry4_epn_q[32:51]; + assign entry4_xbit_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[52] : + entry4_xbit_q; + assign entry4_size_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry4_size_q[0:2]; + assign entry4_class_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry4_class_q[0:1]; + assign entry4_extclass_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry4_extclass_q[0:1]; + assign entry4_hv_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[65] : + entry4_hv_q; + assign entry4_ds_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[66] : + entry4_ds_q; + assign entry4_pid_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry4_pid_q[0:7]; + assign entry4_cmpmask_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry4_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry4_parity_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry4_parity_q[0:3]; + assign entry4_parity_d[4:6] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry4_parity_q[4:6]; + assign entry4_parity_d[7] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry4_parity_q[7]; + assign entry4_parity_d[8] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry4_parity_q[8]; + assign entry4_parity_d[9] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry4_parity_q[9]; + assign wr_entry5_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00101)) ? 1'b1 : + 1'b0; + assign wr_entry5_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00101)) ? 1'b1 : + 1'b0; + assign entry5_epn_d[0:31] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry5_epn_q[0:31]; + assign entry5_epn_d[32:51] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry5_epn_q[32:51]; + assign entry5_xbit_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[52] : + entry5_xbit_q; + assign entry5_size_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry5_size_q[0:2]; + assign entry5_class_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry5_class_q[0:1]; + assign entry5_extclass_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry5_extclass_q[0:1]; + assign entry5_hv_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[65] : + entry5_hv_q; + assign entry5_ds_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[66] : + entry5_ds_q; + assign entry5_pid_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry5_pid_q[0:7]; + assign entry5_cmpmask_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry5_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry5_parity_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry5_parity_q[0:3]; + assign entry5_parity_d[4:6] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry5_parity_q[4:6]; + assign entry5_parity_d[7] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry5_parity_q[7]; + assign entry5_parity_d[8] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry5_parity_q[8]; + assign entry5_parity_d[9] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry5_parity_q[9]; + assign wr_entry6_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00110)) ? 1'b1 : + 1'b0; + assign wr_entry6_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00110)) ? 1'b1 : + 1'b0; + assign entry6_epn_d[0:31] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry6_epn_q[0:31]; + assign entry6_epn_d[32:51] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry6_epn_q[32:51]; + assign entry6_xbit_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[52] : + entry6_xbit_q; + assign entry6_size_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry6_size_q[0:2]; + assign entry6_class_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry6_class_q[0:1]; + assign entry6_extclass_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry6_extclass_q[0:1]; + assign entry6_hv_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[65] : + entry6_hv_q; + assign entry6_ds_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[66] : + entry6_ds_q; + assign entry6_pid_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry6_pid_q[0:7]; + assign entry6_cmpmask_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry6_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry6_parity_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry6_parity_q[0:3]; + assign entry6_parity_d[4:6] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry6_parity_q[4:6]; + assign entry6_parity_d[7] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry6_parity_q[7]; + assign entry6_parity_d[8] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry6_parity_q[8]; + assign entry6_parity_d[9] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry6_parity_q[9]; + assign wr_entry7_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00111)) ? 1'b1 : + 1'b0; + assign wr_entry7_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00111)) ? 1'b1 : + 1'b0; + assign entry7_epn_d[0:31] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry7_epn_q[0:31]; + assign entry7_epn_d[32:51] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry7_epn_q[32:51]; + assign entry7_xbit_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[52] : + entry7_xbit_q; + assign entry7_size_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry7_size_q[0:2]; + assign entry7_class_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry7_class_q[0:1]; + assign entry7_extclass_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry7_extclass_q[0:1]; + assign entry7_hv_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[65] : + entry7_hv_q; + assign entry7_ds_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[66] : + entry7_ds_q; + assign entry7_pid_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry7_pid_q[0:7]; + assign entry7_cmpmask_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry7_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry7_parity_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry7_parity_q[0:3]; + assign entry7_parity_d[4:6] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry7_parity_q[4:6]; + assign entry7_parity_d[7] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry7_parity_q[7]; + assign entry7_parity_d[8] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry7_parity_q[8]; + assign entry7_parity_d[9] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry7_parity_q[9]; + assign wr_entry8_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01000)) ? 1'b1 : + 1'b0; + assign wr_entry8_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01000)) ? 1'b1 : + 1'b0; + assign entry8_epn_d[0:31] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry8_epn_q[0:31]; + assign entry8_epn_d[32:51] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry8_epn_q[32:51]; + assign entry8_xbit_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[52] : + entry8_xbit_q; + assign entry8_size_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry8_size_q[0:2]; + assign entry8_class_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry8_class_q[0:1]; + assign entry8_extclass_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry8_extclass_q[0:1]; + assign entry8_hv_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[65] : + entry8_hv_q; + assign entry8_ds_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[66] : + entry8_ds_q; + assign entry8_pid_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry8_pid_q[0:7]; + assign entry8_cmpmask_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry8_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry8_parity_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry8_parity_q[0:3]; + assign entry8_parity_d[4:6] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry8_parity_q[4:6]; + assign entry8_parity_d[7] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry8_parity_q[7]; + assign entry8_parity_d[8] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry8_parity_q[8]; + assign entry8_parity_d[9] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry8_parity_q[9]; + assign wr_entry9_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01001)) ? 1'b1 : + 1'b0; + assign wr_entry9_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01001)) ? 1'b1 : + 1'b0; + assign entry9_epn_d[0:31] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry9_epn_q[0:31]; + assign entry9_epn_d[32:51] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry9_epn_q[32:51]; + assign entry9_xbit_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[52] : + entry9_xbit_q; + assign entry9_size_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry9_size_q[0:2]; + assign entry9_class_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry9_class_q[0:1]; + assign entry9_extclass_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry9_extclass_q[0:1]; + assign entry9_hv_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[65] : + entry9_hv_q; + assign entry9_ds_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[66] : + entry9_ds_q; + assign entry9_pid_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry9_pid_q[0:7]; + assign entry9_cmpmask_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry9_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry9_parity_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry9_parity_q[0:3]; + assign entry9_parity_d[4:6] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry9_parity_q[4:6]; + assign entry9_parity_d[7] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry9_parity_q[7]; + assign entry9_parity_d[8] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry9_parity_q[8]; + assign entry9_parity_d[9] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry9_parity_q[9]; + assign wr_entry10_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01010)) ? 1'b1 : + 1'b0; + assign wr_entry10_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01010)) ? 1'b1 : + 1'b0; + assign entry10_epn_d[0:31] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry10_epn_q[0:31]; + assign entry10_epn_d[32:51] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry10_epn_q[32:51]; + assign entry10_xbit_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[52] : + entry10_xbit_q; + assign entry10_size_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry10_size_q[0:2]; + assign entry10_class_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry10_class_q[0:1]; + assign entry10_extclass_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry10_extclass_q[0:1]; + assign entry10_hv_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[65] : + entry10_hv_q; + assign entry10_ds_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[66] : + entry10_ds_q; + assign entry10_pid_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry10_pid_q[0:7]; + assign entry10_cmpmask_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry10_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry10_parity_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry10_parity_q[0:3]; + assign entry10_parity_d[4:6] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry10_parity_q[4:6]; + assign entry10_parity_d[7] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry10_parity_q[7]; + assign entry10_parity_d[8] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry10_parity_q[8]; + assign entry10_parity_d[9] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry10_parity_q[9]; + assign wr_entry11_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01011)) ? 1'b1 : + 1'b0; + assign wr_entry11_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01011)) ? 1'b1 : + 1'b0; + assign entry11_epn_d[0:31] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry11_epn_q[0:31]; + assign entry11_epn_d[32:51] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry11_epn_q[32:51]; + assign entry11_xbit_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[52] : + entry11_xbit_q; + assign entry11_size_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry11_size_q[0:2]; + assign entry11_class_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry11_class_q[0:1]; + assign entry11_extclass_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry11_extclass_q[0:1]; + assign entry11_hv_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[65] : + entry11_hv_q; + assign entry11_ds_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[66] : + entry11_ds_q; + assign entry11_pid_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry11_pid_q[0:7]; + assign entry11_cmpmask_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry11_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry11_parity_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry11_parity_q[0:3]; + assign entry11_parity_d[4:6] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry11_parity_q[4:6]; + assign entry11_parity_d[7] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry11_parity_q[7]; + assign entry11_parity_d[8] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry11_parity_q[8]; + assign entry11_parity_d[9] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry11_parity_q[9]; + assign wr_entry12_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01100)) ? 1'b1 : + 1'b0; + assign wr_entry12_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01100)) ? 1'b1 : + 1'b0; + assign entry12_epn_d[0:31] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry12_epn_q[0:31]; + assign entry12_epn_d[32:51] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry12_epn_q[32:51]; + assign entry12_xbit_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[52] : + entry12_xbit_q; + assign entry12_size_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry12_size_q[0:2]; + assign entry12_class_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry12_class_q[0:1]; + assign entry12_extclass_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry12_extclass_q[0:1]; + assign entry12_hv_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[65] : + entry12_hv_q; + assign entry12_ds_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[66] : + entry12_ds_q; + assign entry12_pid_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry12_pid_q[0:7]; + assign entry12_cmpmask_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry12_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry12_parity_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry12_parity_q[0:3]; + assign entry12_parity_d[4:6] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry12_parity_q[4:6]; + assign entry12_parity_d[7] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry12_parity_q[7]; + assign entry12_parity_d[8] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry12_parity_q[8]; + assign entry12_parity_d[9] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry12_parity_q[9]; + assign wr_entry13_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01101)) ? 1'b1 : + 1'b0; + assign wr_entry13_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01101)) ? 1'b1 : + 1'b0; + assign entry13_epn_d[0:31] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry13_epn_q[0:31]; + assign entry13_epn_d[32:51] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry13_epn_q[32:51]; + assign entry13_xbit_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[52] : + entry13_xbit_q; + assign entry13_size_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry13_size_q[0:2]; + assign entry13_class_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry13_class_q[0:1]; + assign entry13_extclass_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry13_extclass_q[0:1]; + assign entry13_hv_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[65] : + entry13_hv_q; + assign entry13_ds_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[66] : + entry13_ds_q; + assign entry13_pid_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry13_pid_q[0:7]; + assign entry13_cmpmask_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry13_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry13_parity_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry13_parity_q[0:3]; + assign entry13_parity_d[4:6] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry13_parity_q[4:6]; + assign entry13_parity_d[7] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry13_parity_q[7]; + assign entry13_parity_d[8] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry13_parity_q[8]; + assign entry13_parity_d[9] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry13_parity_q[9]; + assign wr_entry14_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01110)) ? 1'b1 : + 1'b0; + assign wr_entry14_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01110)) ? 1'b1 : + 1'b0; + assign entry14_epn_d[0:31] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry14_epn_q[0:31]; + assign entry14_epn_d[32:51] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry14_epn_q[32:51]; + assign entry14_xbit_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[52] : + entry14_xbit_q; + assign entry14_size_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry14_size_q[0:2]; + assign entry14_class_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry14_class_q[0:1]; + assign entry14_extclass_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry14_extclass_q[0:1]; + assign entry14_hv_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[65] : + entry14_hv_q; + assign entry14_ds_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[66] : + entry14_ds_q; + assign entry14_pid_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry14_pid_q[0:7]; + assign entry14_cmpmask_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry14_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry14_parity_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry14_parity_q[0:3]; + assign entry14_parity_d[4:6] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry14_parity_q[4:6]; + assign entry14_parity_d[7] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry14_parity_q[7]; + assign entry14_parity_d[8] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry14_parity_q[8]; + assign entry14_parity_d[9] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry14_parity_q[9]; + assign wr_entry15_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01111)) ? 1'b1 : + 1'b0; + assign wr_entry15_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01111)) ? 1'b1 : + 1'b0; + assign entry15_epn_d[0:31] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry15_epn_q[0:31]; + assign entry15_epn_d[32:51] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry15_epn_q[32:51]; + assign entry15_xbit_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[52] : + entry15_xbit_q; + assign entry15_size_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry15_size_q[0:2]; + assign entry15_class_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry15_class_q[0:1]; + assign entry15_extclass_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry15_extclass_q[0:1]; + assign entry15_hv_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[65] : + entry15_hv_q; + assign entry15_ds_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[66] : + entry15_ds_q; + assign entry15_pid_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry15_pid_q[0:7]; + assign entry15_cmpmask_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry15_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry15_parity_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry15_parity_q[0:3]; + assign entry15_parity_d[4:6] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry15_parity_q[4:6]; + assign entry15_parity_d[7] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry15_parity_q[7]; + assign entry15_parity_d[8] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry15_parity_q[8]; + assign entry15_parity_d[9] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry15_parity_q[9]; + assign wr_entry16_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10000)) ? 1'b1 : + 1'b0; + assign wr_entry16_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10000)) ? 1'b1 : + 1'b0; + assign entry16_epn_d[0:31] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry16_epn_q[0:31]; + assign entry16_epn_d[32:51] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry16_epn_q[32:51]; + assign entry16_xbit_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[52] : + entry16_xbit_q; + assign entry16_size_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry16_size_q[0:2]; + assign entry16_class_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry16_class_q[0:1]; + assign entry16_extclass_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry16_extclass_q[0:1]; + assign entry16_hv_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[65] : + entry16_hv_q; + assign entry16_ds_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[66] : + entry16_ds_q; + assign entry16_pid_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry16_pid_q[0:7]; + assign entry16_cmpmask_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry16_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry16_parity_d[0:3] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry16_parity_q[0:3]; + assign entry16_parity_d[4:6] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry16_parity_q[4:6]; + assign entry16_parity_d[7] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry16_parity_q[7]; + assign entry16_parity_d[8] = (wr_entry16_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry16_parity_q[8]; + assign entry16_parity_d[9] = (wr_entry16_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry16_parity_q[9]; + assign wr_entry17_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10001)) ? 1'b1 : + 1'b0; + assign wr_entry17_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10001)) ? 1'b1 : + 1'b0; + assign entry17_epn_d[0:31] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry17_epn_q[0:31]; + assign entry17_epn_d[32:51] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry17_epn_q[32:51]; + assign entry17_xbit_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[52] : + entry17_xbit_q; + assign entry17_size_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry17_size_q[0:2]; + assign entry17_class_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry17_class_q[0:1]; + assign entry17_extclass_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry17_extclass_q[0:1]; + assign entry17_hv_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[65] : + entry17_hv_q; + assign entry17_ds_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[66] : + entry17_ds_q; + assign entry17_pid_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry17_pid_q[0:7]; + assign entry17_cmpmask_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry17_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry17_parity_d[0:3] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry17_parity_q[0:3]; + assign entry17_parity_d[4:6] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry17_parity_q[4:6]; + assign entry17_parity_d[7] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry17_parity_q[7]; + assign entry17_parity_d[8] = (wr_entry17_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry17_parity_q[8]; + assign entry17_parity_d[9] = (wr_entry17_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry17_parity_q[9]; + assign wr_entry18_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10010)) ? 1'b1 : + 1'b0; + assign wr_entry18_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10010)) ? 1'b1 : + 1'b0; + assign entry18_epn_d[0:31] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry18_epn_q[0:31]; + assign entry18_epn_d[32:51] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry18_epn_q[32:51]; + assign entry18_xbit_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[52] : + entry18_xbit_q; + assign entry18_size_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry18_size_q[0:2]; + assign entry18_class_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry18_class_q[0:1]; + assign entry18_extclass_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry18_extclass_q[0:1]; + assign entry18_hv_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[65] : + entry18_hv_q; + assign entry18_ds_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[66] : + entry18_ds_q; + assign entry18_pid_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry18_pid_q[0:7]; + assign entry18_cmpmask_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry18_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry18_parity_d[0:3] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry18_parity_q[0:3]; + assign entry18_parity_d[4:6] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry18_parity_q[4:6]; + assign entry18_parity_d[7] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry18_parity_q[7]; + assign entry18_parity_d[8] = (wr_entry18_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry18_parity_q[8]; + assign entry18_parity_d[9] = (wr_entry18_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry18_parity_q[9]; + assign wr_entry19_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10011)) ? 1'b1 : + 1'b0; + assign wr_entry19_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10011)) ? 1'b1 : + 1'b0; + assign entry19_epn_d[0:31] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry19_epn_q[0:31]; + assign entry19_epn_d[32:51] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry19_epn_q[32:51]; + assign entry19_xbit_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[52] : + entry19_xbit_q; + assign entry19_size_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry19_size_q[0:2]; + assign entry19_class_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry19_class_q[0:1]; + assign entry19_extclass_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry19_extclass_q[0:1]; + assign entry19_hv_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[65] : + entry19_hv_q; + assign entry19_ds_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[66] : + entry19_ds_q; + assign entry19_pid_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry19_pid_q[0:7]; + assign entry19_cmpmask_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry19_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry19_parity_d[0:3] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry19_parity_q[0:3]; + assign entry19_parity_d[4:6] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry19_parity_q[4:6]; + assign entry19_parity_d[7] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry19_parity_q[7]; + assign entry19_parity_d[8] = (wr_entry19_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry19_parity_q[8]; + assign entry19_parity_d[9] = (wr_entry19_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry19_parity_q[9]; + assign wr_entry20_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10100)) ? 1'b1 : + 1'b0; + assign wr_entry20_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10100)) ? 1'b1 : + 1'b0; + assign entry20_epn_d[0:31] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry20_epn_q[0:31]; + assign entry20_epn_d[32:51] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry20_epn_q[32:51]; + assign entry20_xbit_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[52] : + entry20_xbit_q; + assign entry20_size_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry20_size_q[0:2]; + assign entry20_class_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry20_class_q[0:1]; + assign entry20_extclass_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry20_extclass_q[0:1]; + assign entry20_hv_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[65] : + entry20_hv_q; + assign entry20_ds_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[66] : + entry20_ds_q; + assign entry20_pid_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry20_pid_q[0:7]; + assign entry20_cmpmask_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry20_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry20_parity_d[0:3] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry20_parity_q[0:3]; + assign entry20_parity_d[4:6] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry20_parity_q[4:6]; + assign entry20_parity_d[7] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry20_parity_q[7]; + assign entry20_parity_d[8] = (wr_entry20_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry20_parity_q[8]; + assign entry20_parity_d[9] = (wr_entry20_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry20_parity_q[9]; + assign wr_entry21_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10101)) ? 1'b1 : + 1'b0; + assign wr_entry21_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10101)) ? 1'b1 : + 1'b0; + assign entry21_epn_d[0:31] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry21_epn_q[0:31]; + assign entry21_epn_d[32:51] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry21_epn_q[32:51]; + assign entry21_xbit_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[52] : + entry21_xbit_q; + assign entry21_size_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry21_size_q[0:2]; + assign entry21_class_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry21_class_q[0:1]; + assign entry21_extclass_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry21_extclass_q[0:1]; + assign entry21_hv_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[65] : + entry21_hv_q; + assign entry21_ds_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[66] : + entry21_ds_q; + assign entry21_pid_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry21_pid_q[0:7]; + assign entry21_cmpmask_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry21_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry21_parity_d[0:3] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry21_parity_q[0:3]; + assign entry21_parity_d[4:6] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry21_parity_q[4:6]; + assign entry21_parity_d[7] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry21_parity_q[7]; + assign entry21_parity_d[8] = (wr_entry21_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry21_parity_q[8]; + assign entry21_parity_d[9] = (wr_entry21_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry21_parity_q[9]; + assign wr_entry22_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10110)) ? 1'b1 : + 1'b0; + assign wr_entry22_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10110)) ? 1'b1 : + 1'b0; + assign entry22_epn_d[0:31] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry22_epn_q[0:31]; + assign entry22_epn_d[32:51] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry22_epn_q[32:51]; + assign entry22_xbit_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[52] : + entry22_xbit_q; + assign entry22_size_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry22_size_q[0:2]; + assign entry22_class_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry22_class_q[0:1]; + assign entry22_extclass_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry22_extclass_q[0:1]; + assign entry22_hv_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[65] : + entry22_hv_q; + assign entry22_ds_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[66] : + entry22_ds_q; + assign entry22_pid_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry22_pid_q[0:7]; + assign entry22_cmpmask_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry22_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry22_parity_d[0:3] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry22_parity_q[0:3]; + assign entry22_parity_d[4:6] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry22_parity_q[4:6]; + assign entry22_parity_d[7] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry22_parity_q[7]; + assign entry22_parity_d[8] = (wr_entry22_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry22_parity_q[8]; + assign entry22_parity_d[9] = (wr_entry22_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry22_parity_q[9]; + assign wr_entry23_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10111)) ? 1'b1 : + 1'b0; + assign wr_entry23_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10111)) ? 1'b1 : + 1'b0; + assign entry23_epn_d[0:31] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry23_epn_q[0:31]; + assign entry23_epn_d[32:51] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry23_epn_q[32:51]; + assign entry23_xbit_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[52] : + entry23_xbit_q; + assign entry23_size_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry23_size_q[0:2]; + assign entry23_class_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry23_class_q[0:1]; + assign entry23_extclass_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry23_extclass_q[0:1]; + assign entry23_hv_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[65] : + entry23_hv_q; + assign entry23_ds_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[66] : + entry23_ds_q; + assign entry23_pid_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry23_pid_q[0:7]; + assign entry23_cmpmask_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry23_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry23_parity_d[0:3] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry23_parity_q[0:3]; + assign entry23_parity_d[4:6] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry23_parity_q[4:6]; + assign entry23_parity_d[7] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry23_parity_q[7]; + assign entry23_parity_d[8] = (wr_entry23_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry23_parity_q[8]; + assign entry23_parity_d[9] = (wr_entry23_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry23_parity_q[9]; + assign wr_entry24_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11000)) ? 1'b1 : + 1'b0; + assign wr_entry24_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11000)) ? 1'b1 : + 1'b0; + assign entry24_epn_d[0:31] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry24_epn_q[0:31]; + assign entry24_epn_d[32:51] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry24_epn_q[32:51]; + assign entry24_xbit_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[52] : + entry24_xbit_q; + assign entry24_size_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry24_size_q[0:2]; + assign entry24_class_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry24_class_q[0:1]; + assign entry24_extclass_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry24_extclass_q[0:1]; + assign entry24_hv_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[65] : + entry24_hv_q; + assign entry24_ds_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[66] : + entry24_ds_q; + assign entry24_pid_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry24_pid_q[0:7]; + assign entry24_cmpmask_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry24_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry24_parity_d[0:3] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry24_parity_q[0:3]; + assign entry24_parity_d[4:6] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry24_parity_q[4:6]; + assign entry24_parity_d[7] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry24_parity_q[7]; + assign entry24_parity_d[8] = (wr_entry24_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry24_parity_q[8]; + assign entry24_parity_d[9] = (wr_entry24_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry24_parity_q[9]; + assign wr_entry25_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11001)) ? 1'b1 : + 1'b0; + assign wr_entry25_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11001)) ? 1'b1 : + 1'b0; + assign entry25_epn_d[0:31] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry25_epn_q[0:31]; + assign entry25_epn_d[32:51] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry25_epn_q[32:51]; + assign entry25_xbit_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[52] : + entry25_xbit_q; + assign entry25_size_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry25_size_q[0:2]; + assign entry25_class_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry25_class_q[0:1]; + assign entry25_extclass_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry25_extclass_q[0:1]; + assign entry25_hv_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[65] : + entry25_hv_q; + assign entry25_ds_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[66] : + entry25_ds_q; + assign entry25_pid_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry25_pid_q[0:7]; + assign entry25_cmpmask_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry25_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry25_parity_d[0:3] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry25_parity_q[0:3]; + assign entry25_parity_d[4:6] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry25_parity_q[4:6]; + assign entry25_parity_d[7] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry25_parity_q[7]; + assign entry25_parity_d[8] = (wr_entry25_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry25_parity_q[8]; + assign entry25_parity_d[9] = (wr_entry25_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry25_parity_q[9]; + assign wr_entry26_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11010)) ? 1'b1 : + 1'b0; + assign wr_entry26_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11010)) ? 1'b1 : + 1'b0; + assign entry26_epn_d[0:31] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry26_epn_q[0:31]; + assign entry26_epn_d[32:51] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry26_epn_q[32:51]; + assign entry26_xbit_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[52] : + entry26_xbit_q; + assign entry26_size_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry26_size_q[0:2]; + assign entry26_class_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry26_class_q[0:1]; + assign entry26_extclass_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry26_extclass_q[0:1]; + assign entry26_hv_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[65] : + entry26_hv_q; + assign entry26_ds_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[66] : + entry26_ds_q; + assign entry26_pid_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry26_pid_q[0:7]; + assign entry26_cmpmask_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry26_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry26_parity_d[0:3] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry26_parity_q[0:3]; + assign entry26_parity_d[4:6] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry26_parity_q[4:6]; + assign entry26_parity_d[7] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry26_parity_q[7]; + assign entry26_parity_d[8] = (wr_entry26_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry26_parity_q[8]; + assign entry26_parity_d[9] = (wr_entry26_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry26_parity_q[9]; + assign wr_entry27_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11011)) ? 1'b1 : + 1'b0; + assign wr_entry27_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11011)) ? 1'b1 : + 1'b0; + assign entry27_epn_d[0:31] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry27_epn_q[0:31]; + assign entry27_epn_d[32:51] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry27_epn_q[32:51]; + assign entry27_xbit_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[52] : + entry27_xbit_q; + assign entry27_size_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry27_size_q[0:2]; + assign entry27_class_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry27_class_q[0:1]; + assign entry27_extclass_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry27_extclass_q[0:1]; + assign entry27_hv_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[65] : + entry27_hv_q; + assign entry27_ds_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[66] : + entry27_ds_q; + assign entry27_pid_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry27_pid_q[0:7]; + assign entry27_cmpmask_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry27_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry27_parity_d[0:3] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry27_parity_q[0:3]; + assign entry27_parity_d[4:6] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry27_parity_q[4:6]; + assign entry27_parity_d[7] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry27_parity_q[7]; + assign entry27_parity_d[8] = (wr_entry27_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry27_parity_q[8]; + assign entry27_parity_d[9] = (wr_entry27_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry27_parity_q[9]; + assign wr_entry28_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11100)) ? 1'b1 : + 1'b0; + assign wr_entry28_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11100)) ? 1'b1 : + 1'b0; + assign entry28_epn_d[0:31] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry28_epn_q[0:31]; + assign entry28_epn_d[32:51] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry28_epn_q[32:51]; + assign entry28_xbit_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[52] : + entry28_xbit_q; + assign entry28_size_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry28_size_q[0:2]; + assign entry28_class_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry28_class_q[0:1]; + assign entry28_extclass_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry28_extclass_q[0:1]; + assign entry28_hv_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[65] : + entry28_hv_q; + assign entry28_ds_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[66] : + entry28_ds_q; + assign entry28_pid_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry28_pid_q[0:7]; + assign entry28_cmpmask_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry28_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry28_parity_d[0:3] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry28_parity_q[0:3]; + assign entry28_parity_d[4:6] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry28_parity_q[4:6]; + assign entry28_parity_d[7] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry28_parity_q[7]; + assign entry28_parity_d[8] = (wr_entry28_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry28_parity_q[8]; + assign entry28_parity_d[9] = (wr_entry28_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry28_parity_q[9]; + assign wr_entry29_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11101)) ? 1'b1 : + 1'b0; + assign wr_entry29_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11101)) ? 1'b1 : + 1'b0; + assign entry29_epn_d[0:31] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry29_epn_q[0:31]; + assign entry29_epn_d[32:51] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry29_epn_q[32:51]; + assign entry29_xbit_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[52] : + entry29_xbit_q; + assign entry29_size_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry29_size_q[0:2]; + assign entry29_class_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry29_class_q[0:1]; + assign entry29_extclass_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry29_extclass_q[0:1]; + assign entry29_hv_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[65] : + entry29_hv_q; + assign entry29_ds_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[66] : + entry29_ds_q; + assign entry29_pid_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry29_pid_q[0:7]; + assign entry29_cmpmask_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry29_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry29_parity_d[0:3] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry29_parity_q[0:3]; + assign entry29_parity_d[4:6] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry29_parity_q[4:6]; + assign entry29_parity_d[7] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry29_parity_q[7]; + assign entry29_parity_d[8] = (wr_entry29_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry29_parity_q[8]; + assign entry29_parity_d[9] = (wr_entry29_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry29_parity_q[9]; + assign wr_entry30_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11110)) ? 1'b1 : + 1'b0; + assign wr_entry30_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11110)) ? 1'b1 : + 1'b0; + assign entry30_epn_d[0:31] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry30_epn_q[0:31]; + assign entry30_epn_d[32:51] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry30_epn_q[32:51]; + assign entry30_xbit_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[52] : + entry30_xbit_q; + assign entry30_size_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry30_size_q[0:2]; + assign entry30_class_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry30_class_q[0:1]; + assign entry30_extclass_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry30_extclass_q[0:1]; + assign entry30_hv_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[65] : + entry30_hv_q; + assign entry30_ds_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[66] : + entry30_ds_q; + assign entry30_pid_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry30_pid_q[0:7]; + assign entry30_cmpmask_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry30_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry30_parity_d[0:3] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry30_parity_q[0:3]; + assign entry30_parity_d[4:6] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry30_parity_q[4:6]; + assign entry30_parity_d[7] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry30_parity_q[7]; + assign entry30_parity_d[8] = (wr_entry30_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry30_parity_q[8]; + assign entry30_parity_d[9] = (wr_entry30_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry30_parity_q[9]; + assign wr_entry31_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11111)) ? 1'b1 : + 1'b0; + assign wr_entry31_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11111)) ? 1'b1 : + 1'b0; + assign entry31_epn_d[0:31] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry31_epn_q[0:31]; + assign entry31_epn_d[32:51] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry31_epn_q[32:51]; + assign entry31_xbit_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[52] : + entry31_xbit_q; + assign entry31_size_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry31_size_q[0:2]; + assign entry31_class_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry31_class_q[0:1]; + assign entry31_extclass_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry31_extclass_q[0:1]; + assign entry31_hv_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[65] : + entry31_hv_q; + assign entry31_ds_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[66] : + entry31_ds_q; + assign entry31_pid_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry31_pid_q[0:7]; + assign entry31_cmpmask_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry31_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry31_parity_d[0:3] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry31_parity_q[0:3]; + assign entry31_parity_d[4:6] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry31_parity_q[4:6]; + assign entry31_parity_d[7] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry31_parity_q[7]; + assign entry31_parity_d[8] = (wr_entry31_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry31_parity_q[8]; + assign entry31_parity_d[9] = (wr_entry31_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry31_parity_q[9]; + + + // entry valid and thdid next state logic + assign entry0_inval = (comp_invalidate & match_vec[0]) | flash_invalidate; + assign entry0_v_muxsel[0:1] = ({entry0_inval, wr_entry0_sel[0]}); + assign entry0_v_d = (entry0_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry0_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry0_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry0_v_q; + assign entry0_thdid_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry0_thdid_q[0:3]; + assign entry1_inval = (comp_invalidate & match_vec[1]) | flash_invalidate; + assign entry1_v_muxsel[0:1] = ({entry1_inval, wr_entry1_sel[0]}); + assign entry1_v_d = (entry1_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry1_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry1_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry1_v_q; + assign entry1_thdid_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry1_thdid_q[0:3]; + assign entry2_inval = (comp_invalidate & match_vec[2]) | flash_invalidate; + assign entry2_v_muxsel[0:1] = ({entry2_inval, wr_entry2_sel[0]}); + assign entry2_v_d = (entry2_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry2_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry2_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry2_v_q; + assign entry2_thdid_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry2_thdid_q[0:3]; + assign entry3_inval = (comp_invalidate & match_vec[3]) | flash_invalidate; + assign entry3_v_muxsel[0:1] = ({entry3_inval, wr_entry3_sel[0]}); + assign entry3_v_d = (entry3_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry3_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry3_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry3_v_q; + assign entry3_thdid_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry3_thdid_q[0:3]; + assign entry4_inval = (comp_invalidate & match_vec[4]) | flash_invalidate; + assign entry4_v_muxsel[0:1] = ({entry4_inval, wr_entry4_sel[0]}); + assign entry4_v_d = (entry4_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry4_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry4_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry4_v_q; + assign entry4_thdid_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry4_thdid_q[0:3]; + assign entry5_inval = (comp_invalidate & match_vec[5]) | flash_invalidate; + assign entry5_v_muxsel[0:1] = ({entry5_inval, wr_entry5_sel[0]}); + assign entry5_v_d = (entry5_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry5_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry5_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry5_v_q; + assign entry5_thdid_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry5_thdid_q[0:3]; + assign entry6_inval = (comp_invalidate & match_vec[6]) | flash_invalidate; + assign entry6_v_muxsel[0:1] = ({entry6_inval, wr_entry6_sel[0]}); + assign entry6_v_d = (entry6_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry6_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry6_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry6_v_q; + assign entry6_thdid_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry6_thdid_q[0:3]; + assign entry7_inval = (comp_invalidate & match_vec[7]) | flash_invalidate; + assign entry7_v_muxsel[0:1] = ({entry7_inval, wr_entry7_sel[0]}); + assign entry7_v_d = (entry7_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry7_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry7_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry7_v_q; + assign entry7_thdid_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry7_thdid_q[0:3]; + assign entry8_inval = (comp_invalidate & match_vec[8]) | flash_invalidate; + assign entry8_v_muxsel[0:1] = ({entry8_inval, wr_entry8_sel[0]}); + assign entry8_v_d = (entry8_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry8_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry8_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry8_v_q; + assign entry8_thdid_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry8_thdid_q[0:3]; + assign entry9_inval = (comp_invalidate & match_vec[9]) | flash_invalidate; + assign entry9_v_muxsel[0:1] = ({entry9_inval, wr_entry9_sel[0]}); + assign entry9_v_d = (entry9_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry9_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry9_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry9_v_q; + assign entry9_thdid_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry9_thdid_q[0:3]; + assign entry10_inval = (comp_invalidate & match_vec[10]) | flash_invalidate; + assign entry10_v_muxsel[0:1] = ({entry10_inval, wr_entry10_sel[0]}); + assign entry10_v_d = (entry10_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry10_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry10_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry10_v_q; + assign entry10_thdid_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry10_thdid_q[0:3]; + assign entry11_inval = (comp_invalidate & match_vec[11]) | flash_invalidate; + assign entry11_v_muxsel[0:1] = ({entry11_inval, wr_entry11_sel[0]}); + assign entry11_v_d = (entry11_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry11_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry11_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry11_v_q; + assign entry11_thdid_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry11_thdid_q[0:3]; + assign entry12_inval = (comp_invalidate & match_vec[12]) | flash_invalidate; + assign entry12_v_muxsel[0:1] = ({entry12_inval, wr_entry12_sel[0]}); + assign entry12_v_d = (entry12_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry12_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry12_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry12_v_q; + assign entry12_thdid_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry12_thdid_q[0:3]; + assign entry13_inval = (comp_invalidate & match_vec[13]) | flash_invalidate; + assign entry13_v_muxsel[0:1] = ({entry13_inval, wr_entry13_sel[0]}); + assign entry13_v_d = (entry13_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry13_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry13_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry13_v_q; + assign entry13_thdid_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry13_thdid_q[0:3]; + assign entry14_inval = (comp_invalidate & match_vec[14]) | flash_invalidate; + assign entry14_v_muxsel[0:1] = ({entry14_inval, wr_entry14_sel[0]}); + assign entry14_v_d = (entry14_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry14_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry14_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry14_v_q; + assign entry14_thdid_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry14_thdid_q[0:3]; + assign entry15_inval = (comp_invalidate & match_vec[15]) | flash_invalidate; + assign entry15_v_muxsel[0:1] = ({entry15_inval, wr_entry15_sel[0]}); + assign entry15_v_d = (entry15_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry15_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry15_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry15_v_q; + assign entry15_thdid_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry15_thdid_q[0:3]; + assign entry16_inval = (comp_invalidate & match_vec[16]) | flash_invalidate; + assign entry16_v_muxsel[0:1] = ({entry16_inval, wr_entry16_sel[0]}); + assign entry16_v_d = (entry16_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry16_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry16_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry16_v_q; + assign entry16_thdid_d[0:3] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry16_thdid_q[0:3]; + assign entry17_inval = (comp_invalidate & match_vec[17]) | flash_invalidate; + assign entry17_v_muxsel[0:1] = ({entry17_inval, wr_entry17_sel[0]}); + assign entry17_v_d = (entry17_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry17_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry17_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry17_v_q; + assign entry17_thdid_d[0:3] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry17_thdid_q[0:3]; + assign entry18_inval = (comp_invalidate & match_vec[18]) | flash_invalidate; + assign entry18_v_muxsel[0:1] = ({entry18_inval, wr_entry18_sel[0]}); + assign entry18_v_d = (entry18_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry18_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry18_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry18_v_q; + assign entry18_thdid_d[0:3] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry18_thdid_q[0:3]; + assign entry19_inval = (comp_invalidate & match_vec[19]) | flash_invalidate; + assign entry19_v_muxsel[0:1] = ({entry19_inval, wr_entry19_sel[0]}); + assign entry19_v_d = (entry19_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry19_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry19_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry19_v_q; + assign entry19_thdid_d[0:3] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry19_thdid_q[0:3]; + assign entry20_inval = (comp_invalidate & match_vec[20]) | flash_invalidate; + assign entry20_v_muxsel[0:1] = ({entry20_inval, wr_entry20_sel[0]}); + assign entry20_v_d = (entry20_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry20_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry20_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry20_v_q; + assign entry20_thdid_d[0:3] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry20_thdid_q[0:3]; + assign entry21_inval = (comp_invalidate & match_vec[21]) | flash_invalidate; + assign entry21_v_muxsel[0:1] = ({entry21_inval, wr_entry21_sel[0]}); + assign entry21_v_d = (entry21_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry21_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry21_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry21_v_q; + assign entry21_thdid_d[0:3] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry21_thdid_q[0:3]; + assign entry22_inval = (comp_invalidate & match_vec[22]) | flash_invalidate; + assign entry22_v_muxsel[0:1] = ({entry22_inval, wr_entry22_sel[0]}); + assign entry22_v_d = (entry22_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry22_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry22_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry22_v_q; + assign entry22_thdid_d[0:3] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry22_thdid_q[0:3]; + assign entry23_inval = (comp_invalidate & match_vec[23]) | flash_invalidate; + assign entry23_v_muxsel[0:1] = ({entry23_inval, wr_entry23_sel[0]}); + assign entry23_v_d = (entry23_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry23_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry23_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry23_v_q; + assign entry23_thdid_d[0:3] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry23_thdid_q[0:3]; + assign entry24_inval = (comp_invalidate & match_vec[24]) | flash_invalidate; + assign entry24_v_muxsel[0:1] = ({entry24_inval, wr_entry24_sel[0]}); + assign entry24_v_d = (entry24_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry24_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry24_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry24_v_q; + assign entry24_thdid_d[0:3] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry24_thdid_q[0:3]; + assign entry25_inval = (comp_invalidate & match_vec[25]) | flash_invalidate; + assign entry25_v_muxsel[0:1] = ({entry25_inval, wr_entry25_sel[0]}); + assign entry25_v_d = (entry25_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry25_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry25_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry25_v_q; + assign entry25_thdid_d[0:3] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry25_thdid_q[0:3]; + assign entry26_inval = (comp_invalidate & match_vec[26]) | flash_invalidate; + assign entry26_v_muxsel[0:1] = ({entry26_inval, wr_entry26_sel[0]}); + assign entry26_v_d = (entry26_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry26_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry26_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry26_v_q; + assign entry26_thdid_d[0:3] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry26_thdid_q[0:3]; + assign entry27_inval = (comp_invalidate & match_vec[27]) | flash_invalidate; + assign entry27_v_muxsel[0:1] = ({entry27_inval, wr_entry27_sel[0]}); + assign entry27_v_d = (entry27_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry27_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry27_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry27_v_q; + assign entry27_thdid_d[0:3] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry27_thdid_q[0:3]; + assign entry28_inval = (comp_invalidate & match_vec[28]) | flash_invalidate; + assign entry28_v_muxsel[0:1] = ({entry28_inval, wr_entry28_sel[0]}); + assign entry28_v_d = (entry28_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry28_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry28_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry28_v_q; + assign entry28_thdid_d[0:3] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry28_thdid_q[0:3]; + assign entry29_inval = (comp_invalidate & match_vec[29]) | flash_invalidate; + assign entry29_v_muxsel[0:1] = ({entry29_inval, wr_entry29_sel[0]}); + assign entry29_v_d = (entry29_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry29_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry29_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry29_v_q; + assign entry29_thdid_d[0:3] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry29_thdid_q[0:3]; + assign entry30_inval = (comp_invalidate & match_vec[30]) | flash_invalidate; + assign entry30_v_muxsel[0:1] = ({entry30_inval, wr_entry30_sel[0]}); + assign entry30_v_d = (entry30_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry30_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry30_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry30_v_q; + assign entry30_thdid_d[0:3] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry30_thdid_q[0:3]; + assign entry31_inval = (comp_invalidate & match_vec[31]) | flash_invalidate; + assign entry31_v_muxsel[0:1] = ({entry31_inval, wr_entry31_sel[0]}); + assign entry31_v_d = (entry31_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry31_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry31_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry31_v_q; + assign entry31_thdid_d[0:3] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry31_thdid_q[0:3]; + + + // CAM compare data out mux + assign entry0_cam_vec = {entry0_epn_q, entry0_xbit_q, entry0_size_q, entry0_v_q, entry0_thdid_q, entry0_class_q, entry0_extclass_q, entry0_hv_q, entry0_ds_q, entry0_pid_q, entry0_cmpmask_q}; + assign entry1_cam_vec = {entry1_epn_q, entry1_xbit_q, entry1_size_q, entry1_v_q, entry1_thdid_q, entry1_class_q, entry1_extclass_q, entry1_hv_q, entry1_ds_q, entry1_pid_q, entry1_cmpmask_q}; + assign entry2_cam_vec = {entry2_epn_q, entry2_xbit_q, entry2_size_q, entry2_v_q, entry2_thdid_q, entry2_class_q, entry2_extclass_q, entry2_hv_q, entry2_ds_q, entry2_pid_q, entry2_cmpmask_q}; + assign entry3_cam_vec = {entry3_epn_q, entry3_xbit_q, entry3_size_q, entry3_v_q, entry3_thdid_q, entry3_class_q, entry3_extclass_q, entry3_hv_q, entry3_ds_q, entry3_pid_q, entry3_cmpmask_q}; + assign entry4_cam_vec = {entry4_epn_q, entry4_xbit_q, entry4_size_q, entry4_v_q, entry4_thdid_q, entry4_class_q, entry4_extclass_q, entry4_hv_q, entry4_ds_q, entry4_pid_q, entry4_cmpmask_q}; + assign entry5_cam_vec = {entry5_epn_q, entry5_xbit_q, entry5_size_q, entry5_v_q, entry5_thdid_q, entry5_class_q, entry5_extclass_q, entry5_hv_q, entry5_ds_q, entry5_pid_q, entry5_cmpmask_q}; + assign entry6_cam_vec = {entry6_epn_q, entry6_xbit_q, entry6_size_q, entry6_v_q, entry6_thdid_q, entry6_class_q, entry6_extclass_q, entry6_hv_q, entry6_ds_q, entry6_pid_q, entry6_cmpmask_q}; + assign entry7_cam_vec = {entry7_epn_q, entry7_xbit_q, entry7_size_q, entry7_v_q, entry7_thdid_q, entry7_class_q, entry7_extclass_q, entry7_hv_q, entry7_ds_q, entry7_pid_q, entry7_cmpmask_q}; + assign entry8_cam_vec = {entry8_epn_q, entry8_xbit_q, entry8_size_q, entry8_v_q, entry8_thdid_q, entry8_class_q, entry8_extclass_q, entry8_hv_q, entry8_ds_q, entry8_pid_q, entry8_cmpmask_q}; + assign entry9_cam_vec = {entry9_epn_q, entry9_xbit_q, entry9_size_q, entry9_v_q, entry9_thdid_q, entry9_class_q, entry9_extclass_q, entry9_hv_q, entry9_ds_q, entry9_pid_q, entry9_cmpmask_q}; + assign entry10_cam_vec = {entry10_epn_q, entry10_xbit_q, entry10_size_q, entry10_v_q, entry10_thdid_q, entry10_class_q, entry10_extclass_q, entry10_hv_q, entry10_ds_q, entry10_pid_q, entry10_cmpmask_q}; + assign entry11_cam_vec = {entry11_epn_q, entry11_xbit_q, entry11_size_q, entry11_v_q, entry11_thdid_q, entry11_class_q, entry11_extclass_q, entry11_hv_q, entry11_ds_q, entry11_pid_q, entry11_cmpmask_q}; + assign entry12_cam_vec = {entry12_epn_q, entry12_xbit_q, entry12_size_q, entry12_v_q, entry12_thdid_q, entry12_class_q, entry12_extclass_q, entry12_hv_q, entry12_ds_q, entry12_pid_q, entry12_cmpmask_q}; + assign entry13_cam_vec = {entry13_epn_q, entry13_xbit_q, entry13_size_q, entry13_v_q, entry13_thdid_q, entry13_class_q, entry13_extclass_q, entry13_hv_q, entry13_ds_q, entry13_pid_q, entry13_cmpmask_q}; + assign entry14_cam_vec = {entry14_epn_q, entry14_xbit_q, entry14_size_q, entry14_v_q, entry14_thdid_q, entry14_class_q, entry14_extclass_q, entry14_hv_q, entry14_ds_q, entry14_pid_q, entry14_cmpmask_q}; + assign entry15_cam_vec = {entry15_epn_q, entry15_xbit_q, entry15_size_q, entry15_v_q, entry15_thdid_q, entry15_class_q, entry15_extclass_q, entry15_hv_q, entry15_ds_q, entry15_pid_q, entry15_cmpmask_q}; + assign entry16_cam_vec = {entry16_epn_q, entry16_xbit_q, entry16_size_q, entry16_v_q, entry16_thdid_q, entry16_class_q, entry16_extclass_q, entry16_hv_q, entry16_ds_q, entry16_pid_q, entry16_cmpmask_q}; + assign entry17_cam_vec = {entry17_epn_q, entry17_xbit_q, entry17_size_q, entry17_v_q, entry17_thdid_q, entry17_class_q, entry17_extclass_q, entry17_hv_q, entry17_ds_q, entry17_pid_q, entry17_cmpmask_q}; + assign entry18_cam_vec = {entry18_epn_q, entry18_xbit_q, entry18_size_q, entry18_v_q, entry18_thdid_q, entry18_class_q, entry18_extclass_q, entry18_hv_q, entry18_ds_q, entry18_pid_q, entry18_cmpmask_q}; + assign entry19_cam_vec = {entry19_epn_q, entry19_xbit_q, entry19_size_q, entry19_v_q, entry19_thdid_q, entry19_class_q, entry19_extclass_q, entry19_hv_q, entry19_ds_q, entry19_pid_q, entry19_cmpmask_q}; + assign entry20_cam_vec = {entry20_epn_q, entry20_xbit_q, entry20_size_q, entry20_v_q, entry20_thdid_q, entry20_class_q, entry20_extclass_q, entry20_hv_q, entry20_ds_q, entry20_pid_q, entry20_cmpmask_q}; + assign entry21_cam_vec = {entry21_epn_q, entry21_xbit_q, entry21_size_q, entry21_v_q, entry21_thdid_q, entry21_class_q, entry21_extclass_q, entry21_hv_q, entry21_ds_q, entry21_pid_q, entry21_cmpmask_q}; + assign entry22_cam_vec = {entry22_epn_q, entry22_xbit_q, entry22_size_q, entry22_v_q, entry22_thdid_q, entry22_class_q, entry22_extclass_q, entry22_hv_q, entry22_ds_q, entry22_pid_q, entry22_cmpmask_q}; + assign entry23_cam_vec = {entry23_epn_q, entry23_xbit_q, entry23_size_q, entry23_v_q, entry23_thdid_q, entry23_class_q, entry23_extclass_q, entry23_hv_q, entry23_ds_q, entry23_pid_q, entry23_cmpmask_q}; + assign entry24_cam_vec = {entry24_epn_q, entry24_xbit_q, entry24_size_q, entry24_v_q, entry24_thdid_q, entry24_class_q, entry24_extclass_q, entry24_hv_q, entry24_ds_q, entry24_pid_q, entry24_cmpmask_q}; + assign entry25_cam_vec = {entry25_epn_q, entry25_xbit_q, entry25_size_q, entry25_v_q, entry25_thdid_q, entry25_class_q, entry25_extclass_q, entry25_hv_q, entry25_ds_q, entry25_pid_q, entry25_cmpmask_q}; + assign entry26_cam_vec = {entry26_epn_q, entry26_xbit_q, entry26_size_q, entry26_v_q, entry26_thdid_q, entry26_class_q, entry26_extclass_q, entry26_hv_q, entry26_ds_q, entry26_pid_q, entry26_cmpmask_q}; + assign entry27_cam_vec = {entry27_epn_q, entry27_xbit_q, entry27_size_q, entry27_v_q, entry27_thdid_q, entry27_class_q, entry27_extclass_q, entry27_hv_q, entry27_ds_q, entry27_pid_q, entry27_cmpmask_q}; + assign entry28_cam_vec = {entry28_epn_q, entry28_xbit_q, entry28_size_q, entry28_v_q, entry28_thdid_q, entry28_class_q, entry28_extclass_q, entry28_hv_q, entry28_ds_q, entry28_pid_q, entry28_cmpmask_q}; + assign entry29_cam_vec = {entry29_epn_q, entry29_xbit_q, entry29_size_q, entry29_v_q, entry29_thdid_q, entry29_class_q, entry29_extclass_q, entry29_hv_q, entry29_ds_q, entry29_pid_q, entry29_cmpmask_q}; + assign entry30_cam_vec = {entry30_epn_q, entry30_xbit_q, entry30_size_q, entry30_v_q, entry30_thdid_q, entry30_class_q, entry30_extclass_q, entry30_hv_q, entry30_ds_q, entry30_pid_q, entry30_cmpmask_q}; + assign entry31_cam_vec = {entry31_epn_q, entry31_xbit_q, entry31_size_q, entry31_v_q, entry31_thdid_q, entry31_class_q, entry31_extclass_q, entry31_hv_q, entry31_ds_q, entry31_pid_q, entry31_cmpmask_q}; + + + assign cam_cmp_data_muxsel = {(~(comp_request)), cam_hit_entry_d}; + assign cam_cmp_data_d = (cam_cmp_data_muxsel == 6'b000000) ? entry0_cam_vec : + (cam_cmp_data_muxsel == 6'b000001) ? entry1_cam_vec : + (cam_cmp_data_muxsel == 6'b000010) ? entry2_cam_vec : + (cam_cmp_data_muxsel == 6'b000011) ? entry3_cam_vec : + (cam_cmp_data_muxsel == 6'b000100) ? entry4_cam_vec : + (cam_cmp_data_muxsel == 6'b000101) ? entry5_cam_vec : + (cam_cmp_data_muxsel == 6'b000110) ? entry6_cam_vec : + (cam_cmp_data_muxsel == 6'b000111) ? entry7_cam_vec : + (cam_cmp_data_muxsel == 6'b001000) ? entry8_cam_vec : + (cam_cmp_data_muxsel == 6'b001001) ? entry9_cam_vec : + (cam_cmp_data_muxsel == 6'b001010) ? entry10_cam_vec : + (cam_cmp_data_muxsel == 6'b001011) ? entry11_cam_vec : + (cam_cmp_data_muxsel == 6'b001100) ? entry12_cam_vec : + (cam_cmp_data_muxsel == 6'b001101) ? entry13_cam_vec : + (cam_cmp_data_muxsel == 6'b001110) ? entry14_cam_vec : + (cam_cmp_data_muxsel == 6'b001111) ? entry15_cam_vec : + (cam_cmp_data_muxsel == 6'b010000) ? entry16_cam_vec : + (cam_cmp_data_muxsel == 6'b010001) ? entry17_cam_vec : + (cam_cmp_data_muxsel == 6'b010010) ? entry18_cam_vec : + (cam_cmp_data_muxsel == 6'b010011) ? entry19_cam_vec : + (cam_cmp_data_muxsel == 6'b010100) ? entry20_cam_vec : + (cam_cmp_data_muxsel == 6'b010101) ? entry21_cam_vec : + (cam_cmp_data_muxsel == 6'b010110) ? entry22_cam_vec : + (cam_cmp_data_muxsel == 6'b010111) ? entry23_cam_vec : + (cam_cmp_data_muxsel == 6'b011000) ? entry24_cam_vec : + (cam_cmp_data_muxsel == 6'b011001) ? entry25_cam_vec : + (cam_cmp_data_muxsel == 6'b011010) ? entry26_cam_vec : + (cam_cmp_data_muxsel == 6'b011011) ? entry27_cam_vec : + (cam_cmp_data_muxsel == 6'b011100) ? entry28_cam_vec : + (cam_cmp_data_muxsel == 6'b011101) ? entry29_cam_vec : + (cam_cmp_data_muxsel == 6'b011110) ? entry30_cam_vec : + (cam_cmp_data_muxsel == 6'b011111) ? entry31_cam_vec : + cam_cmp_data_q; + + assign cam_cmp_data_np1 = cam_cmp_data_q; + + // CAM read data out mux + assign rd_cam_data_muxsel = {(~(rd_val)), rw_entry}; + + assign rd_cam_data_d = (rd_cam_data_muxsel == 6'b000000) ? entry0_cam_vec : + (rd_cam_data_muxsel == 6'b000001) ? entry1_cam_vec : + (rd_cam_data_muxsel == 6'b000010) ? entry2_cam_vec : + (rd_cam_data_muxsel == 6'b000011) ? entry3_cam_vec : + (rd_cam_data_muxsel == 6'b000100) ? entry4_cam_vec : + (rd_cam_data_muxsel == 6'b000101) ? entry5_cam_vec : + (rd_cam_data_muxsel == 6'b000110) ? entry6_cam_vec : + (rd_cam_data_muxsel == 6'b000111) ? entry7_cam_vec : + (rd_cam_data_muxsel == 6'b001000) ? entry8_cam_vec : + (rd_cam_data_muxsel == 6'b001001) ? entry9_cam_vec : + (rd_cam_data_muxsel == 6'b001010) ? entry10_cam_vec : + (rd_cam_data_muxsel == 6'b001011) ? entry11_cam_vec : + (rd_cam_data_muxsel == 6'b001100) ? entry12_cam_vec : + (rd_cam_data_muxsel == 6'b001101) ? entry13_cam_vec : + (rd_cam_data_muxsel == 6'b001110) ? entry14_cam_vec : + (rd_cam_data_muxsel == 6'b001111) ? entry15_cam_vec : + (rd_cam_data_muxsel == 6'b010000) ? entry16_cam_vec : + (rd_cam_data_muxsel == 6'b010001) ? entry17_cam_vec : + (rd_cam_data_muxsel == 6'b010010) ? entry18_cam_vec : + (rd_cam_data_muxsel == 6'b010011) ? entry19_cam_vec : + (rd_cam_data_muxsel == 6'b010100) ? entry20_cam_vec : + (rd_cam_data_muxsel == 6'b010101) ? entry21_cam_vec : + (rd_cam_data_muxsel == 6'b010110) ? entry22_cam_vec : + (rd_cam_data_muxsel == 6'b010111) ? entry23_cam_vec : + (rd_cam_data_muxsel == 6'b011000) ? entry24_cam_vec : + (rd_cam_data_muxsel == 6'b011001) ? entry25_cam_vec : + (rd_cam_data_muxsel == 6'b011010) ? entry26_cam_vec : + (rd_cam_data_muxsel == 6'b011011) ? entry27_cam_vec : + (rd_cam_data_muxsel == 6'b011100) ? entry28_cam_vec : + (rd_cam_data_muxsel == 6'b011101) ? entry29_cam_vec : + (rd_cam_data_muxsel == 6'b011110) ? entry30_cam_vec : + (rd_cam_data_muxsel == 6'b011111) ? entry31_cam_vec : + rd_cam_data_q; + + // CAM compare parity out mux + assign cam_cmp_parity_d = (cam_cmp_data_muxsel == 6'b000000) ? entry0_parity_q : + (cam_cmp_data_muxsel == 6'b000001) ? entry1_parity_q : + (cam_cmp_data_muxsel == 6'b000010) ? entry2_parity_q : + (cam_cmp_data_muxsel == 6'b000011) ? entry3_parity_q : + (cam_cmp_data_muxsel == 6'b000100) ? entry4_parity_q : + (cam_cmp_data_muxsel == 6'b000101) ? entry5_parity_q : + (cam_cmp_data_muxsel == 6'b000110) ? entry6_parity_q : + (cam_cmp_data_muxsel == 6'b000111) ? entry7_parity_q : + (cam_cmp_data_muxsel == 6'b001000) ? entry8_parity_q : + (cam_cmp_data_muxsel == 6'b001001) ? entry9_parity_q : + (cam_cmp_data_muxsel == 6'b001010) ? entry10_parity_q : + (cam_cmp_data_muxsel == 6'b001011) ? entry11_parity_q : + (cam_cmp_data_muxsel == 6'b001100) ? entry12_parity_q : + (cam_cmp_data_muxsel == 6'b001101) ? entry13_parity_q : + (cam_cmp_data_muxsel == 6'b001110) ? entry14_parity_q : + (cam_cmp_data_muxsel == 6'b001111) ? entry15_parity_q : + (cam_cmp_data_muxsel == 6'b010000) ? entry16_parity_q : + (cam_cmp_data_muxsel == 6'b010001) ? entry17_parity_q : + (cam_cmp_data_muxsel == 6'b010010) ? entry18_parity_q : + (cam_cmp_data_muxsel == 6'b010011) ? entry19_parity_q : + (cam_cmp_data_muxsel == 6'b010100) ? entry20_parity_q : + (cam_cmp_data_muxsel == 6'b010101) ? entry21_parity_q : + (cam_cmp_data_muxsel == 6'b010110) ? entry22_parity_q : + (cam_cmp_data_muxsel == 6'b010111) ? entry23_parity_q : + (cam_cmp_data_muxsel == 6'b011000) ? entry24_parity_q : + (cam_cmp_data_muxsel == 6'b011001) ? entry25_parity_q : + (cam_cmp_data_muxsel == 6'b011010) ? entry26_parity_q : + (cam_cmp_data_muxsel == 6'b011011) ? entry27_parity_q : + (cam_cmp_data_muxsel == 6'b011100) ? entry28_parity_q : + (cam_cmp_data_muxsel == 6'b011101) ? entry29_parity_q : + (cam_cmp_data_muxsel == 6'b011110) ? entry30_parity_q : + (cam_cmp_data_muxsel == 6'b011111) ? entry31_parity_q : + cam_cmp_parity_q; + + assign array_cmp_data_np1[0:50] = {array_cmp_data_bram[2:31], array_cmp_data_bram[34:39], array_cmp_data_bram[41:55]}; + assign array_cmp_data_np1[51:60] = cam_cmp_parity_q; + assign array_cmp_data_np1[61:67] = array_cmp_data_bramp[66:72]; + + assign array_cmp_data = array_cmp_data_np1; + + // CAM read parity out mux + assign rd_array_data_d[51:60] = (rd_cam_data_muxsel == 6'b000000) ? entry0_parity_q : + (rd_cam_data_muxsel == 6'b000001) ? entry1_parity_q : + (rd_cam_data_muxsel == 6'b000010) ? entry2_parity_q : + (rd_cam_data_muxsel == 6'b000011) ? entry3_parity_q : + (rd_cam_data_muxsel == 6'b000100) ? entry4_parity_q : + (rd_cam_data_muxsel == 6'b000101) ? entry5_parity_q : + (rd_cam_data_muxsel == 6'b000110) ? entry6_parity_q : + (rd_cam_data_muxsel == 6'b000111) ? entry7_parity_q : + (rd_cam_data_muxsel == 6'b001000) ? entry8_parity_q : + (rd_cam_data_muxsel == 6'b001001) ? entry9_parity_q : + (rd_cam_data_muxsel == 6'b001010) ? entry10_parity_q : + (rd_cam_data_muxsel == 6'b001011) ? entry11_parity_q : + (rd_cam_data_muxsel == 6'b001100) ? entry12_parity_q : + (rd_cam_data_muxsel == 6'b001101) ? entry13_parity_q : + (rd_cam_data_muxsel == 6'b001110) ? entry14_parity_q : + (rd_cam_data_muxsel == 6'b001111) ? entry15_parity_q : + (rd_cam_data_muxsel == 6'b010000) ? entry16_parity_q : + (rd_cam_data_muxsel == 6'b010001) ? entry17_parity_q : + (rd_cam_data_muxsel == 6'b010010) ? entry18_parity_q : + (rd_cam_data_muxsel == 6'b010011) ? entry19_parity_q : + (rd_cam_data_muxsel == 6'b010100) ? entry20_parity_q : + (rd_cam_data_muxsel == 6'b010101) ? entry21_parity_q : + (rd_cam_data_muxsel == 6'b010110) ? entry22_parity_q : + (rd_cam_data_muxsel == 6'b010111) ? entry23_parity_q : + (rd_cam_data_muxsel == 6'b011000) ? entry24_parity_q : + (rd_cam_data_muxsel == 6'b011001) ? entry25_parity_q : + (rd_cam_data_muxsel == 6'b011010) ? entry26_parity_q : + (rd_cam_data_muxsel == 6'b011011) ? entry27_parity_q : + (rd_cam_data_muxsel == 6'b011100) ? entry28_parity_q : + (rd_cam_data_muxsel == 6'b011101) ? entry29_parity_q : + (rd_cam_data_muxsel == 6'b011110) ? entry30_parity_q : + (rd_cam_data_muxsel == 6'b011111) ? entry31_parity_q : + rd_array_data_q[51:60]; + + // internal bypass latch input for rpn + // using cam_cmp_data(75:78) cmpmask bits for mux selects + assign rpn_np2_d[22:33] = (comp_addr_np1_q[22:33] & {12{bypass_mux_enab_np1}}) | + (array_cmp_data_np1[0:11] & {12{~(bypass_mux_enab_np1)}}); // real page from cam-array + + //CAM_PgSize_1GB + assign rpn_np2_d[34:39] = (comp_addr_np1_q[34:39] & {6{(~(cam_cmp_data_np1[75])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[12:17] & {6{cam_cmp_data_np1[75] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_1GB or CAM_PgSize_16MB + assign rpn_np2_d[40:43] = (comp_addr_np1_q[40:43] & {4{(~(cam_cmp_data_np1[76])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[18:21] & {4{cam_cmp_data_np1[76] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_1GB or CAM_PgSize_16MB or CAM_PgSize_1MB + assign rpn_np2_d[44:47] = (comp_addr_np1_q[44:47] & {4{(~(cam_cmp_data_np1[77])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[22:25] & {4{cam_cmp_data_np1[77] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_Larger_than_4K + assign rpn_np2_d[48:51] = (comp_addr_np1_q[48:51] & {4{(~(cam_cmp_data_np1[78])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[26:29] & {4{cam_cmp_data_np1[78] & (~bypass_mux_enab_np1)}}); + + // internal bypass latch input for attributes + assign attr_np2_d[0:20] = (bypass_attr_np1[0:20] & {21{bypass_mux_enab_np1}}) | + (array_cmp_data_np1[30:50] & {21{~bypass_mux_enab_np1}}); + + // new port output assignments + assign rpn_np2[22:51] = rpn_np2_q[22:51]; + assign attr_np2[0:20] = attr_np2_q[0:20]; + + //--------------------------------------------------------------------- + // matchline component instantiations + //--------------------------------------------------------------------- + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb0( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry0_size_q), + .entry_cmpmask(entry0_cmpmask_q[0:3]), + .entry_xbit(entry0_xbit_q), + .entry_xbitmask(entry0_cmpmask_q[4:7]), + .entry_epn(entry0_epn_q), + .comp_class(comp_class), + .entry_class(entry0_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry0_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry0_hv_q), + .entry_ds(entry0_ds_q), + .state_enable(state_enable), + .entry_thdid(entry0_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry0_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry0_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[0]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb1( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry1_size_q), + .entry_cmpmask(entry1_cmpmask_q[0:3]), + .entry_xbit(entry1_xbit_q), + .entry_xbitmask(entry1_cmpmask_q[4:7]), + .entry_epn(entry1_epn_q), + .comp_class(comp_class), + .entry_class(entry1_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry1_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry1_hv_q), + .entry_ds(entry1_ds_q), + .state_enable(state_enable), + .entry_thdid(entry1_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry1_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry1_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[1]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb2( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry2_size_q), + .entry_cmpmask(entry2_cmpmask_q[0:3]), + .entry_xbit(entry2_xbit_q), + .entry_xbitmask(entry2_cmpmask_q[4:7]), + .entry_epn(entry2_epn_q), + .comp_class(comp_class), + .entry_class(entry2_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry2_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry2_hv_q), + .entry_ds(entry2_ds_q), + .state_enable(state_enable), + .entry_thdid(entry2_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry2_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry2_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[2]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb3( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry3_size_q), + .entry_cmpmask(entry3_cmpmask_q[0:3]), + .entry_xbit(entry3_xbit_q), + .entry_xbitmask(entry3_cmpmask_q[4:7]), + .entry_epn(entry3_epn_q), + .comp_class(comp_class), + .entry_class(entry3_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry3_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry3_hv_q), + .entry_ds(entry3_ds_q), + .state_enable(state_enable), + .entry_thdid(entry3_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry3_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry3_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[3]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb4( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry4_size_q), + .entry_cmpmask(entry4_cmpmask_q[0:3]), + .entry_xbit(entry4_xbit_q), + .entry_xbitmask(entry4_cmpmask_q[4:7]), + .entry_epn(entry4_epn_q), + .comp_class(comp_class), + .entry_class(entry4_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry4_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry4_hv_q), + .entry_ds(entry4_ds_q), + .state_enable(state_enable), + .entry_thdid(entry4_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry4_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry4_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[4]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb5( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry5_size_q), + .entry_cmpmask(entry5_cmpmask_q[0:3]), + .entry_xbit(entry5_xbit_q), + .entry_xbitmask(entry5_cmpmask_q[4:7]), + .entry_epn(entry5_epn_q), + .comp_class(comp_class), + .entry_class(entry5_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry5_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry5_hv_q), + .entry_ds(entry5_ds_q), + .state_enable(state_enable), + .entry_thdid(entry5_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry5_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry5_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[5]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb6( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry6_size_q), + .entry_cmpmask(entry6_cmpmask_q[0:3]), + .entry_xbit(entry6_xbit_q), + .entry_xbitmask(entry6_cmpmask_q[4:7]), + .entry_epn(entry6_epn_q), + .comp_class(comp_class), + .entry_class(entry6_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry6_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry6_hv_q), + .entry_ds(entry6_ds_q), + .state_enable(state_enable), + .entry_thdid(entry6_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry6_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry6_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[6]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb7( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry7_size_q), + .entry_cmpmask(entry7_cmpmask_q[0:3]), + .entry_xbit(entry7_xbit_q), + .entry_xbitmask(entry7_cmpmask_q[4:7]), + .entry_epn(entry7_epn_q), + .comp_class(comp_class), + .entry_class(entry7_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry7_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry7_hv_q), + .entry_ds(entry7_ds_q), + .state_enable(state_enable), + .entry_thdid(entry7_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry7_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry7_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[7]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb8( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry8_size_q), + .entry_cmpmask(entry8_cmpmask_q[0:3]), + .entry_xbit(entry8_xbit_q), + .entry_xbitmask(entry8_cmpmask_q[4:7]), + .entry_epn(entry8_epn_q), + .comp_class(comp_class), + .entry_class(entry8_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry8_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry8_hv_q), + .entry_ds(entry8_ds_q), + .state_enable(state_enable), + .entry_thdid(entry8_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry8_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry8_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[8]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb9( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry9_size_q), + .entry_cmpmask(entry9_cmpmask_q[0:3]), + .entry_xbit(entry9_xbit_q), + .entry_xbitmask(entry9_cmpmask_q[4:7]), + .entry_epn(entry9_epn_q), + .comp_class(comp_class), + .entry_class(entry9_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry9_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry9_hv_q), + .entry_ds(entry9_ds_q), + .state_enable(state_enable), + .entry_thdid(entry9_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry9_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry9_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[9]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb10( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry10_size_q), + .entry_cmpmask(entry10_cmpmask_q[0:3]), + .entry_xbit(entry10_xbit_q), + .entry_xbitmask(entry10_cmpmask_q[4:7]), + .entry_epn(entry10_epn_q), + .comp_class(comp_class), + .entry_class(entry10_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry10_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry10_hv_q), + .entry_ds(entry10_ds_q), + .state_enable(state_enable), + .entry_thdid(entry10_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry10_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry10_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[10]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb11( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry11_size_q), + .entry_cmpmask(entry11_cmpmask_q[0:3]), + .entry_xbit(entry11_xbit_q), + .entry_xbitmask(entry11_cmpmask_q[4:7]), + .entry_epn(entry11_epn_q), + .comp_class(comp_class), + .entry_class(entry11_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry11_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry11_hv_q), + .entry_ds(entry11_ds_q), + .state_enable(state_enable), + .entry_thdid(entry11_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry11_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry11_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[11]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb12( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry12_size_q), + .entry_cmpmask(entry12_cmpmask_q[0:3]), + .entry_xbit(entry12_xbit_q), + .entry_xbitmask(entry12_cmpmask_q[4:7]), + .entry_epn(entry12_epn_q), + .comp_class(comp_class), + .entry_class(entry12_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry12_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry12_hv_q), + .entry_ds(entry12_ds_q), + .state_enable(state_enable), + .entry_thdid(entry12_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry12_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry12_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[12]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb13( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry13_size_q), + .entry_cmpmask(entry13_cmpmask_q[0:3]), + .entry_xbit(entry13_xbit_q), + .entry_xbitmask(entry13_cmpmask_q[4:7]), + .entry_epn(entry13_epn_q), + .comp_class(comp_class), + .entry_class(entry13_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry13_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry13_hv_q), + .entry_ds(entry13_ds_q), + .state_enable(state_enable), + .entry_thdid(entry13_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry13_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry13_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[13]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb14( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry14_size_q), + .entry_cmpmask(entry14_cmpmask_q[0:3]), + .entry_xbit(entry14_xbit_q), + .entry_xbitmask(entry14_cmpmask_q[4:7]), + .entry_epn(entry14_epn_q), + .comp_class(comp_class), + .entry_class(entry14_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry14_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry14_hv_q), + .entry_ds(entry14_ds_q), + .state_enable(state_enable), + .entry_thdid(entry14_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry14_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry14_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[14]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb15( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry15_size_q), + .entry_cmpmask(entry15_cmpmask_q[0:3]), + .entry_xbit(entry15_xbit_q), + .entry_xbitmask(entry15_cmpmask_q[4:7]), + .entry_epn(entry15_epn_q), + .comp_class(comp_class), + .entry_class(entry15_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry15_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry15_hv_q), + .entry_ds(entry15_ds_q), + .state_enable(state_enable), + .entry_thdid(entry15_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry15_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry15_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[15]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb16( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry16_size_q), + .entry_cmpmask(entry16_cmpmask_q[0:3]), + .entry_xbit(entry16_xbit_q), + .entry_xbitmask(entry16_cmpmask_q[4:7]), + .entry_epn(entry16_epn_q), + .comp_class(comp_class), + .entry_class(entry16_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry16_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry16_hv_q), + .entry_ds(entry16_ds_q), + .state_enable(state_enable), + .entry_thdid(entry16_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry16_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry16_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[16]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb17( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry17_size_q), + .entry_cmpmask(entry17_cmpmask_q[0:3]), + .entry_xbit(entry17_xbit_q), + .entry_xbitmask(entry17_cmpmask_q[4:7]), + .entry_epn(entry17_epn_q), + .comp_class(comp_class), + .entry_class(entry17_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry17_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry17_hv_q), + .entry_ds(entry17_ds_q), + .state_enable(state_enable), + .entry_thdid(entry17_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry17_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry17_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[17]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb18( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry18_size_q), + .entry_cmpmask(entry18_cmpmask_q[0:3]), + .entry_xbit(entry18_xbit_q), + .entry_xbitmask(entry18_cmpmask_q[4:7]), + .entry_epn(entry18_epn_q), + .comp_class(comp_class), + .entry_class(entry18_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry18_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry18_hv_q), + .entry_ds(entry18_ds_q), + .state_enable(state_enable), + .entry_thdid(entry18_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry18_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry18_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[18]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb19( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry19_size_q), + .entry_cmpmask(entry19_cmpmask_q[0:3]), + .entry_xbit(entry19_xbit_q), + .entry_xbitmask(entry19_cmpmask_q[4:7]), + .entry_epn(entry19_epn_q), + .comp_class(comp_class), + .entry_class(entry19_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry19_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry19_hv_q), + .entry_ds(entry19_ds_q), + .state_enable(state_enable), + .entry_thdid(entry19_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry19_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry19_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[19]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb20( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry20_size_q), + .entry_cmpmask(entry20_cmpmask_q[0:3]), + .entry_xbit(entry20_xbit_q), + .entry_xbitmask(entry20_cmpmask_q[4:7]), + .entry_epn(entry20_epn_q), + .comp_class(comp_class), + .entry_class(entry20_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry20_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry20_hv_q), + .entry_ds(entry20_ds_q), + .state_enable(state_enable), + .entry_thdid(entry20_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry20_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry20_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[20]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb21( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry21_size_q), + .entry_cmpmask(entry21_cmpmask_q[0:3]), + .entry_xbit(entry21_xbit_q), + .entry_xbitmask(entry21_cmpmask_q[4:7]), + .entry_epn(entry21_epn_q), + .comp_class(comp_class), + .entry_class(entry21_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry21_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry21_hv_q), + .entry_ds(entry21_ds_q), + .state_enable(state_enable), + .entry_thdid(entry21_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry21_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry21_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[21]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb22( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry22_size_q), + .entry_cmpmask(entry22_cmpmask_q[0:3]), + .entry_xbit(entry22_xbit_q), + .entry_xbitmask(entry22_cmpmask_q[4:7]), + .entry_epn(entry22_epn_q), + .comp_class(comp_class), + .entry_class(entry22_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry22_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry22_hv_q), + .entry_ds(entry22_ds_q), + .state_enable(state_enable), + .entry_thdid(entry22_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry22_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry22_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[22]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb23( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry23_size_q), + .entry_cmpmask(entry23_cmpmask_q[0:3]), + .entry_xbit(entry23_xbit_q), + .entry_xbitmask(entry23_cmpmask_q[4:7]), + .entry_epn(entry23_epn_q), + .comp_class(comp_class), + .entry_class(entry23_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry23_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry23_hv_q), + .entry_ds(entry23_ds_q), + .state_enable(state_enable), + .entry_thdid(entry23_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry23_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry23_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[23]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb24( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry24_size_q), + .entry_cmpmask(entry24_cmpmask_q[0:3]), + .entry_xbit(entry24_xbit_q), + .entry_xbitmask(entry24_cmpmask_q[4:7]), + .entry_epn(entry24_epn_q), + .comp_class(comp_class), + .entry_class(entry24_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry24_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry24_hv_q), + .entry_ds(entry24_ds_q), + .state_enable(state_enable), + .entry_thdid(entry24_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry24_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry24_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[24]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb25( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry25_size_q), + .entry_cmpmask(entry25_cmpmask_q[0:3]), + .entry_xbit(entry25_xbit_q), + .entry_xbitmask(entry25_cmpmask_q[4:7]), + .entry_epn(entry25_epn_q), + .comp_class(comp_class), + .entry_class(entry25_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry25_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry25_hv_q), + .entry_ds(entry25_ds_q), + .state_enable(state_enable), + .entry_thdid(entry25_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry25_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry25_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[25]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb26( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry26_size_q), + .entry_cmpmask(entry26_cmpmask_q[0:3]), + .entry_xbit(entry26_xbit_q), + .entry_xbitmask(entry26_cmpmask_q[4:7]), + .entry_epn(entry26_epn_q), + .comp_class(comp_class), + .entry_class(entry26_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry26_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry26_hv_q), + .entry_ds(entry26_ds_q), + .state_enable(state_enable), + .entry_thdid(entry26_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry26_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry26_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[26]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb27( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry27_size_q), + .entry_cmpmask(entry27_cmpmask_q[0:3]), + .entry_xbit(entry27_xbit_q), + .entry_xbitmask(entry27_cmpmask_q[4:7]), + .entry_epn(entry27_epn_q), + .comp_class(comp_class), + .entry_class(entry27_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry27_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry27_hv_q), + .entry_ds(entry27_ds_q), + .state_enable(state_enable), + .entry_thdid(entry27_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry27_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry27_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[27]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb28( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry28_size_q), + .entry_cmpmask(entry28_cmpmask_q[0:3]), + .entry_xbit(entry28_xbit_q), + .entry_xbitmask(entry28_cmpmask_q[4:7]), + .entry_epn(entry28_epn_q), + .comp_class(comp_class), + .entry_class(entry28_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry28_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry28_hv_q), + .entry_ds(entry28_ds_q), + .state_enable(state_enable), + .entry_thdid(entry28_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry28_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry28_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[28]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb29( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry29_size_q), + .entry_cmpmask(entry29_cmpmask_q[0:3]), + .entry_xbit(entry29_xbit_q), + .entry_xbitmask(entry29_cmpmask_q[4:7]), + .entry_epn(entry29_epn_q), + .comp_class(comp_class), + .entry_class(entry29_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry29_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry29_hv_q), + .entry_ds(entry29_ds_q), + .state_enable(state_enable), + .entry_thdid(entry29_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry29_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry29_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[29]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb30( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry30_size_q), + .entry_cmpmask(entry30_cmpmask_q[0:3]), + .entry_xbit(entry30_xbit_q), + .entry_xbitmask(entry30_cmpmask_q[4:7]), + .entry_epn(entry30_epn_q), + .comp_class(comp_class), + .entry_class(entry30_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry30_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry30_hv_q), + .entry_ds(entry30_ds_q), + .state_enable(state_enable), + .entry_thdid(entry30_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry30_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry30_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[30]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb31( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry31_size_q), + .entry_cmpmask(entry31_cmpmask_q[0:3]), + .entry_xbit(entry31_xbit_q), + .entry_xbitmask(entry31_cmpmask_q[4:7]), + .entry_epn(entry31_epn_q), + .comp_class(comp_class), + .entry_class(entry31_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry31_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry31_hv_q), + .entry_ds(entry31_ds_q), + .state_enable(state_enable), + .entry_thdid(entry31_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry31_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry31_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[31]) + ); + + + //--------------------------------------------------------------------- + // BRAM signal assignments + //--------------------------------------------------------------------- + assign bram0_wea = wr_array_val[0] & gate_fq; + assign bram1_wea = wr_array_val[1] & gate_fq; + assign bram2_wea = wr_array_val[1] & gate_fq; + + assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + assign bram2_addra[10 - NUM_ENTRY_LOG2:9] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + + assign bram0_addrb[9 - NUM_ENTRY_LOG2:8] = cam_hit_entry_q; + assign bram1_addrb[11 - NUM_ENTRY_LOG2:10] = cam_hit_entry_q; + assign bram2_addrb[10 - NUM_ENTRY_LOG2:9] = cam_hit_entry_q; + + // Unused Address Bits + assign bram0_addra[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; + assign bram0_addrb[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; + assign bram1_addra[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; + assign bram1_addrb[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; + assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; + assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; + + // This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) + // uses wr_array_val(0), parity is wr_array_data_bram(66:69) + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram0( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram0_addra), + .ADDRB(bram0_addrb), + .DIA(wr_array_data_bram[0:31]), + .DIB(32'b0), + .DOA(rd_array_data_d_std[0:31]), + .DOB(array_cmp_data_bram_std[0:31]), + .DOPA(rd_array_data_d_std[66:69]), + .DOPB(array_cmp_data_bramp_std[66:69]), + .DIPA(wr_array_data_bram[66:69]), + .DIPB(4'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram0_wea), + .WEB(1'b0) + ); + + // This ram houses the RPN(18:19),R,C,4xResv bits, wr_array_data_bram(32:39) + // uses wr_array_val(1), parity is wr_array_data_bram(70) + RAMB16_S9_S9 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram1( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram1_addra), + .ADDRB(bram1_addrb), + .DIA(wr_array_data_bram[32:39]), + .DIB(8'b0), + .DOA(rd_array_data_d_std[32:39]), + .DOB(array_cmp_data_bram_std[32:39]), + .DOPA(rd_array_data_d_std[70:70]), + .DOPB(array_cmp_data_bramp_std[70:70]), + .DIPA(wr_array_data_bram[70:70]), + .DIPB(1'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram1_wea), + .WEB(1'b0) + ); + + // This ram houses the 1xResv,U0-U3,WIMGE,UX,UW,UR,SX,SW,SR bits, wr_array_data_bram(40:55) + // uses wr_array_val(2), parity is wr_array_data_bram(71:72) + RAMB16_S18_S18 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram2( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram2_addra), + .ADDRB(bram2_addrb), + .DIA(wr_array_data_bram[40:55]), + .DIB(16'b0), + .DOA(rd_array_data_d_std[40:55]), + .DOB(array_cmp_data_bram_std[40:55]), + .DOPA(rd_array_data_d_std[71:72]), + .DOPB(array_cmp_data_bramp_std[71:72]), + .DIPA(wr_array_data_bram[71:72]), + .DIPB(2'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram2_wea), + .WEB(1'b0) + ); + + // array write data swizzle -> convert 68-bit data to 73-bit bram data + // 32x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:47 - UX,UW,UR + // 48:50 - SX,SW,SR + // 51:60 - CAM parity + // 61:67 - Array parity + // + // RTX layout in A2_AvpEratHelper.C + // ram0(0:31): 00 & RPN(0:29) + // ram1(0:7) : 00 & R,C,ResvAttr(0:3) + // ram2(0:15): '0' & U(0:3),WIMGE,UX,UW,UR,SX,SW,SR + assign wr_array_data_bram[0:72] = {2'b00, wr_array_data[0:29], 2'b00, wr_array_data[30:35], 1'b0, wr_array_data[36:50], wr_array_data[51:60], wr_array_data[61:67]}; + + assign rd_array_data_d_std[56:65] = 10'b0; // tie off unused bits + + assign rd_array_data_d[0:29] = rd_array_data_d_std[2:31]; + assign rd_array_data_d[30:35] = rd_array_data_d_std[34:39]; + assign rd_array_data_d[36:50] = rd_array_data_d_std[41:55]; + assign rd_array_data_d[61:67] = rd_array_data_d_std[66:72]; + assign array_cmp_data_bram = array_cmp_data_bram_std; + assign array_cmp_data_bramp = array_cmp_data_bramp_std; + + //--------------------------------------------------------------------- + // entity output assignments + //--------------------------------------------------------------------- + assign rd_array_data = rd_array_data_q; + assign cam_cmp_data = cam_cmp_data_q; + assign rd_cam_data = rd_cam_data_q; + + assign entry_valid[0] = entry0_v_q; + assign entry_valid[1] = entry1_v_q; + assign entry_valid[2] = entry2_v_q; + assign entry_valid[3] = entry3_v_q; + assign entry_valid[4] = entry4_v_q; + assign entry_valid[5] = entry5_v_q; + assign entry_valid[6] = entry6_v_q; + assign entry_valid[7] = entry7_v_q; + assign entry_valid[8] = entry8_v_q; + assign entry_valid[9] = entry9_v_q; + assign entry_valid[10] = entry10_v_q; + assign entry_valid[11] = entry11_v_q; + assign entry_valid[12] = entry12_v_q; + assign entry_valid[13] = entry13_v_q; + assign entry_valid[14] = entry14_v_q; + assign entry_valid[15] = entry15_v_q; + assign entry_valid[16] = entry16_v_q; + assign entry_valid[17] = entry17_v_q; + assign entry_valid[18] = entry18_v_q; + assign entry_valid[19] = entry19_v_q; + assign entry_valid[20] = entry20_v_q; + assign entry_valid[21] = entry21_v_q; + assign entry_valid[22] = entry22_v_q; + assign entry_valid[23] = entry23_v_q; + assign entry_valid[24] = entry24_v_q; + assign entry_valid[25] = entry25_v_q; + assign entry_valid[26] = entry26_v_q; + assign entry_valid[27] = entry27_v_q; + assign entry_valid[28] = entry28_v_q; + assign entry_valid[29] = entry29_v_q; + assign entry_valid[30] = entry30_v_q; + assign entry_valid[31] = entry31_v_q; + + assign entry_match = entry_match_q; + + assign cam_hit_entry = cam_hit_entry_q; + assign cam_hit = cam_hit_q; + + assign func_scan_out = func_scan_in; + assign regfile_scan_out = regfile_scan_in; + assign time_scan_out = time_scan_in; + + assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, + tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, + lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, + pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, pc_fce_2, array_cmp_data_bram[0:1], array_cmp_data_bram[32:33], + array_cmp_data_bram[40], wr_array_data_bram[56:65], + cam_cmp_data_np1[0:74], cam_cmp_data_np1[79:CAM_DATA_WIDTH-1], + rd_array_data_d_std[0:1], rd_array_data_d_std[32:33], + rd_array_data_d_std[40], rd_array_data_d_std[56:65], rd_val_late, wr_val_early}; +endmodule diff --git a/rel/src/verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v b/rel/src/verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v new file mode 100644 index 0000000..eee2d16 --- /dev/null +++ b/rel/src/verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v @@ -0,0 +1,471 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: D-ERAT CAM Match Line Logic for Functional Model +//* +//* NAME: tri_cam_32x143_1r1w1c_matchline +//* +//********************************************************************* + +module tri_cam_32x143_1r1w1c_matchline( + addr_in, + addr_enable, + comp_pgsize, + pgsize_enable, + entry_size, + entry_cmpmask, + entry_xbit, + entry_xbitmask, + entry_epn, + comp_class, + entry_class, + class_enable, + comp_extclass, + entry_extclass, + extclass_enable, + comp_state, + entry_hv, + entry_ds, + state_enable, + entry_thdid, + comp_thdid, + thdid_enable, + entry_pid, + comp_pid, + pid_enable, + entry_v, + comp_invalidate, + match +); + parameter HAVE_XBIT = 1; + parameter NUM_PGSIZES = 5; + parameter HAVE_CMPMASK = 1; + parameter CMPMASK_WIDTH = 4; + + // @{default:nclk}@ + input [0:51] addr_in; + input [0:1] addr_enable; + input [0:2] comp_pgsize; + input pgsize_enable; + input [0:2] entry_size; + input [0:CMPMASK_WIDTH-1] entry_cmpmask; + input entry_xbit; + input [0:CMPMASK_WIDTH-1] entry_xbitmask; + input [0:51] entry_epn; + input [0:1] comp_class; + input [0:1] entry_class; + input [0:2] class_enable; + input [0:1] comp_extclass; + input [0:1] entry_extclass; + input [0:1] extclass_enable; + input [0:1] comp_state; + input entry_hv; + input entry_ds; + input [0:1] state_enable; + input [0:3] entry_thdid; + input [0:3] comp_thdid; + input [0:1] thdid_enable; + input [0:7] entry_pid; + input [0:7] comp_pid; + input pid_enable; + input entry_v; + input comp_invalidate; + + output match; + + // tri_cam_32x143_1r1w1c_matchline + + //---------------------------------------------------------------------- + // Signals + //---------------------------------------------------------------------- + + wire [34:51] entry_epn_b; + wire function_50_51; + wire function_48_51; + wire function_46_51; + wire function_44_51; + wire function_40_51; + wire function_36_51; + wire function_34_51; + wire pgsize_eq_16K; + wire pgsize_eq_64K; + wire pgsize_eq_256K; + wire pgsize_eq_1M; + wire pgsize_eq_16M; + wire pgsize_eq_256M; + wire pgsize_eq_1G; + wire pgsize_gte_16K; + wire pgsize_gte_64K; + wire pgsize_gte_256K; + wire pgsize_gte_1M; + wire pgsize_gte_16M; + wire pgsize_gte_256M; + wire pgsize_gte_1G; + wire comp_or_34_35; + wire comp_or_34_39; + wire comp_or_36_39; + wire comp_or_40_43; + wire comp_or_44_45; + wire comp_or_44_47; + wire comp_or_46_47; + wire comp_or_48_49; + wire comp_or_48_51; + wire comp_or_50_51; + wire [0:72] match_line; + wire pgsize_match; + wire addr_match; + wire class_match; + wire extclass_match; + wire state_match; + wire thdid_match; + wire pid_match; + (* analysis_not_referenced="true" *) + wire [0:2] unused; + + assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^ + {addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]})); + + generate + begin + if (NUM_PGSIZES == 8) + begin : numpgsz8 + // tie off unused signals + assign comp_or_34_39 = 1'b0; + assign comp_or_44_47 = 1'b0; + assign comp_or_48_51 = 1'b0; + assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51}; + + assign entry_epn_b[34:51] = (~(entry_epn[34:51])); + + if (HAVE_CMPMASK == 0) + begin + assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & entry_size[2]); + assign pgsize_eq_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + assign pgsize_eq_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]); + assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))); + assign pgsize_eq_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]); + assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))); + assign pgsize_eq_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]); + + assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & entry_size[2]); + assign pgsize_gte_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_1G; + assign pgsize_gte_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_256M; + assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M; + assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M; + assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_256K; + assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_64K; + + assign unused[1] = |{entry_cmpmask, entry_xbitmask}; + end + + if (HAVE_CMPMASK == 1) + begin + // size entry_cmpmask: 0123456 + // 1GB 0000000 + // 256MB 1000000 + // 16MB 1100000 + // 1MB 1110000 + // 256KB 1111000 + // 64KB 1111100 + // 16KB 1111110 + // 4KB 1111111 + assign pgsize_gte_1G = (~entry_cmpmask[0]); + assign pgsize_gte_256M = (~entry_cmpmask[1]); + assign pgsize_gte_16M = (~entry_cmpmask[2]); + assign pgsize_gte_1M = (~entry_cmpmask[3]); + assign pgsize_gte_256K = (~entry_cmpmask[4]); + assign pgsize_gte_64K = (~entry_cmpmask[5]); + assign pgsize_gte_16K = (~entry_cmpmask[6]); + + // size entry_xbitmask: 0123456 + // 1GB 1000000 + // 256MB 0100000 + // 16MB 0010000 + // 1MB 0001000 + // 256KB 0000100 + // 64KB 0000010 + // 16KB 0000001 + // 4KB 0000000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_256M = entry_xbitmask[1]; + assign pgsize_eq_16M = entry_xbitmask[2]; + assign pgsize_eq_1M = entry_xbitmask[3]; + assign pgsize_eq_256K = entry_xbitmask[4]; + assign pgsize_eq_64K = entry_xbitmask[5]; + assign pgsize_eq_16K = entry_xbitmask[6]; + + assign unused[1] = 1'b0; + end + + if (HAVE_XBIT == 0) + begin + assign function_34_51 = 1'b0; + assign function_36_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_48_51 = 1'b0; + assign function_50_51 = 1'b0; + assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51, + function_46_51, function_48_51, function_50_51, entry_xbit, + entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M, + pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K}; + end + + if (HAVE_XBIT != 0) + begin + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51])); + assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51])); + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51])); + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51])); + assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51])); + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51])); + assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | (|(entry_epn_b[50:51] & addr_in[50:51])); + assign unused[2] = 1'b0; + end + + assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K; + assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K; + assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K; + assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M; + assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M; + assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M; + assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G; + + if (HAVE_XBIT == 0) + begin + assign addr_match = (comp_or_34_35 & // Ignore functions based on page size + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + + if (HAVE_XBIT != 0) + begin + assign addr_match = (function_50_51 & // Exclusion functions + function_48_51 & + function_46_51 & + function_44_51 & + function_40_51 & + function_36_51 & + function_34_51 & + comp_or_34_35 & // Ignore functions based on page size + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[31:33])) & // Regular compare largest page size + (&(match_line[0:30]) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + end // numpgsz8: NUM_PGSIZES = 8 + + + if (NUM_PGSIZES == 5) + begin : numpgsz5 + // tie off unused signals + assign function_50_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_36_51 = 1'b0; + assign pgsize_eq_16K = 1'b0; + assign pgsize_eq_256K = 1'b0; + assign pgsize_eq_256M = 1'b0; + assign pgsize_gte_16K = 1'b0; + assign pgsize_gte_256K = 1'b0; + assign pgsize_gte_256M = 1'b0; + assign comp_or_34_35 = 1'b0; + assign comp_or_36_39 = 1'b0; + assign comp_or_44_45 = 1'b0; + assign comp_or_46_47 = 1'b0; + assign comp_or_48_49 = 1'b0; + assign comp_or_50_51 = 1'b0; + assign unused[0] = |{function_50_51, function_46_51, function_36_51, + pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M, + pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M, + comp_or_34_35, comp_or_36_39, comp_or_44_45, + comp_or_46_47, comp_or_48_49, comp_or_50_51}; + + assign entry_epn_b[34:51] = (~(entry_epn[34:51])); + + if (HAVE_CMPMASK == 0) + begin + // 110 + assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + // 111 + assign pgsize_eq_16M = ( entry_size[0] & entry_size[1] & entry_size[2]); + // 101 + assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]); + // 011 + assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]); + + assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + assign pgsize_gte_16M = ( entry_size[0] & entry_size[1] & entry_size[2]) | pgsize_gte_1G; + assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M; + assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M; + + assign unused[1] = |{entry_cmpmask, entry_xbitmask}; + end + + if (HAVE_CMPMASK == 1) + begin + // size entry_cmpmask: 0123 + // 1GB 0000 + // 16MB 1000 + // 1MB 1100 + // 64KB 1110 + // 4KB 1111 + assign pgsize_gte_1G = (~entry_cmpmask[0]); + assign pgsize_gte_16M = (~entry_cmpmask[1]); + assign pgsize_gte_1M = (~entry_cmpmask[2]); + assign pgsize_gte_64K = (~entry_cmpmask[3]); + + // size entry_xbitmask: 0123 + // 1GB 1000 + // 16MB 0100 + // 1MB 0010 + // 64KB 0001 + // 4KB 0000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_16M = entry_xbitmask[1]; + assign pgsize_eq_1M = entry_xbitmask[2]; + assign pgsize_eq_64K = entry_xbitmask[3]; + + assign unused[1] = 1'b0; + end + + if (HAVE_XBIT == 0) + begin + assign function_34_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_48_51 = 1'b0; + assign unused[2] = |{function_34_51, function_40_51, function_44_51, + function_48_51, entry_xbit, entry_epn_b, + pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K}; + end + + if (HAVE_XBIT != 0) + begin + // 1G + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51])); + // 16M + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51])); + // 1M + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51])); + // 64K + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51])); + assign unused[2] = 1'b0; + end + + assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K; + assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M; + assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M; + assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G; + + if (HAVE_XBIT == 0) + begin + assign addr_match = (comp_or_34_39 & // Ignore functions based on page size + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + + if (HAVE_XBIT != 0) + begin + assign addr_match = (function_48_51 & + function_44_51 & + function_40_51 & + function_34_51 & + comp_or_34_39 & // Ignore functions based on page size + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + end // numpgsz5: NUM_PGSIZES = 5 + + + assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable)); + + assign class_match = (match_line[55] | (~(class_enable[0]))) & + (match_line[56] | (~(class_enable[1]))) & + ((&(match_line[55:56])) | (~(class_enable[2])) | + ((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit + + assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) & // iprot bit + (match_line[58] | (~(extclass_enable[1]))); // pid_nz bit + + assign state_match = (match_line[59] | (~(state_enable[0]))) & + (match_line[60] | (~(state_enable[1]))); + + assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) & + (&(match_line[69:72]) | (~(thdid_enable[1])) | + ((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit + + assign pid_match = (&(match_line[61:68])) | + // entry_pid=0 ignores pid match for compares, + // but not for invalidates. + ((~(entry_extclass[1])) & (~comp_invalidate)) | // pid_nz bit + (~(pid_enable)); + + assign match = addr_match & // Address compare + pgsize_match & // Size compare + class_match & // Class compare + extclass_match & // ExtClass compare + state_match & // State compare + thdid_match & // ThdID compare + pid_match & // PID compare + entry_v; // Valid + end + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_csa22.v b/rel/src/verilog/trilib/tri_csa22.v new file mode 100644 index 0000000..1a5f6ad --- /dev/null +++ b/rel/src/verilog/trilib/tri_csa22.v @@ -0,0 +1,53 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//***************************************************************************** +// Description: XU Population Count +// +//***************************************************************************** + +module tri_csa22( + a, + b, + car, + sum +); + input a; + input b; + output car; + output sum; + + wire car_b; + wire sum_b; + + assign car_b = (~(a & b)); + assign sum_b = (~(car_b & (a | b))); // this is equiv to an xnor + assign car = (~car_b); + assign sum = (~sum_b); + +endmodule diff --git a/rel/src/verilog/trilib/tri_csa32.v b/rel/src/verilog/trilib/tri_csa32.v new file mode 100644 index 0000000..cead546 --- /dev/null +++ b/rel/src/verilog/trilib/tri_csa32.v @@ -0,0 +1,65 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +module tri_csa32( + a, + b, + c, + car, + sum, + vd, + gd +); + input a; + input b; + input c; + output car; + output sum; + (* ANALYSIS_NOT_ASSIGNED="TRUE" *) + (* ANALYSIS_NOT_REFERENCED="TRUE" *) + inout vd; + (* ANALYSIS_NOT_ASSIGNED="TRUE" *) + (* ANALYSIS_NOT_REFERENCED="TRUE" *) + inout gd; + + wire carn1; + wire carn2; + wire carn3; + +// assign sum = a ^ b ^ c; + tri_xor3 CSA42_XOR3_1(sum, a, b, c); + +// assign car = (a & b) | (a & c) | (b & c); + tri_nand2 CSA42_NAND2_1(carn1, a, b); + tri_nand2 CSA42_NAND2_2(carn2, a, c); + tri_nand2 CSA42_NAND2_3(carn3, b, c); + tri_nand3 CSA42_NAND3_4(car, carn1, carn2, carn3); + + +endmodule diff --git a/rel/src/verilog/trilib/tri_csa42.v b/rel/src/verilog/trilib/tri_csa42.v new file mode 100644 index 0000000..7610260 --- /dev/null +++ b/rel/src/verilog/trilib/tri_csa42.v @@ -0,0 +1,85 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +module tri_csa42( + a, + b, + c, + d, + ki, + ko, + car, + sum, + vd, + gd +); + input a; + input b; + input c; + input d; + input ki; + output ko; + output car; + output sum; + (* ANALYSIS_NOT_ASSIGNED="TRUE" *) + (* ANALYSIS_NOT_REFERENCED="TRUE" *) + inout vd; + (* ANALYSIS_NOT_ASSIGNED="TRUE" *) + (* ANALYSIS_NOT_REFERENCED="TRUE" *) + inout gd; + + wire s1; + + wire carn1; + wire carn2; + wire carn3; + wire kon1; + wire kon2; + wire kon3; + +// assign s1 = b ^ c ^ d; + tri_xor3 CSA42_XOR3_1(s1,b,c,d); + +// assign sum = s1 ^ a ^ ki; + tri_xor3 CSA42_XOR3_2(sum,s1,a,ki); + +// assign car = (s1 & a) | (s1 & ki) | (a & ki); + tri_nand2 CSA42_NAND2_1(carn1,s1,a); + tri_nand2 CSA42_NAND2_2(carn2,s1,ki); + tri_nand2 CSA42_NAND2_3(carn3,a,ki); + tri_nand3 CSA42_NAND3_4(car,carn1,carn2,carn3); + +// assign ko = (b & c) | (b & d) | (c & d); + tri_nand2 CSA42_NAND2_5(kon1,b,c); + tri_nand2 CSA42_NAND2_6(kon2,b,d); + tri_nand2 CSA42_NAND2_7(kon3,c,d); + tri_nand3 CSA42_NAND3_8(ko,kon1,kon2,kon3); + + +endmodule diff --git a/rel/src/verilog/trilib/tri_debug_mux16.v b/rel/src/verilog/trilib/tri_debug_mux16.v new file mode 100644 index 0000000..f64b1c9 --- /dev/null +++ b/rel/src/verilog/trilib/tri_debug_mux16.v @@ -0,0 +1,157 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: Debug Mux Component (16:1 Debug Groups; 4:1 Trigger Groups) +//* +//* NAME: tri_debug_mux16.vhdl +//* +//******************************************************************** + +module tri_debug_mux16( +// vd, +// gd, + select_bits, + dbg_group0, + dbg_group1, + dbg_group2, + dbg_group3, + dbg_group4, + dbg_group5, + dbg_group6, + dbg_group7, + dbg_group8, + dbg_group9, + dbg_group10, + dbg_group11, + dbg_group12, + dbg_group13, + dbg_group14, + dbg_group15, + trace_data_in, + trace_data_out, + // Instruction Trace (HTM) Controls + coretrace_ctrls_in, + coretrace_ctrls_out +); + +// Include model build parameters + parameter DBG_WIDTH = 32; // A2o=32; A2i=88 + +//===================================================================== +// Port Definitions +//===================================================================== + + input [0:10] select_bits; + input [0:DBG_WIDTH-1] dbg_group0; + input [0:DBG_WIDTH-1] dbg_group1; + input [0:DBG_WIDTH-1] dbg_group2; + input [0:DBG_WIDTH-1] dbg_group3; + input [0:DBG_WIDTH-1] dbg_group4; + input [0:DBG_WIDTH-1] dbg_group5; + input [0:DBG_WIDTH-1] dbg_group6; + input [0:DBG_WIDTH-1] dbg_group7; + input [0:DBG_WIDTH-1] dbg_group8; + input [0:DBG_WIDTH-1] dbg_group9; + input [0:DBG_WIDTH-1] dbg_group10; + input [0:DBG_WIDTH-1] dbg_group11; + input [0:DBG_WIDTH-1] dbg_group12; + input [0:DBG_WIDTH-1] dbg_group13; + input [0:DBG_WIDTH-1] dbg_group14; + input [0:DBG_WIDTH-1] dbg_group15; + input [0:DBG_WIDTH-1] trace_data_in; + output [0:DBG_WIDTH-1] trace_data_out; + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in; + output [0:3] coretrace_ctrls_out; + +//===================================================================== +// Signal Declarations / Misc +//===================================================================== + parameter DBG_1FOURTH = DBG_WIDTH/4; + parameter DBG_2FOURTH = DBG_WIDTH/2; + parameter DBG_3FOURTH = 3 * DBG_WIDTH/4; + + wire [0:DBG_WIDTH-1] debug_grp_selected; + wire [0:DBG_WIDTH-1] debug_grp_rotated; + +// Don't reference unused inputs: +(* analysis_not_referenced="true" *) + wire unused; + assign unused = select_bits[4]; + +// Instruction Trace controls are passed-through: + assign coretrace_ctrls_out = coretrace_ctrls_in ; + +//===================================================================== +// Mux Function +//===================================================================== + // Debug Mux + assign debug_grp_selected = (select_bits[0:3] == 4'b0000) ? dbg_group0 : + (select_bits[0:3] == 4'b0001) ? dbg_group1 : + (select_bits[0:3] == 4'b0010) ? dbg_group2 : + (select_bits[0:3] == 4'b0011) ? dbg_group3 : + (select_bits[0:3] == 4'b0100) ? dbg_group4 : + (select_bits[0:3] == 4'b0101) ? dbg_group5 : + (select_bits[0:3] == 4'b0110) ? dbg_group6 : + (select_bits[0:3] == 4'b0111) ? dbg_group7 : + (select_bits[0:3] == 4'b1000) ? dbg_group8 : + (select_bits[0:3] == 4'b1001) ? dbg_group9 : + (select_bits[0:3] == 4'b1010) ? dbg_group10 : + (select_bits[0:3] == 4'b1011) ? dbg_group11 : + (select_bits[0:3] == 4'b1100) ? dbg_group12 : + (select_bits[0:3] == 4'b1101) ? dbg_group13 : + (select_bits[0:3] == 4'b1110) ? dbg_group14 : + dbg_group15; + + assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} : + (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} : + (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} : + debug_grp_selected[0:DBG_WIDTH - 1]; + + + assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] : + debug_grp_rotated[0:DBG_1FOURTH - 1]; + + assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] : + debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1]; + + assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] : + debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1]; + + assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] : + debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1]; + + +endmodule + diff --git a/rel/src/verilog/trilib/tri_debug_mux32.v b/rel/src/verilog/trilib/tri_debug_mux32.v new file mode 100644 index 0000000..8eb4ebf --- /dev/null +++ b/rel/src/verilog/trilib/tri_debug_mux32.v @@ -0,0 +1,202 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: Debug Mux Component (32:1 Debug Groups; 4:1 Trigger Groups) +//* +//* NAME: tri_debug_mux32.vhdl +//* +//******************************************************************** + + +module tri_debug_mux32( +// vd, +// gd, + select_bits, + dbg_group0, + dbg_group1, + dbg_group2, + dbg_group3, + dbg_group4, + dbg_group5, + dbg_group6, + dbg_group7, + dbg_group8, + dbg_group9, + dbg_group10, + dbg_group11, + dbg_group12, + dbg_group13, + dbg_group14, + dbg_group15, + dbg_group16, + dbg_group17, + dbg_group18, + dbg_group19, + dbg_group20, + dbg_group21, + dbg_group22, + dbg_group23, + dbg_group24, + dbg_group25, + dbg_group26, + dbg_group27, + dbg_group28, + dbg_group29, + dbg_group30, + dbg_group31, + trace_data_in, + trace_data_out, + + // Instruction Trace (HTM) Controls + coretrace_ctrls_in, + coretrace_ctrls_out +); + +// Include model build parameters + parameter DBG_WIDTH = 32; // A2o=32; A2i=88 + +//===================================================================== +// Port Definitions +//===================================================================== + + input [0:10] select_bits; + input [0:DBG_WIDTH-1] dbg_group0; + input [0:DBG_WIDTH-1] dbg_group1; + input [0:DBG_WIDTH-1] dbg_group2; + input [0:DBG_WIDTH-1] dbg_group3; + input [0:DBG_WIDTH-1] dbg_group4; + input [0:DBG_WIDTH-1] dbg_group5; + input [0:DBG_WIDTH-1] dbg_group6; + input [0:DBG_WIDTH-1] dbg_group7; + input [0:DBG_WIDTH-1] dbg_group8; + input [0:DBG_WIDTH-1] dbg_group9; + input [0:DBG_WIDTH-1] dbg_group10; + input [0:DBG_WIDTH-1] dbg_group11; + input [0:DBG_WIDTH-1] dbg_group12; + input [0:DBG_WIDTH-1] dbg_group13; + input [0:DBG_WIDTH-1] dbg_group14; + input [0:DBG_WIDTH-1] dbg_group15; + input [0:DBG_WIDTH-1] dbg_group16; + input [0:DBG_WIDTH-1] dbg_group17; + input [0:DBG_WIDTH-1] dbg_group18; + input [0:DBG_WIDTH-1] dbg_group19; + input [0:DBG_WIDTH-1] dbg_group20; + input [0:DBG_WIDTH-1] dbg_group21; + input [0:DBG_WIDTH-1] dbg_group22; + input [0:DBG_WIDTH-1] dbg_group23; + input [0:DBG_WIDTH-1] dbg_group24; + input [0:DBG_WIDTH-1] dbg_group25; + input [0:DBG_WIDTH-1] dbg_group26; + input [0:DBG_WIDTH-1] dbg_group27; + input [0:DBG_WIDTH-1] dbg_group28; + input [0:DBG_WIDTH-1] dbg_group29; + input [0:DBG_WIDTH-1] dbg_group30; + input [0:DBG_WIDTH-1] dbg_group31; + input [0:DBG_WIDTH-1] trace_data_in; + output [0:DBG_WIDTH-1] trace_data_out; + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in; + output [0:3] coretrace_ctrls_out; + +//===================================================================== +// Signal Declarations / Misc +//===================================================================== + parameter DBG_1FOURTH = DBG_WIDTH/4; + parameter DBG_2FOURTH = DBG_WIDTH/2; + parameter DBG_3FOURTH = 3 * DBG_WIDTH/4; + + wire [0:DBG_WIDTH-1] debug_grp_selected; + wire [0:DBG_WIDTH-1] debug_grp_rotated; + +// Instruction Trace controls are passed-through: + assign coretrace_ctrls_out = coretrace_ctrls_in ; + +//===================================================================== +// Mux Function +//===================================================================== + // Debug Mux + assign debug_grp_selected = (select_bits[0:4] == 5'b00000) ? dbg_group0 : + (select_bits[0:4] == 5'b00001) ? dbg_group1 : + (select_bits[0:4] == 5'b00010) ? dbg_group2 : + (select_bits[0:4] == 5'b00011) ? dbg_group3 : + (select_bits[0:4] == 5'b00100) ? dbg_group4 : + (select_bits[0:4] == 5'b00101) ? dbg_group5 : + (select_bits[0:4] == 5'b00110) ? dbg_group6 : + (select_bits[0:4] == 5'b00111) ? dbg_group7 : + (select_bits[0:4] == 5'b01000) ? dbg_group8 : + (select_bits[0:4] == 5'b01001) ? dbg_group9 : + (select_bits[0:4] == 5'b01010) ? dbg_group10 : + (select_bits[0:4] == 5'b01011) ? dbg_group11 : + (select_bits[0:4] == 5'b01100) ? dbg_group12 : + (select_bits[0:4] == 5'b01101) ? dbg_group13 : + (select_bits[0:4] == 5'b01110) ? dbg_group14 : + (select_bits[0:4] == 5'b01111) ? dbg_group15 : + (select_bits[0:4] == 5'b10000) ? dbg_group16 : + (select_bits[0:4] == 5'b10001) ? dbg_group17 : + (select_bits[0:4] == 5'b10010) ? dbg_group18 : + (select_bits[0:4] == 5'b10011) ? dbg_group19 : + (select_bits[0:4] == 5'b10100) ? dbg_group20 : + (select_bits[0:4] == 5'b10101) ? dbg_group21 : + (select_bits[0:4] == 5'b10110) ? dbg_group22 : + (select_bits[0:4] == 5'b10111) ? dbg_group23 : + (select_bits[0:4] == 5'b11000) ? dbg_group24 : + (select_bits[0:4] == 5'b11001) ? dbg_group25 : + (select_bits[0:4] == 5'b11010) ? dbg_group26 : + (select_bits[0:4] == 5'b11011) ? dbg_group27 : + (select_bits[0:4] == 5'b11100) ? dbg_group28 : + (select_bits[0:4] == 5'b11101) ? dbg_group29 : + (select_bits[0:4] == 5'b11110) ? dbg_group30 : + dbg_group31; + + assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} : + (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} : + (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} : + debug_grp_selected[0:DBG_WIDTH - 1]; + + + assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] : + debug_grp_rotated[0:DBG_1FOURTH - 1]; + + assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] : + debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1]; + + assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] : + debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1]; + + assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] : + debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1]; + + +endmodule + diff --git a/rel/src/verilog/trilib/tri_debug_mux4.v b/rel/src/verilog/trilib/tri_debug_mux4.v new file mode 100644 index 0000000..8f71b60 --- /dev/null +++ b/rel/src/verilog/trilib/tri_debug_mux4.v @@ -0,0 +1,122 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: Debug Mux Component (4:1 Debug Groups; 4:1 Trigger Groups) +//* +//* NAME: tri_debug_mux4.vhdl +//* +//******************************************************************** + + +module tri_debug_mux4( +// vd, +// gd, + select_bits, + dbg_group0, + dbg_group1, + dbg_group2, + dbg_group3, + trace_data_in, + trace_data_out, + + // Instruction Trace (HTM) Controls + coretrace_ctrls_in, + coretrace_ctrls_out +); + +// Include model build parameters + parameter DBG_WIDTH = 32; // A2o=32; A2i=88 + +//===================================================================== +// Port Definitions +//===================================================================== + + input [0:10] select_bits; + input [0:DBG_WIDTH-1] dbg_group0; + input [0:DBG_WIDTH-1] dbg_group1; + input [0:DBG_WIDTH-1] dbg_group2; + input [0:DBG_WIDTH-1] dbg_group3; + input [0:DBG_WIDTH-1] trace_data_in; + output [0:DBG_WIDTH-1] trace_data_out; + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in; + output [0:3] coretrace_ctrls_out; + +//===================================================================== +// Signal Declarations / Misc +//===================================================================== + parameter DBG_1FOURTH = DBG_WIDTH/4; + parameter DBG_2FOURTH = DBG_WIDTH/2; + parameter DBG_3FOURTH = 3 * DBG_WIDTH/4; + + wire [0:DBG_WIDTH-1] debug_grp_selected; + wire [0:DBG_WIDTH-1] debug_grp_rotated; + +// Don't reference unused inputs: +(* analysis_not_referenced="true" *) + wire unused; + assign unused = (|select_bits[2:4]) ; + +// Instruction Trace controls are passed-through: + assign coretrace_ctrls_out = coretrace_ctrls_in ; + +//===================================================================== +// Mux Function +//===================================================================== + // Debug Mux + assign debug_grp_selected = (select_bits[0:1] == 2'b00) ? dbg_group0 : + (select_bits[0:1] == 2'b01) ? dbg_group1 : + (select_bits[0:1] == 2'b10) ? dbg_group2 : + dbg_group3; + + assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} : + (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} : + (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} : + debug_grp_selected[0:DBG_WIDTH - 1]; + + + assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] : + debug_grp_rotated[0:DBG_1FOURTH - 1]; + + assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] : + debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1]; + + assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] : + debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1]; + + assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] : + debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1]; + + +endmodule diff --git a/rel/src/verilog/trilib/tri_debug_mux8.v b/rel/src/verilog/trilib/tri_debug_mux8.v new file mode 100644 index 0000000..e30bbe6 --- /dev/null +++ b/rel/src/verilog/trilib/tri_debug_mux8.v @@ -0,0 +1,132 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: Debug Mux Component (8:1 Debug Groups; 4:1 Trigger Groups) +//* +//* NAME: tri_debug_mux8.vhdl +//* +//******************************************************************** + +module tri_debug_mux8( +// vd, +// gd, + select_bits, + dbg_group0, + dbg_group1, + dbg_group2, + dbg_group3, + dbg_group4, + dbg_group5, + dbg_group6, + dbg_group7, + trace_data_in, + trace_data_out, + // Instruction Trace (HTM) Controls + coretrace_ctrls_in, + coretrace_ctrls_out +); + +// Include model build parameters + parameter DBG_WIDTH = 32; // A2o=32; A2i=88 + +//===================================================================== +// Port Definitions +//===================================================================== + + input [0:10] select_bits; + input [0:DBG_WIDTH-1] dbg_group0; + input [0:DBG_WIDTH-1] dbg_group1; + input [0:DBG_WIDTH-1] dbg_group2; + input [0:DBG_WIDTH-1] dbg_group3; + input [0:DBG_WIDTH-1] dbg_group4; + input [0:DBG_WIDTH-1] dbg_group5; + input [0:DBG_WIDTH-1] dbg_group6; + input [0:DBG_WIDTH-1] dbg_group7; + input [0:DBG_WIDTH-1] trace_data_in; + output [0:DBG_WIDTH-1] trace_data_out; + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in; + output [0:3] coretrace_ctrls_out; + +//===================================================================== +// Signal Declarations / Misc +//===================================================================== + parameter DBG_1FOURTH = DBG_WIDTH/4; + parameter DBG_2FOURTH = DBG_WIDTH/2; + parameter DBG_3FOURTH = 3 * DBG_WIDTH/4; + + wire [0:DBG_WIDTH-1] debug_grp_selected; + wire [0:DBG_WIDTH-1] debug_grp_rotated; + +// Don't reference unused inputs: +(* analysis_not_referenced="true" *) + wire unused; + assign unused = (|select_bits[3:4]) ; + +// Instruction Trace controls are passed-through: + assign coretrace_ctrls_out = coretrace_ctrls_in ; + +//===================================================================== +// Mux Function +//===================================================================== + // Debug Mux + + assign debug_grp_selected = (select_bits[0:2] == 3'b000) ? dbg_group0 : + (select_bits[0:2] == 3'b001) ? dbg_group1 : + (select_bits[0:2] == 3'b010) ? dbg_group2 : + (select_bits[0:2] == 3'b011) ? dbg_group3 : + (select_bits[0:2] == 3'b100) ? dbg_group4 : + (select_bits[0:2] == 3'b101) ? dbg_group5 : + (select_bits[0:2] == 3'b110) ? dbg_group6 : + dbg_group7; + + assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} : + (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} : + (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} : + debug_grp_selected[0:DBG_WIDTH - 1]; + + + assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] : + debug_grp_rotated[0:DBG_1FOURTH - 1]; + + assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] : + debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1]; + + assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] : + debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1]; + + assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] : + debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1]; + +endmodule diff --git a/rel/src/verilog/trilib/tri_direct_err_rpt.v b/rel/src/verilog/trilib/tri_direct_err_rpt.v new file mode 100644 index 0000000..4ad6b15 --- /dev/null +++ b/rel/src/verilog/trilib/tri_direct_err_rpt.v @@ -0,0 +1,57 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_direct_err_rpt.v +// *! DESCRIPTION : Error Reporting Component +// *!**************************************************************** + +module tri_direct_err_rpt( + vd, + gd, + err_in, + err_out +); + parameter WIDTH = 1; // use to bundle error reporting checkers of the same exact type + inout vd; + inout gd; + + input [0:WIDTH-1] err_in; + output [0:WIDTH-1] err_out; + + // tri_direct_err_rpt + + (* analysis_not_referenced="true" *) + wire unused; + + assign unused = vd | gd; + + assign err_out = err_in; +endmodule diff --git a/rel/src/verilog/trilib/tri_eccchk.v b/rel/src/verilog/trilib/tri_eccchk.v new file mode 100644 index 0000000..82976c2 --- /dev/null +++ b/rel/src/verilog/trilib/tri_eccchk.v @@ -0,0 +1,284 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU ECC Check Macro +// +//***************************************************************************** + +module tri_eccchk( + din, + encorr, + nsyn, + corrd, + sbe, + ue +); + + parameter REGSIZE = 64; + + input [0:REGSIZE-1] din; + input encorr; + input [0:8-(64/REGSIZE)] nsyn; + output [0:REGSIZE-1] corrd; + output sbe; + output ue; + + generate // syndrome bits inverted + if (REGSIZE == 64) + begin : ecc64 + wire [0:7] syn; + wire [0:71] DcdD; // decode data bits + wire synzero; + wire sbe_int; + wire [0:3] A0to1; + wire [0:3] A2to3; + wire [0:3] A4to5; + wire [0:2] A6to7; + + // ==================================================================== + // 64 Data Bits, 8 Check bits + // Single bit error correction, Double bit error detection + // ==================================================================== + // ECC Matrix Description + // ==================================================================== + // Syn 0 111011010011101001100101101101001100101101001011001101001110100110000000 + // Syn 1 110110101011010101010101011010101010101010101010101010101101010101000000 + // Syn 2 101101100110110011001100110110011001100110011001100110011011001100100000 + // Syn 3 011100011110001111000011110001111000011110000111100001111000111100010000 + // Syn 4 000011111110000000111111110000000111111110000000011111111000000000001000 + // Syn 5 000000000001111111111111110000000000000001111111111111111000000000000100 + // Syn 6 000000000000000000000000001111111111111111111111111111111000000000000010 + // Syn 7 000000000000000000000000000000000000000000000000000000000111111100000001 + + assign syn = (~nsyn[0:7]); + + assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr)); + assign A0to1[1] = (~(nsyn[0] & syn[1] & encorr)); + assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr)); + assign A0to1[3] = (~( syn[0] & syn[1] & encorr)); + + assign A2to3[0] = (~(nsyn[2] & nsyn[3])); + assign A2to3[1] = (~(nsyn[2] & syn[3])); + assign A2to3[2] = (~( syn[2] & nsyn[3])); + assign A2to3[3] = (~( syn[2] & syn[3])); + + assign A4to5[0] = (~(nsyn[4] & nsyn[5])); + assign A4to5[1] = (~(nsyn[4] & syn[5])); + assign A4to5[2] = (~( syn[4] & nsyn[5])); + assign A4to5[3] = (~( syn[4] & syn[5])); + + assign A6to7[0] = (~(nsyn[6] & nsyn[7])); + assign A6to7[1] = (~(nsyn[6] & syn[7])); + assign A6to7[2] = (~( syn[6] & nsyn[7])); + //assign A6to7[3] = (~( syn[6] & syn[7])); + + assign DcdD[0] = (~(A0to1[3] | A2to3[2] | A4to5[0] | A6to7[0])); // 11 10 00 00 + assign DcdD[1] = (~(A0to1[3] | A2to3[1] | A4to5[0] | A6to7[0])); // 11 01 00 00 + assign DcdD[2] = (~(A0to1[2] | A2to3[3] | A4to5[0] | A6to7[0])); // 10 11 00 00 + assign DcdD[3] = (~(A0to1[1] | A2to3[3] | A4to5[0] | A6to7[0])); // 01 11 00 00 + assign DcdD[4] = (~(A0to1[3] | A2to3[0] | A4to5[2] | A6to7[0])); // 11 00 10 00 + assign DcdD[5] = (~(A0to1[2] | A2to3[2] | A4to5[2] | A6to7[0])); // 10 10 10 00 + assign DcdD[6] = (~(A0to1[1] | A2to3[2] | A4to5[2] | A6to7[0])); // 01 10 10 00 + assign DcdD[7] = (~(A0to1[2] | A2to3[1] | A4to5[2] | A6to7[0])); // 10 01 10 00 + assign DcdD[8] = (~(A0to1[1] | A2to3[1] | A4to5[2] | A6to7[0])); // 01 01 10 00 + assign DcdD[9] = (~(A0to1[0] | A2to3[3] | A4to5[2] | A6to7[0])); // 00 11 10 00 + assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to5[2] | A6to7[0])); // 11 11 10 00 + assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to5[1] | A6to7[0])); // 11 00 01 00 + assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to5[1] | A6to7[0])); // 10 10 01 00 + assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to5[1] | A6to7[0])); // 01 10 01 00 + assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to5[1] | A6to7[0])); // 10 01 01 00 + assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to5[1] | A6to7[0])); // 01 01 01 00 + assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to5[1] | A6to7[0])); // 00 11 01 00 + assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to5[1] | A6to7[0])); // 11 11 01 00 + assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to5[3] | A6to7[0])); // 10 00 11 00 + assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to5[3] | A6to7[0])); // 01 00 11 00 + assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to5[3] | A6to7[0])); // 00 10 11 00 + assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to5[3] | A6to7[0])); // 11 10 11 00 + assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to5[3] | A6to7[0])); // 00 01 11 00 + assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to5[3] | A6to7[0])); // 11 01 11 00 + assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to5[3] | A6to7[0])); // 10 11 11 00 + assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to5[3] | A6to7[0])); // 01 11 11 00 + assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[2])); // 11 00 00 10 + assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[2])); // 10 10 00 10 + assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[2])); // 01 10 00 10 + assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[2])); // 10 01 00 10 + assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[2])); // 01 01 00 10 + assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[2])); // 00 11 00 10 + assign DcdD[32] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[2])); // 11 11 00 10 + assign DcdD[33] = (~(A0to1[2] | A2to3[0] | A4to5[2] | A6to7[2])); // 10 00 10 10 + assign DcdD[34] = (~(A0to1[1] | A2to3[0] | A4to5[2] | A6to7[2])); // 01 00 10 10 + assign DcdD[35] = (~(A0to1[0] | A2to3[2] | A4to5[2] | A6to7[2])); // 00 10 10 10 + assign DcdD[36] = (~(A0to1[3] | A2to3[2] | A4to5[2] | A6to7[2])); // 11 10 10 10 + assign DcdD[37] = (~(A0to1[0] | A2to3[1] | A4to5[2] | A6to7[2])); // 00 01 10 10 + assign DcdD[38] = (~(A0to1[3] | A2to3[1] | A4to5[2] | A6to7[2])); // 11 01 10 10 + assign DcdD[39] = (~(A0to1[2] | A2to3[3] | A4to5[2] | A6to7[2])); // 10 11 10 10 + assign DcdD[40] = (~(A0to1[1] | A2to3[3] | A4to5[2] | A6to7[2])); // 01 11 10 10 + assign DcdD[41] = (~(A0to1[2] | A2to3[0] | A4to5[1] | A6to7[2])); // 10 00 01 10 + assign DcdD[42] = (~(A0to1[1] | A2to3[0] | A4to5[1] | A6to7[2])); // 01 00 01 10 + assign DcdD[43] = (~(A0to1[0] | A2to3[2] | A4to5[1] | A6to7[2])); // 00 10 01 10 + assign DcdD[44] = (~(A0to1[3] | A2to3[2] | A4to5[1] | A6to7[2])); // 11 10 01 10 + assign DcdD[45] = (~(A0to1[0] | A2to3[1] | A4to5[1] | A6to7[2])); // 00 01 01 10 + assign DcdD[46] = (~(A0to1[3] | A2to3[1] | A4to5[1] | A6to7[2])); // 11 01 01 10 + assign DcdD[47] = (~(A0to1[2] | A2to3[3] | A4to5[1] | A6to7[2])); // 10 11 01 10 + assign DcdD[48] = (~(A0to1[1] | A2to3[3] | A4to5[1] | A6to7[2])); // 01 11 01 10 + assign DcdD[49] = (~(A0to1[0] | A2to3[0] | A4to5[3] | A6to7[2])); // 00 00 11 10 + assign DcdD[50] = (~(A0to1[3] | A2to3[0] | A4to5[3] | A6to7[2])); // 11 00 11 10 + assign DcdD[51] = (~(A0to1[2] | A2to3[2] | A4to5[3] | A6to7[2])); // 10 10 11 10 + assign DcdD[52] = (~(A0to1[1] | A2to3[2] | A4to5[3] | A6to7[2])); // 01 10 11 10 + assign DcdD[53] = (~(A0to1[2] | A2to3[1] | A4to5[3] | A6to7[2])); // 10 01 11 10 + assign DcdD[54] = (~(A0to1[1] | A2to3[1] | A4to5[3] | A6to7[2])); // 01 01 11 10 + assign DcdD[55] = (~(A0to1[0] | A2to3[3] | A4to5[3] | A6to7[2])); // 00 11 11 10 + assign DcdD[56] = (~(A0to1[3] | A2to3[3] | A4to5[3] | A6to7[2])); // 11 11 11 10 + assign DcdD[57] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[1])); // 11 00 00 01 + assign DcdD[58] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[1])); // 10 10 00 01 + assign DcdD[59] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[1])); // 01 10 00 01 + assign DcdD[60] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[1])); // 10 01 00 01 + assign DcdD[61] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[1])); // 01 01 00 01 + assign DcdD[62] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[1])); // 00 11 00 01 + assign DcdD[63] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[1])); // 11 11 00 01 + assign DcdD[64] = (~(A0to1[2] | A2to3[0] | A4to5[0] | A6to7[0])); // 10 00 00 00 + assign DcdD[65] = (~(A0to1[1] | A2to3[0] | A4to5[0] | A6to7[0])); // 01 00 00 00 + assign DcdD[66] = (~(A0to1[0] | A2to3[2] | A4to5[0] | A6to7[0])); // 00 10 00 00 + assign DcdD[67] = (~(A0to1[0] | A2to3[1] | A4to5[0] | A6to7[0])); // 00 01 00 00 + assign DcdD[68] = (~(A0to1[0] | A2to3[0] | A4to5[2] | A6to7[0])); // 00 00 10 00 + assign DcdD[69] = (~(A0to1[0] | A2to3[0] | A4to5[1] | A6to7[0])); // 00 00 01 00 + assign DcdD[70] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[2])); // 00 00 00 10 + assign DcdD[71] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[1])); // 00 00 00 01 + assign synzero = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[0])); // 00 00 00 00 + + assign corrd[0:63] = din[0:63] ^ DcdD[0:63]; + + assign sbe_int = (DcdD[0:71] != {72{1'b0}}) ? 1'b1 : + 1'b0; + assign sbe = sbe_int; + assign ue = (~sbe_int) & (~synzero) & encorr; + end + endgenerate + + generate // syndrome bits inverted + if (REGSIZE == 32) + begin : ecc32 + wire [0:6] syn; + wire [0:38] DcdD; // decode data bits + wire synzero; + wire sbe_int; + wire [0:3] A0to1; + wire [0:3] A2to3; + wire [0:7] A4to6; + + // ==================================================================== + // 32 Data Bits, 7 Check bits + // Single bit error correction, Double bit error detection + // ==================================================================== + // ECC Matrix Description + // ==================================================================== + // Syn 0 111011010011101001100101101101001000000 + // Syn 1 110110101011010101010101011010100100000 + // Syn 2 101101100110110011001100110110010010000 + // Syn 3 011100011110001111000011110001110001000 + // Syn 4 000011111110000000111111110000000000100 + // Syn 5 000000000001111111111111110000000000010 + // Syn 6 000000000000000000000000001111110000001 + + assign syn = (~nsyn[0:6]); + + assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr)); + assign A0to1[1] = (~(nsyn[0] & syn[1] & encorr)); + assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr)); + assign A0to1[3] = (~( syn[0] & syn[1] & encorr)); + + assign A2to3[0] = (~(nsyn[2] & nsyn[3])); + assign A2to3[1] = (~(nsyn[2] & syn[3])); + assign A2to3[2] = (~( syn[2] & nsyn[3])); + assign A2to3[3] = (~( syn[2] & syn[3])); + + assign A4to6[0] = (~(nsyn[4] & nsyn[5] & nsyn[6])); + assign A4to6[1] = (~(nsyn[4] & nsyn[5] & syn[6])); + assign A4to6[2] = (~(nsyn[4] & syn[5] & nsyn[6])); + assign A4to6[3] = (~(nsyn[4] & syn[5] & syn[6])); + assign A4to6[4] = (~( syn[4] & nsyn[5] & nsyn[6])); + assign A4to6[5] = (~( syn[4] & nsyn[5] & syn[6])); + assign A4to6[6] = (~( syn[4] & syn[5] & nsyn[6])); + assign A4to6[7] = (~( syn[4] & syn[5] & syn[6])); + + assign DcdD[0] = (~(A0to1[3] | A2to3[2] | A4to6[0])); // 11 10 000 + assign DcdD[1] = (~(A0to1[3] | A2to3[1] | A4to6[0])); // 11 01 000 + assign DcdD[2] = (~(A0to1[2] | A2to3[3] | A4to6[0])); // 10 11 000 + assign DcdD[3] = (~(A0to1[1] | A2to3[3] | A4to6[0])); // 01 11 000 + assign DcdD[4] = (~(A0to1[3] | A2to3[0] | A4to6[4])); // 11 00 100 + assign DcdD[5] = (~(A0to1[2] | A2to3[2] | A4to6[4])); // 10 10 100 + assign DcdD[6] = (~(A0to1[1] | A2to3[2] | A4to6[4])); // 01 10 100 + assign DcdD[7] = (~(A0to1[2] | A2to3[1] | A4to6[4])); // 10 01 100 + assign DcdD[8] = (~(A0to1[1] | A2to3[1] | A4to6[4])); // 01 01 100 + assign DcdD[9] = (~(A0to1[0] | A2to3[3] | A4to6[4])); // 00 11 100 + assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to6[4])); // 11 11 100 + assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to6[2])); // 11 00 010 + assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to6[2])); // 10 10 010 + assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to6[2])); // 01 10 010 + assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to6[2])); // 10 01 010 + assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to6[2])); // 01 01 010 + assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to6[2])); // 00 11 010 + assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to6[2])); // 11 11 010 + assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to6[6])); // 10 00 110 + assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to6[6])); // 01 00 110 + assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to6[6])); // 00 10 110 + assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to6[6])); // 11 10 110 + assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to6[6])); // 00 01 110 + assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to6[6])); // 11 01 110 + assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to6[6])); // 10 11 110 + assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to6[6])); // 01 11 110 + assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to6[1])); // 11 00 001 + assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to6[1])); // 10 10 001 + assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to6[1])); // 01 10 001 + assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to6[1])); // 10 01 001 + assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to6[1])); // 01 01 001 + assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to6[1])); // 00 11 001 + assign DcdD[32] = (~(A0to1[2] | A2to3[0] | A4to6[0])); // 10 00 000 + assign DcdD[33] = (~(A0to1[1] | A2to3[0] | A4to6[0])); // 01 00 000 + assign DcdD[34] = (~(A0to1[0] | A2to3[2] | A4to6[0])); // 00 10 000 + assign DcdD[35] = (~(A0to1[0] | A2to3[1] | A4to6[0])); // 00 01 000 + assign DcdD[36] = (~(A0to1[0] | A2to3[0] | A4to6[4])); // 00 00 100 + assign DcdD[37] = (~(A0to1[0] | A2to3[0] | A4to6[2])); // 00 00 010 + assign DcdD[38] = (~(A0to1[0] | A2to3[0] | A4to6[1])); // 00 00 001 + assign synzero = (~(A0to1[0] | A2to3[0] | A4to6[0])); // 00 00 000 + + assign corrd[0:31] = din[0:31] ^ DcdD[0:31]; + + assign sbe_int = (DcdD[0:38] != {39{1'b0}}) ? 1'b1 : + 1'b0; + assign sbe = sbe_int; + assign ue = (~sbe_int) & (~synzero) & encorr; + + //mark_unused(A4to6(3)); + //mark_unused(A4to6(5)); + //mark_unused(A4to6(7)); + end + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_eccgen.v b/rel/src/verilog/trilib/tri_eccgen.v new file mode 100644 index 0000000..e6199cd --- /dev/null +++ b/rel/src/verilog/trilib/tri_eccgen.v @@ -0,0 +1,145 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU ECC Generation Macro +// +//***************************************************************************** + +module tri_eccgen( + din, + syn +); + parameter REGSIZE = 64; + input [0:REGSIZE+8-(64/REGSIZE)] din; + output [0:8-(64/REGSIZE)] syn; + + generate // syndrome bits inverted + if (REGSIZE == 64) + begin : ecc64 + wire [0:71] e; + wire [0:22] l1term; + + // ==================================================================== + // 64 data bits, 8 check bits + // single bit error correction, double bit error detection + // ==================================================================== + // ecc matrix description + // ==================================================================== + // syn 0 111011010011101001100101101101001100101101001011001101001110100110000000 + // syn 1 110110101011010101010101011010101010101010101010101010101101010101000000 + // syn 2 101101100110110011001100110110011001100110011001100110011011001100100000 + // syn 3 011100011110001111000011110001111000011110000111100001111000111100010000 + // syn 4 000011111110000000111111110000000111111110000000011111111000000000001000 + // syn 5 000000000001111111111111110000000000000001111111111111111000000000000100 + // syn 6 000000000000000000000000001111111111111111111111111111111000000000000010 + // syn 7 000000000000000000000000000000000000000000000000000000000111111100000001 + + assign e[0:71] = din[0:71]; + + assign l1term[0] = e[0] ^ e[10] ^ e[17] ^ e[21] ^ e[32] ^ e[36] ^ e[44] ^ e[56]; + assign l1term[1] = e[22] ^ e[23] ^ e[24] ^ e[25] ^ e[53] ^ e[54] ^ e[55] ^ e[56]; + assign l1term[2] = e[1] ^ e[4] ^ e[11] ^ e[23] ^ e[26] ^ e[38] ^ e[46] ^ e[50]; + assign l1term[3] = e[2] ^ e[5] ^ e[12] ^ e[24] ^ e[27] ^ e[39] ^ e[47] ^ e[51]; + assign l1term[4] = e[3] ^ e[6] ^ e[13] ^ e[25] ^ e[28] ^ e[40] ^ e[48] ^ e[52]; + assign l1term[5] = e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[37] ^ e[38] ^ e[39] ^ e[40]; + assign l1term[6] = e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[45] ^ e[46] ^ e[47] ^ e[48]; + assign l1term[7] = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[49] ^ e[50] ^ e[51] ^ e[52]; + assign l1term[8] = e[7] ^ e[14] ^ e[18] ^ e[29] ^ e[33] ^ e[41] ^ e[53] ^ e[57]; + assign l1term[9] = e[58] ^ e[60] ^ e[63] ^ e[64]; + assign l1term[10] = e[8] ^ e[15] ^ e[19] ^ e[30] ^ e[34] ^ e[42] ^ e[54] ^ e[57]; + assign l1term[11] = e[59] ^ e[61] ^ e[63] ^ e[65]; + assign l1term[12] = e[9] ^ e[16] ^ e[20] ^ e[31] ^ e[35] ^ e[43] ^ e[55] ^ e[58]; + assign l1term[13] = e[59] ^ e[62] ^ e[63] ^ e[66]; + assign l1term[14] = e[1] ^ e[2] ^ e[3] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[60]; + assign l1term[15] = e[61] ^ e[62] ^ e[63] ^ e[67]; + assign l1term[16] = e[4] ^ e[5] ^ e[6] ^ e[33] ^ e[34] ^ e[35] ^ e[36] ^ e[68]; + assign l1term[17] = e[11] ^ e[12] ^ e[13] ^ e[41] ^ e[42] ^ e[43] ^ e[44] ^ e[69]; + assign l1term[18] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[33]; + assign l1term[19] = e[34] ^ e[35] ^ e[36] ^ e[37] ^ e[38] ^ e[39] ^ e[40] ^ e[41]; + assign l1term[20] = e[42] ^ e[43] ^ e[44] ^ e[45] ^ e[46] ^ e[47] ^ e[48] ^ e[49]; + assign l1term[21] = e[50] ^ e[51] ^ e[52] ^ e[53] ^ e[54] ^ e[55] ^ e[56] ^ e[70]; + assign l1term[22] = e[57] ^ e[58] ^ e[59] ^ e[60] ^ e[61] ^ e[62] ^ e[63] ^ e[71]; + assign syn[0] = l1term[0] ^ l1term[2] ^ l1term[3] ^ l1term[8] ^ l1term[9]; + assign syn[1] = l1term[0] ^ l1term[2] ^ l1term[4] ^ l1term[10] ^ l1term[11]; + assign syn[2] = l1term[0] ^ l1term[3] ^ l1term[4] ^ l1term[12] ^ l1term[13]; + assign syn[3] = l1term[1] ^ l1term[5] ^ l1term[6] ^ l1term[14] ^ l1term[15]; + assign syn[4] = l1term[1] ^ l1term[5] ^ l1term[7] ^ l1term[16]; + assign syn[5] = l1term[1] ^ l1term[6] ^ l1term[7] ^ l1term[17]; + assign syn[6] = l1term[18] ^ l1term[19] ^ l1term[20] ^ l1term[21]; + assign syn[7] = l1term[22]; + end + endgenerate + + generate // syndrome bits inverted + if (REGSIZE == 32) + begin : ecc32 + wire [0:38] e; + wire [0:13] l1term; + + // ==================================================================== + // 32 Data Bits, 7 Check bits + // Single bit error correction, Double bit error detection + // ==================================================================== + // ECC Matrix Description + // ==================================================================== + // Syn 0 111011010011101001100101101101001000000 + // Syn 1 110110101011010101010101011010100100000 + // Syn 2 101101100110110011001100110110010010000 + // Syn 3 011100011110001111000011110001110001000 + // Syn 4 000011111110000000111111110000000000100 + // Syn 5 000000000001111111111111110000000000010 + // Syn 6 000000000000000000000000001111110000001 + + assign e[0:38] = din[0:38]; + + assign l1term[0] = e[0] ^ e[1] ^ e[4] ^ e[10] ^ e[11] ^ e[17] ^ e[21] ^ e[23]; + assign l1term[1] = e[2] ^ e[3] ^ e[9] ^ e[10] ^ e[16] ^ e[17] ^ e[24] ^ e[25]; + assign l1term[2] = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[22] ^ e[23] ^ e[24] ^ e[25]; + assign l1term[3] = e[2] ^ e[5] ^ e[7] ^ e[12] ^ e[14] ^ e[18] ^ e[24] ^ e[26]; + assign l1term[4] = e[27] ^ e[29] ^ e[32]; + assign l1term[5] = e[3] ^ e[6] ^ e[8] ^ e[13] ^ e[15] ^ e[19] ^ e[25] ^ e[26]; + assign l1term[6] = e[28] ^ e[30] ^ e[33]; + assign l1term[7] = e[0] ^ e[5] ^ e[6] ^ e[12] ^ e[13] ^ e[20] ^ e[21] ^ e[27]; + assign l1term[8] = e[28] ^ e[31] ^ e[34]; + assign l1term[9] = e[1] ^ e[7] ^ e[8] ^ e[14] ^ e[15] ^ e[22] ^ e[23] ^ e[29]; + assign l1term[10] = e[30] ^ e[31] ^ e[35]; + assign l1term[11] = e[4] ^ e[5] ^ e[6] ^ e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[36]; + assign l1term[12] = e[11] ^ e[12] ^ e[13] ^ e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[37]; + assign l1term[13] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[38]; + assign syn[0] = l1term[0] ^ l1term[3] ^ l1term[4]; + assign syn[1] = l1term[0] ^ l1term[5] ^ l1term[6]; + assign syn[2] = l1term[1] ^ l1term[7] ^ l1term[8]; + assign syn[3] = l1term[1] ^ l1term[9] ^ l1term[10]; + assign syn[4] = l1term[2] ^ l1term[11]; + assign syn[5] = l1term[2] ^ l1term[12]; + assign syn[6] = l1term[13]; + end + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_err_rpt.v b/rel/src/verilog/trilib/tri_err_rpt.v new file mode 100644 index 0000000..19f2e46 --- /dev/null +++ b/rel/src/verilog/trilib/tri_err_rpt.v @@ -0,0 +1,142 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_err_rpt.v +// *! DESCRIPTION : Error Reporting Component +// *!**************************************************************** + +`include "tri.vh" + +module tri_err_rpt( + vd, + gd, + err_d1clk, + err_d2clk, + err_lclk, + err_scan_in, + err_scan_out, + mode_dclk, + mode_lclk, + mode_scan_in, + mode_scan_out, + err_in, + err_out, + hold_out, + mask_out +); + parameter WIDTH = 1; // number of errors of the same type + parameter MASK_RESET_VALUE = 1'b0; // use to set default/flush value for mask bits + parameter INLINE = 1'b0; // make hold latch be inline; err_out is sticky -- default to shadow + parameter SHARE_MASK = 1'b0; // PERMISSION NEEDED for true + // used for WIDTH >1 to reduce area of mask (common error disable) + parameter USE_NLATS = 1'b0; // only necessary in standby area to be able to reset to init value + parameter NEEDS_SRESET = 1; // for inferred latches + + inout vd; + inout gd; + input err_d1clk; // caution1: if lcb uses powersavings, errors must always get reported + input err_d2clk; // caution2: if use_nlats is used these are also the clocks for the mask latches + input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks + // caution2: and all bits in the "func" chain have to be connected to the mode chain + // error scan chain (func or mode) + input [0:WIDTH-1] err_scan_in; // NOTE: connected to mode or func ring + output [0:WIDTH-1] err_scan_out; + // clock gateable mode clocks + input mode_dclk; + input [0:`NCLK_WIDTH-1] mode_lclk; + // mode scan chain + input [0:WIDTH-1] mode_scan_in; + output [0:WIDTH-1] mode_scan_out; + + input [0:WIDTH-1] err_in; + output [0:WIDTH-1] err_out; + + output [0:WIDTH-1] hold_out; // sticky error hold latch for trap usage + output [0:WIDTH-1] mask_out; + + // tri_err_rpt + + parameter [0:WIDTH-1] mask_initv = MASK_RESET_VALUE; + wire [0:WIDTH-1] hold_in; + wire [0:WIDTH-1] hold_lt; + wire [0:WIDTH-1] mask_lt; + (* analysis_not_referenced="true" *) + wire unused; + wire [0:WIDTH-1] unused_q_b; + // hold latches + assign hold_in = err_in | hold_lt; + + tri_nlat_scan #(.WIDTH(WIDTH), .NEEDS_SRESET(NEEDS_SRESET)) + hold( + .vd(vd), + .gd(gd), + .d1clk(err_d1clk), + .d2clk(err_d2clk), + .lclk(err_lclk), + .scan_in(err_scan_in[0:WIDTH - 1]), + .scan_out(err_scan_out[0:WIDTH - 1]), + .din(hold_in), + .q(hold_lt), + .q_b(unused_q_b) + ); + + generate + begin + // mask + if (SHARE_MASK == 1'b0) + begin : m + assign mask_lt = mask_initv; + end + if (SHARE_MASK == 1'b1) + begin : sm + assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}}; + end + + assign mode_scan_out = {WIDTH{1'b0}}; + + // assign outputs + assign hold_out = hold_lt; + assign mask_out = mask_lt; + + if (INLINE == 1'b1) + begin : inline_hold + assign err_out = hold_lt & (~mask_lt); + end + + if (INLINE == 1'b0) + begin : side_hold + assign err_out = err_in & (~mask_lt); + end + + assign unused = | {mode_dclk, mode_lclk, mode_scan_in, unused_q_b}; + end + endgenerate +endmodule diff --git a/rel/src/verilog/trilib/tri_event_mux1t.v b/rel/src/verilog/trilib/tri_event_mux1t.v new file mode 100644 index 0000000..f864cf5 --- /dev/null +++ b/rel/src/verilog/trilib/tri_event_mux1t.v @@ -0,0 +1,164 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: Performance Event Mux Component - 1 Thread; 4 bits +//* +//* NAME: tri_event_mux1t.v +//* +//******************************************************************** + +module tri_event_mux1t( + vd, + gd, + select_bits, + unit_events_in, + event_bus_in, + event_bus_out +); + parameter EVENTS_IN = 32; // Valid Settings: 16; 32; 64 + parameter EVENTS_OUT = 4; // Valid Settings: 4 outputs per event mux + // Select bit size depends on total events: 16 events=16, 32 events=20; 64 events=24 + input [0:((EVENTS_IN/32+4)*EVENTS_OUT)-1] select_bits; + + input [1:EVENTS_IN-1] unit_events_in; + + input [0:EVENTS_OUT-1] event_bus_in; + + output [0:EVENTS_OUT-1] event_bus_out; + + inout vd; + + inout gd; + + +//===================================================================== +// Signal and Function Declarations +//===================================================================== +// Constants used to split up select_bits for the decoder +// Mux Size: 16 32 64 + parameter INCR = EVENTS_IN/32 + 4; // INCR: 4 5 6 + + // For each output bit decode select bits to select an input mux to use. + wire [0:EVENTS_OUT*EVENTS_IN-1] inMuxDec; + wire [0:EVENTS_OUT*EVENTS_IN-1] inMuxOut; + +// Paramaterized decoder function - decode mux value based on input select_bits +// Input size based on EVENTS_IN parameter: 16=4, 32=5, 64=6 + function [0:EVENTS_IN-1] decode_a; + input [0:INCR-1] decode_input; + (* analysis_not_referenced="true" *) + integer i; + + for(i=0; i s_neg(0) , --i-- + // SX => s_x(0) , --i-- + // SX2 => s_x2(0) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(0) , --i-- [n+1] + // LEFT => left_xtd_2(0) , --o-- [n] + // Q => xtd_2_sub(0)); --o-- + + + tri_fu_mul_bthrow bm_00( + .s_neg(s_neg[0]), //i-- + .s_x(s_x[0]), //i-- + .s_x2(s_x2[0]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_00[4:58]), //o-- + .hot_one(hot_one_din) //o-- + ); + + //-------------------------------------------------------------------------- + + assign pp0_01[4] = tiup; + assign pp0_01[5] = xtd_2_add[1]; + + assign xtd_2_add[1] = (~(s_neg[1] & (s_x[1] | s_x2[1]))); + // sx_01_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(1) , --i-- + // SX => s_x(1) , --i-- + // SX2 => s_x2(1) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(1) , --i-- [n+1] + // LEFT => left_xtd_2(1) , --o-- [n] + // Q => xtd_2_sub(1)); --o-- + + + tri_fu_mul_bthrow bm_01( + .s_neg(s_neg[1]), //i-- + .s_x(s_x[1]), //i-- + .s_x2(s_x2[1]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_01[6:60]), //o-- + .hot_one(pp0_00[60]) //i-- + ); + assign pp0_00[59] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_02[6] = tiup; + assign pp0_02[7] = xtd_2_add[2]; + + assign xtd_2_add[2] = (~(s_neg[2] & (s_x[2] | s_x2[2]))); + // sx_02_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(2) , --i-- + // SX => s_x(2) , --i-- + // SX2 => s_x2(2) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(2) , --i-- [n+1] + // LEFT => left_xtd_2(2) , --o-- [n] + // Q => xtd_2_sub(2)); --o-- + + + tri_fu_mul_bthrow bm_02( + .s_neg(s_neg[2]), //i-- + .s_x(s_x[2]), //i-- + .s_x2(s_x2[2]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_02[8:62]), //o-- + .hot_one(pp0_01[62]) //i-- + ); + assign pp0_01[61] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_03[8] = tiup; + assign pp0_03[9] = xtd_2_add[3]; + + assign xtd_2_add[3] = (~(s_neg[3] & (s_x[3] | s_x2[3]))); + // sx_03_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(3) , --i-- + // SX => s_x(3) , --i-- + // SX2 => s_x2(3) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(3) , --i-- [n+1] + // LEFT => left_xtd_2(3) , --o-- [n] + // Q => xtd_2_sub(3)); --o-- + + + tri_fu_mul_bthrow bm_03( + .s_neg(s_neg[3]), //i-- + .s_x(s_x[3]), //i-- + .s_x2(s_x2[3]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_03[10:64]), //o-- + .hot_one(pp0_02[64]) //i-- + ); + assign pp0_02[63] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_04[10] = tiup; + assign pp0_04[11] = xtd_2_add[4]; + + assign xtd_2_add[4] = (~(s_neg[4] & (s_x[4] | s_x2[4]))); + // sx_04_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(4) , --i-- + // SX => s_x(4) , --i-- + // SX2 => s_x2(4) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(4) , --i-- [n+1] + // LEFT => left_xtd_2(4) , --o-- [n] + // Q => xtd_2_sub(4)); --o-- + + + tri_fu_mul_bthrow bm_04( + .s_neg(s_neg[4]), //i-- + .s_x(s_x[4]), //i-- + .s_x2(s_x2[4]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_04[12:66]), //o-- + .hot_one(pp0_03[66]) //i-- + ); + assign pp0_03[65] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_05[12] = tiup; + assign pp0_05[13] = xtd_2_add[5]; + + assign xtd_2_add[5] = (~(s_neg[5] & (s_x[5] | s_x2[5]))); + // sx_05_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(5) , --i-- + // SX => s_x(5) , --i-- + // SX2 => s_x2(5) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(5) , --i-- [n+1] + // LEFT => left_xtd_2(5) , --o-- [n] + // Q => xtd_2_sub(5)); --o-- + + + tri_fu_mul_bthrow bm_05( + .s_neg(s_neg[5]), //i-- + .s_x(s_x[5]), //i-- + .s_x2(s_x2[5]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_05[14:68]), //o-- + .hot_one(pp0_04[68]) //i-- + ); + assign pp0_04[67] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_06[14] = tiup; + assign pp0_06[15] = xtd_2_add[6]; + + assign xtd_2_add[6] = (~(s_neg[6] & (s_x[6] | s_x2[6]))); + // sx_06_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(6) , --i-- + // SX => s_x(6) , --i-- + // SX2 => s_x2(6) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(6) , --i-- [n+1] + // LEFT => left_xtd_2(6) , --o-- [n] + // Q => xtd_2_sub(6)); --o-- + + + tri_fu_mul_bthrow bm_06( + .s_neg(s_neg[6]), //i-- + .s_x(s_x[6]), //i-- + .s_x2(s_x2[6]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_06[16:70]), //o-- + .hot_one(pp0_05[70]) //i-- + ); + assign pp0_05[69] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_07[16] = tiup; + assign pp0_07[17] = xtd_2_add[7]; + + assign xtd_2_add[7] = (~(s_neg[7] & (s_x[7] | s_x2[7]))); + // sx_07_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(7) , --i-- + // SX => s_x(7) , --i-- + // SX2 => s_x2(7) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(7) , --i-- [n+1] + // LEFT => left_xtd_2(7) , --o-- [n] + // Q => xtd_2_sub(7)); --o-- + + + tri_fu_mul_bthrow bm_07( + .s_neg(s_neg[7]), //i-- + .s_x(s_x[7]), //i-- + .s_x2(s_x2[7]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_07[18:72]), //o-- + .hot_one(pp0_06[72]) //i-- + ); + assign pp0_06[71] = tidn; + + //-------------------------------------------------------------------------- + // LSB ROW OF LSB 9:2 HAS unique sign extension + //-------------------------------------------------------------------------- + + // to get a "1" ctl_s=1 ctl_a=1 + // to get a "0" ctl_s=0 ctl_a=0 + // to get a "A" ctl_s=0 ctl_a=1 + // to get a "S" ctl_s=1 ctl_a=0 + + // ctl_lsb_92_b <= not ctl_lsb_92; + + ///####################################################################### + ///# this is the unique part for the 3 version of tri_fu_mul_92 + ///# MSB/LSB sx_08_0 sx_08_1 sx_08_2 + ///# mul_92_0 10 '0' '1' Add + ///# mul_92_1 00 '0' '1' Add + ///# mul_92_2 01 Add Sub Sub + ///####################################################################### + + generate + if (inst == 0) + begin : g0 + //inst.0 + assign pp0_08[17] = tidn; // inst.0 + assign pp0_08[18] = tiup; // inst.0 + assign pp0_08[19] = (~(s_neg[8] & (s_x[8] | s_x2[8]))); // inst.0 + end + endgenerate + + generate + if (inst == 1) + begin : g1 + //inst.0 + assign pp0_08[17] = tidn; // inst.0 + assign pp0_08[18] = tiup; // inst.0 + assign pp0_08[19] = (~(s_neg[8] & (s_x[8] | s_x2[8]))); // inst.0 + end + endgenerate + + generate + if (inst == 2) + begin : g2 + //inst.2 + //inst.2 + //inst.2 + assign pp0_08[17] = (~(s_neg[8] & (s_x[8] | s_x2[8]))); // inst.2 + assign pp0_08[18] = (s_neg[8] & (s_x[8] | s_x2[8])); // inst.2 + assign pp0_08[19] = (s_neg[8] & (s_x[8] | s_x2[8])); // inst.2 + end + endgenerate + + + tri_fu_mul_bthrow bm_08( + .s_neg(s_neg[8]), //i-- + .s_x(s_x[8]), //i-- + .s_x2(s_x2[8]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_08[20:74]), //o-- + .hot_one(pp0_07[74]) //i-- + ); + assign pp0_07[73] = tidn; + + ////################################################## + ////# Compressor Level 1 + ////################################################## + + ////########################################################### + ////# LEON CHART + ////########################################################### + // o: no logic done on the signal + // c: carry + // u: sum + // h: hot1 + // H: hot 1 latched + // s: sign + // a: ! sign + // d: data from the booth muxes + // wWW: 01a / ass + // Kz: 1a / 00 + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# 0 ..zzddddddddddddddddddddddddddddddddddddddddddddddddddddddd0h................................................ + ////# 1 ....1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.............................................. + ////# 2 ......1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h............................................ + ////# 3 ........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.......................................... + ////# 4 ..........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h........................................ + ////# 5 ............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h...................................... + ////# 6 ..............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................... + ////# 7 ................1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................. + ////# 8 .................wWWddddddddddddddddddddddddddddddddddddddddddddddddddddddd0h................................ + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# 8 .................wWWddddddddddddddddddddddddddddddddddddddddddddddddddddddd.................................. pp0_08 + ////# 7 ................1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................. pp0_07 + ////# 6 ..............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................... pp0_06 + ////# ------------------------------------------------------------------------------------- + ////# ................233333333333333333333333333333333333333333333333333333323.... + ////# ...............ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo................................. pp1_05 + ////# ..............occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o................................. pp1_04 + + assign pp1_05[74] = pp0_08[74]; + assign pp1_05[73] = pp0_08[73]; + + assign pp1_04[74] = pp0_07[74]; + assign pp1_04[73] = tidn; + assign pp1_04[72] = tidn; + + + tri_csa32 pp1_02_csa_72( + .vd(vdd), + .gd(gnd), + .a(pp0_08[72]), //i-- + .b(pp0_07[72]), //i-- + .c(pp0_06[72]), //i-- + .sum(pp1_05[72]), //o-- + .car(pp1_04[71]) //o-- + ); + + tri_fu_csa22_h2 pp1_02_csa_71( + .a(pp0_08[71]), //i-- + .b(pp0_07[71]), //i-- + .sum(pp1_05[71]), //o-- + .car(pp1_04[70]) //o-- + ); + + tri_csa32 pp1_02_csa_70( + .vd(vdd), + .gd(gnd), + .a(pp0_08[70]), //i-- + .b(pp0_07[70]), //i-- + .c(pp0_06[70]), //i-- + .sum(pp1_05[70]), //o-- + .car(pp1_04[69]) //o-- + ); + + tri_csa32 pp1_02_csa_69( + .vd(vdd), + .gd(gnd), + .a(pp0_08[69]), //i-- + .b(pp0_07[69]), //i-- + .c(pp0_06[69]), //i-- + .sum(pp1_05[69]), //o-- + .car(pp1_04[68]) //o-- + ); + + tri_csa32 pp1_02_csa_68( + .vd(vdd), + .gd(gnd), + .a(pp0_08[68]), //i-- + .b(pp0_07[68]), //i-- + .c(pp0_06[68]), //i-- + .sum(pp1_05[68]), //o-- + .car(pp1_04[67]) //o-- + ); + + tri_csa32 pp1_02_csa_67( + .vd(vdd), + .gd(gnd), + .a(pp0_08[67]), //i-- + .b(pp0_07[67]), //i-- + .c(pp0_06[67]), //i-- + .sum(pp1_05[67]), //o-- + .car(pp1_04[66]) //o-- + ); + + tri_csa32 pp1_02_csa_66( + .vd(vdd), + .gd(gnd), + .a(pp0_08[66]), //i-- + .b(pp0_07[66]), //i-- + .c(pp0_06[66]), //i-- + .sum(pp1_05[66]), //o-- + .car(pp1_04[65]) //o-- + ); + + tri_csa32 pp1_02_csa_65( + .vd(vdd), + .gd(gnd), + .a(pp0_08[65]), //i-- + .b(pp0_07[65]), //i-- + .c(pp0_06[65]), //i-- + .sum(pp1_05[65]), //o-- + .car(pp1_04[64]) //o-- + ); + + tri_csa32 pp1_02_csa_64( + .vd(vdd), + .gd(gnd), + .a(pp0_08[64]), //i-- + .b(pp0_07[64]), //i-- + .c(pp0_06[64]), //i-- + .sum(pp1_05[64]), //o-- + .car(pp1_04[63]) //o-- + ); + + tri_csa32 pp1_02_csa_63( + .vd(vdd), + .gd(gnd), + .a(pp0_08[63]), //i-- + .b(pp0_07[63]), //i-- + .c(pp0_06[63]), //i-- + .sum(pp1_05[63]), //o-- + .car(pp1_04[62]) //o-- + ); + + tri_csa32 pp1_02_csa_62( + .vd(vdd), + .gd(gnd), + .a(pp0_08[62]), //i-- + .b(pp0_07[62]), //i-- + .c(pp0_06[62]), //i-- + .sum(pp1_05[62]), //o-- + .car(pp1_04[61]) //o-- + ); + + tri_csa32 pp1_02_csa_61( + .vd(vdd), + .gd(gnd), + .a(pp0_08[61]), //i-- + .b(pp0_07[61]), //i-- + .c(pp0_06[61]), //i-- + .sum(pp1_05[61]), //o-- + .car(pp1_04[60]) //o-- + ); + + tri_csa32 pp1_02_csa_60( + .vd(vdd), + .gd(gnd), + .a(pp0_08[60]), //i-- + .b(pp0_07[60]), //i-- + .c(pp0_06[60]), //i-- + .sum(pp1_05[60]), //o-- + .car(pp1_04[59]) //o-- + ); + + tri_csa32 pp1_02_csa_59( + .vd(vdd), + .gd(gnd), + .a(pp0_08[59]), //i-- + .b(pp0_07[59]), //i-- + .c(pp0_06[59]), //i-- + .sum(pp1_05[59]), //o-- + .car(pp1_04[58]) //o-- + ); + + tri_csa32 pp1_02_csa_58( + .vd(vdd), + .gd(gnd), + .a(pp0_08[58]), //i-- + .b(pp0_07[58]), //i-- + .c(pp0_06[58]), //i-- + .sum(pp1_05[58]), //o-- + .car(pp1_04[57]) //o-- + ); + + tri_csa32 pp1_02_csa_57( + .vd(vdd), + .gd(gnd), + .a(pp0_08[57]), //i-- + .b(pp0_07[57]), //i-- + .c(pp0_06[57]), //i-- + .sum(pp1_05[57]), //o-- + .car(pp1_04[56]) //o-- + ); + + tri_csa32 pp1_02_csa_56( + .vd(vdd), + .gd(gnd), + .a(pp0_08[56]), //i-- + .b(pp0_07[56]), //i-- + .c(pp0_06[56]), //i-- + .sum(pp1_05[56]), //o-- + .car(pp1_04[55]) //o-- + ); + + tri_csa32 pp1_02_csa_55( + .vd(vdd), + .gd(gnd), + .a(pp0_08[55]), //i-- + .b(pp0_07[55]), //i-- + .c(pp0_06[55]), //i-- + .sum(pp1_05[55]), //o-- + .car(pp1_04[54]) //o-- + ); + + tri_csa32 pp1_02_csa_54( + .vd(vdd), + .gd(gnd), + .a(pp0_08[54]), //i-- + .b(pp0_07[54]), //i-- + .c(pp0_06[54]), //i-- + .sum(pp1_05[54]), //o-- + .car(pp1_04[53]) //o-- + ); + + tri_csa32 pp1_02_csa_53( + .vd(vdd), + .gd(gnd), + .a(pp0_08[53]), //i-- + .b(pp0_07[53]), //i-- + .c(pp0_06[53]), //i-- + .sum(pp1_05[53]), //o-- + .car(pp1_04[52]) //o-- + ); + + tri_csa32 pp1_02_csa_52( + .vd(vdd), + .gd(gnd), + .a(pp0_08[52]), //i-- + .b(pp0_07[52]), //i-- + .c(pp0_06[52]), //i-- + .sum(pp1_05[52]), //o-- + .car(pp1_04[51]) //o-- + ); + + tri_csa32 pp1_02_csa_51( + .vd(vdd), + .gd(gnd), + .a(pp0_08[51]), //i-- + .b(pp0_07[51]), //i-- + .c(pp0_06[51]), //i-- + .sum(pp1_05[51]), //o-- + .car(pp1_04[50]) //o-- + ); + + tri_csa32 pp1_02_csa_50( + .vd(vdd), + .gd(gnd), + .a(pp0_08[50]), //i-- + .b(pp0_07[50]), //i-- + .c(pp0_06[50]), //i-- + .sum(pp1_05[50]), //o-- + .car(pp1_04[49]) //o-- + ); + + tri_csa32 pp1_02_csa_49( + .vd(vdd), + .gd(gnd), + .a(pp0_08[49]), //i-- + .b(pp0_07[49]), //i-- + .c(pp0_06[49]), //i-- + .sum(pp1_05[49]), //o-- + .car(pp1_04[48]) //o-- + ); + + tri_csa32 pp1_02_csa_48( + .vd(vdd), + .gd(gnd), + .a(pp0_08[48]), //i-- + .b(pp0_07[48]), //i-- + .c(pp0_06[48]), //i-- + .sum(pp1_05[48]), //o-- + .car(pp1_04[47]) //o-- + ); + + tri_csa32 pp1_02_csa_47( + .vd(vdd), + .gd(gnd), + .a(pp0_08[47]), //i-- + .b(pp0_07[47]), //i-- + .c(pp0_06[47]), //i-- + .sum(pp1_05[47]), //o-- + .car(pp1_04[46]) //o-- + ); + + tri_csa32 pp1_02_csa_46( + .vd(vdd), + .gd(gnd), + .a(pp0_08[46]), //i-- + .b(pp0_07[46]), //i-- + .c(pp0_06[46]), //i-- + .sum(pp1_05[46]), //o-- + .car(pp1_04[45]) //o-- + ); + + tri_csa32 pp1_02_csa_45( + .vd(vdd), + .gd(gnd), + .a(pp0_08[45]), //i-- + .b(pp0_07[45]), //i-- + .c(pp0_06[45]), //i-- + .sum(pp1_05[45]), //o-- + .car(pp1_04[44]) //o-- + ); + + tri_csa32 pp1_02_csa_44( + .vd(vdd), + .gd(gnd), + .a(pp0_08[44]), //i-- + .b(pp0_07[44]), //i-- + .c(pp0_06[44]), //i-- + .sum(pp1_05[44]), //o-- + .car(pp1_04[43]) //o-- + ); + + tri_csa32 pp1_02_csa_43( + .vd(vdd), + .gd(gnd), + .a(pp0_08[43]), //i-- + .b(pp0_07[43]), //i-- + .c(pp0_06[43]), //i-- + .sum(pp1_05[43]), //o-- + .car(pp1_04[42]) //o-- + ); + + tri_csa32 pp1_02_csa_42( + .vd(vdd), + .gd(gnd), + .a(pp0_08[42]), //i-- + .b(pp0_07[42]), //i-- + .c(pp0_06[42]), //i-- + .sum(pp1_05[42]), //o-- + .car(pp1_04[41]) //o-- + ); + + tri_csa32 pp1_02_csa_41( + .vd(vdd), + .gd(gnd), + .a(pp0_08[41]), //i-- + .b(pp0_07[41]), //i-- + .c(pp0_06[41]), //i-- + .sum(pp1_05[41]), //o-- + .car(pp1_04[40]) //o-- + ); + + tri_csa32 pp1_02_csa_40( + .vd(vdd), + .gd(gnd), + .a(pp0_08[40]), //i-- + .b(pp0_07[40]), //i-- + .c(pp0_06[40]), //i-- + .sum(pp1_05[40]), //o-- + .car(pp1_04[39]) //o-- + ); + + tri_csa32 pp1_02_csa_39( + .vd(vdd), + .gd(gnd), + .a(pp0_08[39]), //i-- + .b(pp0_07[39]), //i-- + .c(pp0_06[39]), //i-- + .sum(pp1_05[39]), //o-- + .car(pp1_04[38]) //o-- + ); + + tri_csa32 pp1_02_csa_38( + .vd(vdd), + .gd(gnd), + .a(pp0_08[38]), //i-- + .b(pp0_07[38]), //i-- + .c(pp0_06[38]), //i-- + .sum(pp1_05[38]), //o-- + .car(pp1_04[37]) //o-- + ); + + tri_csa32 pp1_02_csa_37( + .vd(vdd), + .gd(gnd), + .a(pp0_08[37]), //i-- + .b(pp0_07[37]), //i-- + .c(pp0_06[37]), //i-- + .sum(pp1_05[37]), //o-- + .car(pp1_04[36]) //o-- + ); + + tri_csa32 pp1_02_csa_36( + .vd(vdd), + .gd(gnd), + .a(pp0_08[36]), //i-- + .b(pp0_07[36]), //i-- + .c(pp0_06[36]), //i-- + .sum(pp1_05[36]), //o-- + .car(pp1_04[35]) //o-- + ); + + tri_csa32 pp1_02_csa_35( + .vd(vdd), + .gd(gnd), + .a(pp0_08[35]), //i-- + .b(pp0_07[35]), //i-- + .c(pp0_06[35]), //i-- + .sum(pp1_05[35]), //o-- + .car(pp1_04[34]) //o-- + ); + + tri_csa32 pp1_02_csa_34( + .vd(vdd), + .gd(gnd), + .a(pp0_08[34]), //i-- + .b(pp0_07[34]), //i-- + .c(pp0_06[34]), //i-- + .sum(pp1_05[34]), //o-- + .car(pp1_04[33]) //o-- + ); + + tri_csa32 pp1_02_csa_33( + .vd(vdd), + .gd(gnd), + .a(pp0_08[33]), //i-- + .b(pp0_07[33]), //i-- + .c(pp0_06[33]), //i-- + .sum(pp1_05[33]), //o-- + .car(pp1_04[32]) //o-- + ); + + tri_csa32 pp1_02_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp0_08[32]), //i-- + .b(pp0_07[32]), //i-- + .c(pp0_06[32]), //i-- + .sum(pp1_05[32]), //o-- + .car(pp1_04[31]) //o-- + ); + + tri_csa32 pp1_02_csa_31( + .vd(vdd), + .gd(gnd), + .a(pp0_08[31]), //i-- + .b(pp0_07[31]), //i-- + .c(pp0_06[31]), //i-- + .sum(pp1_05[31]), //o-- + .car(pp1_04[30]) //o-- + ); + + tri_csa32 pp1_02_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp0_08[30]), //i-- + .b(pp0_07[30]), //i-- + .c(pp0_06[30]), //i-- + .sum(pp1_05[30]), //o-- + .car(pp1_04[29]) //o-- + ); + + tri_csa32 pp1_02_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp0_08[29]), //i-- + .b(pp0_07[29]), //i-- + .c(pp0_06[29]), //i-- + .sum(pp1_05[29]), //o-- + .car(pp1_04[28]) //o-- + ); + + tri_csa32 pp1_02_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp0_08[28]), //i-- + .b(pp0_07[28]), //i-- + .c(pp0_06[28]), //i-- + .sum(pp1_05[28]), //o-- + .car(pp1_04[27]) //o-- + ); + + tri_csa32 pp1_02_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp0_08[27]), //i-- + .b(pp0_07[27]), //i-- + .c(pp0_06[27]), //i-- + .sum(pp1_05[27]), //o-- + .car(pp1_04[26]) //o-- + ); + + tri_csa32 pp1_02_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp0_08[26]), //i-- + .b(pp0_07[26]), //i-- + .c(pp0_06[26]), //i-- + .sum(pp1_05[26]), //o-- + .car(pp1_04[25]) //o-- + ); + + tri_csa32 pp1_02_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp0_08[25]), //i-- + .b(pp0_07[25]), //i-- + .c(pp0_06[25]), //i-- + .sum(pp1_05[25]), //o-- + .car(pp1_04[24]) //o-- + ); + + tri_csa32 pp1_02_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp0_08[24]), //i-- + .b(pp0_07[24]), //i-- + .c(pp0_06[24]), //i-- + .sum(pp1_05[24]), //o-- + .car(pp1_04[23]) //o-- + ); + + tri_csa32 pp1_02_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp0_08[23]), //i-- + .b(pp0_07[23]), //i-- + .c(pp0_06[23]), //i-- + .sum(pp1_05[23]), //o-- + .car(pp1_04[22]) //o-- + ); + + tri_csa32 pp1_02_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp0_08[22]), //i-- + .b(pp0_07[22]), //i-- + .c(pp0_06[22]), //i-- + .sum(pp1_05[22]), //o-- + .car(pp1_04[21]) //o-- + ); + + tri_csa32 pp1_02_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp0_08[21]), //i-- + .b(pp0_07[21]), //i-- + .c(pp0_06[21]), //i-- + .sum(pp1_05[21]), //o-- + .car(pp1_04[20]) //o-- + ); + + tri_csa32 pp1_02_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp0_08[20]), //i-- + .b(pp0_07[20]), //i-- + .c(pp0_06[20]), //i-- + .sum(pp1_05[20]), //o-- + .car(pp1_04[19]) //o-- + ); + + tri_csa32 pp1_02_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp0_08[19]), //i-- + .b(pp0_07[19]), //i-- + .c(pp0_06[19]), //i-- + .sum(pp1_05[19]), //o-- + .car(pp1_04[18]) //o-- + ); + + tri_csa32 pp1_02_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp0_08[18]), //i-- + .b(pp0_07[18]), //i-- + .c(pp0_06[18]), //i-- + .sum(pp1_05[18]), //o-- + .car(pp1_04[17]) //o-- + ); + + tri_csa32 pp1_02_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp0_08[17]), //i-- + .b(pp0_07[17]), //i-- + .c(pp0_06[17]), //i-- + .sum(pp1_05[17]), //o-- + .car(pp1_04[16]) //o-- + ); + + tri_fu_csa22_h2 pp1_02_csa_16( + .a(tiup), //i-- + .b(pp0_06[16]), //i-- + .sum(pp1_05[16]), //o-- + .car(pp1_04[15]) //o-- + ); + assign pp1_05[15] = pp0_06[15]; + assign pp1_05[14] = tiup; + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# 5 ............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h...................................... pp0_05 + ////# 4 ..........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h........................................ pp0_04 + ////# 3 ........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.......................................... pp0_03 + ////# ------------------------------------------------------------------------------------- + ////# ..........223333333333333333333333333333333333333333333333333333323.... + ////# .........ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o..................................... pp1_03 + ////# ........occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o....................................... pp1_02 + + assign pp1_03[70] = pp0_05[70]; + assign pp1_03[69] = tidn; + assign pp1_03[68] = pp0_05[68]; + assign pp1_03[67] = pp0_05[67]; + + assign pp1_02[68] = pp0_04[68]; + assign pp1_02[67] = tidn; + assign pp1_02[66] = tidn; + + + tri_csa32 pp1_01_csa_66( + .vd(vdd), + .gd(gnd), + .a(pp0_05[66]), //i-- + .b(pp0_04[66]), //i-- + .c(pp0_03[66]), //i-- + .sum(pp1_03[66]), //o-- + .car(pp1_02[65]) //o-- + ); + + tri_fu_csa22_h2 pp1_01_csa_65( + .a(pp0_05[65]), //i-- + .b(pp0_04[65]), //i-- + .sum(pp1_03[65]), //o-- + .car(pp1_02[64]) //o-- + ); + + tri_csa32 pp1_01_csa_64( + .vd(vdd), + .gd(gnd), + .a(pp0_05[64]), //i-- + .b(pp0_04[64]), //i-- + .c(pp0_03[64]), //i-- + .sum(pp1_03[64]), //o-- + .car(pp1_02[63]) //o-- + ); + + tri_csa32 pp1_01_csa_63( + .vd(vdd), + .gd(gnd), + .a(pp0_05[63]), //i-- + .b(pp0_04[63]), //i-- + .c(pp0_03[63]), //i-- + .sum(pp1_03[63]), //o-- + .car(pp1_02[62]) //o-- + ); + + tri_csa32 pp1_01_csa_62( + .vd(vdd), + .gd(gnd), + .a(pp0_05[62]), //i-- + .b(pp0_04[62]), //i-- + .c(pp0_03[62]), //i-- + .sum(pp1_03[62]), //o-- + .car(pp1_02[61]) //o-- + ); + + tri_csa32 pp1_01_csa_61( + .vd(vdd), + .gd(gnd), + .a(pp0_05[61]), //i-- + .b(pp0_04[61]), //i-- + .c(pp0_03[61]), //i-- + .sum(pp1_03[61]), //o-- + .car(pp1_02[60]) //o-- + ); + + tri_csa32 pp1_01_csa_60( + .vd(vdd), + .gd(gnd), + .a(pp0_05[60]), //i-- + .b(pp0_04[60]), //i-- + .c(pp0_03[60]), //i-- + .sum(pp1_03[60]), //o-- + .car(pp1_02[59]) //o-- + ); + + tri_csa32 pp1_01_csa_59( + .vd(vdd), + .gd(gnd), + .a(pp0_05[59]), //i-- + .b(pp0_04[59]), //i-- + .c(pp0_03[59]), //i-- + .sum(pp1_03[59]), //o-- + .car(pp1_02[58]) //o-- + ); + + tri_csa32 pp1_01_csa_58( + .vd(vdd), + .gd(gnd), + .a(pp0_05[58]), //i-- + .b(pp0_04[58]), //i-- + .c(pp0_03[58]), //i-- + .sum(pp1_03[58]), //o-- + .car(pp1_02[57]) //o-- + ); + + tri_csa32 pp1_01_csa_57( +