cores
/
a2o
mirror of https://github.com/OpenPOWERFoundation/a2o
3
1
Fork 1
Code Issues Projects Releases Wiki Activity

remove remaining nclk[] usages

Browse Source
pull/18/head
openpowerwtf 1 year ago
parent af556071b0
commit 3a65b3deaf
56 changed files with 531 additions and 501 deletions
Show Stats Download Patch File Download Diff File

11
dev/verilog/trilib/tri.vh
Unescape Escape View File

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

// *!****************************************************************
// *! FILENAME : tri_a2o.param
@ -36,8 +36,9 @@
`ifndef _tri_vh_
`define _tri_vh_

`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk
//`define EXPAND_TYPE 1
// separate clk, rst now
//`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk
`define EXPAND_TYPE 1

// Do NOT add any defines below this line
`endif //_tri_vh_

6
dev/verilog/trilib/tri_256x144_8w_1r1w.v
Unescape Escape View File

@ -227,7 +227,8 @@ wire [0:(port_bitwidth*ways)-1] data_out_b_q;

wire [0:ways-1] my_d1clk;
wire [0:ways-1] my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk[0:ways-1];
//wire [0:`NCLK_WIDTH-1] my_lclk[0:ways-1];
wire my_lclk[0:ways-1];
wire tiup;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
@ -491,7 +492,8 @@ generate
tri_inv_nlats #(.WIDTH(port_bitwidth), .INIT(0), .BTR("NLI0001_X4_A12TH"), .NEEDS_SRESET(0)) data_out_reg(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk[way]),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk[way]),
.d2clk(my_d2clk[way]),
.scanin(siv[data_out_offset + (port_bitwidth*way):data_out_offset + (port_bitwidth*(way+1)) - 1]),

3
dev/verilog/trilib/tri_a2o.vh
Unescape Escape View File

@ -165,6 +165,9 @@
`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504
//`define INIT_CPCR1 32'h00010100 // 1/1

// table walks?
`define MM_THREADS2

// IERAT boot config entry values
`define IERAT_BCFG_EPN_0TO15 0
`define IERAT_BCFG_EPN_16TO31 0

36
dev/verilog/trilib/tri_err_rpt.v
Unescape Escape View File

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

@ -40,7 +40,8 @@ module tri_err_rpt(
gd,
err_d1clk,
err_d2clk,
err_lclk,
clk,
rst,
err_scan_in,
err_scan_out,
mode_dclk,
@ -64,14 +65,17 @@ module tri_err_rpt(
inout gd;
input err_d1clk; // caution1: if lcb uses powersavings, errors must always get reported
input err_d2clk; // caution2: if use_nlats is used these are also the clocks for the mask latches
input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks
//input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks
// caution2: and all bits in the "func" chain have to be connected to the mode chain
input clk;
input rst;
// error scan chain (func or mode)
input [0:WIDTH-1] err_scan_in; // NOTE: connected to mode or func ring
output [0:WIDTH-1] err_scan_out;
// clock gateable mode clocks
input mode_dclk;
input [0:`NCLK_WIDTH-1] mode_lclk;
//input [0:`NCLK_WIDTH-1] mode_lclk;
input mode_lclk;
// mode scan chain
input [0:WIDTH-1] mode_scan_in;
output [0:WIDTH-1] mode_scan_out;
@ -82,8 +86,6 @@ module tri_err_rpt(
output [0:WIDTH-1] hold_out; // sticky error hold latch for trap usage
output [0:WIDTH-1] mask_out;

// tri_err_rpt

parameter [0:WIDTH-1] mask_initv = MASK_RESET_VALUE;
wire [0:WIDTH-1] hold_in;
wire [0:WIDTH-1] hold_lt;
@ -100,7 +102,8 @@ module tri_err_rpt(
.gd(gd),
.d1clk(err_d1clk),
.d2clk(err_d2clk),
.lclk(err_lclk),
.clk(clk),
.rst(rst),
.scan_in(err_scan_in[0:WIDTH - 1]),
.scan_out(err_scan_out[0:WIDTH - 1]),
.din(hold_in),
@ -111,12 +114,9 @@ module tri_err_rpt(
generate
begin
// mask
if (SHARE_MASK == 1'b0)
begin : m
if (SHARE_MASK == 1'b0) begin
assign mask_lt = mask_initv;
end
if (SHARE_MASK == 1'b1)
begin : sm
end else begin
assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}};
end

@ -126,13 +126,9 @@ module tri_err_rpt(
assign hold_out = hold_lt;
assign mask_out = mask_lt;

if (INLINE == 1'b1)
begin : inline_hold
if (INLINE == 1'b1) begin
assign err_out = hold_lt & (~mask_lt);
end

if (INLINE == 1'b0)
begin : side_hold
end else begin
assign err_out = err_in & (~mask_lt);
end


9
dev/verilog/trilib/tri_fu_mul_92.v
Unescape Escape View File

@ -118,7 +118,8 @@ module tri_fu_mul_92(
wire [0:70] pp3_lat_car_so;
wire mul92_d1clk;
wire mul92_d2clk;
wire [0:`NCLK_WIDTH-1] mul92_lclk;
//wire [0:`NCLK_WIDTH-1] mul92_lclk;
wire mul92_lclk;

wire unused;

@ -4403,7 +4404,8 @@ module tri_fu_mul_92(
tri_inv_nlats #(.WIDTH(73), .NEEDS_SRESET(0)) pp3_lat_sum(
.vd(vdd),
.gd(gnd),
.lclk(mul92_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(mul92_d1clk),
.d2clk(mul92_d2clk),
.scanin({si,
@ -4417,7 +4419,8 @@ module tri_fu_mul_92(
tri_inv_nlats #(.WIDTH(71), .NEEDS_SRESET(0)) pp3_lat_car(
.vd(vdd),
.gd(gnd),
.lclk(mul92_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(mul92_d1clk),
.d2clk(mul92_d2clk),
.scanin({ pp3_lat_car_so[1:70],

19
dev/verilog/trilib/tri_inv_nlats.v
Unescape Escape View File

@ -38,7 +38,8 @@
module tri_inv_nlats(
vd,
gd,
lclk,
clk,
rst,
d1clk,
d2clk,
scanin,
@ -58,7 +59,8 @@ module tri_inv_nlats(

inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input clk;
input rst;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
@ -86,12 +88,9 @@ module tri_inv_nlats(
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
if (NEEDS_SRESET == 1) begin
assign sreset = rst;
end else begin
assign sreset = 1'b0;
end

@ -106,7 +105,7 @@ module tri_inv_nlats(
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};

always @(posedge lclk[0]) begin: l
always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset)
int_dout <= int_din;
@ -117,7 +116,7 @@ module tri_inv_nlats(
assign qb = (~int_dout);
assign scanout = ZEROS;

assign unused = | {vd, gd, lclk, scanin};
assign unused = | {vd, gd, scanin};
end
endgenerate
endmodule

4
dev/verilog/trilib/tri_lcbnd.v
Unescape Escape View File

@ -66,7 +66,7 @@ module tri_lcbnd (
input thold_b;
output d1clk;
output d2clk;
output[0:`NCLK_WIDTH-1] lclk;
output lclk;

// tri_lcbnd
wire gate_b;
@ -79,5 +79,5 @@ module tri_lcbnd (

assign d1clk = gate_b;
assign d2clk = thold_b;
assign lclk = {clk,rst,{`NCLK_WIDTH-2{1'b0}}};
assign lclk = clk;
endmodule

1
dev/verilog/trilib/tri_lcbs.v → dev/verilog/trilib/tri_lcbs_UNUSED.v
Unescape Escape View File

@ -35,7 +35,6 @@

`include "tri_a2o.vh"

//wtf this should be changed to output clk,rst instead of lclk; think it's only for alternate ring lats?
module tri_lcbs (
vd,
gd,

19
dev/verilog/trilib/tri_nand2_nlats.v
Unescape Escape View File

@ -38,7 +38,8 @@
module tri_nand2_nlats(
vd,
gd,
lclk,
clk,
rst,
d1clk,
d2clk,
scanin,
@ -58,7 +59,8 @@ module tri_nand2_nlats(

inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input clk;
input rst;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
@ -86,12 +88,9 @@ module tri_nand2_nlats(
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
if (NEEDS_SRESET == 1) begin
assign sreset = rst;
end else begin
assign sreset = 1'b0;
end

@ -106,7 +105,7 @@ module tri_nand2_nlats(
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};

always @(posedge lclk[0]) begin: l
always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset)
int_dout <= int_din;
@ -117,6 +116,6 @@ module tri_nand2_nlats(
assign qb = (~int_dout);
assign scanout = ZEROS;

assign unused = | {vd, gd, lclk, scanin};
assign unused = | {vd, gd, scanin};
endgenerate
endmodule

19
dev/verilog/trilib/tri_nlat.v
Unescape Escape View File

@ -40,7 +40,8 @@ module tri_nlat(
gd,
d1clk,
d2clk,
lclk,
clk,
rst,
scan_in,
din,
q,
@ -63,7 +64,8 @@ module tri_nlat(
inout gd;
input d1clk;
input d2clk;
input [0:`NCLK_WIDTH-1] lclk;
input clk;
input rst;
input scan_in;
input [OFFSET:OFFSET+WIDTH-1] din;
output [OFFSET:OFFSET+WIDTH-1] q;
@ -88,12 +90,9 @@ module tri_nlat(
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
if (NEEDS_SRESET == 1) begin
assign sreset = rst;
end else begin
assign sreset = 1'b0;
end

@ -107,7 +106,7 @@ module tri_nlat(
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};

always @(posedge lclk[0]) begin: l
always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset)
int_dout <= int_din;
@ -119,7 +118,7 @@ module tri_nlat(
assign q_b = (~int_dout);
assign scan_out = 1'b0;

assign unused = | {vd, gd, lclk, scan_in};
assign unused = | {vd, gd, scan_in};
end
endgenerate
endmodule

19
dev/verilog/trilib/tri_nlat_scan.v
Unescape Escape View File

@ -40,7 +40,8 @@ module tri_nlat_scan(
gd,
d1clk,
d2clk,
lclk,
clk,
rst,
din,
scan_in,
q,
@ -59,9 +60,10 @@ module tri_nlat_scan(

inout vd;
inout gd;
input clk;
input rst;
input d1clk;
input d2clk;
input [0:`NCLK_WIDTH-1] lclk;
input [OFFSET:OFFSET+WIDTH-1] din;
input [OFFSET:OFFSET+WIDTH-1] scan_in;
output [OFFSET:OFFSET+WIDTH-1] q;
@ -87,12 +89,9 @@ module tri_nlat_scan(
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
if (NEEDS_SRESET == 1) begin
assign sreset = rst;
end else begin
assign sreset = 1'b0;
end

@ -106,7 +105,7 @@ module tri_nlat_scan(
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};

always @(posedge lclk[0]) begin: l
always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset)
int_dout <= int_din;
@ -118,7 +117,7 @@ module tri_nlat_scan(
assign q_b = (~int_dout);
assign scan_out = ZEROS;

assign unused = | {vd, gd, lclk, scan_in};
assign unused = | {vd, gd, scan_in};
end
endgenerate
endmodule

21
dev/verilog/trilib/tri_rot16_ru.v
Unescape Escape View File

@ -104,7 +104,8 @@ output scan_out;

wire my_d1clk;
wire my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk;
//wire [0:`NCLK_WIDTH-1] my_lclk;
wire my_lclk;


wire [0:15] data_latched_b;
@ -473,7 +474,8 @@ tri_lcbnd my_lcb(
tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) bele_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]),
@ -485,7 +487,8 @@ tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]),
@ -497,7 +500,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]),
@ -509,7 +513,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]),
@ -521,7 +526,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]),
@ -533,7 +539,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) mask_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[mask_din_offset:mask_din_offset + 5 - 1]),

33
dev/verilog/trilib/tri_rot16s_ru.v
Unescape Escape View File

@ -115,7 +115,8 @@ output scan_out;

wire my_d1clk;
wire my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk;
//wire [0:`NCLK_WIDTH-1] my_lclk;
wire my_lclk;

wire [0:15] data_latched_b;

@ -632,7 +633,8 @@ tri_lcbnd my_lcb(
tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) bele_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]),
@ -644,7 +646,8 @@ tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]),
@ -656,7 +659,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]),
@ -668,7 +672,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]),
@ -680,7 +685,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]),
@ -692,7 +698,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) mask_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[mask_din_offset:mask_din_offset + 5 - 1]),
@ -704,7 +711,8 @@ tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_sgn0_din_offset:be_shx04_sgn0_din_offset + 4 - 1]),
@ -716,7 +724,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_sgn0_din_offset:be_shx01_sgn0_din_offset + 4 - 1]),
@ -728,7 +737,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_sgn0_din_offset:le_shx04_sgn0_din_offset + 4 - 1]),
@ -740,7 +750,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_sgn0_din_offset:le_shx01_sgn0_din_offset + 4 - 1]),

63
dev/verilog/trilib/tri_serial_scom2.v
Unescape Escape View File

@ -118,12 +118,14 @@ module tri_serial_scom2 (

// for mask slat inside of c_err_rpt
input dcfg_scan_dclk;
input [0:`NCLK_WIDTH-1] dcfg_scan_lclk;
//input [0:`NCLK_WIDTH-1] dcfg_scan_lclk;
input dcfg_scan_lclk;

//! for nlats inside of c_err_rpt
input dcfg_d1clk; // needed for one bit only, always or scom_local_act clocked dcfg
input dcfg_d2clk; // needed for one bit only, always or scom_local_act clocked dcfg
input [0:`NCLK_WIDTH-1] dcfg_lclk; // needed for one bit only, always or scom_local_act clocked dcfg
//input [0:`NCLK_WIDTH-1] dcfg_lclk; // needed for one bit only, always or scom_local_act clocked dcfg
input dcfg_lclk;

// contains mask slat and hold nlat of c_err_rpt
input [0:1] dcfg_scan_in;
@ -296,7 +298,7 @@ module tri_serial_scom2 (
wire func_thold_b;
wire d1clk;
wire d2clk;
wire [0:`NCLK_WIDTH-1] lclk;
//wire [0:`NCLK_WIDTH-1] lclk;
wire local_act;
wire local_act_int;
wire scom_err_in;
@ -338,6 +340,7 @@ module tri_serial_scom2 (
.thold_b(func_thold_b)
);

/*
tri_lcbnd lcb_func(
.vd(vdd),
.gd(gnd),
@ -355,6 +358,9 @@ module tri_serial_scom2 (
.d2clk(d2clk),
.lclk(lclk)
);
*/
assign d1clk = local_act_int;
assign d2clk = func_thold_b;

//-----------------------------------------------------------------------------
tri_err_rpt #(.WIDTH(1), // use to bundle error reporting checkers of the same exact type
@ -366,7 +372,8 @@ module tri_serial_scom2 (
.gd(gnd),
.err_d1clk(dcfg_d1clk),
.err_d2clk(dcfg_d2clk),
.err_lclk(dcfg_lclk),
.clk(clk),
.rst(rst),
.err_scan_in(dcfg_scan_in[0:0]),
.err_scan_out(dcfg_scan_out[0:0]),
.mode_dclk(dcfg_scan_dclk),
@ -640,7 +647,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]),
@ -697,7 +705,8 @@ module tri_serial_scom2 (
.vd(vdd),
.gd(gnd),
.d2clk(d2clk),
.lclk(lclk),
.clk(clk),
.rst(rst),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i]),
.din(dec_addr_in[i]),
@ -779,7 +788,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ 0:STATE_WIDTH-1]),
.scan_out(func_scan_out[0:STATE_WIDTH-1]),
@ -792,7 +802,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH:STATE_WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH:STATE_WIDTH+6]),
@ -805,7 +816,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+7:STATE_WIDTH+WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH+7:STATE_WIDTH+WIDTH+6]),
@ -818,7 +830,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+6]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+6]),
@ -831,7 +844,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+6]),
@ -844,7 +858,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+11]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+11]),
@ -857,7 +872,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+12]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+12]),
@ -870,7 +886,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+13:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+14]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+13:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+14]),
@ -883,7 +900,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+15]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+15]),
@ -896,7 +914,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+16:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+17]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+16:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+17]),
@ -909,7 +928,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+18]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+18]),
@ -922,7 +942,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+19]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+19]),
@ -935,7 +956,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+20]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+20]),
@ -948,7 +970,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+21]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+21]),

3
dev/verilog/trilib/tri_slat_scan.v
Unescape Escape View File

@ -56,7 +56,8 @@ module tri_slat_scan(
inout vd;
inout gd;
input dclk;
input [0:`NCLK_WIDTH-1] lclk;
//input [0:`NCLK_WIDTH-1] lclk;
input lclk;
input [OFFSET:OFFSET+WIDTH-1] scan_in;
output [OFFSET:OFFSET+WIDTH-1] scan_out;
output [OFFSET:OFFSET+WIDTH-1] q;

30
dev/verilog/trilib/tri_st_mult_core.v
Unescape Escape View File

@ -99,8 +99,10 @@ module tri_st_mult_core(
wire ex5_d1clk;
wire ex4_d2clk;
wire ex5_d2clk;
wire [0:`NCLK_WIDTH-1] ex4_lclk;
wire [0:`NCLK_WIDTH-1] ex5_lclk;
//wire [0:`NCLK_WIDTH-1] ex4_lclk;
//wire [0:`NCLK_WIDTH-1] ex5_lclk;
wire ex4_lclk;
wire ex6_lclk;

wire [198:240] ex4_pp2_0c_din;
wire [198:240] ex4_pp2_0c;
@ -7271,7 +7273,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_0s_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_0s_lat_si),
@ -7283,7 +7286,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(43), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_0c_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_0c_lat_si),
@ -7296,7 +7300,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(47), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_1s_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_1s_lat_si),
@ -7309,7 +7314,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_1c_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_1c_lat_si),
@ -7322,7 +7328,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_2s_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_2s_lat_si),
@ -7335,7 +7342,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(44), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_2c_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_2c_lat_si),
@ -7348,7 +7356,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(69), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) ex5_pp5_0s_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex5_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex5_d1clk),
.d2clk(ex5_d2clk),
.scanin(ex5_pp5_0s_lat_si),
@ -7361,7 +7370,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(68), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) ex5_pp5_0c_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex5_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex5_d1clk),
.d2clk(ex5_d2clk),
.scanin(ex5_pp5_0c_lat_si),

12
dev/verilog/trilib/tri_st_rot.v
Unescape Escape View File

@ -189,7 +189,8 @@ module tri_st_rot(
localparam scan_right = dummy_offset + 1;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
wire [0:`NCLK_WIDTH-1] rot_lclk_int;
//wire [0:`NCLK_WIDTH-1] rot_lclk_int;
wire rot_lclk_int;
wire rot_d1clk_int;
wire rot_d2clk_int;
wire ex2_zm;
@ -1082,7 +1083,8 @@ module tri_st_rot(
tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X1_A12TH"), .INIT(0)) rot_lat(
.vd(vdd),
.gd(gnd),
.lclk(rot_lclk_int),
.clk(clk),
.rst(rst),
.d1clk(rot_d1clk_int),
.d2clk(rot_d2clk_int),
.scanin(siv[ex3_rotate_b_offset:ex3_rotate_b_offset + 64 - 1]),
@ -1094,7 +1096,8 @@ module tri_st_rot(
tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X2_A12TH"), .INIT(0)) res_lat(
.vd(vdd),
.gd(gnd),
.lclk(rot_lclk_int),
.clk(clk),
.rst(rst),
.d1clk(rot_d1clk_int),
.d2clk(rot_d2clk_int),
.scanin(siv[ex3_result_b_offset:ex3_result_b_offset + 64 - 1]),
@ -1106,7 +1109,8 @@ module tri_st_rot(
tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X1_A12TH"), .INIT(0)) msk_lat(
.vd(vdd),
.gd(gnd),
.lclk(rot_lclk_int),
.clk(clk),
.rst(rst),
.d1clk(rot_d1clk_int),
.d2clk(rot_d2clk_int),
.scanin(siv[ex3_mask_b_offset:ex3_mask_b_offset + 64 - 1]),

36
dev/verilog/work/c_perv_rp.v
Unescape Escape View File

@ -269,13 +269,13 @@ module c_perv_rp(
wire slat_force;
wire func_slat_thold_b;
wire func_slat_d2clk;
wire [0:`NCLK_WIDTH-1] func_slat_lclk;
//wire [0:`NCLK_WIDTH-1] func_slat_lclk;
wire abst_slat_thold_b;
wire abst_slat_d2clk;
wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
//wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
wire cfg_slat_thold_b;
wire cfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
//wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
//
wire sg_3_int;
wire func_sl_thold_3_int;
@ -434,6 +434,7 @@ module c_perv_rp(
assign abst_slat_thold_b = (~abst_sl_thold_0);
assign cfg_slat_thold_b = (~cfg_sl_thold_0);

/*
tri_lcbs lcbs_func(
.vd(vdd),
.gd(gnd),
@ -469,6 +470,15 @@ module c_perv_rp(
.dclk(cfg_slat_d2clk),
.lclk(cfg_slat_lclk)
);
*/
// tri_lcbs dclk=thold lclk=clk,rst
wire func_slat_lclk, abst_slat_lclk, cfg_slat_lclk;
assign func_slat_d2clk = 0;
assign func_slat_lclk = 0;
assign abst_slat_d2clk = 0;
assign abst_slat_lclk = 0;
assign cfg_slat_d2clk = 0;
assign cfg_slat_lclk = 0;

// *****************************************************************************
// CLOCK REPOWERING LOGIC
@ -478,9 +488,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(an_ac_ccflush_dc),

.din({rtim_sl_thold_8, func_sl_thold_8, func_nsl_thold_8,
ary_nsl_thold_8, sg_8, fce_8 }),

@ -500,10 +509,9 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4,
@ -520,9 +528,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4,
pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4,
@ -540,9 +547,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
@ -560,9 +566,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
@ -580,9 +585,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4,
pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4,

12
dev/verilog/work/fu_add.v
Unescape Escape View File

@ -206,7 +206,8 @@ module fu_add(
wire ex4_flag_eq_cp1;
wire add_ex5_d1clk;
wire add_ex5_d2clk;
wire [0:`NCLK_WIDTH-1] add_ex5_lclk;
//wire [0:`NCLK_WIDTH-1] add_ex5_lclk;
wire add_ex5_lclk;

wire [53:162] ex4_s_p0n;
wire [53:162] ex4_res_p0n_b;
@ -624,7 +625,8 @@ module fu_add(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex5_res_hi_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_res_si[0:52]),
@ -637,7 +639,8 @@ module fu_add(
tri_inv_nlats #(.WIDTH(110), .NEEDS_SRESET(0)) ex5_res_lo_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_res_si[53:162]),
@ -654,7 +657,8 @@ module fu_add(
tri_inv_nlats #(.WIDTH(10), .NEEDS_SRESET(0)) ex5_cmp_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_cmp_si),

14
dev/verilog/work/fu_alg.v
Unescape Escape View File

@ -352,9 +352,8 @@ module fu_alg(
wire ex3_sh16_163;
wire alg_ex3_d1clk;
wire alg_ex3_d2clk;

wire [0:`NCLK_WIDTH-1] alg_ex3_lclk;

//wire [0:`NCLK_WIDTH-1] alg_ex3_lclk;
wire alg_ex3_lclk;
wire [6:9] ex3_bsha_b;
wire ex3_bsha_neg_b;
wire ex3_sh_ovf_b;
@ -665,7 +664,8 @@ module fu_alg(
tri_inv_nlats #(.WIDTH(68), .NEEDS_SRESET(0)) ex3_shd_lat(
.vd(vdd),
.gd(gnd),
.lclk(alg_ex3_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(alg_ex3_d1clk),
.d2clk(alg_ex3_d2clk),
.scanin(ex3_shd_si),
@ -680,7 +680,8 @@ module fu_alg(
tri_inv_nlats #(.WIDTH(25), .NEEDS_SRESET(0)) ex3_shc_lat(
.vd(vdd),
.gd(gnd),
.lclk(alg_ex3_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(alg_ex3_d1clk),
.d2clk(alg_ex3_d2clk),
.scanin(ex3_shc_si),
@ -767,7 +768,8 @@ module fu_alg(
tri_inv_nlats #(.WIDTH(15), .NEEDS_SRESET(0)) ex3_ctl_lat(
.vd(vdd),
.gd(gnd),
.lclk(alg_ex3_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(alg_ex3_d1clk),
.d2clk(alg_ex3_d2clk),
.scanin(ex3_ctl_si),

48
dev/verilog/work/fu_byp.v
Unescape Escape View File

@ -631,7 +631,8 @@ module fu_byp(

wire byp_ex2_d1clk;
wire byp_ex2_d2clk;
wire [0:`NCLK_WIDTH-1] byp_ex2_lclk;
//wire [0:`NCLK_WIDTH-1] byp_ex2_lclk;
wire byp_ex2_lclk;
wire ex1_c_frac_pre3_hulp_b;
wire ex1_hulp_sp;
wire ex1_c_frac_pre_hulp;
@ -1989,7 +1990,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_b_alg_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_b_frac_si), //in
@ -2002,7 +2004,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_a_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_frac_a_fmt_si), //in
@ -2015,7 +2018,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_c_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_frac_c_fmt_si), //in
@ -2028,7 +2032,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_b_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_frac_b_fmt_si), //in
@ -2051,7 +2056,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(54), .NEEDS_SRESET(0)) ex2_frac_c_mul_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(frac_mul_c_si), //in
@ -2065,7 +2071,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(55), .NEEDS_SRESET(0)) ex2_frac_a_mul_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(frac_mul_a_si), //in
@ -2198,7 +2205,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_alg_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_b_alg_si), //in
@ -2213,7 +2221,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex2_expo_c_alg_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_c_alg_si), //in
@ -2226,7 +2235,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex2_expo_a_alg_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_a_alg_si), //in
@ -2239,7 +2249,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_b_fmt_si), //in
@ -2254,7 +2265,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_a_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_a_fmt_si), //in
@ -2269,7 +2281,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_c_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_c_fmt_si), //in
@ -2284,7 +2297,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_eie_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_b_eie_si), //in
@ -2299,7 +2313,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14),.NEEDS_SRESET(0)) ex2_expo_a_eie_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_a_eie_si), //in
@ -2314,7 +2329,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_c_eie_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_c_eie_si), //in

10
dev/verilog/work/fu_dcd.v
Unescape Escape View File

@ -1531,7 +1531,7 @@ module fu_dcd(
wire func_slp_sl_force;
wire func_slp_sl_thold_0_b;
wire cfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
//wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;

assign tilo = 1'b0;
assign tihi = 1'b1;
@ -1719,17 +1719,23 @@ module fu_dcd(
.thold_b(func_slp_sl_thold_0_b)
);

/*
tri_lcbs lcbs_cfg(
.vd(vdd),
.gd(gnd),
.delay_lclkr(delay_lclkr[9]),
.clk(clk),
.rst(rst),
.rst(rst),
.force_t(cfg_sl_force),
.thold_b(cfg_sl_thold_0_b),
.dclk(cfg_slat_d2clk),
.lclk(cfg_slat_lclk)
);
*/
// tri_lcbs dclk=thold lclk=clk,rst
wire func_slat_lclk, abst_slat_lclk, cfg_slat_lclk;
assign cfg_slat_d2clk = 0;
assign cfg_slat_lclk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) cfg_stg(
.vd(vdd),

12
dev/verilog/work/fu_eov.v
Unescape Escape View File

@ -337,7 +337,8 @@ module fu_eov(
wire ex5_unf_calc_1_b;
wire ex6_d1clk;
wire ex6_d2clk;
wire [0:`NCLK_WIDTH-1] ex6_lclk;
//wire [0:`NCLK_WIDTH-1] ex6_lclk;
wire ex6_lclk;
(* analysis_not_referenced="TRUE" *) // unused
wire unused;

@ -965,7 +966,8 @@ module fu_eov(
tri_nand2_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex6_urnd0_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_urnd0_si),
@ -978,7 +980,8 @@ module fu_eov(
tri_nand2_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex6_urnd1_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_urnd1_si),
@ -991,7 +994,8 @@ module fu_eov(
tri_nand2_nlats #(.WIDTH(3), .NEEDS_SRESET(0)) ex6_ovctl_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_ovctl_si),

18
dev/verilog/work/fu_lza.v
Unescape Escape View File