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a2o
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remove remaining nclk[] usages

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pull/18/head
openpowerwtf 3 years ago
parent af556071b0
commit 3a65b3deaf
56 changed files with 531 additions and 501 deletions
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11
dev/verilog/trilib/tri.vh
Unescape Escape View File

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

// *!****************************************************************
// *! FILENAME : tri_a2o.param
@ -36,8 +36,9 @@
`ifndef _tri_vh_
`define _tri_vh_

`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk
//`define EXPAND_TYPE 1
// separate clk, rst now
//`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk
`define EXPAND_TYPE 1

// Do NOT add any defines below this line
`endif //_tri_vh_

6
dev/verilog/trilib/tri_256x144_8w_1r1w.v
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@ -227,7 +227,8 @@ wire [0:(port_bitwidth*ways)-1] data_out_b_q;

wire [0:ways-1] my_d1clk;
wire [0:ways-1] my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk[0:ways-1];
//wire [0:`NCLK_WIDTH-1] my_lclk[0:ways-1];
wire my_lclk[0:ways-1];
wire tiup;
wire [0:scan_right] siv;
wire [0:scan_right] sov;
@ -491,7 +492,8 @@ generate
tri_inv_nlats #(.WIDTH(port_bitwidth), .INIT(0), .BTR("NLI0001_X4_A12TH"), .NEEDS_SRESET(0)) data_out_reg(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk[way]),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk[way]),
.d2clk(my_d2clk[way]),
.scanin(siv[data_out_offset + (port_bitwidth*way):data_out_offset + (port_bitwidth*(way+1)) - 1]),

3
dev/verilog/trilib/tri_a2o.vh
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@ -165,6 +165,9 @@
`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504
//`define INIT_CPCR1 32'h00010100 // 1/1

// table walks?
`define MM_THREADS2

// IERAT boot config entry values
`define IERAT_BCFG_EPN_0TO15 0
`define IERAT_BCFG_EPN_16TO31 0

36
dev/verilog/trilib/tri_err_rpt.v
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@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

@ -40,7 +40,8 @@ module tri_err_rpt(
gd,
err_d1clk,
err_d2clk,
err_lclk,
clk,
rst,
err_scan_in,
err_scan_out,
mode_dclk,
@ -64,14 +65,17 @@ module tri_err_rpt(
inout gd;
input err_d1clk; // caution1: if lcb uses powersavings, errors must always get reported
input err_d2clk; // caution2: if use_nlats is used these are also the clocks for the mask latches
input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks
//input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks
// caution2: and all bits in the "func" chain have to be connected to the mode chain
input clk;
input rst;
// error scan chain (func or mode)
input [0:WIDTH-1] err_scan_in; // NOTE: connected to mode or func ring
output [0:WIDTH-1] err_scan_out;
// clock gateable mode clocks
input mode_dclk;
input [0:`NCLK_WIDTH-1] mode_lclk;
//input [0:`NCLK_WIDTH-1] mode_lclk;
input mode_lclk;
// mode scan chain
input [0:WIDTH-1] mode_scan_in;
output [0:WIDTH-1] mode_scan_out;
@ -82,8 +86,6 @@ module tri_err_rpt(
output [0:WIDTH-1] hold_out; // sticky error hold latch for trap usage
output [0:WIDTH-1] mask_out;

// tri_err_rpt

parameter [0:WIDTH-1] mask_initv = MASK_RESET_VALUE;
wire [0:WIDTH-1] hold_in;
wire [0:WIDTH-1] hold_lt;
@ -100,7 +102,8 @@ module tri_err_rpt(
.gd(gd),
.d1clk(err_d1clk),
.d2clk(err_d2clk),
.lclk(err_lclk),
.clk(clk),
.rst(rst),
.scan_in(err_scan_in[0:WIDTH - 1]),
.scan_out(err_scan_out[0:WIDTH - 1]),
.din(hold_in),
@ -111,12 +114,9 @@ module tri_err_rpt(
generate
begin
// mask
if (SHARE_MASK == 1'b0)
begin : m
if (SHARE_MASK == 1'b0) begin
assign mask_lt = mask_initv;
end
if (SHARE_MASK == 1'b1)
begin : sm
end else begin
assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}};
end

@ -126,13 +126,9 @@ module tri_err_rpt(
assign hold_out = hold_lt;
assign mask_out = mask_lt;

if (INLINE == 1'b1)
begin : inline_hold
if (INLINE == 1'b1) begin
assign err_out = hold_lt & (~mask_lt);
end

if (INLINE == 1'b0)
begin : side_hold
end else begin
assign err_out = err_in & (~mask_lt);
end


9
dev/verilog/trilib/tri_fu_mul_92.v
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@ -118,7 +118,8 @@ module tri_fu_mul_92(
wire [0:70] pp3_lat_car_so;
wire mul92_d1clk;
wire mul92_d2clk;
wire [0:`NCLK_WIDTH-1] mul92_lclk;
//wire [0:`NCLK_WIDTH-1] mul92_lclk;
wire mul92_lclk;

wire unused;

@ -4403,7 +4404,8 @@ module tri_fu_mul_92(
tri_inv_nlats #(.WIDTH(73), .NEEDS_SRESET(0)) pp3_lat_sum(
.vd(vdd),
.gd(gnd),
.lclk(mul92_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(mul92_d1clk),
.d2clk(mul92_d2clk),
.scanin({si,
@ -4417,7 +4419,8 @@ module tri_fu_mul_92(
tri_inv_nlats #(.WIDTH(71), .NEEDS_SRESET(0)) pp3_lat_car(
.vd(vdd),
.gd(gnd),
.lclk(mul92_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(mul92_d1clk),
.d2clk(mul92_d2clk),
.scanin({ pp3_lat_car_so[1:70],

19
dev/verilog/trilib/tri_inv_nlats.v
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@ -38,7 +38,8 @@
module tri_inv_nlats(
vd,
gd,
lclk,
clk,
rst,
d1clk,
d2clk,
scanin,
@ -58,7 +59,8 @@ module tri_inv_nlats(

inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input clk;
input rst;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
@ -86,12 +88,9 @@ module tri_inv_nlats(
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
if (NEEDS_SRESET == 1) begin
assign sreset = rst;
end else begin
assign sreset = 1'b0;
end

@ -106,7 +105,7 @@ module tri_inv_nlats(
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};

always @(posedge lclk[0]) begin: l
always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset)
int_dout <= int_din;
@ -117,7 +116,7 @@ module tri_inv_nlats(
assign qb = (~int_dout);
assign scanout = ZEROS;

assign unused = | {vd, gd, lclk, scanin};
assign unused = | {vd, gd, scanin};
end
endgenerate
endmodule

4
dev/verilog/trilib/tri_lcbnd.v
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@ -66,7 +66,7 @@ module tri_lcbnd (
input thold_b;
output d1clk;
output d2clk;
output[0:`NCLK_WIDTH-1] lclk;
output lclk;

// tri_lcbnd
wire gate_b;
@ -79,5 +79,5 @@ module tri_lcbnd (

assign d1clk = gate_b;
assign d2clk = thold_b;
assign lclk = {clk,rst,{`NCLK_WIDTH-2{1'b0}}};
assign lclk = clk;
endmodule

1
dev/verilog/trilib/tri_lcbs.v → dev/verilog/trilib/tri_lcbs_UNUSED.v
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@ -35,7 +35,6 @@

`include "tri_a2o.vh"

//wtf this should be changed to output clk,rst instead of lclk; think it's only for alternate ring lats?
module tri_lcbs (
vd,
gd,

19
dev/verilog/trilib/tri_nand2_nlats.v
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@ -38,7 +38,8 @@
module tri_nand2_nlats(
vd,
gd,
lclk,
clk,
rst,
d1clk,
d2clk,
scanin,
@ -58,7 +59,8 @@ module tri_nand2_nlats(

inout vd;
inout gd;
input [0:`NCLK_WIDTH-1] lclk;
input clk;
input rst;
input d1clk;
input d2clk;
input [OFFSET:OFFSET+WIDTH-1] scanin;
@ -86,12 +88,9 @@ module tri_nand2_nlats(
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
if (NEEDS_SRESET == 1) begin
assign sreset = rst;
end else begin
assign sreset = 1'b0;
end

@ -106,7 +105,7 @@ module tri_nand2_nlats(
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};

always @(posedge lclk[0]) begin: l
always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset)
int_dout <= int_din;
@ -117,6 +116,6 @@ module tri_nand2_nlats(
assign qb = (~int_dout);
assign scanout = ZEROS;

assign unused = | {vd, gd, lclk, scanin};
assign unused = | {vd, gd, scanin};
endgenerate
endmodule

19
dev/verilog/trilib/tri_nlat.v
Unescape Escape View File

@ -40,7 +40,8 @@ module tri_nlat(
gd,
d1clk,
d2clk,
lclk,
clk,
rst,
scan_in,
din,
q,
@ -63,7 +64,8 @@ module tri_nlat(
inout gd;
input d1clk;
input d2clk;
input [0:`NCLK_WIDTH-1] lclk;
input clk;
input rst;
input scan_in;
input [OFFSET:OFFSET+WIDTH-1] din;
output [OFFSET:OFFSET+WIDTH-1] q;
@ -88,12 +90,9 @@ module tri_nlat(
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
if (NEEDS_SRESET == 1) begin
assign sreset = rst;
end else begin
assign sreset = 1'b0;
end

@ -107,7 +106,7 @@ module tri_nlat(
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};

always @(posedge lclk[0]) begin: l
always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset)
int_dout <= int_din;
@ -119,7 +118,7 @@ module tri_nlat(
assign q_b = (~int_dout);
assign scan_out = 1'b0;

assign unused = | {vd, gd, lclk, scan_in};
assign unused = | {vd, gd, scan_in};
end
endgenerate
endmodule

19
dev/verilog/trilib/tri_nlat_scan.v
Unescape Escape View File

@ -40,7 +40,8 @@ module tri_nlat_scan(
gd,
d1clk,
d2clk,
lclk,
clk,
rst,
din,
scan_in,
q,
@ -59,9 +60,10 @@ module tri_nlat_scan(

inout vd;
inout gd;
input clk;
input rst;
input d1clk;
input d2clk;
input [0:`NCLK_WIDTH-1] lclk;
input [OFFSET:OFFSET+WIDTH-1] din;
input [OFFSET:OFFSET+WIDTH-1] scan_in;
output [OFFSET:OFFSET+WIDTH-1] q;
@ -87,12 +89,9 @@ module tri_nlat_scan(
(* analysis_not_referenced="true" *)
wire unused;

if (NEEDS_SRESET == 1)
begin : rst
assign sreset = lclk[1];
end
if (NEEDS_SRESET != 1)
begin : no_rst
if (NEEDS_SRESET == 1) begin
assign sreset = rst;
end else begin
assign sreset = 1'b0;
end

@ -106,7 +105,7 @@ module tri_nlat_scan(
assign vthold_b = {WIDTH{d2clk}};
assign vthold = {WIDTH{~d2clk}};

always @(posedge lclk[0]) begin: l
always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset)
int_dout <= int_din;
@ -118,7 +117,7 @@ module tri_nlat_scan(
assign q_b = (~int_dout);
assign scan_out = ZEROS;

assign unused = | {vd, gd, lclk, scan_in};
assign unused = | {vd, gd, scan_in};
end
endgenerate
endmodule

21
dev/verilog/trilib/tri_rot16_ru.v
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@ -104,7 +104,8 @@ output scan_out;

wire my_d1clk;
wire my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk;
//wire [0:`NCLK_WIDTH-1] my_lclk;
wire my_lclk;


wire [0:15] data_latched_b;
@ -473,7 +474,8 @@ tri_lcbnd my_lcb(
tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) bele_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]),
@ -485,7 +487,8 @@ tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]),
@ -497,7 +500,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]),
@ -509,7 +513,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]),
@ -521,7 +526,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]),
@ -533,7 +539,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) mask_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[mask_din_offset:mask_din_offset + 5 - 1]),

33
dev/verilog/trilib/tri_rot16s_ru.v
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@ -115,7 +115,8 @@ output scan_out;

wire my_d1clk;
wire my_d2clk;
wire [0:`NCLK_WIDTH-1] my_lclk;
//wire [0:`NCLK_WIDTH-1] my_lclk;
wire my_lclk;

wire [0:15] data_latched_b;

@ -632,7 +633,8 @@ tri_lcbnd my_lcb(
tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) bele_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]),
@ -644,7 +646,8 @@ tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]),
@ -656,7 +659,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]),
@ -668,7 +672,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]),
@ -680,7 +685,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_gp0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]),
@ -692,7 +698,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) mask_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[mask_din_offset:mask_din_offset + 5 - 1]),
@ -704,7 +711,8 @@ tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx04_sgn0_din_offset:be_shx04_sgn0_din_offset + 4 - 1]),
@ -716,7 +724,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[be_shx01_sgn0_din_offset:be_shx01_sgn0_din_offset + 4 - 1]),
@ -728,7 +737,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx04_sgn0_din_offset:le_shx04_sgn0_din_offset + 4 - 1]),
@ -740,7 +750,8 @@ tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(
tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_sgn0_lat(
.vd(vdd),
.gd(gnd),
.lclk(my_lclk),
.clk(clk),
.rst(rst),
.d1clk(my_d1clk),
.d2clk(my_d2clk),
.scanin(siv[le_shx01_sgn0_din_offset:le_shx01_sgn0_din_offset + 4 - 1]),

63
dev/verilog/trilib/tri_serial_scom2.v
Unescape Escape View File

@ -118,12 +118,14 @@ module tri_serial_scom2 (

// for mask slat inside of c_err_rpt
input dcfg_scan_dclk;
input [0:`NCLK_WIDTH-1] dcfg_scan_lclk;
//input [0:`NCLK_WIDTH-1] dcfg_scan_lclk;
input dcfg_scan_lclk;

//! for nlats inside of c_err_rpt
input dcfg_d1clk; // needed for one bit only, always or scom_local_act clocked dcfg
input dcfg_d2clk; // needed for one bit only, always or scom_local_act clocked dcfg
input [0:`NCLK_WIDTH-1] dcfg_lclk; // needed for one bit only, always or scom_local_act clocked dcfg
//input [0:`NCLK_WIDTH-1] dcfg_lclk; // needed for one bit only, always or scom_local_act clocked dcfg
input dcfg_lclk;

// contains mask slat and hold nlat of c_err_rpt
input [0:1] dcfg_scan_in;
@ -296,7 +298,7 @@ module tri_serial_scom2 (
wire func_thold_b;
wire d1clk;
wire d2clk;
wire [0:`NCLK_WIDTH-1] lclk;
//wire [0:`NCLK_WIDTH-1] lclk;
wire local_act;
wire local_act_int;
wire scom_err_in;
@ -338,6 +340,7 @@ module tri_serial_scom2 (
.thold_b(func_thold_b)
);

/*
tri_lcbnd lcb_func(
.vd(vdd),
.gd(gnd),
@ -355,6 +358,9 @@ module tri_serial_scom2 (
.d2clk(d2clk),
.lclk(lclk)
);
*/
assign d1clk = local_act_int;
assign d2clk = func_thold_b;

//-----------------------------------------------------------------------------
tri_err_rpt #(.WIDTH(1), // use to bundle error reporting checkers of the same exact type
@ -366,7 +372,8 @@ module tri_serial_scom2 (
.gd(gnd),
.err_d1clk(dcfg_d1clk),
.err_d2clk(dcfg_d2clk),
.err_lclk(dcfg_lclk),
.clk(clk),
.rst(rst),
.err_scan_in(dcfg_scan_in[0:0]),
.err_scan_out(dcfg_scan_out[0:0]),
.mode_dclk(dcfg_scan_dclk),
@ -640,7 +647,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]),
@ -697,7 +705,8 @@ module tri_serial_scom2 (
.vd(vdd),
.gd(gnd),
.d2clk(d2clk),
.lclk(lclk),
.clk(clk),
.rst(rst),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+22 +i]),
.din(dec_addr_in[i]),
@ -779,7 +788,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ 0:STATE_WIDTH-1]),
.scan_out(func_scan_out[0:STATE_WIDTH-1]),
@ -792,7 +802,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH:STATE_WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH:STATE_WIDTH+6]),
@ -805,7 +816,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+7:STATE_WIDTH+WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH+7:STATE_WIDTH+WIDTH+6]),
@ -818,7 +830,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+6]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+6]),
@ -831,7 +844,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+6]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+6]),
@ -844,7 +858,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+11]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+7:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+11]),
@ -857,7 +872,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+12]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+12]),
@ -870,7 +886,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+13:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+14]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+13:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+14]),
@ -883,7 +900,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+15]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+15]),
@ -896,7 +914,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+16:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+17]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+16:STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+17]),
@ -909,7 +928,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+18]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+18]),
@ -922,7 +942,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+19]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+19]),
@ -935,7 +956,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+20]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+20]),
@ -948,7 +970,8 @@ module tri_serial_scom2 (
.d1clk(d1clk),
.vd(vdd),
.gd(gnd),
.lclk(lclk),
.clk(clk),
.rst(rst),
.d2clk(d2clk),
.scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+21]),
.scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+21]),

3
dev/verilog/trilib/tri_slat_scan.v
Unescape Escape View File

@ -56,7 +56,8 @@ module tri_slat_scan(
inout vd;
inout gd;
input dclk;
input [0:`NCLK_WIDTH-1] lclk;
//input [0:`NCLK_WIDTH-1] lclk;
input lclk;
input [OFFSET:OFFSET+WIDTH-1] scan_in;
output [OFFSET:OFFSET+WIDTH-1] scan_out;
output [OFFSET:OFFSET+WIDTH-1] q;

30
dev/verilog/trilib/tri_st_mult_core.v
Unescape Escape View File

@ -99,8 +99,10 @@ module tri_st_mult_core(
wire ex5_d1clk;
wire ex4_d2clk;
wire ex5_d2clk;
wire [0:`NCLK_WIDTH-1] ex4_lclk;
wire [0:`NCLK_WIDTH-1] ex5_lclk;
//wire [0:`NCLK_WIDTH-1] ex4_lclk;
//wire [0:`NCLK_WIDTH-1] ex5_lclk;
wire ex4_lclk;
wire ex6_lclk;

wire [198:240] ex4_pp2_0c_din;
wire [198:240] ex4_pp2_0c;
@ -7271,7 +7273,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_0s_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_0s_lat_si),
@ -7283,7 +7286,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(43), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_0c_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_0c_lat_si),
@ -7296,7 +7300,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(47), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_1s_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_1s_lat_si),
@ -7309,7 +7314,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_1c_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_1c_lat_si),
@ -7322,7 +7328,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_2s_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_2s_lat_si),
@ -7335,7 +7342,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(44), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_2c_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex4_d1clk),
.d2clk(ex4_d2clk),
.scanin(ex4_pp2_2c_lat_si),
@ -7348,7 +7356,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(69), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) ex5_pp5_0s_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex5_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex5_d1clk),
.d2clk(ex5_d2clk),
.scanin(ex5_pp5_0s_lat_si),
@ -7361,7 +7370,8 @@ module tri_st_mult_core(
tri_inv_nlats #(.WIDTH(68), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) ex5_pp5_0c_lat(
.vd(vdd), //inout
.gd(gnd), //inout
.lclk(ex5_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex5_d1clk),
.d2clk(ex5_d2clk),
.scanin(ex5_pp5_0c_lat_si),

12
dev/verilog/trilib/tri_st_rot.v
Unescape Escape View File

@ -189,7 +189,8 @@ module tri_st_rot(
localparam scan_right = dummy_offset + 1;
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
wire [0:`NCLK_WIDTH-1] rot_lclk_int;
//wire [0:`NCLK_WIDTH-1] rot_lclk_int;
wire rot_lclk_int;
wire rot_d1clk_int;
wire rot_d2clk_int;
wire ex2_zm;
@ -1082,7 +1083,8 @@ module tri_st_rot(
tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X1_A12TH"), .INIT(0)) rot_lat(
.vd(vdd),
.gd(gnd),
.lclk(rot_lclk_int),
.clk(clk),
.rst(rst),
.d1clk(rot_d1clk_int),
.d2clk(rot_d2clk_int),
.scanin(siv[ex3_rotate_b_offset:ex3_rotate_b_offset + 64 - 1]),
@ -1094,7 +1096,8 @@ module tri_st_rot(
tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X2_A12TH"), .INIT(0)) res_lat(
.vd(vdd),
.gd(gnd),
.lclk(rot_lclk_int),
.clk(clk),
.rst(rst),
.d1clk(rot_d1clk_int),
.d2clk(rot_d2clk_int),
.scanin(siv[ex3_result_b_offset:ex3_result_b_offset + 64 - 1]),
@ -1106,7 +1109,8 @@ module tri_st_rot(
tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X1_A12TH"), .INIT(0)) msk_lat(
.vd(vdd),
.gd(gnd),
.lclk(rot_lclk_int),
.clk(clk),
.rst(rst),
.d1clk(rot_d1clk_int),
.d2clk(rot_d2clk_int),
.scanin(siv[ex3_mask_b_offset:ex3_mask_b_offset + 64 - 1]),

36
dev/verilog/work/c_perv_rp.v
Unescape Escape View File

@ -269,13 +269,13 @@ module c_perv_rp(
wire slat_force;
wire func_slat_thold_b;
wire func_slat_d2clk;
wire [0:`NCLK_WIDTH-1] func_slat_lclk;
//wire [0:`NCLK_WIDTH-1] func_slat_lclk;
wire abst_slat_thold_b;
wire abst_slat_d2clk;
wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
//wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
wire cfg_slat_thold_b;
wire cfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
//wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
//
wire sg_3_int;
wire func_sl_thold_3_int;
@ -434,6 +434,7 @@ module c_perv_rp(
assign abst_slat_thold_b = (~abst_sl_thold_0);
assign cfg_slat_thold_b = (~cfg_sl_thold_0);

/*
tri_lcbs lcbs_func(
.vd(vdd),
.gd(gnd),
@ -469,6 +470,15 @@ module c_perv_rp(
.dclk(cfg_slat_d2clk),
.lclk(cfg_slat_lclk)
);
*/
// tri_lcbs dclk=thold lclk=clk,rst
wire func_slat_lclk, abst_slat_lclk, cfg_slat_lclk;
assign func_slat_d2clk = 0;
assign func_slat_lclk = 0;
assign abst_slat_d2clk = 0;
assign abst_slat_lclk = 0;
assign cfg_slat_d2clk = 0;
assign cfg_slat_lclk = 0;

// *****************************************************************************
// CLOCK REPOWERING LOGIC
@ -478,9 +488,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(an_ac_ccflush_dc),

.din({rtim_sl_thold_8, func_sl_thold_8, func_nsl_thold_8,
ary_nsl_thold_8, sg_8, fce_8 }),

@ -500,10 +509,9 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4,
@ -520,9 +528,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4,
pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4,
@ -540,9 +547,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
@ -560,9 +566,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4,
pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4,
@ -580,9 +585,8 @@ module c_perv_rp(
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.flush(pc_rp_ccflush_out_dc),

.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4,
pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4,

12
dev/verilog/work/fu_add.v
Unescape Escape View File

@ -206,7 +206,8 @@ module fu_add(
wire ex4_flag_eq_cp1;
wire add_ex5_d1clk;
wire add_ex5_d2clk;
wire [0:`NCLK_WIDTH-1] add_ex5_lclk;
//wire [0:`NCLK_WIDTH-1] add_ex5_lclk;
wire add_ex5_lclk;

wire [53:162] ex4_s_p0n;
wire [53:162] ex4_res_p0n_b;
@ -624,7 +625,8 @@ module fu_add(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex5_res_hi_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_res_si[0:52]),
@ -637,7 +639,8 @@ module fu_add(
tri_inv_nlats #(.WIDTH(110), .NEEDS_SRESET(0)) ex5_res_lo_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_res_si[53:162]),
@ -654,7 +657,8 @@ module fu_add(
tri_inv_nlats #(.WIDTH(10), .NEEDS_SRESET(0)) ex5_cmp_lat(
.vd(vdd),
.gd(gnd),
.lclk(add_ex5_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(add_ex5_d1clk),
.d2clk(add_ex5_d2clk),
.scanin(ex5_cmp_si),

14
dev/verilog/work/fu_alg.v
Unescape Escape View File

@ -352,9 +352,8 @@ module fu_alg(
wire ex3_sh16_163;
wire alg_ex3_d1clk;
wire alg_ex3_d2clk;

wire [0:`NCLK_WIDTH-1] alg_ex3_lclk;

//wire [0:`NCLK_WIDTH-1] alg_ex3_lclk;
wire alg_ex3_lclk;
wire [6:9] ex3_bsha_b;
wire ex3_bsha_neg_b;
wire ex3_sh_ovf_b;
@ -665,7 +664,8 @@ module fu_alg(
tri_inv_nlats #(.WIDTH(68), .NEEDS_SRESET(0)) ex3_shd_lat(
.vd(vdd),
.gd(gnd),
.lclk(alg_ex3_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(alg_ex3_d1clk),
.d2clk(alg_ex3_d2clk),
.scanin(ex3_shd_si),
@ -680,7 +680,8 @@ module fu_alg(
tri_inv_nlats #(.WIDTH(25), .NEEDS_SRESET(0)) ex3_shc_lat(
.vd(vdd),
.gd(gnd),
.lclk(alg_ex3_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(alg_ex3_d1clk),
.d2clk(alg_ex3_d2clk),
.scanin(ex3_shc_si),
@ -767,7 +768,8 @@ module fu_alg(
tri_inv_nlats #(.WIDTH(15), .NEEDS_SRESET(0)) ex3_ctl_lat(
.vd(vdd),
.gd(gnd),
.lclk(alg_ex3_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(alg_ex3_d1clk),
.d2clk(alg_ex3_d2clk),
.scanin(ex3_ctl_si),

48
dev/verilog/work/fu_byp.v
Unescape Escape View File

@ -631,7 +631,8 @@ module fu_byp(

wire byp_ex2_d1clk;
wire byp_ex2_d2clk;
wire [0:`NCLK_WIDTH-1] byp_ex2_lclk;
//wire [0:`NCLK_WIDTH-1] byp_ex2_lclk;
wire byp_ex2_lclk;
wire ex1_c_frac_pre3_hulp_b;
wire ex1_hulp_sp;
wire ex1_c_frac_pre_hulp;
@ -1989,7 +1990,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_b_alg_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_b_frac_si), //in
@ -2002,7 +2004,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_a_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_frac_a_fmt_si), //in
@ -2015,7 +2018,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_c_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_frac_c_fmt_si), //in
@ -2028,7 +2032,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_b_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_frac_b_fmt_si), //in
@ -2051,7 +2056,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(54), .NEEDS_SRESET(0)) ex2_frac_c_mul_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(frac_mul_c_si), //in
@ -2065,7 +2071,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(55), .NEEDS_SRESET(0)) ex2_frac_a_mul_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(frac_mul_a_si), //in
@ -2198,7 +2205,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_alg_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_b_alg_si), //in
@ -2213,7 +2221,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex2_expo_c_alg_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_c_alg_si), //in
@ -2226,7 +2235,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex2_expo_a_alg_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_a_alg_si), //in
@ -2239,7 +2249,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_b_fmt_si), //in
@ -2254,7 +2265,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_a_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_a_fmt_si), //in
@ -2269,7 +2281,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_c_fmt_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_c_fmt_si), //in
@ -2284,7 +2297,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_eie_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_b_eie_si), //in
@ -2299,7 +2313,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14),.NEEDS_SRESET(0)) ex2_expo_a_eie_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_a_eie_si), //in
@ -2314,7 +2329,8 @@ module fu_byp(
tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_c_eie_lat(
.vd(vdd),
.gd(gnd),
.lclk(byp_ex2_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(byp_ex2_d1clk), //in
.d2clk(byp_ex2_d2clk), //in
.scanin(ex2_expo_c_eie_si), //in

10
dev/verilog/work/fu_dcd.v
Unescape Escape View File

@ -1531,7 +1531,7 @@ module fu_dcd(
wire func_slp_sl_force;
wire func_slp_sl_thold_0_b;
wire cfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
//wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;

assign tilo = 1'b0;
assign tihi = 1'b1;
@ -1719,17 +1719,23 @@ module fu_dcd(
.thold_b(func_slp_sl_thold_0_b)
);

/*
tri_lcbs lcbs_cfg(
.vd(vdd),
.gd(gnd),
.delay_lclkr(delay_lclkr[9]),
.clk(clk),
.rst(rst),
.rst(rst),
.force_t(cfg_sl_force),
.thold_b(cfg_sl_thold_0_b),
.dclk(cfg_slat_d2clk),
.lclk(cfg_slat_lclk)
);
*/
// tri_lcbs dclk=thold lclk=clk,rst
wire func_slat_lclk, abst_slat_lclk, cfg_slat_lclk;
assign cfg_slat_d2clk = 0;
assign cfg_slat_lclk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) cfg_stg(
.vd(vdd),

12
dev/verilog/work/fu_eov.v
Unescape Escape View File

@ -337,7 +337,8 @@ module fu_eov(
wire ex5_unf_calc_1_b;
wire ex6_d1clk;
wire ex6_d2clk;
wire [0:`NCLK_WIDTH-1] ex6_lclk;
//wire [0:`NCLK_WIDTH-1] ex6_lclk;
wire ex6_lclk;
(* analysis_not_referenced="TRUE" *) // unused
wire unused;

@ -965,7 +966,8 @@ module fu_eov(
tri_nand2_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex6_urnd0_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_urnd0_si),
@ -978,7 +980,8 @@ module fu_eov(
tri_nand2_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex6_urnd1_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_urnd1_si),
@ -991,7 +994,8 @@ module fu_eov(
tri_nand2_nlats #(.WIDTH(3), .NEEDS_SRESET(0)) ex6_ovctl_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_ovctl_si),

18
dev/verilog/work/fu_lza.v
Unescape Escape View File

@ -160,8 +160,10 @@ module fu_lza(
wire lza_ex5_d2clk;
wire lza_ex4_d1clk;
wire lza_ex4_d2clk;
wire [0:`NCLK_WIDTH-1] lza_ex5_lclk;
wire [0:`NCLK_WIDTH-1] lza_ex4_lclk;
//wire [0:`NCLK_WIDTH-1] lza_ex5_lclk;
//wire [0:`NCLK_WIDTH-1] lza_ex4_lclk;
wire lza_ex4_lclk;
wire lza_ex5_lclk;

//=###############################################################
//= map block attributes
@ -285,7 +287,8 @@ module fu_lza(
tri_inv_nlats #(.WIDTH(163), .NEEDS_SRESET(0)) ex4_lzo_lat(
.vd(vdd),
.gd(gnd),
.lclk(lza_ex4_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(lza_ex4_d1clk),
.d2clk(lza_ex4_d2clk),
.scanin(ex4_lzo_si),
@ -304,7 +307,8 @@ module fu_lza(
tri_inv_nlats #(.WIDTH(1), .NEEDS_SRESET(0)) ex4_sub_lat(
.vd(vdd),
.gd(gnd),
.lclk(lza_ex4_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(lza_ex4_d1clk),
.d2clk(lza_ex4_d2clk),
.scanin(ex4_sub_si[0]),
@ -370,7 +374,8 @@ module fu_lza(
tri_inv_nlats #(.WIDTH(9), .NEEDS_SRESET(0)) ex5_dcd_lat(
.vd(vdd),
.gd(gnd),
.lclk(lza_ex5_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(lza_ex5_d1clk),
.d2clk(lza_ex5_d2clk),
.scanin(ex5_dcd_si[0:8]),
@ -400,7 +405,8 @@ module fu_lza(
tri_nand2_nlats #(.WIDTH(16), .NEEDS_SRESET(0)) ex5_amt_lat(
.vd(vdd),
.gd(gnd),
.lclk(lza_ex5_lclk), //in --lclk.clk
.clk(clk), //in --lclk.clk
.rst(rst),
.d1clk(lza_ex5_d1clk), //in
.d2clk(lza_ex5_d2clk), //in
.scanin(ex5_amt_si[0:15]),

12
dev/verilog/work/fu_nrm.v
Unescape Escape View File

@ -203,7 +203,8 @@ module fu_nrm(
wire ex5_sticky_sp_x1;
wire ex6_d1clk;
wire ex6_d2clk;
wire [0:`NCLK_WIDTH-1] ex6_lclk;
//wire [0:`NCLK_WIDTH-1] ex6_lclk;
wire ex6_lclk;
wire ex5_sticky_stuff;

// sticky bit sp/dp does not look at all the bits
@ -484,7 +485,8 @@ module fu_nrm(
tri_nand2_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex6_res_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_res_si),
@ -498,7 +500,8 @@ module fu_nrm(
tri_nand2_nlats #(.WIDTH(4), .NEEDS_SRESET(0)) ex6_nrm_lg_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_nrm_lg_si),
@ -524,7 +527,8 @@ module fu_nrm(
tri_nand2_nlats #(.WIDTH(3), .NEEDS_SRESET(0)) ex6_nrm_x_lat(
.vd(vdd),
.gd(gnd),
.lclk(ex6_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(ex6_d1clk),
.d2clk(ex6_d2clk),
.scanin(ex6_nrm_x_si),

12
dev/verilog/work/fu_sa3.v
Unescape Escape View File

@ -120,7 +120,8 @@ module fu_sa3(
wire [53:161] ex4_car_add_b;
wire sa3_ex4_d2clk;
wire sa3_ex4_d1clk;
wire [0:`NCLK_WIDTH-1] sa3_ex4_lclk;
//wire [0:`NCLK_WIDTH-1] sa3_ex4_lclk;
wire sa3_ex4_lclk;


wire [0:52] ex3_alg_b;
@ -1258,7 +1259,8 @@ module fu_sa3(
tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex4_000_lat(
.vd(vdd),
.gd(gnd),
.lclk(sa3_ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(sa3_ex4_d1clk),
.d2clk(sa3_ex4_d2clk),
.scanin(ex4_000_si),
@ -1270,7 +1272,8 @@ module fu_sa3(
tri_inv_nlats #(.WIDTH(110), .NEEDS_SRESET(0)) ex4_053_sum_lat(
.vd(vdd),
.gd(gnd),
.lclk(sa3_ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(sa3_ex4_d1clk),
.d2clk(sa3_ex4_d2clk),
.scanin(ex4_053_sum_si),
@ -1282,7 +1285,8 @@ module fu_sa3(
tri_inv_nlats #(.WIDTH(109), .NEEDS_SRESET(0)) ex4_053_car_lat(
.vd(vdd),
.gd(gnd),
.lclk(sa3_ex4_lclk), //lclk.clk
.clk(clk), //lclk.clk
.rst(rst),
.d1clk(sa3_ex4_d1clk),
.d2clk(sa3_ex4_d2clk),
.scanin(ex4_053_car_si),

18
dev/verilog/work/fu_tbllut.v
Unescape Escape View File

@ -202,8 +202,10 @@ module fu_tbllut(
wire tbl_ex4_d2clk;
wire tbl_ex5_d1clk;
wire tbl_ex5_d2clk;
wire [0:`NCLK_WIDTH-1] tbl_ex4_lclk;
wire [0:`NCLK_WIDTH-1] tbl_ex5_lclk;
//wire [0:`NCLK_WIDTH-1] tbl_ex4_lclk;
//wire [0:`NCLK_WIDTH-1] tbl_ex5_lclk;
wire tbl_ex4_lclk;
wire tbl_ex5_lclk;
wire unused;
wire [0:36] ex5_tbl_sum_b;
wire [0:35] ex5_tbl_car_b;
@ -312,7 +314,8 @@ module fu_tbllut(
tri_inv_nlats #(.WIDTH(20), .NEEDS_SRESET(0)) ex4_lut_e_lat(
.vd(vdd),
.gd(gnd),
.lclk(tbl_ex4_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(tbl_ex4_d1clk),
.d2clk(tbl_ex4_d2clk),
.scanin(ex4_lut_e_si),
@ -325,7 +328,8 @@ module fu_tbllut(
tri_inv_nlats #(.WIDTH(15), .NEEDS_SRESET(0)) ex4_lut_r_lat(
.vd(vdd),
.gd(gnd),
.lclk(tbl_ex4_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(tbl_ex4_d1clk),
.d2clk(tbl_ex4_d2clk),
.scanin(ex4_lut_r_si),
@ -338,7 +342,8 @@ module fu_tbllut(
tri_inv_nlats #(.WIDTH(16), .NEEDS_SRESET(0)) ex4_lut_b_lat(
.vd(vdd),
.gd(gnd),
.lclk(tbl_ex4_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(tbl_ex4_d1clk),
.d2clk(tbl_ex4_d2clk),
.scanin(ex4_lut_b_si),
@ -374,7 +379,8 @@ module fu_tbllut(
tri_inv_nlats #(.WIDTH(80), .NEEDS_SRESET(0)) ex5_lut_lat(
.vd(vdd),
.gd(gnd),
.lclk(tbl_ex5_lclk), // lclk.clk
.clk(clk), // lclk.clk
.rst(rst),
.d1clk(tbl_ex5_d1clk),
.d2clk(tbl_ex5_d2clk),
.scanin(ex5_lut_si),

9
dev/verilog/work/iuq_ic_ierat.v
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@ -946,7 +946,7 @@ module iuq_ic_ierat(
wire pc_cfg_slp_sl_thold_0_b;
wire pc_cfg_slp_sl_force;
wire lcb_dclk;
wire [0:`NCLK_WIDTH-1] lcb_lclk;
//wire [0:`NCLK_WIDTH-1] lcb_lclk;
wire init_alias;

// Clock Gating
@ -7413,7 +7413,7 @@ assign ex6_data_maskpar =
//------------------------------------------------
// local clock buffer for boot config
//------------------------------------------------

/*
tri_lcbs bcfg_lcb(
.vd(vdd),
.gd(gnd),
@ -7425,6 +7425,11 @@ assign ex6_data_maskpar =
.dclk(lcb_dclk),
.lclk(lcb_lclk)
);
*/
// tri_lcbs dclk=thold lclk=clk,rst
wire lcb_lclk;
assign lcb_lclk = 0;
assign lcb_dclk = 0;

// these terms in the absence of another lcbor component
// that drives the thold_b and force into the bcfg_lcb for slat's

5
dev/verilog/work/iuq_ram.v
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@ -28,6 +28,8 @@

`timescale 1 ns / 1 ns

`include "tri_a2o.vh"

// *********************************************************************
//
// This is the ENTITY for iuq_ram
@ -60,9 +62,6 @@ module iuq_ram(
scan_in,
scan_out
);
`include "tri_a2o.vh"
// parameter `EXPAND_TYPE = 2;
// parameter `THREADS = 2; // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg
input [0:31] pc_iu_ram_instr;
input [0:3] pc_iu_ram_instr_ext;
input pc_iu_ram_issue;

3
dev/verilog/work/iuq_spr.v
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@ -697,11 +697,10 @@ module iuq_spr(

//init 0x000000F9
tri_rlmreg_p #(.WIDTH(16), .INIT(`INIT_IUCR0)) iucr0_reg(
// generic map (width => iucr0_l2'length, init => 249, `EXPAND_TYPE => `EXPAND_TYPE)
.vd(vdd),
.gd(gnd),
.clk(clk),
.rst(rst),
.rst(rst),
.act(iucr0_wren),
.thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0),

9
dev/verilog/work/lq_arb.v
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@ -41,15 +41,6 @@

`include "tri_a2o.vh"

// parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
// `define LOAD_CREDITS 16
// `define STORE_CREDITS 32
// parameter ITAG_SIZE_ENC = 7;
// parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE
// parameter THREADS = 2; // Number of Threads in the system
// parameter STQ_DATA_SIZE = 64; // 64 or 128 Bit store data sizes supported
// parameter REAL_IFAR_WIDTH = 42; // real addressing bits

module lq_arb(
imq_arb_iuq_ld_req_avail,
imq_arb_iuq_tid,

72
dev/verilog/work/lq_ctl.v
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@ -519,37 +519,6 @@ module lq_ctl(
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2;
//parameter `GPR_WIDTH_ENC = 6;
//parameter `XER_POOL_ENC = 4;
//parameter `CR_POOL_ENC = 5;
//parameter `GPR_POOL_ENC = 6;
//parameter `AXU_SPARE_ENC = 3;
//parameter `THREADS_POOL_ENC = 1;
//parameter `ITAG_SIZE_ENC = 7; // Instruction Tag Size
//parameter `CR_WIDTH = 4;
//parameter `UCODE_ENTRIES_ENC = 3;
//parameter `STQ_DATA_SIZE = 64; // 64 or 128 Bit store data sizes supported
//parameter ``FXU0_PIPE_START = 2;
//parameter `XU0_PIPE_END = 8;
//parameter ``FXU1_PIPE_START = 2;
//parameter `XU1_PIPE_END = 5;
//parameter `LQ_LOAD_PIPE_START = 4;
//parameter `LQ_LOAD_PIPE_END = 8;
//parameter `LQ_REL_PIPE_START = 2;
//parameter `LQ_REL_PIPE_END = 4;
//parameter `THREADS = 2;
//parameter `DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D$
//parameter `CL_SIZE = 6;
//parameter `LMQ_ENTRIES = 8;
//parameter `EMQ_ENTRIES = 4;
//parameter `REAL_IFAR_WIDTH = 42; // 42 bit real address
//parameter `LDSTQ_ENTRIES = 16; // Order Queue Size
//parameter `PF_IFAR_WIDTH = 12; // number of IAR bits used by prefetch
//parameter `BUILD_PFETCH = 1; // 1=> include pfetch in the build, 0=> build without pfetch
//parameter `PFETCH_INITIAL_DEPTH = 0; // the initial value for the SPR that determines how many lines to prefetch
//parameter ``PFETCH_Q_SIZE_ENC = 3; // number of bits to address queue size (3 => 8 entries, 4 => 16 entries)
//parameter `PFETCH_Q_SIZE = 8; // number of entries in prefetch queue
parameter WAYDATASIZE = 34; // TagSize + Parity Bits
parameter XU0_PIPE_START = `FXU0_PIPE_START+1;
parameter XU0_PIPE_END = `FXU0_PIPE_END;
@ -1577,19 +1546,19 @@ wire [4:9] pc_lq_abist_waddr_0
wire slat_force;
wire abst_slat_thold_b;
wire abst_slat_d2clk;
wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
//wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
wire time_slat_thold_b;
wire time_slat_d2clk;
wire [0:`NCLK_WIDTH-1] time_slat_lclk;
//wire [0:`NCLK_WIDTH-1] time_slat_lclk;
wire repr_slat_thold_b;
wire repr_slat_d2clk;
wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
//wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
wire func_slat_thold_b;
wire func_slat_d2clk;
wire [0:`NCLK_WIDTH-1] func_slat_lclk;
//wire [0:`NCLK_WIDTH-1] func_slat_lclk;
wire regf_slat_thold_b;
wire regf_slat_d2clk;
wire [0:`NCLK_WIDTH-1] regf_slat_lclk;
//wire [0:`NCLK_WIDTH-1] regf_slat_lclk;
wire [0:3] abst_scan_q;
wire [0:3] abst_scan_q_b;
wire [0:3] time_scan_q;
@ -3558,7 +3527,7 @@ assign repr_slat_thold_b = (~repr_sl_thold_0);
assign func_slat_thold_b = (~func_sl_thold_0);
assign regf_slat_thold_b = (~regf_slp_sl_thold_0);


/*
tri_lcbs perv_lcbs_abst(
.vd(vdd),
.gd(gnd),
@ -3570,6 +3539,11 @@ tri_lcbs perv_lcbs_abst(
.dclk(abst_slat_d2clk),
.lclk(abst_slat_lclk)
);
*/
// tri_lcbs dclk=thold lclk=clk,rst
wire abst_slat_lclk;
assign abst_slat_lclk = 0;
assign abst_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_abst_stg(
.vd(vdd),
@ -3588,6 +3562,7 @@ tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_abst_stg(
.q_b(abst_scan_q_b)
);

/*
tri_lcbs perv_lcbs_time(
.vd(vdd),
.gd(gnd),
@ -3599,7 +3574,11 @@ tri_lcbs perv_lcbs_time(
.dclk(time_slat_d2clk),
.lclk(time_slat_lclk)
);

*/
// tri_lcbs dclk=thold lclk=clk,rst
wire time_slat_lclk;
assign time_slat_lclk = 0;
assign time_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_time_stg(
.vd(vdd),
@ -3618,6 +3597,7 @@ tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_time_stg(
.q_b(time_scan_q_b)
);

/*
tri_lcbs perv_lcbs_repr(
.vd(vdd),
.gd(gnd),
@ -3629,7 +3609,10 @@ tri_lcbs perv_lcbs_repr(
.dclk(repr_slat_d2clk),
.lclk(repr_slat_lclk)
);

*/
wire repr_slat_lclk;
assign repr_slat_lclk = 0;
assign repr_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) perv_repr_stg(
.vd(vdd),
@ -3646,6 +3629,7 @@ tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) perv_repr_stg(
.q_b(repr_scan_q_b)
);

/*
tri_lcbs perv_lcbs_func(
.vd(vdd),
.gd(gnd),
@ -3657,6 +3641,10 @@ tri_lcbs perv_lcbs_func(
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk)
);
*/
wire func_slat_lclk;
assign func_slat_lclk = 0;
assign func_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(22), .INIT(22'b0000000000000000000000)) perv_func_stg(
.vd(vdd),
@ -3711,6 +3699,7 @@ tri_slat_scan #(.WIDTH(22), .INIT(22'b0000000000000000000000)) perv_func_stg(
.q_b(func_scan_q_b)
);

/*
tri_lcbs perv_lcbs_regf(
.vd(vdd),
.gd(gnd),
@ -3722,7 +3711,10 @@ tri_lcbs perv_lcbs_regf(
.dclk(regf_slat_d2clk),
.lclk(regf_slat_lclk)
);

*/
wire regf_slat_lclk;
assign regf_slat_lclk = 0;
assign regf_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(14), .INIT(14'b00000000000000)) perv_regf_stg(
.vd(vdd),

43
dev/verilog/work/lq_data.v
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@ -131,13 +131,6 @@ module lq_data(
func_scan_out
);

//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//parameter GPR_WIDTH_ENC = 6; // Register Mode 5 = 32bit, 6 = 64bit
//parameter DC_SIZE = 15; // 2^15 = 32768 Bytes L1 D$

// Execution Pipe
input ctl_dat_ex1_data_act;
input [52:59] ctl_dat_ex2_eff_addr;
@ -378,16 +371,16 @@ wire pc_lq_abist_g8t1p_renb_0_q;
wire slat_force;
wire abst_slat_thold_b;
wire abst_slat_d2clk;
wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
//wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
wire time_slat_thold_b;
wire time_slat_d2clk;
wire [0:`NCLK_WIDTH-1] time_slat_lclk;
//wire [0:`NCLK_WIDTH-1] time_slat_lclk;
wire repr_slat_thold_b;
wire repr_slat_d2clk;
wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
//wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
wire func_slat_thold_b;
wire func_slat_d2clk;
wire [0:`NCLK_WIDTH-1] func_slat_lclk;
//wire [0:`NCLK_WIDTH-1] func_slat_lclk;
wire [0:7] abst_scan_q;
wire [0:7] abst_scan_q_b;
wire [0:1] time_scan_q;
@ -1052,7 +1045,7 @@ assign time_slat_thold_b = (~time_sl_thold_0);
assign repr_slat_thold_b = (~repr_sl_thold_0);
assign func_slat_thold_b = (~func_sl_thold_0);


/*
tri_lcbs perv_lcbs_abst(
.vd(vdd),
.gd(gnd),
@ -1064,7 +1057,10 @@ tri_lcbs perv_lcbs_abst(
.dclk(abst_slat_d2clk),
.lclk(abst_slat_lclk)
);

*/
wire abst_slat_lclk;
assign abst_slat_lclk = 0;
assign abst_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(8), .INIT(8'b00000000)) perv_abst_stg(
.vd(vdd),
@ -1077,7 +1073,7 @@ tri_slat_scan #(.WIDTH(8), .INIT(8'b00000000)) perv_abst_stg(
.q_b(abst_scan_q_b)
);


/*
tri_lcbs perv_lcbs_time(
.vd(vdd),
.gd(gnd),
@ -1089,7 +1085,10 @@ tri_lcbs perv_lcbs_time(
.dclk(time_slat_d2clk),
.lclk(time_slat_lclk)
);

*/
wire time_slat_lclk;
assign time_slat_lclk = 0;
assign time_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_time_stg(
.vd(vdd),
@ -1102,7 +1101,7 @@ tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_time_stg(
.q_b(time_scan_q_b)
);


/*
tri_lcbs perv_lcbs_repr(
.vd(vdd),
.gd(gnd),
@ -1114,7 +1113,10 @@ tri_lcbs perv_lcbs_repr(
.dclk(repr_slat_d2clk),
.lclk(repr_slat_lclk)
);

*/
wire repr_slat_lclk;
assign repr_slat_lclk = 0;;
assign repr_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_repr_stg(
.vd(vdd),
@ -1127,7 +1129,7 @@ tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_repr_stg(
.q_b(repr_scan_q_b)
);


/*
tri_lcbs perv_lcbs_func(
.vd(vdd),
.gd(gnd),
@ -1139,7 +1141,10 @@ tri_lcbs perv_lcbs_func(
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk)
);

*/
wire func_slat_lclk;
assign func_slat_lclk = 0;
assign func_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(14), .INIT(14'b00000000000000)) perv_func_stg(
.vd(vdd),

20
dev/verilog/work/lq_dec.v
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@ -33,8 +33,6 @@

`include "tri_a2o.vh"



module lq_dec(
clk,
rst,
@ -210,24 +208,6 @@ module lq_dec(
dcc_dec_ex5_wren
);

//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2;
//parameter `GPR_WIDTH_ENC = 6;
//parameter `XER_POOL_ENC = 4;
//parameter `CR_POOL_ENC = 5;
//parameter `GPR_POOL_ENC = 6;
//parameter `AXU_SPARE_ENC = 3;
//parameter `CL_SIZE = 6;
//parameter `REAL_IFAR_WIDTH = 42;
//parameter `UCODE_ENTRIES_ENC = 3;
//parameter `THREADS = 2;
//parameter `THREADS_POOL_ENC = 1;
//parameter `ITAG_SIZE_ENC = 7;



inout vdd;
inout gnd;
input clk;

22
dev/verilog/work/lq_derat.v
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@ -209,18 +209,6 @@ module lq_derat(
derat_xu_debug_group3
);

// Parameters used from tri_a2o.vh

// parameter EXPAND_TYPE = 1;
// parameter GPR_WIDTH_ENC = 6;
// parameter ITAG_SIZE_ENC = 7;
// parameter EMQ_ENTRIES = 4;
// parameter THREADS = 2;





inout gnd;
inout vdd;
inout vcs;
@ -1245,7 +1233,7 @@ module lq_derat(
wire pc_cfg_slp_sl_thold_0_b;
wire pc_cfg_slp_sl_force;
wire lcb_dclk;
wire [0:`NCLK_WIDTH-1] lcb_lclk;
//wire [0:`NCLK_WIDTH-1] lcb_lclk;
wire init_alias;
// Clock Gating
wire clkg_ctl_override_d;
@ -10338,18 +10326,22 @@ module lq_derat(
//------------------------------------------------
// local clock buffer for boot config
//------------------------------------------------

/*
tri_lcbs bcfg_lcb(
.vd(vdd),
.gd(gnd),
.delay_lclkr(lcb_delay_lclkr_dc[0]),
.clk(clk),
.rst(rst),
.rst(rst),
.force_t(pc_cfg_slp_sl_force),
.thold_b(pc_cfg_slp_sl_thold_0_b),
.dclk(lcb_dclk),
.lclk(lcb_lclk)
);
*/
wire lcb_lclk;
assign lcb_lclk = 0;
assign lcb_dclk = 0;
// these terms in the absence of another lcbor component
// that drives the thold_b and force into the bcfg_lcb for slat's
assign pc_cfg_slp_sl_thold_0_b = (~pc_cfg_slp_sl_thold_0);

10
dev/verilog/work/lq_dir.v
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@ -207,16 +207,6 @@ module lq_dir(
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2;
//parameter THREADS = 2;
//parameter ITAG_SIZE_ENC = 7;
//parameter DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D$
//parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE
//parameter LMQ_ENTRIES = 8;
//parameter CR_POOL_ENC = 5;
//parameter UCODE_ENTRIES_ENC = 3;
//parameter REAL_IFAR_WIDTH = 42;
//parameter `GPR_WIDTH_ENC = 6;
parameter WAYDATASIZE = 34; // TagSize + Parity Bits
parameter PARBITS = 4;


8
dev/verilog/work/lq_dir_lru.v
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@ -148,14 +148,6 @@ module lq_dir_lru(
scan_out
);

//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//parameter LMQ_ENTRIES = 8; // Number of Loadmiss Queue Entries
//parameter DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D$
//parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE

// ACT's
input dcc_dir_ex2_stg_act;
input dcc_dir_ex3_stg_act;

4
dev/verilog/work/lq_dir_tag.v
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@ -121,10 +121,6 @@ module lq_dir_tag(
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2;
//parameter `DC_SIZE = 15;
//parameter `CL_SIZE = 6;
//parameter `REAL_IFAR_WIDTH = 42;
parameter WAYDATASIZE = 34; // TagSize + Parity Bits
parameter PARBITS = 4;


4
dev/verilog/work/lq_dir_tag_arr.v
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@ -93,10 +93,6 @@ module lq_dir_tag_arr(
//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//parameter `DC_SIZE = 15; // 2^14 = 16384, 2^15 = 32768 Bytes L1 D$
//parameter `CL_SIZE = 6; // 2^6 = 64 Bytes CacheLines
//parameter `REAL_IFAR_WIDTH = 42; // 42 bit real address
parameter WAYDATASIZE = 34; // TagSize + Parity Bits
parameter PARBITS = 4; // Parity Bits


8
dev/verilog/work/lq_dir_val.v
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@ -224,14 +224,6 @@ module lq_dir_val(
scan_out
);

//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//parameter THREADS = 2;
//parameter DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D$
//parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE

// ACT's
input dcc_dir_ex2_stg_act;
input dcc_dir_ex3_stg_act;

9
dev/verilog/work/lq_fgen.v
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@ -177,15 +177,6 @@ module lq_fgen(
scan_out
);

//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2;
//parameter THREADS = 2;
//parameter UCODE_ENTRIES_ENC = 3;
//parameter THREADS_POOL_ENC = 1;
//parameter ITAG_SIZE_ENC = 7;

// IU Dispatch to RV0
input [0:`THREADS-1] ex0_i0_vld;
input ex0_i0_ucode_preissue;

6
dev/verilog/work/lq_imq.v
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@ -42,12 +42,6 @@

`include "tri_a2o.vh"

// parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
// parameter THREADS = 2; // Number of Threads
// `define IUQ_ENTRIES 4 // Instruction Fetch Queue Size
// `define MMQ_ENTRIES 2 // MMU Queue Size
// parameter REAL_IFAR_WIDTH = 42; // real addressing bits

module lq_imq(
iu_lq_request,
iu_lq_cTag,

16
dev/verilog/work/lq_ldq.v
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@ -277,22 +277,6 @@ module lq_ldq(
repr_scan_out
);

//-------------------------------------------------------------------
// Generics
//-------------------------------------------------------------------
//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
//parameter `THREADS = 2; // Number of `THREADS in the System
//parameter `GPR_WIDTH_ENC = 6; // Register Mode 5 = 32bit, 6 = 64bit
//parameter `GPR_POOL_ENC = 6;
//parameter `AXU_SPARE_ENC = 3;
//parameter `THREADS_POOL_ENC = 1;
//parameter `LMQ_ENTRIES = 8; // Load/Store Queue Size
//parameter `LGQ_ENTRIES = 8; // Load Gather Queue Size
//parameter `ITAG_SIZE_ENC = 7; // ITAG size
//parameter `DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D$
//parameter `CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE
//parameter `REAL_IFAR_WIDTH = 42; // real addressing bits

// RV1 RV Issue Valid
input [0:`THREADS-1] rv_lq_vld;
input rv_lq_isLoad;

62
dev/verilog/work/lq_lsq.v
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@ -404,31 +404,7 @@ module lq_lsq(
repr_scan_out,
func_scan_out
);
// parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
// parameter GPR_WIDTH_ENC = 6; // Register Mode 5 = 32bit, 6 = 64bit
// parameter LDSTQ_ENTRIES = 16; // Order Queue Size
// parameter LDSTQ_ENTRIES_ENC = 4; // Order Queue Size Encoded
// parameter LMQ_ENTRIES = 8; // Loadmiss Queue Size
// parameter LMQ_ENTRIES_ENC = 3; // Loadmiss Queue Size Encoded
// parameter LGQ_ENTRIES = 8; // Load Gather Queue Size
// parameter STQ_ENTRIES = 12; // Store Queue Size
// parameter STQ_ENTRIES_ENC = 4; // Store Queue Size Encoded
// parameter STQ_FWD_ENTRIES = 4; // number of stq entries that can be forwarded from
// parameter STQ_DATA_SIZE = 64; // 64 or 128 Bit store data sizes supported
// parameter IUQ_ENTRIES = 4; // Instruction Fetch Queue Size
// parameter MMQ_ENTRIES = 1; // Memory Management Queue Size
// parameter ITAG_SIZE_ENC = 7; // ITAG size
// parameter CR_POOL_ENC = 5; // Encode of CR rename pool size
// parameter GPR_POOL_ENC = 6;
// parameter AXU_SPARE_ENC = 3;
// parameter THREADS_POOL_ENC = 1;
// parameter DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D
// parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE
// parameter LOAD_CREDITS = 8;
// parameter STORE_CREDITS = 32;
// parameter THREADS = 2; // Number of Threads in the System
// parameter CR_WIDTH = 4;
// parameter REAL_IFAR_WIDTH = 42; // real addressing bits

parameter WAYDATASIZE = 34; // TagSize + Parity Bits

// IU interface to RV for instruction insertion
@ -1228,16 +1204,16 @@ module lq_lsq(
wire slat_force;
wire abst_slat_thold_b;
wire abst_slat_d2clk;
wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
//wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
wire time_slat_thold_b;
wire time_slat_d2clk;
wire [0:`NCLK_WIDTH-1] time_slat_lclk;
//wire [0:`NCLK_WIDTH-1] time_slat_lclk;
wire repr_slat_thold_b;
wire repr_slat_d2clk;
wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
//wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
wire func_slat_thold_b;
wire func_slat_d2clk;
wire [0:`NCLK_WIDTH-1] func_slat_lclk;
//wire [0:`NCLK_WIDTH-1] func_slat_lclk;

wire [0:3] abst_scan_q;
wire [0:3] abst_scan_q_b;
@ -3661,7 +3637,7 @@ module lq_lsq(
assign repr_slat_thold_b = (~repr_sl_thold_0);
assign func_slat_thold_b = (~func_sl_thold_0);


/*
tri_lcbs perv_lcbs_abst(
.vd(vdd),
.gd(gnd),
@ -3673,7 +3649,10 @@ module lq_lsq(
.dclk(abst_slat_d2clk),
.lclk(abst_slat_lclk)
);

*/
wire abst_slat_lclk;
assign abst_slat_lclk = 0;
assign abst_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_abst_stg(
.vd(vdd),
@ -3692,7 +3671,7 @@ module lq_lsq(
.q_b(abst_scan_q_b)
);


/*
tri_lcbs perv_lcbs_time(
.vd(vdd),
.gd(gnd),
@ -3704,7 +3683,10 @@ module lq_lsq(
.dclk(time_slat_d2clk),
.lclk(time_slat_lclk)
);

*/
wire time_slat_lclk;
assign time_slat_lclk = 0;
assign time_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) perv_time_stg(
.vd(vdd),
@ -3721,7 +3703,7 @@ module lq_lsq(
.q_b(time_scan_q_b)
);


/*
tri_lcbs perv_lcbs_repr(
.vd(vdd),
.gd(gnd),
@ -3733,7 +3715,10 @@ module lq_lsq(
.dclk(repr_slat_d2clk),
.lclk(repr_slat_lclk)
);

*/
wire repr_slat_lclk;
assign repr_slat_lclk = 0;
assign repr_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) perv_repr_stg(
.vd(vdd),
@ -3750,7 +3735,7 @@ module lq_lsq(
.q_b(repr_scan_q_b)
);


/*
tri_lcbs perv_lcbs_func(
.vd(vdd),
.gd(gnd),
@ -3762,7 +3747,10 @@ module lq_lsq(
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk)
);

*/
wire func_slat_lclk;
assign func_slat_lclk = 0;
assign func_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(14), .INIT(14'b00000000000000)) perv_func_stg(
.vd(vdd),

12
dev/verilog/work/lq_pfetch.v
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@ -35,18 +35,6 @@

`include "tri_a2o.vh"

// parameter EXPAND_TYPE = 2;
// parameter GPR_WIDTH_ENC = 6; // 5 = 32bit mode, 6 = 64bit mode
// parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE
// parameter THREADS = 2; // Number of Threads in the system
// parameter REAL_IFAR_WIDTH = 42; // width of the read address
// parameter ITAG_SIZE_ENC = 7;
// parameter LDSTQ_ENTRIES = 16; // Order Queue Size
// `define PF_IFAR_WIDTH 12 // number of IAR bits used by prefetch
// `define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch
// `define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries)
// `define PFETCH_Q_SIZE 8 // number of entries in prefetch queue

module lq_pfetch(
rv_lq_rv1_i0_vld,
rv_lq_rv1_i0_rte_lq,

17
dev/verilog/work/lq_stq.v
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@ -42,23 +42,6 @@

`include "tri_a2o.vh"

// `define `EXPAND_TYPE 2;
// `define `GPR_WIDTH_ENC 6; // Register Mode 5 32bit, 6 64bit
// `define `STQ_ENTRIES 12; // Store Queue Size
// `define STQ_FWD_ENTRIES 4; // number of stq entries that can be forwarded from
// `define `STQ_ENTRIES_ENC 4; // Store Queue Encoded Size
// `define STQ_DATA_SIZE 64; // 64 or 128 Bit store data sizes supported
// `define `ITAG_SIZE_ENC 7; // ITAG size
// `define `CR_POOL_ENC 5; // Encode of CR rename pool size
// `define `GPR_POOL_ENC 6;
// `define AXU_SPARE_ENC 3;
// `define THREADS_POOL_ENC 1;
// `define DC_SIZE 15; // 14 > 16K L1D$, 15 > 32K L1D$
// `define CL_SIZE 6; // 6 > 64B CLINE, 7 > 128B CLINE
// `define REAL_IFAR_WIDTH 42; // real addressing bits
// `define `THREADS 2;
// `define LMQ_ENTRIES 8;

module lq_stq(
rv_lq_rv1_i0_vld,
rv_lq_rv1_i0_ucode_preissue,

4
dev/verilog/work/mmq.v
Unescape Escape View File

@ -1851,7 +1851,6 @@ mmq_spr #(.BCFG_MMUCR1_VALUE(BCFG_MMUCR1_VALUE), .BCFG_MMUCR2_VALUE(BCFG_MMUCR2_
// Debug Trace component instantiation
//---------------------------------------------------------------------

//work.mmq_dbg #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`TLB_TAG_WIDTH(`TLB_TAG_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_dbg(
mmq_dbg mmq_dbg(
.vdd(vdd),
.gnd(gnd),
@ -2225,7 +2224,6 @@ mmq_dbg mmq_dbg(
// Performance Event component instantiation
//---------------------------------------------------------------------

//work.mmq_perf #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_perf(
mmq_perf mmq_perf(
.vdd(vdd),
.gnd(gnd),
@ -2341,7 +2339,6 @@ mmq_perf mmq_perf(
// Pervasive and LCB Control Component Instantiation
//---------------------------------------------------------------------

//work.mmq_perv #(.`EXPAND_TYPE(`EXPAND_TYPE)) mmq_perv(
mmq_perv mmq_perv(
.vdd(vdd),
.gnd(gnd),
@ -2694,7 +2691,6 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1];
//---------------------------------------------------------------------
// TLB Request Queue Component Instantiation
//---------------------------------------------------------------------
//work.mmq_tlb_req #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`PID_WIDTH(`PID_WIDTH), .`PID_WIDTH_erat(`PID_WIDTH_erat), .`LPID_WIDTH(`LPID_WIDTH), .`EPN_WIDTH(`EPN_WIDTH), .`RS_DATA_WIDTH(`RS_DATA_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_tlb_req(
mmq_tlb_req mmq_tlb_req(
.vdd(vdd),
.gnd(gnd),

74
dev/verilog/work/mmq_perv.v
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@ -275,28 +275,28 @@ module mmq_perv(
wire [0:1] slat_force;
wire abst_slat_thold_b;
wire abst_slat_d2clk;
wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
//wire [0:`NCLK_WIDTH-1] abst_slat_lclk;
wire time_slat_thold_b;
wire time_slat_d2clk;
wire [0:`NCLK_WIDTH-1] time_slat_lclk;
//wire [0:`NCLK_WIDTH-1] time_slat_lclk;
wire repr_slat_thold_b;
wire repr_slat_d2clk;
wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
//wire [0:`NCLK_WIDTH-1] repr_slat_lclk;
wire gptr_slat_thold_b;
wire gptr_slat_d2clk;
wire [0:`NCLK_WIDTH-1] gptr_slat_lclk;
//wire [0:`NCLK_WIDTH-1] gptr_slat_lclk;
wire bcfg_slat_thold_b;
wire bcfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] bcfg_slat_lclk;
//wire [0:`NCLK_WIDTH-1] bcfg_slat_lclk;
wire ccfg_slat_thold_b;
wire ccfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] ccfg_slat_lclk;
//wire [0:`NCLK_WIDTH-1] ccfg_slat_lclk;
wire dcfg_slat_thold_b;
wire dcfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] dcfg_slat_lclk;
//wire [0:`NCLK_WIDTH-1] dcfg_slat_lclk;
wire func_slat_thold_b;
wire func_slat_d2clk;
wire [0:`NCLK_WIDTH-1] func_slat_lclk;
//wire [0:`NCLK_WIDTH-1] func_slat_lclk;

wire pc_abst_sl_thold_0_b;
wire pc_abst_sl_force;
@ -570,7 +570,7 @@ module mmq_perv(
assign dcfg_slat_thold_b = (~pc_cfg_sl_thold_0_int);
assign func_slat_thold_b = (~pc_func_sl_thold_0_int[0]);


/*
tri_lcbs perv_lcbs_abst(
.vd(vdd),
.gd(gnd),
@ -582,7 +582,10 @@ module mmq_perv(
.dclk(abst_slat_d2clk),
.lclk(abst_slat_lclk)
);

*/
wire abst_slat_lclk;
assign abst_slat_lclk = 0;
assign abst_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_abst_stg(
.vd(vdd),
@ -595,7 +598,7 @@ module mmq_perv(
.q_b( perv_abst_stg_q_b)
);


/*
tri_lcbs perv_lcbs_time(
.vd(vdd),
.gd(gnd),
@ -607,7 +610,10 @@ module mmq_perv(
.dclk(time_slat_d2clk),
.lclk(time_slat_lclk)
);

*/
wire time_slat_lclk;
assign time_slat_lclk = 0;
assign time_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_time_stg(
.vd(vdd),
@ -620,7 +626,7 @@ module mmq_perv(
.q_b( perv_time_stg_q_b)
);


/*
tri_lcbs perv_lcbs_repr(
.vd(vdd),
.gd(gnd),
@ -632,7 +638,10 @@ module mmq_perv(
.dclk(repr_slat_d2clk),
.lclk(repr_slat_lclk)
);

*/
wire repr_slat_lclk;
assign repr_slat_lclk = 0;
assign repr_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_repr_stg(
.vd(vdd),
@ -645,8 +654,8 @@ module mmq_perv(
.q_b( perv_repr_stg_q_b)
);


tri_lcbs perv_lcbs_gptr(
/*
tri_lcbs perv_lcbs_gptr(
.vd(vdd),
.gd(gnd),
.delay_lclkr(tiup),
@ -657,7 +666,10 @@ module mmq_perv(
.dclk(gptr_slat_d2clk),
.lclk(gptr_slat_lclk)
);

*/
wire gptr_slat_lclk;
assign gptr_slat_lclk = 0;
assign gptr_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_gptr_stg(
.vd(vdd),
@ -670,7 +682,7 @@ module mmq_perv(
.q_b( perv_gptr_stg_q_b)
);


/*
tri_lcbs perv_lcbs_bcfg(
.vd(vdd),
.gd(gnd),
@ -682,7 +694,10 @@ module mmq_perv(
.dclk(bcfg_slat_d2clk),
.lclk(bcfg_slat_lclk)
);

*/
wire bcfg_slat_lclk;
assign bcfg_slat_lclk = 0;
assign bcfg_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_bcfg_stg(
.vd(vdd),
@ -695,7 +710,7 @@ module mmq_perv(
.q_b( perv_bcfg_stg_q_b)
);


/*
tri_lcbs perv_lcbs_ccfg(
.vd(vdd),
.gd(gnd),
@ -707,7 +722,10 @@ module mmq_perv(
.dclk(ccfg_slat_d2clk),
.lclk(ccfg_slat_lclk)
);

*/
wire ccfg_slat_lclk;
assign ccfg_slat_lclk = 0;
assign ccfg_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_ccfg_stg(
.vd(vdd),
@ -720,7 +738,7 @@ module mmq_perv(
.q_b( perv_ccfg_stg_q_b)
);


/*
tri_lcbs perv_lcbs_dcfg(
.vd(vdd),
.gd(gnd),
@ -732,7 +750,10 @@ module mmq_perv(
.dclk(dcfg_slat_d2clk),
.lclk(dcfg_slat_lclk)
);

*/
wire dcfg_slat_lclk;
assign dcfg_slat_lclk = 0;
assign dcfg_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_dcfg_stg(
.vd(vdd),
@ -745,7 +766,7 @@ module mmq_perv(
.q_b( perv_dcfg_stg_q_b)
);


/*
tri_lcbs perv_lcbs_func(
.vd(vdd),
.gd(gnd),
@ -757,7 +778,10 @@ module mmq_perv(
.dclk(func_slat_d2clk),
.lclk(func_slat_lclk)
);

*/
wire func_slat_lclk;
assign func_slat_lclk = 0;
assign func_slat_d2clk = 0;

tri_slat_scan #(.WIDTH(20), .INIT(20'b00000000000000000000)) perv_func_stg(
.vd(vdd),

10
dev/verilog/work/mmq_spr.v
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@ -1046,7 +1046,7 @@ module mmq_spr(
wire pc_cfg_sl_thold_0_b;
wire pc_cfg_sl_force;
wire lcb_dclk;
wire [0:`NCLK_WIDTH-1] lcb_lclk;
//wire [0:`NCLK_WIDTH-1] lcb_lclk;
wire [47:48] mmucfg_q_b;
wire [45:47] tlb0cfg_q_b;
wire [0:15] bcfg_spare_q_b;
@ -5913,7 +5913,7 @@ endgenerate
//------------------------------------------------
// local clock buffer for boot config
//------------------------------------------------

/*
tri_lcbs bcfg_lcb(
.vd(vdd),
.gd(gnd),
@ -5925,10 +5925,14 @@ endgenerate
.dclk(lcb_dclk),
.lclk(lcb_lclk)
);

*/
wire lcb_lclk;
assign lcb_lclk = 0;
assign lcb_dclk = 0;
end
endgenerate

//wtf why is this an fpga gen only??
generate
if (`EXPAND_TYPE == 1)
begin : fpga_bcfg_gen

6
dev/verilog/work/mmu_a2o.vh
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@ -36,11 +36,12 @@
`ifndef _mmu_a2o_vh_
`define _mmu_a2o_vh_

// why not use main setting?
// there are some expand_type generates within mmq!
`ifndef EXPAND_TYPE
`define EXPAND_TYPE 1 // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG)
`endif


`ifndef EXPAND_TLB_TYPE
`define EXPAND_TLB_TYPE 2 // 0 = erat-only, 1 = tlb logic, 2 = tlb array
`endif
@ -59,7 +60,10 @@
`define WAIT_UPDATES

// Use this line for 2 mmu h/w thread. Comment out for 1 thread design.
//wtf why not use THREADS1 everywhere??? i guess to allow 2 walks even with one thread? (I+D)
`ifndef MM_THREADS2
`define MM_THREADS2
`endif

// set this variable for internal thread-wise generates
`ifdef MM_THREADS2

45
dev/verilog/work/pcq_local_fir2.v
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@ -133,13 +133,13 @@ module pcq_local_fir2(
// Clocks
wire func_d1clk;
wire func_d2clk;
wire [0:`NCLK_WIDTH-1] func_lclk;
//wire [0:`NCLK_WIDTH-1] func_lclk;
wire mode_d1clk;
wire mode_d2clk;
wire [0:`NCLK_WIDTH-1] mode_lclk;
//wire [0:`NCLK_WIDTH-1] mode_lclk;
wire scom_mode_d1clk;
wire scom_mode_d2clk;
wire [0:`NCLK_WIDTH-1] scom_mode_lclk;
//wire [0:`NCLK_WIDTH-1] scom_mode_lclk;
wire func_thold_b;
wire func_force;
wire mode_thold_b;
@ -233,7 +233,6 @@ module pcq_local_fir2(
.lclk(func_lclk)
);


// config ring regs; NOT power managed
tri_lcbor mode_lcbor(
.clkoff_b(lcb_clkoff_dc_b),
@ -246,6 +245,7 @@ module pcq_local_fir2(

assign fir_act = sc_active | (|error_in);

/*
tri_lcbnd mode_lcb(
.act(fir_act), // active during scom access or FIR error input
.vd(vdd),
@ -279,6 +279,7 @@ module pcq_local_fir2(
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk)
);
*/

//--------------------------------------------------------------------
// Mode Registers
@ -288,7 +289,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.clk(clk),
.rst(rst),
.scan_in( mode_si[0:WIDTH - 1]),
.scan_out(mode_so[0:WIDTH - 1]),
.din(fir_action0_in),
@ -300,7 +302,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.clk(clk),
.rst(rst),
.scan_in( mode_si[WIDTH:WIDTH]),
.scan_out(mode_so[WIDTH:WIDTH]),
.din(fir_action0_par_in),
@ -312,7 +315,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.clk(clk),
.rst(rst),
.scan_in( mode_si[(WIDTH + 1):(2*WIDTH)]),
.scan_out(mode_so[(WIDTH + 1):(2*WIDTH)]),
.din(fir_action1_in),
@ -324,7 +328,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.clk(clk),
.rst(rst),
.scan_in( mode_si[(2*WIDTH + 1):(2*WIDTH + 1)]),
.scan_out(mode_so[(2*WIDTH + 1):(2*WIDTH + 1)]),
.din(fir_action1_par_in),
@ -336,7 +341,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.clk(clk),
.rst(rst),
.scan_in( mode_si[(2*WIDTH + 2):(3*WIDTH + 1)]),
.scan_out(mode_so[(2*WIDTH + 2):(3*WIDTH + 1)]),
.din(fir_mask_in),
@ -348,7 +354,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(scom_mode_d1clk),
.d2clk(scom_mode_d2clk),
.lclk(scom_mode_lclk),
.clk(clk),
.rst(rst),
.scan_in( mode_si[(3*WIDTH + 2):(3*WIDTH + 2)]),
.scan_out(mode_so[(3*WIDTH + 2):(3*WIDTH + 2)]),
.din(fir_mask_par_in),
@ -360,7 +367,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(mode_d1clk),
.d2clk(mode_d2clk),
.lclk(mode_lclk),
.clk(clk),
.rst(rst),
.scan_in( mode_si[(3*WIDTH + 3):(4*WIDTH + 2)]),
.scan_out(mode_so[(3*WIDTH + 3):(4*WIDTH + 2)]),
.din(fir_in),
@ -376,7 +384,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.scan_in(func_si[1]),
.scan_out(func_so[1]),
.din(sys_xstop_in),
@ -388,7 +397,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.scan_in(func_si[2]),
.scan_out(func_so[2]),
.din(recov_in),
@ -400,7 +410,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.scan_in(func_si[3]),
.scan_out(func_so[3]),
.din(xstop_in),
@ -412,7 +423,8 @@ module pcq_local_fir2(
.gd(gnd),
.d1clk(func_d1clk),
.d2clk(func_d2clk),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.scan_in(func_si[4]),
.scan_out(func_so[4]),
.din(trace_error_in),
@ -542,7 +554,8 @@ module pcq_local_fir2(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.d2clk(func_d2clk),
.scan_in(func_si[0]),
.scan_out(func_so[0]),

10
dev/verilog/work/pcq_regs.v
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@ -344,10 +344,11 @@ module pcq_regs(
wire force_funcslp;
wire cfgslp_d1clk;
wire cfgslp_d2clk;
wire [0:`NCLK_WIDTH-1] cfgslp_lclk;
//wire [0:`NCLK_WIDTH-1] cfgslp_lclk;
wire cfgslp_lclk;
wire cfg_slat_force;
wire cfg_slat_d2clk;
wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
//wire [0:`NCLK_WIDTH-1] cfg_slat_lclk;
wire cfg_slat_thold_b;
// SCOM satellite/decode signals
wire scom_cch_q;
@ -2377,6 +2378,7 @@ module pcq_regs(
assign cfg_slat_thold_b = (~lcb_cfg_sl_thold_0);
assign cfg_slat_force = lcb_sg_0;

/*
tri_lcbs lcbs_cfg(
.vd(vdd),
.gd(gnd),
@ -2388,6 +2390,10 @@ module pcq_regs(
.dclk(cfg_slat_d2clk),
.lclk(cfg_slat_lclk)
);
*/
wire cfg_slat_lclk;
assign cfg_slat_lclk = 0;
assign cfg_slat_d2clk = 0;

// Config ring thold staging - NOT power managed
tri_lcbor lcbor_cfgslp(

26
dev/verilog/work/pcq_regs_fir.v
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@ -53,9 +53,11 @@ module pcq_regs_fir(
input lcb_cfg_slp_sl_thold_0,
input cfgslp_d1clk,
input cfgslp_d2clk,
input [0:`NCLK_WIDTH-1] cfgslp_lclk,
//input [0:`NCLK_WIDTH-1] cfgslp_lclk,
input cfgslp_lclk,
input cfg_slat_d2clk,
input [0:`NCLK_WIDTH-1] cfg_slat_lclk,
//input [0:`NCLK_WIDTH-1] cfg_slat_lclk,
input cfg_slat_lclk,
input bcfg_scan_in,
output bcfg_scan_out,
input func_scan_in,
@ -216,7 +218,7 @@ module pcq_regs_fir(
// Clocks
wire func_d1clk;
wire func_d2clk;
wire [0:`NCLK_WIDTH-1] func_lclk;
//wire [0:`NCLK_WIDTH-1] func_lclk;
wire func_thold_b;
wire func_force;
// SCOM
@ -658,7 +660,8 @@ module pcq_regs_fir(
.gd(gnd),
.err_d1clk(cfgslp_d1clk), // CAUTION: if LCB uses powersavings,
.err_d2clk(cfgslp_d2clk), // errors must always get reported
.err_lclk(cfgslp_lclk),
.clk(clk),
.rst(rst),
.err_scan_in(bcfg_siv[ BCFG_ERPT1_HLD_OFFSET:BCFG_ERPT1_HLD_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]),
.err_scan_out(bcfg_sov[BCFG_ERPT1_HLD_OFFSET:BCFG_ERPT1_HLD_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]),
.mode_dclk(cfg_slat_d2clk),
@ -681,7 +684,8 @@ module pcq_regs_fir(
.gd(gnd),
.err_d1clk(cfgslp_d1clk), // CAUTION: if LCB uses powersavings,
.err_d2clk(cfgslp_d2clk), // errors must always get reported
.err_lclk(cfgslp_lclk),
.clk(clk),
.rst(rst),
.err_scan_in(bcfg_siv[ BCFG_ERPT2_HLD_OFFSET:BCFG_ERPT2_HLD_OFFSET + SCACK_ERR_RPT_WIDTH - 1]),
.err_scan_out(bcfg_sov[BCFG_ERPT2_HLD_OFFSET:BCFG_ERPT2_HLD_OFFSET + SCACK_ERR_RPT_WIDTH - 1]),
.mode_dclk(cfg_slat_d2clk),
@ -899,7 +903,8 @@ module pcq_regs_fir(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.d2clk(func_d2clk),
.scan_in(func_siv[ FUNC_ERROUT_OFFSET:FUNC_ERROUT_OFFSET + ERROUT_FUNC_SIZE - 1]),
.scan_out(func_sov[FUNC_ERROUT_OFFSET:FUNC_ERROUT_OFFSET + ERROUT_FUNC_SIZE - 1]),
@ -920,7 +925,8 @@ module pcq_regs_fir(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.d2clk(func_d2clk),
.scan_in(func_siv[ FUNC_F0ERR_OFFSET:FUNC_F0ERR_OFFSET + FIR0_WIDTH - 1]),
.scan_out(func_sov[FUNC_F0ERR_OFFSET:FUNC_F0ERR_OFFSET + FIR0_WIDTH - 1]),
@ -932,7 +938,8 @@ module pcq_regs_fir(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.d2clk(func_d2clk),
.scan_in(func_siv[ FUNC_F1ERR_OFFSET:FUNC_F1ERR_OFFSET + FIR1_WIDTH - 1]),
.scan_out(func_sov[FUNC_F1ERR_OFFSET:FUNC_F1ERR_OFFSET + FIR1_WIDTH - 1]),
@ -944,7 +951,8 @@ module pcq_regs_fir(
.d1clk(func_d1clk),
.vd(vdd),
.gd(gnd),
.lclk(func_lclk),
.clk(clk),
.rst(rst),
.d2clk(func_d2clk),
.scan_in(func_siv[ FUNC_F2ERR_OFFSET:FUNC_F2ERR_OFFSET + FIR2_WIDTH - 1]),
.scan_out(func_sov[FUNC_F2ERR_OFFSET:FUNC_F2ERR_OFFSET + FIR2_WIDTH - 1]),

6
dev/verilog/work/xu_alu_add.v
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@ -91,7 +91,8 @@ module xu_alu_add
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;
// Signals
wire [0:`NCLK_WIDTH-1] ex1_rs0_inv_lclk;
//wire [0:`NCLK_WIDTH-1] ex1_rs0_inv_lclk;
wire ex1_rs0_inv_lclk;
wire ex1_rs0_inv_d1clk;
wire ex1_rs0_inv_d2clk;
wire [64-`GPR_WIDTH:63] ex2_rs1_b;
@ -192,7 +193,8 @@ module xu_alu_add
tri_inv_nlats #(.WIDTH(`GPR_WIDTH), .BTR("NLI0001_X1_A12TH"), .INIT(0)) ex1_rs0_inv_b_latch(
.vd(vdd),
.gd(gnd),
.lclk(ex1_rs0_inv_lclk),
.clk(clk),
.rst(rst),
.d1clk(ex1_rs0_inv_d1clk),
.d2clk(ex1_rs0_inv_d2clk),
.scanin(siv[ex2_rs1_inv_b_offset:ex2_rs1_inv_b_offset + `GPR_WIDTH - 1]),

6
dev/verilog/work/xu_spr_cspr.v
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@ -637,7 +637,8 @@ module xu_spr_cspr
wire [0:scan_right_dcfg-1] sov_dcfg;
// Signals
wire [00:63] tidn;
wire [0:`NCLK_WIDTH-1] spare_0_lclk;
//wire [0:`NCLK_WIDTH-1] spare_0_lclk;
wire spare_0_lclk;
wire spare_0_d1clk;
wire spare_0_d2clk;
wire [00:63] tb;
@ -5003,7 +5004,8 @@ wire [0:0] core_event;
tri_inv_nlats #(.WIDTH(16), .BTR("NLI0001_X2_A12TH"), .INIT(0)) spare_0_latch(
.vd(vdd),
.gd(gnd),
.lclk(spare_0_lclk),
.clk(clk),
.rst(rst),
.d1clk(spare_0_d1clk),
.d2clk(spare_0_d2clk),
.scanin(siv[spare_0_offset:spare_0_offset + 16 - 1]),

6
dev/verilog/work/xu_spr_tspr.v
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@ -540,7 +540,8 @@ module xu_spr_tspr
wire [0:scan_right_dcfg-1] sov_dcfg;
// Signals
wire [00:63] tidn;
wire [0:`NCLK_WIDTH-1] spare_0_lclk;
//wire [0:`NCLK_WIDTH-1] spare_0_lclk;
wire spare_0_lclk;
wire spare_0_d1clk;
wire spare_0_d2clk;
wire ex1_opcode_is_31;
@ -4623,7 +4624,8 @@ endgenerate
tri_inv_nlats #(.WIDTH(16), .BTR("NLI0001_X2_A12TH"), .INIT(0)) spare_0_latch(
.vd(vdd),
.gd(gnd),
.lclk(spare_0_lclk),
.clk(clk),
.rst(rst),
.d1clk(spare_0_d1clk),
.d2clk(spare_0_d2clk),
.scanin(siv[spare_0_offset:spare_0_offset + 16 - 1]),

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