start code build process
openpowerwtf
2 years ago
parent
f6a3d5bbf2
commit
373adc7962
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|
||||
10034000
|
||||
00000000
|
||||
10035FFF
|
||||
00000000
|
||||
10034000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
8002F000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
10000000
|
||||
00000000
|
||||
10036000
|
||||
00000000
|
||||
10037FFF
|
||||
00000000
|
||||
10036000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000080
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7CBE6AA6
|
||||
78A53664
|
||||
38A50A80
|
||||
38C50018
|
||||
E8E60000
|
||||
38C50020
|
||||
E9060000
|
||||
7D074050
|
||||
39080001
|
||||
7D0903A6
|
||||
38C00000
|
||||
7CE83B78
|
||||
98C80000
|
||||
39080001
|
||||
4200FFF8
|
||||
39050028
|
||||
F8E80000
|
||||
4E800020
|
||||
480000B8
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
80000A00
|
||||
7C000124
|
||||
4C00012C
|
||||
4BFFF894
|
||||
480000F0
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7C0802A6
|
||||
2C230001
|
||||
41820038
|
||||
2C230010
|
||||
41820070
|
||||
2C230100
|
||||
418200A8
|
||||
2C230107
|
||||
41820120
|
||||
3860FFFF
|
||||
7C0803A6
|
||||
4C000064
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7C7E6AA6
|
||||
4C000064
|
||||
48000038
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7C6C42A6
|
||||
4C000064
|
||||
48000038
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7CBE6AA6
|
||||
78A53664
|
||||
38A50A80
|
||||
38C50028
|
||||
E8E60000
|
||||
98870000
|
||||
38E70001
|
||||
39050020
|
||||
E9080000
|
||||
7C274000
|
||||
38600000
|
||||
40810010
|
||||
39050018
|
||||
E8E80000
|
||||
3860FFFF
|
||||
F8E60000
|
||||
4C000064
|
||||
4800003C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7C6902A6
|
||||
4BFFFCBD
|
||||
7C6903A6
|
||||
7C0803A6
|
||||
38600000
|
||||
4C000064
|
||||
@ -0,0 +1,30 @@
|
||||
9421FFE0
|
||||
90610018
|
||||
81210018
|
||||
9121000C
|
||||
39200000
|
||||
91210008
|
||||
48000024
|
||||
8141000C
|
||||
81210008
|
||||
7D2A4A14
|
||||
39290001
|
||||
9121000C
|
||||
81210008
|
||||
39290001
|
||||
91210008
|
||||
81210008
|
||||
28090009
|
||||
4081FFD8
|
||||
81210018
|
||||
39290037
|
||||
8141000C
|
||||
7C0A4800
|
||||
4082000C
|
||||
39200000
|
||||
4800000C
|
||||
8121000C
|
||||
3D290800
|
||||
7D234B78
|
||||
38210020
|
||||
4E800020
|
||||
@ -0,0 +1,5 @@
|
||||
# Kernel updates/build process
|
||||
|
||||
* test1 - minimal updates to kernel; add linker script and build kernel and test separately
|
||||
* passed coco sim
|
||||
|
||||
@ -0,0 +1 @@
|
||||
../bin
|
||||
@ -0,0 +1,633 @@
|
||||
# © IBM Corp. 2022
|
||||
# Licensed under and subject to the terms of the CC-BY 4.0
|
||||
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
# Additional rights, including the right to physically implement a softcore
|
||||
# that is compliant with the required sections of the Power ISA
|
||||
# Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
# This README will be updated with additional information when OpenPOWER's
|
||||
# license is available.
|
||||
|
||||
# start conversion to simple boot which jumps to bios
|
||||
# this version will work similarly to original fpga test version
|
||||
# the original version did not run from rom; eventually will assume rom and do r/w data copy/init
|
||||
# the rom and test are built into separate memory loads or a single one with addr/data format
|
||||
|
||||
# boot kernel
|
||||
# set up translations
|
||||
# set up timer facilities
|
||||
# set up threads
|
||||
# call user code
|
||||
# process user rc
|
||||
|
||||
# todo:
|
||||
# 1. skip_printf_init flag should be threaded
|
||||
|
||||
.include "defines.s"
|
||||
|
||||
# constants from linker script, or defsym
|
||||
.ifndef STACKSIZE
|
||||
.set STACKSIZE,_stack_size
|
||||
.endif
|
||||
|
||||
.ifndef STACK0
|
||||
.set STACK0,_stack_0
|
||||
.endif
|
||||
|
||||
.ifndef STACK1
|
||||
.set STACK1,_stack_1
|
||||
.endif
|
||||
|
||||
.set STACK2, 0
|
||||
.set STACK3, 0
|
||||
|
||||
.ifndef TEST
|
||||
.set TEST,_test_start
|
||||
.endif
|
||||
|
||||
.section .text
|
||||
|
||||
.global _start
|
||||
_start:
|
||||
|
||||
int_000:
|
||||
b boot_start
|
||||
|
||||
# critical input
|
||||
.align 5
|
||||
int_020:
|
||||
b .
|
||||
|
||||
# debug
|
||||
.align 5
|
||||
int_040:
|
||||
b .
|
||||
|
||||
# dsi
|
||||
.align 5
|
||||
int_060:
|
||||
b .
|
||||
|
||||
# isi
|
||||
.align 5
|
||||
int_080:
|
||||
b .
|
||||
|
||||
# external
|
||||
.align 5
|
||||
int_0A0:
|
||||
b .
|
||||
|
||||
# alignment
|
||||
.align 5
|
||||
int_0C0:
|
||||
b .
|
||||
|
||||
# program
|
||||
.align 5
|
||||
int_0E0:
|
||||
b .
|
||||
|
||||
# fp unavailable
|
||||
.align 5
|
||||
int_100:
|
||||
b .
|
||||
|
||||
# sc
|
||||
.align 5
|
||||
int_120:
|
||||
b int_120_handler
|
||||
|
||||
# apu unavailable
|
||||
.align 5
|
||||
int_140:
|
||||
b .
|
||||
|
||||
# decrementer
|
||||
.align 5
|
||||
int_160:
|
||||
b .
|
||||
|
||||
# fit
|
||||
.align 5
|
||||
int_180:
|
||||
b .
|
||||
|
||||
# watchdog
|
||||
.align 5
|
||||
int_1A0:
|
||||
b .
|
||||
|
||||
# dtlb
|
||||
.align 5
|
||||
int_1C0:
|
||||
b .
|
||||
|
||||
# itlb
|
||||
.align 5
|
||||
int_1E0:
|
||||
b .
|
||||
|
||||
# vector unavailable
|
||||
.align 5
|
||||
int_200:
|
||||
b .
|
||||
|
||||
#
|
||||
.align 5
|
||||
int_220:
|
||||
b .
|
||||
|
||||
#
|
||||
.align 5
|
||||
int_240:
|
||||
b .
|
||||
|
||||
#
|
||||
.align 5
|
||||
int_260:
|
||||
b .
|
||||
|
||||
# doorbell
|
||||
.align 5
|
||||
int_280:
|
||||
b .
|
||||
|
||||
# doorbell critical
|
||||
.align 5
|
||||
int_2A0:
|
||||
b .
|
||||
|
||||
# doorbell guest
|
||||
.align 5
|
||||
int_2C0:
|
||||
b .
|
||||
|
||||
# doorbell guest critical
|
||||
.align 5
|
||||
int_2E0:
|
||||
b .
|
||||
|
||||
# hvsc
|
||||
.align 8
|
||||
int_300:
|
||||
b int_300_handler
|
||||
|
||||
# hvpriv
|
||||
.align 5
|
||||
int_320:
|
||||
b .
|
||||
|
||||
# lrat
|
||||
.align 5
|
||||
int_340:
|
||||
b .
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# initial translation
|
||||
# both erats:
|
||||
# 00000000 1M: (boot)
|
||||
# 10000000 1M: (test)
|
||||
|
||||
.align 8
|
||||
boot_start:
|
||||
|
||||
mfspr r5,tir # who am i?
|
||||
cmpdi r5,0x00 # skip unless T0
|
||||
bne init_t123
|
||||
|
||||
lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
# derat 31 @00000000
|
||||
|
||||
li r0,0x001F # entry #31
|
||||
li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
mtspr mmucr0,r3
|
||||
eratwe r2,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
lwz r10,CONFIG+S_ERATW2(r0) # load parms for erat settings
|
||||
|
||||
# derat 30 @100000000
|
||||
|
||||
li r0,0x001E # entry #30
|
||||
lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
oris r8,r8,0x1000
|
||||
|
||||
eratwe r10,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
# ierat 15 @00000000
|
||||
|
||||
li r0,0x000F # entry #15
|
||||
li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
|
||||
mtspr mmucr0,r3
|
||||
eratwe r2,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
# *** leave the init'd entry 14 for MT access to FFFFFFC0
|
||||
# ierat 13 @10000000
|
||||
|
||||
li r0,0x000D # entry #13
|
||||
lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
|
||||
oris r8,r8,0x1000
|
||||
|
||||
eratwe r10,r0,2
|
||||
eratwe r4,r0,1
|
||||
eratwe r8,r0,0
|
||||
isync
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# init
|
||||
#
|
||||
|
||||
# T0-only
|
||||
# set up any core facilities, then enable the others if config'd
|
||||
init_t0:
|
||||
|
||||
# switch to 64b
|
||||
|
||||
lwz r10,CONFIG+S_MSR(r0)
|
||||
mtmsr r10
|
||||
isync
|
||||
|
||||
# other init
|
||||
|
||||
lis r1,0x0300 # icm=gicm=1
|
||||
mtspr epcr,r1
|
||||
|
||||
# set up timer facs
|
||||
|
||||
li r1,0 # clear
|
||||
mtspr dec,r1
|
||||
mtspr tbh,r1
|
||||
mtspr tbl,r1
|
||||
|
||||
lis r2,0xFE00 # mask: clear enw,wis,wrs,dis,fis,udis
|
||||
mtspr tsr,r2
|
||||
|
||||
mfspr r2,xucr0
|
||||
andi. r2,r2,0x0200 # set tcs=0
|
||||
mtspr xucr0,r2
|
||||
|
||||
mtspr tsr,r1 # clear tsr
|
||||
mtspr tcr,r1 # disable all timers
|
||||
|
||||
# set thread configuration
|
||||
|
||||
lwz r1,CONFIG+S_FLAGS(r0)
|
||||
andi. r1,r1,0xF
|
||||
mtspr tens,r1 # 60:63 = tid 3:0 enabled
|
||||
#not r1,r1
|
||||
#mtspr tenc,r1 # in case T0 is marked disabled
|
||||
isync
|
||||
|
||||
b boot_complete
|
||||
|
||||
# except T0
|
||||
# just worry about myself
|
||||
|
||||
init_t123:
|
||||
|
||||
# switch to 64b
|
||||
|
||||
lwz r10,CONFIG+S_MSR(r0)
|
||||
mtmsr r10
|
||||
isync
|
||||
|
||||
b boot_complete
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
boot_complete:
|
||||
|
||||
# set up thread and hop to it
|
||||
|
||||
lwz r1,CONFIG+S_FLAGS(r0)
|
||||
andis. r1,r1,0x8000 # 1=skip initial printf init
|
||||
bne boot_complete_1
|
||||
bl printf_reset # wipe buffer
|
||||
|
||||
boot_complete_1:
|
||||
|
||||
lwz r1,CONFIG+S_FLAGS(r0)
|
||||
lis r2,0x7FFF # clear printf flag
|
||||
ori r2,r2,0xFFFF
|
||||
and r1,r1,r2
|
||||
stw r1,CONFIG+S_FLAGS(r0)
|
||||
|
||||
mfspr r5,tir # who am i?
|
||||
sldi r5,r5,6 # 64B offset
|
||||
addi r5,r5,CONFIG+T_CONFIG
|
||||
|
||||
lwz r11,T_MSR(r5)
|
||||
ld r12,T_STACK(r5)
|
||||
ld r13,T_ENTRY(r5)
|
||||
|
||||
lwz r1,CONFIG+S_FLAGS(r0)
|
||||
andi. r1,r1,FLAG_EOT_SC
|
||||
beq eot_blr
|
||||
|
||||
eot_sc:
|
||||
|
||||
lwz r2,CONFIG+S_EOT_SC(r0)
|
||||
lis r1,0x4400 # 'sc 1'
|
||||
ori r1,r1,0022
|
||||
std r1,0x0(r2)
|
||||
mtlr r1 # prog will blr to sc
|
||||
b process_start
|
||||
|
||||
eot_blr:
|
||||
|
||||
bl 4
|
||||
mflr r1
|
||||
addi r1,r1,0x30 # !!!!!!!!!!!!!!! <-- WARNING!
|
||||
mtlr r1 # prog will blr to exec_complete
|
||||
|
||||
process_start:
|
||||
|
||||
mtspr srr1,r11 # msr
|
||||
mtspr srr0,r13 # @entry
|
||||
mr r1,r12 # @stack
|
||||
mfspr r3,tir # tid - main(tid) if yall want it
|
||||
|
||||
mfspr r2,tb
|
||||
std r2,T_TIMER_START(r5)
|
||||
rfi
|
||||
nop # !!!!!!!!!!!!!!! pads for lr calc
|
||||
nop
|
||||
nop
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
exec_complete:
|
||||
# allow blr to here, or it will be entered by sc directly
|
||||
|
||||
# user blr'd here...
|
||||
sc 1 # hvsc back to sup state
|
||||
|
||||
exec_complete_sup:
|
||||
mfspr r5,tir # who am i?
|
||||
sldi r5,r5,6 # 64B offset
|
||||
addi r5,r5,CONFIG+T_CONFIG
|
||||
|
||||
mfspr r2,tb
|
||||
std r2,T_TIMER_END(r5)
|
||||
|
||||
cmpdi r3,0 # check rc
|
||||
beq pass
|
||||
b fail
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# dead zone
|
||||
.align 8
|
||||
fail:
|
||||
b .
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# happy ending
|
||||
.align 8
|
||||
pass:
|
||||
b .
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
# dec
|
||||
.align 11
|
||||
int_800:
|
||||
b .
|
||||
|
||||
# perf
|
||||
.align 5
|
||||
int_820:
|
||||
b .
|
||||
|
||||
.set CONFIG,0x0A00
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# config info
|
||||
.align 9
|
||||
|
||||
.long 0x8002B000 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.long 0x80000001 # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0)
|
||||
|
||||
# LE
|
||||
# .long 0x000000BF # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
# BE
|
||||
.long 0x0000003F # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
|
||||
.long 0x10000000 # @user eot sc
|
||||
|
||||
# per-thread configs (64B each)
|
||||
.align 7
|
||||
.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.long 0x00000000 #
|
||||
.long 0x00000000 #
|
||||
.long STACK0 # @stack
|
||||
.long 0x00000000 #
|
||||
.long TEST # @entry
|
||||
.long 0
|
||||
.long 0x10030000 # @print_start
|
||||
.long 0
|
||||
.long 0x10031FFF # @print_end
|
||||
.long 0
|
||||
.long 0x10030000 # print ptr
|
||||
.quad 0 # start tb
|
||||
.quad 0 # end tb
|
||||
|
||||
.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.long 0x00000000 #
|
||||
.long 0x00000000 #
|
||||
.long STACK1 # @stack
|
||||
.long 0x00000000 #
|
||||
.long TEST # @entry
|
||||
.long 0
|
||||
.long 0x10032000 # @print_start
|
||||
.long 0
|
||||
.long 0x10033FFF # @print_end
|
||||
.long 0
|
||||
.long 0x10032000 # print ptr
|
||||
.quad 0 # start tb
|
||||
.quad 0 # end tb
|
||||
|
||||
.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.long 0x00000000 # flags
|
||||
.long 0x00000000 #
|
||||
.long STACK2 # @stack
|
||||
.long 0x00000000 #
|
||||
.long TEST # @entry
|
||||
.long 0
|
||||
.long 0x10034000 # @print_start
|
||||
.long 0
|
||||
.long 0x10035FFF # @print_end
|
||||
.long 0
|
||||
.long 0x10034000 # print ptr
|
||||
.quad 0 # start tb
|
||||
.quad 0 # end tb
|
||||
|
||||
.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.long 0x00000000 # flags
|
||||
.long 0x00000000 #
|
||||
.long STACK3 # @stack
|
||||
.long 0x00000000 #
|
||||
.long TEST # @entry
|
||||
.long 0
|
||||
.long 0x10036000 # @print_start
|
||||
.long 0
|
||||
.long 0x10037FFF # @print_end
|
||||
.long 0
|
||||
.long 0x10036000 # print ptr
|
||||
.quad 0 # start tb
|
||||
.quad 0 # end tb
|
||||
|
||||
|
||||
.set S_MSR,0x00
|
||||
.set S_FLAGS,0x04
|
||||
.set S_ERATW2,0x08
|
||||
.set S_EOT_SC,0x0C
|
||||
|
||||
.set T_CONFIG,0x80
|
||||
.set T_MSR,0x00
|
||||
.set T_FLAGS,0x04
|
||||
.set T_STACK,0x08
|
||||
.set T_ENTRY,0x10
|
||||
.set T_TIMER_START,0x30
|
||||
.set T_TIMER_END,0x38
|
||||
.set T_PRINTSTART, 0x18
|
||||
.set T_PRINTEND, 0x20
|
||||
.set T_PRINTF, 0x28
|
||||
.set FLAG_EOT_SC,0x10
|
||||
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# other stuff
|
||||
.align 10
|
||||
|
||||
# clear buffer and reset pointer to start
|
||||
.align 6
|
||||
printf_reset:
|
||||
|
||||
mfspr r5,tir # who am i?
|
||||
sldi r5,r5,6 # 64B offset
|
||||
addi r5,r5,CONFIG+T_CONFIG
|
||||
|
||||
addi r6,r5,T_PRINTSTART
|
||||
ld r7,0(r6) # buffer start
|
||||
addi r6,r5,T_PRINTEND
|
||||
ld r8,0(r6) # buffer end
|
||||
sub r8,r8,r7
|
||||
addi r8,r8,1 # num bytes
|
||||
|
||||
mtctr r8
|
||||
li r6,0
|
||||
mr r8,r7
|
||||
printf_reset_clr:
|
||||
stb r6,0(r8)
|
||||
addi r8,r8,1
|
||||
bdnz printf_reset_clr
|
||||
|
||||
addi r8,r5,T_PRINTF
|
||||
std r7,0(r8) # reset ptr
|
||||
|
||||
blr
|
||||
|
||||
|
||||
# hvsc
|
||||
.align 8
|
||||
# go to exec_complete_sup in sup mode
|
||||
int_300_handler:
|
||||
|
||||
lwz r0,CONFIG+S_MSR(r0)
|
||||
mtmsr r0
|
||||
isync
|
||||
b exec_complete_sup
|
||||
|
||||
# sc
|
||||
.align 8
|
||||
# r3 is id, remaining are function-specific
|
||||
# not preserving r0, r3-r9 right now
|
||||
#
|
||||
# 0001 whoami
|
||||
# 0010 tick
|
||||
# 0100 putchar r4=c
|
||||
# 0106 printf_mode *NI*
|
||||
# 0107 printf_rst
|
||||
#
|
||||
int_120_handler:
|
||||
|
||||
mflr r0
|
||||
|
||||
cmpdi r3,0x0001
|
||||
beq sc_whoami
|
||||
cmpdi r3,0x0010
|
||||
beq sc_tick
|
||||
cmpdi r3,0x100
|
||||
beq sc_putchar
|
||||
cmpdi r3,0x107
|
||||
beq sc_printf_rst
|
||||
|
||||
li r3,-1
|
||||
mtlr r0
|
||||
rfi
|
||||
|
||||
# thread id
|
||||
.align 6
|
||||
sc_whoami:
|
||||
mfspr r3,tir
|
||||
rfi
|
||||
|
||||
# tb
|
||||
.align 6
|
||||
sc_tick:
|
||||
mfspr r3,tb
|
||||
rfi
|
||||
|
||||
# wrap buffer; could add flag to stop when full, or reset
|
||||
.align 6
|
||||
sc_putchar:
|
||||
|
||||
mfspr r5,tir # who am i?
|
||||
sldi r5,r5,6 # 64B offset
|
||||
addi r5,r5,CONFIG+T_CONFIG
|
||||
|
||||
addi r6,r5,T_PRINTF
|
||||
ld r7,0(r6) # buffer ptr
|
||||
stb r4,0(r7) # store char
|
||||
addi r7,r7,1
|
||||
|
||||
addi r8,r5,T_PRINTEND
|
||||
ld r8,0(r8) # buffer end
|
||||
cmpd r7,r8
|
||||
li r3,0 # rc=normal
|
||||
ble sc_putchar_ok
|
||||
addi r8,r5,T_PRINTSTART
|
||||
ld r7,0(r8) # buffer start
|
||||
li r3,-1 # rc=full
|
||||
sc_putchar_ok:
|
||||
std r7,0(r6) # save ptr
|
||||
|
||||
rfi
|
||||
|
||||
# clear buffer and reset pointer to start
|
||||
.align 6
|
||||
sc_printf_rst:
|
||||
|
||||
mfctr r3
|
||||
|
||||
bl printf_reset
|
||||
|
||||
mtctr r3
|
||||
mtlr r0
|
||||
li r3,0
|
||||
|
||||
rfi
|
||||
|
||||
@ -0,0 +1,71 @@
|
||||
#!/usr/bin/bash
|
||||
|
||||
export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
|
||||
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"
|
||||
|
||||
# defines
|
||||
|
||||
## define vars to init rom with csr's it uses...
|
||||
|
||||
#
|
||||
#csr_base=`grep '#define CSR_BASE' generated/csr.h | cut -d ' ' -f 3 | cut -c 1-6`
|
||||
#uart_base=`grep 'CSR_UART_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#UART_ADDR="${csr_base}${uart_base}"
|
||||
#defsyms="-defsym $UART_ADDR"
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_1_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_1_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_1_ADDR"
|
||||
#fi
|
||||
#
|
||||
#uart_base=`grep 'CSR_UART_2_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$uart_base" != "" ]] ; then
|
||||
# UART_2_ADDR="${csr_base}${uart_base}"
|
||||
# defsyms="$defsyms -defsym $UART_2_ADDR"
|
||||
#fi
|
||||
#
|
||||
#leds_base=`grep 'CSR_LEDS_BASE' generated/csr.h | cut -d ' ' -f 5 | cut -c 3-6`
|
||||
#if [[ "$leds_base" != "" ]] ; then
|
||||
# LEDS_ADDR="${csr_base}${leds_base}"
|
||||
# defsyms="$defsyms -defsym $LEDS_ADDR"
|
||||
#fi
|
||||
#
|
||||
#echo "CSR Addresses"
|
||||
#echo "Console UART: ${UART_ADDR}"
|
||||
#echo " LEDS: ${LEDS_ADDR}"
|
||||
#echo " UART_1: ${UART_1_ADDR}"
|
||||
#echo " UART_2: ${UART_1_ADDR}"
|
||||
|
||||
# a2o nanokernel
|
||||
|
||||
echo -n "Compiling..."
|
||||
|
||||
echo -n "asm/boot.s "
|
||||
#powerpc-linux-gnu-as -defsym UART_ADDR=$UART_ADDR -defsym LEDS_ADDR=$LEDS_ADDR -defsym UNHANDLED=1 -mbig-endian -mpower9 -I./asm asm/cmod7-boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
powerpc-linux-gnu-as -mbig-endian -ma2 -I. boot.s -ahlnd -o crt0.o > crt0.lst
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
echo ""
|
||||
echo "Linking..."
|
||||
powerpc-linux-gnu-ld -nostdlib -nodefaultlibs -T linker-kernel.ld crt0.o -o rom
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
powerpc-linux-gnu-objdump -d rom > rom.d #wtf: why not getting labels in asm code?
|
||||
powerpc-linux-gnu-objdump -s rom > rom.s
|
||||
powerpc-linux-gnu-objcopy -O binary rom rom.bin
|
||||
|
||||
# make rom.bin.hex
|
||||
bin/bin2init rom.bin
|
||||
mv rom.bin.hex rom.init
|
||||
|
||||
echo "Built rom.d, rom.s, rom.init."
|
||||
|
||||
romsize=`grep rom regions.ld | cut -d " " -f 8 | cut -c 3-10`
|
||||
|
||||
echo "Hardware ROM Size $romsize"
|
||||
|
||||
@ -0,0 +1,26 @@
|
||||
#!/usr/bin/bash
|
||||
|
||||
export COMMONFLAGS="-ffreestanding -fomit-frame-pointer -Wall -fno-stack-protector"
|
||||
export CFLAGS="$COMMONFLAGS -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"
|
||||
|
||||
echo -n "Compiling..."
|
||||
|
||||
echo -n "test.c "
|
||||
powerpc-linux-gnu-gcc -c -I. $CFLAGS test.c
|
||||
|
||||
echo ""
|
||||
echo "Linking..."
|
||||
powerpc-linux-gnu-ld -nostdlib -nodefaultlibs -T linker.ld test.o -o test
|
||||
if [ $? -ne 0 ]; then
|
||||
exit
|
||||
fi
|
||||
|
||||
powerpc-linux-gnu-objdump -d test > test.d #wtf: why not getting labels in asm code?
|
||||
powerpc-linux-gnu-objdump -s test > test.s
|
||||
powerpc-linux-gnu-objcopy -O binary test test.bin
|
||||
|
||||
# make rom.bin.hex
|
||||
bin/bin2init test.bin
|
||||
mv test.bin.hex test.init
|
||||
|
||||
echo "Built test.d, test.s, test.init."
|
||||
@ -0,0 +1,944 @@
|
||||
1 # © IBM Corp. 2022
|
||||
2 # Licensed under and subject to the terms of the CC-BY 4.0
|
||||
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
4 # Additional rights, including the right to physically implement a softcore
|
||||
5 # that is compliant with the required sections of the Power ISA
|
||||
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
7 # This README will be updated with additional information when OpenPOWER's
|
||||
8 # license is available.
|
||||
9
|
||||
10 # start conversion to simple boot which jumps to bios
|
||||
11 # this version will work similarly to original fpga test version
|
||||
12 # the original version did not run from rom; eventually will assume rom and do r/w data copy/init
|
||||
13 # the rom and test are built into separate memory loads or a single one with addr/data format
|
||||
14
|
||||
15 # boot kernel
|
||||
16 # set up translations
|
||||
17 # set up timer facilities
|
||||
18 # set up threads
|
||||
19 # call user code
|
||||
20 # process user rc
|
||||
21
|
||||
22 # todo:
|
||||
23 # 1. skip_printf_init flag should be threaded
|
||||
24
|
||||
25 .include "defines.s"
|
||||
1 # © IBM Corp. 2020
|
||||
2 # Licensed under and subject to the terms of the CC-BY 4.0
|
||||
3 # license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
4 # Additional rights, including the right to physically implement a softcore
|
||||
5 # that is compliant with the required sections of the Power ISA
|
||||
6 # Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
7 # This README will be updated with additional information when OpenPOWER's
|
||||
8 # license is available.
|
||||
9
|
||||
10 #-----------------------------------------
|
||||
11 # Defines
|
||||
12 #-----------------------------------------
|
||||
13
|
||||
14 # Regs
|
||||
15
|
||||
16 .set r0, 0
|
||||
17 .set r1, 1
|
||||
18 .set r2, 2
|
||||
19 .set r3, 3
|
||||
20 .set r4, 4
|
||||
21 .set r5, 5
|
||||
22 .set r6, 6
|
||||
23 .set r7, 7
|
||||
24 .set r8, 8
|
||||
25 .set r9, 9
|
||||
26 .set r10,10
|
||||
27 .set r11,11
|
||||
28 .set r12,12
|
||||
29 .set r13,13
|
||||
30 .set r14,14
|
||||
31 .set r15,15
|
||||
32 .set r16,16
|
||||
33 .set r17,17
|
||||
34 .set r18,18
|
||||
35 .set r19,19
|
||||
36 .set r20,20
|
||||
37 .set r21,21
|
||||
38 .set r22,22
|
||||
39 .set r23,23
|
||||
40 .set r24,24
|
||||
41 .set r25,25
|
||||
42 .set r26,26
|
||||
43 .set r27,27
|
||||
44 .set r28,28
|
||||
45 .set r29,29
|
||||
46 .set r30,30
|
||||
47 .set r31,31
|
||||
48
|
||||
49 .set f0, 0
|
||||
50 .set f1, 1
|
||||
51 .set f2, 2
|
||||
52 .set f3, 3
|
||||
53 .set f4, 4
|
||||
54 .set f5, 5
|
||||
55 .set f6, 6
|
||||
56 .set f7, 7
|
||||
57 .set f8, 8
|
||||
58 .set f9, 9
|
||||
59 .set f10,10
|
||||
60 .set f11,11
|
||||
61 .set f12,12
|
||||
62 .set f13,13
|
||||
63 .set f14,14
|
||||
64 .set f15,15
|
||||
65 .set f16,16
|
||||
66 .set f17,17
|
||||
67 .set f18,18
|
||||
68 .set f19,19
|
||||
69 .set f20,20
|
||||
70 .set f21,21
|
||||
71 .set f22,22
|
||||
72 .set f23,23
|
||||
73 .set f24,24
|
||||
74 .set f25,25
|
||||
75 .set f26,26
|
||||
76 .set f27,27
|
||||
77 .set f28,28
|
||||
78 .set f29,29
|
||||
79 .set f30,30
|
||||
80 .set f31,31
|
||||
81
|
||||
82 .set cr0, 0
|
||||
83 .set cr1, 1
|
||||
84 .set cr2, 2
|
||||
85 .set cr3, 3
|
||||
86 .set cr4, 4
|
||||
87 .set cr5, 5
|
||||
88 .set cr6, 6
|
||||
89 .set cr7, 7
|
||||
90
|
||||
91 # SPR numbers
|
||||
92
|
||||
93 .set srr0, 26
|
||||
94 .set srr1, 27
|
||||
95 .set epcr, 307
|
||||
96 .set tar, 815
|
||||
97
|
||||
98 .set dbsr, 304
|
||||
99 .set dbcr0, 308
|
||||
100 .set dbcr1, 309
|
||||
101 .set dbcr2, 310
|
||||
102 .set dbcr3, 848
|
||||
103
|
||||
104 .set ivpr, 63
|
||||
105
|
||||
106 .set iucr0, 1011
|
||||
107 .set iucr1, 883
|
||||
108 .set iucr2, 884
|
||||
109
|
||||
110 .set iudbg0, 888
|
||||
111 .set iudbg1, 889
|
||||
112 .set iudbg2, 890
|
||||
113 .set iulfsr, 891
|
||||
114 .set iullcr, 892
|
||||
115
|
||||
116 .set mmucr0, 1020
|
||||
117 .set mmucr1, 1021
|
||||
118 .set mmucr2, 1022
|
||||
119 .set mmucr3, 1023
|
||||
120
|
||||
121 .set tb, 268
|
||||
122 .set tbl, 284
|
||||
123 .set tbh, 285
|
||||
124
|
||||
125 .set dec, 22
|
||||
126 .set udec, 550
|
||||
127 .set tsr, 336
|
||||
128 .set tcr, 340
|
||||
129
|
||||
130 .set xucr0, 1014
|
||||
131 .set xucr1, 851
|
||||
132 .set xucr2, 1016
|
||||
133 .set xucr3, 852
|
||||
134 .set xucr4, 853
|
||||
135
|
||||
136 .set tens, 438
|
||||
137 .set tenc, 439
|
||||
138 .set tensr, 437
|
||||
139
|
||||
140 .set pid, 48
|
||||
141 .set pir, 286
|
||||
142 .set pvr, 287
|
||||
143 .set tir, 446
|
||||
144
|
||||
26
|
||||
27 # constants from linker script, or defsym
|
||||
28 .ifndef STACKSIZE
|
||||
29 .set STACKSIZE,_stack_size
|
||||
30 .endif
|
||||
31
|
||||
32 .ifndef STACK0
|
||||
33 .set STACK0,_stack_0
|
||||
34 .endif
|
||||
35
|
||||
36 .ifndef STACK1
|
||||
37 .set STACK1,_stack_1
|
||||
38 .endif
|
||||
39
|
||||
40 .set STACK2, 0
|
||||
41 .set STACK3, 0
|
||||
42
|
||||
43 .ifndef TEST
|
||||
44 .set TEST,_test_start
|
||||
45 .endif
|
||||
46
|
||||
47 .section .text
|
||||
48
|
||||
49 .global _start
|
||||
50 _start:
|
||||
51
|
||||
52 int_000:
|
||||
53 0000 48000400 b boot_start
|
||||
54
|
||||
55 # critical input
|
||||
56 0004 4800001C .align 5
|
||||
56 60000000
|
||||
56 60000000
|
||||
56 60000000
|
||||
56 60000000
|
||||
57 int_020:
|
||||
58 0020 48000000 b .
|
||||
59
|
||||
60 # debug
|
||||
61 0024 4800001C .align 5
|
||||
61 60000000
|
||||
61 60000000
|
||||
61 60000000
|
||||
61 60000000
|
||||
62 int_040:
|
||||
63 0040 48000000 b .
|
||||
64
|
||||
65 # dsi
|
||||
66 0044 4800001C .align 5
|
||||
66 60000000
|
||||
66 60000000
|
||||
66 60000000
|
||||
66 60000000
|
||||
67 int_060:
|
||||
68 0060 48000000 b .
|
||||
69
|
||||
70 # isi
|
||||
71 0064 4800001C .align 5
|
||||
71 60000000
|
||||
71 60000000
|
||||
71 60000000
|
||||
71 60000000
|
||||
72 int_080:
|
||||
73 0080 48000000 b .
|
||||
74
|
||||
75 # external
|
||||
76 0084 4800001C .align 5
|
||||
76 60000000
|
||||
76 60000000
|
||||
76 60000000
|
||||
76 60000000
|
||||
77 int_0A0:
|
||||
78 00a0 48000000 b .
|
||||
79
|
||||
80 # alignment
|
||||
81 00a4 4800001C .align 5
|
||||
81 60000000
|
||||
81 60000000
|
||||
81 60000000
|
||||
81 60000000
|
||||
82 int_0C0:
|
||||
83 00c0 48000000 b .
|
||||
84
|
||||
85 # program
|
||||
86 00c4 4800001C .align 5
|
||||
86 60000000
|
||||
86 60000000
|
||||
86 60000000
|
||||
86 60000000
|
||||
87 int_0E0:
|
||||
88 00e0 48000000 b .
|
||||
89
|
||||
90 # fp unavailable
|
||||
91 00e4 4800001C .align 5
|
||||
91 60000000
|
||||
91 60000000
|
||||
91 60000000
|
||||
91 60000000
|
||||
92 int_100:
|
||||
93 0100 48000000 b .
|
||||
94
|
||||
95 # sc
|
||||
96 0104 4800001C .align 5
|
||||
96 60000000
|
||||
96 60000000
|
||||
96 60000000
|
||||
96 60000000
|
||||
97 int_120:
|
||||
98 0120 48000CE0 b int_120_handler
|
||||
99
|
||||
100 # apu unavailable
|
||||
101 0124 4800001C .align 5
|
||||
101 60000000
|
||||
101 60000000
|
||||
101 60000000
|
||||
101 60000000
|
||||
102 int_140:
|
||||
103 0140 48000000 b .
|
||||
104
|
||||
105 # decrementer
|
||||
106 0144 4800001C .align 5
|
||||
106 60000000
|
||||
106 60000000
|
||||
106 60000000
|
||||
106 60000000
|
||||
107 int_160:
|
||||
108 0160 48000000 b .
|
||||
109
|
||||
110 # fit
|
||||
111 0164 4800001C .align 5
|
||||
111 60000000
|
||||
111 60000000
|
||||
111 60000000
|
||||
111 60000000
|
||||
112 int_180:
|
||||
113 0180 48000000 b .
|
||||
114
|
||||
115 # watchdog
|
||||
116 0184 4800001C .align 5
|
||||
116 60000000
|
||||
116 60000000
|
||||
116 60000000
|
||||
116 60000000
|
||||
117 int_1A0:
|
||||
118 01a0 48000000 b .
|
||||
119
|
||||
120 # dtlb
|
||||
121 01a4 4800001C .align 5
|
||||
121 60000000
|
||||
121 60000000
|
||||
121 60000000
|
||||
121 60000000
|
||||
122 int_1C0:
|
||||
123 01c0 48000000 b .
|
||||
124
|
||||
125 # itlb
|
||||
126 01c4 4800001C .align 5
|
||||
126 60000000
|
||||
126 60000000
|
||||
126 60000000
|
||||
126 60000000
|
||||
127 int_1E0:
|
||||
128 01e0 48000000 b .
|
||||
129
|
||||
130 # vector unavailable
|
||||
131 01e4 4800001C .align 5
|
||||
131 60000000
|
||||
131 60000000
|
||||
131 60000000
|
||||
131 60000000
|
||||
132 int_200:
|
||||
133 0200 48000000 b .
|
||||
134
|
||||
135 #
|
||||
136 0204 4800001C .align 5
|
||||
136 60000000
|
||||
136 60000000
|
||||
136 60000000
|
||||
136 60000000
|
||||
137 int_220:
|
||||
138 0220 48000000 b .
|
||||
139
|
||||
140 #
|
||||
141 0224 4800001C .align 5
|
||||
141 60000000
|
||||
141 60000000
|
||||
141 60000000
|
||||
141 60000000
|
||||
142 int_240:
|
||||
143 0240 48000000 b .
|
||||
144
|
||||
145 #
|
||||
146 0244 4800001C .align 5
|
||||
146 60000000
|
||||
146 60000000
|
||||
146 60000000
|
||||
146 60000000
|
||||
147 int_260:
|
||||
148 0260 48000000 b .
|
||||
149
|
||||
150 # doorbell
|
||||
151 0264 4800001C .align 5
|
||||
151 60000000
|
||||
151 60000000
|
||||
151 60000000
|
||||
151 60000000
|
||||
152 int_280:
|
||||
153 0280 48000000 b .
|
||||
154
|
||||
155 # doorbell critical
|
||||
156 0284 4800001C .align 5
|
||||
156 60000000
|
||||
156 60000000
|
||||
156 60000000
|
||||
156 60000000
|
||||
157 int_2A0:
|
||||
158 02a0 48000000 b .
|
||||
159
|
||||
160 # doorbell guest
|
||||
161 02a4 4800001C .align 5
|
||||
161 60000000
|
||||
161 60000000
|
||||
161 60000000
|
||||
161 60000000
|
||||
162 int_2C0:
|
||||
163 02c0 48000000 b .
|
||||
164
|
||||
165 # doorbell guest critical
|
||||
166 02c4 4800001C .align 5
|
||||
166 60000000
|
||||
166 60000000
|
||||
166 60000000
|
||||
166 60000000
|
||||
167 int_2E0:
|
||||
168 02e0 48000000 b .
|
||||
169
|
||||
170 # hvsc
|
||||
171 02e4 4800001C .align 8
|
||||
171 60000000
|
||||
171 60000000
|
||||
171 60000000
|
||||
171 60000000
|
||||
172 int_300:
|
||||
173 0300 48000A00 b int_300_handler
|
||||
174
|
||||
175 # hvpriv
|
||||
176 0304 4800001C .align 5
|
||||
176 60000000
|
||||
176 60000000
|
||||
176 60000000
|
||||
176 60000000
|
||||
177 int_320:
|
||||
178 0320 48000000 b .
|
||||
179
|
||||
180 # lrat
|
||||
181 0324 4800001C .align 5
|
||||
181 60000000
|
||||
181 60000000
|
||||
181 60000000
|
||||
181 60000000
|
||||
182 int_340:
|
||||
183 0340 48000000 b .
|
||||
184
|
||||
185 # -------------------------------------------------------------------------------------------------
|
||||
186 # initial translation
|
||||
187 # both erats:
|
||||
188 # 00000000 1M: (boot)
|
||||
189 # 10000000 1M: (test)
|
||||
190
|
||||
191 0344 480000BC .align 8
|
||||
191 60000000
|
||||
191 60000000
|
||||
191 60000000
|
||||
191 60000000
|
||||
192 boot_start:
|
||||
193
|
||||
194 0400 7CBE6AA6 mfspr r5,tir # who am i?
|
||||
195 0404 2C250000 cmpdi r5,0x00 # skip unless T0
|
||||
196 0408 408200EC bne init_t123
|
||||
197
|
||||
198 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
199 # derat 31 @00000000
|
||||
200
|
||||
201 0410 3800001F li r0,0x001F # entry #31
|
||||
202 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
|
||||
203 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
204 041c 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
205
|
||||
206 0420 7C7CFBA6 mtspr mmucr0,r3
|
||||
207 0424 7C4011A6 eratwe r2,r0,2
|
||||
208 0428 7C8009A6 eratwe r4,r0,1
|
||||
209 042c 7D0001A6 eratwe r8,r0,0
|
||||
210 0430 4C00012C isync
|
||||
211
|
||||
212 0434 81400A08 lwz r10,CONFIG+S_ERATW2(r0) # load parms for erat settings
|
||||
213
|
||||
214 # derat 30 @100000000
|
||||
215
|
||||
216 0438 3800001E li r0,0x001E # entry #30
|
||||
217 043c 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
218 0440 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
219 0444 65081000 oris r8,r8,0x1000
|
||||
220
|
||||
221 0448 7D4011A6 eratwe r10,r0,2
|
||||
222 044c 7C8009A6 eratwe r4,r0,1
|
||||
223 0450 7D0001A6 eratwe r8,r0,0
|
||||
224 0454 4C00012C isync
|
||||
225
|
||||
226 0458 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
|
||||
227 # ierat 15 @00000000
|
||||
228
|
||||
229 045c 3800000F li r0,0x000F # entry #15
|
||||
230 0460 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/
|
||||
231 0464 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
232 0468 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
233
|
||||
234 046c 7C7CFBA6 mtspr mmucr0,r3
|
||||
235 0470 7C4011A6 eratwe r2,r0,2
|
||||
236 0474 7C8009A6 eratwe r4,r0,1
|
||||
237 0478 7D0001A6 eratwe r8,r0,0
|
||||
238 047c 4C00012C isync
|
||||
239
|
||||
240 # *** leave the init'd entry 14 for MT access to FFFFFFC0
|
||||
241 # ierat 13 @10000000
|
||||
242
|
||||
243 0480 3800000D li r0,0x000D # entry #13
|
||||
244 0484 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
|
||||
245 0488 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s
|
||||
246 048c 65081000 oris r8,r8,0x1000
|
||||
247
|
||||
248 0490 7D4011A6 eratwe r10,r0,2
|
||||
249 0494 7C8009A6 eratwe r4,r0,1
|
||||
250 0498 7D0001A6 eratwe r8,r0,0
|
||||
251 049c 4C00012C isync
|
||||
252
|
||||
253 # -------------------------------------------------------------------------------------------------
|
||||
254 # init
|
||||
255 #
|
||||
256
|
||||
257 # T0-only
|
||||
258 # set up any core facilities, then enable the others if config'd
|
||||
259 init_t0:
|
||||
260
|
||||
261 # switch to 64b
|
||||
262
|
||||
263 04a0 81400A00 lwz r10,CONFIG+S_MSR(r0)
|
||||
264 04a4 7D400124 mtmsr r10
|
||||
265 04a8 4C00012C isync
|
||||
266
|
||||
267 # other init
|
||||
268
|
||||
269 04ac 3C200300 lis r1,0x0300 # icm=gicm=1
|
||||
270 04b0 7C334BA6 mtspr epcr,r1
|
||||
271
|
||||
272 # set up timer facs
|
||||
273
|
||||
274 04b4 38200000 li r1,0 # clear
|
||||
275 04b8 7C3603A6 mtspr dec,r1
|
||||
276 04bc 7C3D43A6 mtspr tbh,r1
|
||||
277 04c0 7C3C43A6 mtspr tbl,r1
|
||||
278
|
||||
279 04c4 3C40FE00 lis r2,0xFE00 # mask: clear enw,wis,wrs,dis,fis,udis
|
||||
280 04c8 7C5053A6 mtspr tsr,r2
|
||||
281
|
||||
282 04cc 7C56FAA6 mfspr r2,xucr0
|
||||
283 04d0 70420200 andi. r2,r2,0x0200 # set tcs=0
|
||||
284 04d4 7C56FBA6 mtspr xucr0,r2
|
||||
285
|
||||
286 04d8 7C3053A6 mtspr tsr,r1 # clear tsr
|
||||
287 04dc 7C3453A6 mtspr tcr,r1 # disable all timers
|
||||
288
|
||||
289 # set thread configuration
|
||||
290
|
||||
291 04e0 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
|
||||
292 04e4 7021000F andi. r1,r1,0xF
|
||||
293 04e8 7C366BA6 mtspr tens,r1 # 60:63 = tid 3:0 enabled
|
||||
294 #not r1,r1
|
||||
295 #mtspr tenc,r1 # in case T0 is marked disabled
|
||||
296 04ec 4C00012C isync
|
||||
297
|
||||
298 04f0 48000014 b boot_complete
|
||||
299
|
||||
300 # except T0
|
||||
301 # just worry about myself
|
||||
302
|
||||
303 init_t123:
|
||||
304
|
||||
305 # switch to 64b
|
||||
306
|
||||
307 04f4 81400A00 lwz r10,CONFIG+S_MSR(r0)
|
||||
308 04f8 7D400124 mtmsr r10
|
||||
309 04fc 4C00012C isync
|
||||
310
|
||||
311 0500 48000004 b boot_complete
|
||||
312
|
||||
313 # -------------------------------------------------------------------------------------------------
|
||||
314 boot_complete:
|
||||
315
|
||||
316 # set up thread and hop to it
|
||||
317
|
||||
318 0504 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
|
||||
319 0508 74218000 andis. r1,r1,0x8000 # 1=skip initial printf init
|
||||
320 050c 40820008 bne boot_complete_1
|
||||
321 0510 480006F1 bl printf_reset # wipe buffer
|
||||
322
|
||||
323 boot_complete_1:
|
||||
324
|
||||
325 0514 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
|
||||
326 0518 3C407FFF lis r2,0x7FFF # clear printf flag
|
||||
327 051c 6042FFFF ori r2,r2,0xFFFF
|
||||
328 0520 7C211038 and r1,r1,r2
|
||||
329 0524 90200A04 stw r1,CONFIG+S_FLAGS(r0)
|
||||
330
|
||||
331 0528 7CBE6AA6 mfspr r5,tir # who am i?
|
||||
332 052c 78A53664 sldi r5,r5,6 # 64B offset
|
||||
333 0530 38A50A80 addi r5,r5,CONFIG+T_CONFIG
|
||||
334
|
||||
335 0534 81650000 lwz r11,T_MSR(r5)
|
||||
336 0538 E9850008 ld r12,T_STACK(r5)
|
||||
337 053c E9A50010 ld r13,T_ENTRY(r5)
|
||||
338
|
||||
339 0540 80200A04 lwz r1,CONFIG+S_FLAGS(r0)
|
||||
340 0544 70210010 andi. r1,r1,FLAG_EOT_SC
|
||||
341 0548 4182001C beq eot_blr
|
||||
342
|
||||
343 eot_sc:
|
||||
344
|
||||
345 054c 80400A0C lwz r2,CONFIG+S_EOT_SC(r0)
|
||||
346 0550 3C204400 lis r1,0x4400 # 'sc 1'
|
||||
347 0554 60210012 ori r1,r1,0022
|
||||
348 0558 F8220000 std r1,0x0(r2)
|
||||
349 055c 7C2803A6 mtlr r1 # prog will blr to sc
|
||||
350 0560 48000014 b process_start
|
||||
351
|
||||
352 eot_blr:
|
||||
353
|
||||
354 0564 48000005 bl 4
|
||||
355 0568 7C2802A6 mflr r1
|
||||
356 056c 38210030 addi r1,r1,0x30 # !!!!!!!!!!!!!!! <-- WARNING!
|
||||
357 0570 7C2803A6 mtlr r1 # prog will blr to exec_complete
|
||||
358
|
||||
359 process_start:
|
||||
360
|
||||
361 0574 7D7B03A6 mtspr srr1,r11 # msr
|
||||
362 0578 7DBA03A6 mtspr srr0,r13 # @entry
|
||||
363 057c 7D816378 mr r1,r12 # @stack
|
||||
364 0580 7C7E6AA6 mfspr r3,tir # tid - main(tid) if yall want it
|
||||
365
|
||||
366 0584 7C4C42A6 mfspr r2,tb
|
||||
367 0588 F8450030 std r2,T_TIMER_START(r5)
|
||||
368 058c 4C000064 rfi
|
||||
369 0590 60000000 nop # !!!!!!!!!!!!!!! pads for lr calc
|
||||
370 0594 60000000 nop
|
||||
371 0598 60000000 nop
|
||||
372
|
||||
373 # -------------------------------------------------------------------------------------------------
|
||||
374 exec_complete:
|
||||
375 # allow blr to here, or it will be entered by sc directly
|
||||
376
|
||||
377 # user blr'd here...
|
||||
378 059c 44000022 sc 1 # hvsc back to sup state
|
||||
379
|
||||
380 exec_complete_sup:
|
||||
381 05a0 7CBE6AA6 mfspr r5,tir # who am i?
|
||||
382 05a4 78A53664 sldi r5,r5,6 # 64B offset
|
||||
383 05a8 38A50A80 addi r5,r5,CONFIG+T_CONFIG
|
||||
384
|
||||
385 05ac 7C4C42A6 mfspr r2,tb
|
||||
386 05b0 F8450038 std r2,T_TIMER_END(r5)
|
||||
387
|
||||
388 05b4 2C230000 cmpdi r3,0 # check rc
|
||||
389 05b8 41820148 beq pass
|
||||
390 05bc 48000044 b fail
|
||||
391
|
||||
392 # -------------------------------------------------------------------------------------------------
|
||||
393 # dead zone
|
||||
394 05c0 48000040 .align 8
|
||||
394 60000000
|
||||
394 60000000
|
||||
394 60000000
|
||||
394 60000000
|
||||
395 fail:
|
||||
396 0600 48000000 b .
|
||||
397
|
||||
398 # -------------------------------------------------------------------------------------------------
|
||||
399 # happy ending
|
||||
400 0604 480000FC .align 8
|
||||
400 60000000
|
||||
400 60000000
|
||||
400 60000000
|
||||
400 60000000
|
||||
401 pass:
|
||||
402 0700 48000000 b .
|
||||
403
|
||||
404 # -------------------------------------------------------------------------------------------------
|
||||
405
|
||||
406 # dec
|
||||
407 0704 480000FC .align 11
|
||||
407 60000000
|
||||
407 60000000
|
||||
407 60000000
|
||||
407 60000000
|
||||
408 int_800:
|
||||
409 0800 48000000 b .
|
||||
410
|
||||
411 # perf
|
||||
412 0804 4800001C .align 5
|
||||
412 60000000
|
||||
412 60000000
|
||||
412 60000000
|
||||
412 60000000
|
||||
413 int_820:
|
||||
414 0820 48000000 b .
|
||||
415
|
||||
416 .set CONFIG,0x0A00
|
||||
417 # -------------------------------------------------------------------------------------------------
|
||||
418 # config info
|
||||
419 0824 480001DC .align 9
|
||||
419 60000000
|
||||
419 60000000
|
||||
419 60000000
|
||||
419 60000000
|
||||
420
|
||||
421 0a00 8002B000 .long 0x8002B000 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
422 0a04 80000001 .long 0x80000001 # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0)
|
||||
423
|
||||
424 # LE
|
||||
425 # .long 0x000000BF # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wi
|
||||
426 # BE
|
||||
427 0a08 0000003F .long 0x0000003F # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wi
|
||||
428 0a0c 10000000 .long 0x10000000 # @user eot sc
|
||||
429
|
||||
430 # per-thread configs (64B each)
|
||||
431 0a10 48000070 .align 7
|
||||
431 60000000
|
||||
431 60000000
|
||||
431 60000000
|
||||
431 60000000
|
||||
432 0a80 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
433 0a84 00000000 .long 0x00000000 #
|
||||
434 0a88 00000000 .long 0x00000000 #
|
||||
435 0a8c 00000000 .long STACK0 # @stack
|
||||
436 0a90 00000000 .long 0x00000000 #
|
||||
437 0a94 00000000 .long TEST # @entry
|
||||
438 0a98 00000000 .long 0
|
||||
439 0a9c 10030000 .long 0x10030000 # @print_start
|
||||
440 0aa0 00000000 .long 0
|
||||
441 0aa4 10031FFF .long 0x10031FFF # @print_end
|
||||
442 0aa8 00000000 .long 0
|
||||
443 0aac 10030000 .long 0x10030000 # print ptr
|
||||
444 0ab0 00000000 .quad 0 # start tb
|
||||
444 00000000
|
||||
445 0ab8 00000000 .quad 0 # end tb
|
||||
445 00000000
|
||||
446
|
||||
447 0ac0 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
448 0ac4 00000000 .long 0x00000000 #
|
||||
449 0ac8 00000000 .long 0x00000000 #
|
||||
450 0acc 00000000 .long STACK1 # @stack
|
||||
451 0ad0 00000000 .long 0x00000000 #
|
||||
452 0ad4 00000000 .long TEST # @entry
|
||||
453 0ad8 00000000 .long 0
|
||||
454 0adc 10032000 .long 0x10032000 # @print_start
|
||||
455 0ae0 00000000 .long 0
|
||||
456 0ae4 10033FFF .long 0x10033FFF # @print_end
|
||||
457 0ae8 00000000 .long 0
|
||||
458 0aec 10032000 .long 0x10032000 # print ptr
|
||||
459 0af0 00000000 .quad 0 # start tb
|
||||
459 00000000
|
||||
460 0af8 00000000 .quad 0 # end tb
|
||||
460 00000000
|
||||
461
|
||||
462 0b00 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
463 0b04 00000000 .long 0x00000000 # flags
|
||||
464 0b08 00000000 .long 0x00000000 #
|
||||
465 0b0c 00000000 .long STACK2 # @stack
|
||||
466 0b10 00000000 .long 0x00000000 #
|
||||
467 0b14 00000000 .long TEST # @entry
|
||||
468 0b18 00000000 .long 0
|
||||
469 0b1c 10034000 .long 0x10034000 # @print_start
|
||||
470 0b20 00000000 .long 0
|
||||
471 0b24 10035FFF .long 0x10035FFF # @print_end
|
||||
472 0b28 00000000 .long 0
|
||||
473 0b2c 10034000 .long 0x10034000 # print ptr
|
||||
474 0b30 00000000 .quad 0 # start tb
|
||||
474 00000000
|
||||
475 0b38 00000000 .quad 0 # end tb
|
||||
475 00000000
|
||||
476
|
||||
477 0b40 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
478 0b44 00000000 .long 0x00000000 # flags
|
||||
479 0b48 00000000 .long 0x00000000 #
|
||||
480 0b4c 00000000 .long STACK3 # @stack
|
||||
481 0b50 00000000 .long 0x00000000 #
|
||||
482 0b54 00000000 .long TEST # @entry
|
||||
483 0b58 00000000 .long 0
|
||||
484 0b5c 10036000 .long 0x10036000 # @print_start
|
||||
485 0b60 00000000 .long 0
|
||||
486 0b64 10037FFF .long 0x10037FFF # @print_end
|
||||
487 0b68 00000000 .long 0
|
||||
488 0b6c 10036000 .long 0x10036000 # print ptr
|
||||
489 0b70 00000000 .quad 0 # start tb
|
||||
489 00000000
|
||||
490 0b78 00000000 .quad 0 # end tb
|
||||
490 00000000
|
||||
491
|
||||
492
|
||||
493 .set S_MSR,0x00
|
||||
494 .set S_FLAGS,0x04
|
||||
495 .set S_ERATW2,0x08
|
||||
496 .set S_EOT_SC,0x0C
|
||||
497
|
||||
498 .set T_CONFIG,0x80
|
||||
499 .set T_MSR,0x00
|
||||
500 .set T_FLAGS,0x04
|
||||
501 .set T_STACK,0x08
|
||||
502 .set T_ENTRY,0x10
|
||||
503 .set T_TIMER_START,0x30
|
||||
504 .set T_TIMER_END,0x38
|
||||
505 .set T_PRINTSTART, 0x18
|
||||
506 .set T_PRINTEND, 0x20
|
||||
507 .set T_PRINTF, 0x28
|
||||
508 .set FLAG_EOT_SC,0x10
|
||||
509
|
||||
510
|
||||
511 # -------------------------------------------------------------------------------------------------
|
||||
512 # other stuff
|
||||
513 0b80 48000080 .align 10
|
||||
513 60000000
|
||||
513 60000000
|
||||
513 60000000
|
||||
513 60000000
|
||||
514
|
||||
515 # clear buffer and reset pointer to start
|
||||
516 .align 6
|
||||
517 printf_reset:
|
||||
518
|
||||
519 0c00 7CBE6AA6 mfspr r5,tir # who am i?
|
||||
520 0c04 78A53664 sldi r5,r5,6 # 64B offset
|
||||
521 0c08 38A50A80 addi r5,r5,CONFIG+T_CONFIG
|
||||
522
|
||||
523 0c0c 38C50018 addi r6,r5,T_PRINTSTART
|
||||
524 0c10 E8E60000 ld r7,0(r6) # buffer start
|
||||
525 0c14 38C50020 addi r6,r5,T_PRINTEND
|
||||
526 0c18 E9060000 ld r8,0(r6) # buffer end
|
||||
527 0c1c 7D074050 sub r8,r8,r7
|
||||
528 0c20 39080001 addi r8,r8,1 # num bytes
|
||||
529
|
||||
530 0c24 7D0903A6 mtctr r8
|
||||
531 0c28 38C00000 li r6,0
|
||||
532 0c2c 7CE83B78 mr r8,r7
|
||||
533 printf_reset_clr:
|
||||
534 0c30 98C80000 stb r6,0(r8)
|
||||
535 0c34 39080001 addi r8,r8,1
|
||||
536 0c38 4200FFF8 bdnz printf_reset_clr
|
||||
537
|
||||
538 0c3c 39050028 addi r8,r5,T_PRINTF
|
||||
539 0c40 F8E80000 std r7,0(r8) # reset ptr
|
||||
540
|
||||
541 0c44 4E800020 blr
|
||||
542
|
||||
543
|
||||
544 # hvsc
|
||||
545 0c48 480000B8 .align 8
|
||||
545 60000000
|
||||
545 60000000
|
||||
545 60000000
|
||||
545 60000000
|
||||
546 # go to exec_complete_sup in sup mode
|
||||
547 int_300_handler:
|
||||
548
|
||||
549 0d00 80000A00 lwz r0,CONFIG+S_MSR(r0)
|
||||
550 0d04 7C000124 mtmsr r0
|
||||
551 0d08 4C00012C isync
|
||||
552 0d0c 4BFFF894 b exec_complete_sup
|
||||
553
|
||||
554 # sc
|
||||
555 0d10 480000F0 .align 8
|
||||
555 60000000
|
||||
555 60000000
|
||||
555 60000000
|
||||
555 60000000
|
||||
556 # r3 is id, remaining are function-specific
|
||||
557 # not preserving r0, r3-r9 right now
|
||||
558 #
|
||||
559 # 0001 whoami
|
||||
560 # 0010 tick
|
||||
561 # 0100 putchar r4=c
|
||||
562 # 0106 printf_mode *NI*
|
||||
563 # 0107 printf_rst
|
||||
564 #
|
||||
565 int_120_handler:
|
||||
566
|
||||
567 0e00 7C0802A6 mflr r0
|
||||
568
|
||||
569 0e04 2C230001 cmpdi r3,0x0001
|
||||
570 0e08 41820038 beq sc_whoami
|
||||
571 0e0c 2C230010 cmpdi r3,0x0010
|
||||
572 0e10 41820070 beq sc_tick
|
||||
573 0e14 2C230100 cmpdi r3,0x100
|
||||
574 0e18 418200A8 beq sc_putchar
|
||||
575 0e1c 2C230107 cmpdi r3,0x107
|
||||
576 0e20 41820120 beq sc_printf_rst
|
||||
577
|
||||
578 0e24 3860FFFF li r3,-1
|
||||
579 0e28 7C0803A6 mtlr r0
|
||||
580 0e2c 4C000064 rfi
|
||||
581
|
||||
582 # thread id
|
||||
583 0e30 60000000 .align 6
|
||||
583 60000000
|
||||
583 60000000
|
||||
583 60000000
|
||||
584 sc_whoami:
|
||||
585 0e40 7C7E6AA6 mfspr r3,tir
|
||||
586 0e44 4C000064 rfi
|
||||
587
|
||||
588 # tb
|
||||
589 0e48 48000038 .align 6
|
||||
589 60000000
|
||||
589 60000000
|
||||
589 60000000
|
||||
589 60000000
|
||||
590 sc_tick:
|
||||
591 0e80 7C6C42A6 mfspr r3,tb
|
||||
592 0e84 4C000064 rfi
|
||||
593
|
||||
594 # wrap buffer; could add flag to stop when full, or reset
|
||||
595 0e88 48000038 .align 6
|
||||
595 60000000
|
||||
595 60000000
|
||||
595 60000000
|
||||
595 60000000
|
||||
596 sc_putchar:
|
||||
597
|
||||
598 0ec0 7CBE6AA6 mfspr r5,tir # who am i?
|
||||
599 0ec4 78A53664 sldi r5,r5,6 # 64B offset
|
||||
600 0ec8 38A50A80 addi r5,r5,CONFIG+T_CONFIG
|
||||
601
|
||||
602 0ecc 38C50028 addi r6,r5,T_PRINTF
|
||||
603 0ed0 E8E60000 ld r7,0(r6) # buffer ptr
|
||||
604 0ed4 98870000 stb r4,0(r7) # store char
|
||||
605 0ed8 38E70001 addi r7,r7,1
|
||||
606
|
||||
607 0edc 39050020 addi r8,r5,T_PRINTEND
|
||||
608 0ee0 E9080000 ld r8,0(r8) # buffer end
|
||||
609 0ee4 7C274000 cmpd r7,r8
|
||||
610 0ee8 38600000 li r3,0 # rc=normal
|
||||
611 0eec 40810010 ble sc_putchar_ok
|
||||
612 0ef0 39050018 addi r8,r5,T_PRINTSTART
|
||||
613 0ef4 E8E80000 ld r7,0(r8) # buffer start
|
||||
614 0ef8 3860FFFF li r3,-1 # rc=full
|
||||
615 sc_putchar_ok:
|
||||
616 0efc F8E60000 std r7,0(r6) # save ptr
|
||||
617
|
||||
618 0f00 4C000064 rfi
|
||||
619
|
||||
620 # clear buffer and reset pointer to start
|
||||
621 0f04 4800003C .align 6
|
||||
621 60000000
|
||||
621 60000000
|
||||
621 60000000
|
||||
621 60000000
|
||||
622 sc_printf_rst:
|
||||
623
|
||||
624 0f40 7C6902A6 mfctr r3
|
||||
625
|
||||
626 0f44 4BFFFCBD bl printf_reset
|
||||
627
|
||||
628 0f48 7C6903A6 mtctr r3
|
||||
629 0f4c 7C0803A6 mtlr r0
|
||||
630 0f50 38600000 li r3,0
|
||||
631
|
||||
632 0f54 4C000064 rfi
|
||||
633
|
||||
Binary file not shown.
@ -0,0 +1,144 @@
|
||||
# © IBM Corp. 2020
|
||||
# Licensed under and subject to the terms of the CC-BY 4.0
|
||||
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
# Additional rights, including the right to physically implement a softcore
|
||||
# that is compliant with the required sections of the Power ISA
|
||||
# Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
# This README will be updated with additional information when OpenPOWER's
|
||||
# license is available.
|
||||
|
||||
#-----------------------------------------
|
||||
# Defines
|
||||
#-----------------------------------------
|
||||
|
||||
# Regs
|
||||
|
||||
.set r0, 0
|
||||
.set r1, 1
|
||||
.set r2, 2
|
||||
.set r3, 3
|
||||
.set r4, 4
|
||||
.set r5, 5
|
||||
.set r6, 6
|
||||
.set r7, 7
|
||||
.set r8, 8
|
||||
.set r9, 9
|
||||
.set r10,10
|
||||
.set r11,11
|
||||
.set r12,12
|
||||
.set r13,13
|
||||
.set r14,14
|
||||
.set r15,15
|
||||
.set r16,16
|
||||
.set r17,17
|
||||
.set r18,18
|
||||
.set r19,19
|
||||
.set r20,20
|
||||
.set r21,21
|
||||
.set r22,22
|
||||
.set r23,23
|
||||
.set r24,24
|
||||
.set r25,25
|
||||
.set r26,26
|
||||
.set r27,27
|
||||
.set r28,28
|
||||
.set r29,29
|
||||
.set r30,30
|
||||
.set r31,31
|
||||
|
||||
.set f0, 0
|
||||
.set f1, 1
|
||||
.set f2, 2
|
||||
.set f3, 3
|
||||
.set f4, 4
|
||||
.set f5, 5
|
||||
.set f6, 6
|
||||
.set f7, 7
|
||||
.set f8, 8
|
||||
.set f9, 9
|
||||
.set f10,10
|
||||
.set f11,11
|
||||
.set f12,12
|
||||
.set f13,13
|
||||
.set f14,14
|
||||
.set f15,15
|
||||
.set f16,16
|
||||
.set f17,17
|
||||
.set f18,18
|
||||
.set f19,19
|
||||
.set f20,20
|
||||
.set f21,21
|
||||
.set f22,22
|
||||
.set f23,23
|
||||
.set f24,24
|
||||
.set f25,25
|
||||
.set f26,26
|
||||
.set f27,27
|
||||
.set f28,28
|
||||
.set f29,29
|
||||
.set f30,30
|
||||
.set f31,31
|
||||
|
||||
.set cr0, 0
|
||||
.set cr1, 1
|
||||
.set cr2, 2
|
||||
.set cr3, 3
|
||||
.set cr4, 4
|
||||
.set cr5, 5
|
||||
.set cr6, 6
|
||||
.set cr7, 7
|
||||
|
||||
# SPR numbers
|
||||
|
||||
.set srr0, 26
|
||||
.set srr1, 27
|
||||
.set epcr, 307
|
||||
.set tar, 815
|
||||
|
||||
.set dbsr, 304
|
||||
.set dbcr0, 308
|
||||
.set dbcr1, 309
|
||||
.set dbcr2, 310
|
||||
.set dbcr3, 848
|
||||
|
||||
.set ivpr, 63
|
||||
|
||||
.set iucr0, 1011
|
||||
.set iucr1, 883
|
||||
.set iucr2, 884
|
||||
|
||||
.set iudbg0, 888
|
||||
.set iudbg1, 889
|
||||
.set iudbg2, 890
|
||||
.set iulfsr, 891
|
||||
.set iullcr, 892
|
||||
|
||||
.set mmucr0, 1020
|
||||
.set mmucr1, 1021
|
||||
.set mmucr2, 1022
|
||||
.set mmucr3, 1023
|
||||
|
||||
.set tb, 268
|
||||
.set tbl, 284
|
||||
.set tbh, 285
|
||||
|
||||
.set dec, 22
|
||||
.set udec, 550
|
||||
.set tsr, 336
|
||||
.set tcr, 340
|
||||
|
||||
.set xucr0, 1014
|
||||
.set xucr1, 851
|
||||
.set xucr2, 1016
|
||||
.set xucr3, 852
|
||||
.set xucr4, 853
|
||||
|
||||
.set tens, 438
|
||||
.set tenc, 439
|
||||
.set tensr, 437
|
||||
|
||||
.set pid, 48
|
||||
.set pir, 286
|
||||
.set pvr, 287
|
||||
.set tir, 446
|
||||
|
||||
@ -0,0 +1,31 @@
|
||||
/* simple loader of kernel only */
|
||||
|
||||
/* define format
|
||||
INCLUDE output_format.ld */
|
||||
OUTPUT_FORMAT("elf64-powerpc")
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
/* define origin, len of rom, ram, csr */
|
||||
INCLUDE regions.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* kernel code */
|
||||
.kernel :
|
||||
{
|
||||
/*_fkernel = .; */
|
||||
*crt0*(.text)
|
||||
KEEP(*crt0*(.text))
|
||||
*(.gnu.linkonce.t.*)
|
||||
_ekernel = .;
|
||||
} > rom
|
||||
}
|
||||
|
||||
PROVIDE(_stack_size = 0x00010000);
|
||||
PROVIDE(_stack_0 = ORIGIN(ram) + LENGTH(ram) - 4);
|
||||
PROVIDE(_stack_1 = _stack_0 - _stack_size);
|
||||
|
||||
PROVIDE(_fdata_rom = LOADADDR(.data));
|
||||
PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
|
||||
PROVIDE(_test_start = ORIGIN(ram));
|
||||
@ -0,0 +1,86 @@
|
||||
/* hacked version of litex */
|
||||
|
||||
/* define format
|
||||
INCLUDE output_format.ld */
|
||||
OUTPUT_FORMAT("elf64-powerpc")
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
/* define origin, len of rom, ram, csr */
|
||||
INCLUDE regions.ld
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* kernel code */
|
||||
.kernel :
|
||||
{
|
||||
/*_fkernel = .; */
|
||||
*crt0*(.text)
|
||||
KEEP(*crt0*(.text))
|
||||
*(.gnu.linkonce.t.*)
|
||||
_ekernel = .;
|
||||
} > rom
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_frodata = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
*(.rodata1)
|
||||
*(.got2 .got2.*)
|
||||
*(.toc .toc.*)
|
||||
FILL(0);
|
||||
. = ALIGN(8);
|
||||
_erodata = .;
|
||||
} > rom
|
||||
|
||||
/* kernel data to be copied to ram by rom code...*/
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_fdata = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
FILL(0);
|
||||
. = ALIGN(8);
|
||||
_edata = .;
|
||||
} > ram AT > rom
|
||||
|
||||
/* test code */
|
||||
.test :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*test.o (.text .text* .gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} > ram
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_fbss = .;
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(8);
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
} > ram
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.eh_frame)
|
||||
*(.comment)
|
||||
*(.gnu.attributes)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
PROVIDE(_stack_size = 0x00010000);
|
||||
PROVIDE(_stack_0 = ORIGIN(ram) + LENGTH(ram) - 4);
|
||||
PROVIDE(_stack_1 = _stack_0 - _stack_size);
|
||||
|
||||
PROVIDE(_fdata_rom = LOADADDR(.data));
|
||||
PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data));
|
||||
PROVIDE(_test_start = LOADADDR(.test));
|
||||
@ -0,0 +1,13 @@
|
||||
# Updating build process - test1
|
||||
|
||||
* original test kernel with updates to use link symbols
|
||||
* still build kernel and test separately
|
||||
|
||||
```
|
||||
build-kernel
|
||||
build-test
|
||||
|
||||
# create mem files for coco sim
|
||||
cp rom.init test1/.
|
||||
cp test.init test1/.
|
||||
```
|
||||
@ -0,0 +1,5 @@
|
||||
MEMORY {
|
||||
rom : ORIGIN = 0x00000000, LENGTH = 0x00010000
|
||||
ram : ORIGIN = 0x10000000, LENGTH = 0x00100000
|
||||
csr : ORIGIN = 0xFFF00000, LENGTH = 0x00010000
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
@ -0,0 +1,969 @@
|
||||
|
||||
rom: file format elf64-powerpc
|
||||
|
||||
|
||||
Disassembly of section .kernel:
|
||||
|
||||
0000000000000000 <_start>:
|
||||
0: 48 00 04 00 b 400 <_start+0x400>
|
||||
4: 48 00 00 1c b 20 <_start+0x20>
|
||||
8: 60 00 00 00 nop
|
||||
c: 60 00 00 00 nop
|
||||
10: 60 00 00 00 nop
|
||||
14: 60 00 00 00 nop
|
||||
18: 60 00 00 00 nop
|
||||
1c: 60 00 00 00 nop
|
||||
20: 48 00 00 00 b 20 <_start+0x20>
|
||||
24: 48 00 00 1c b 40 <_start+0x40>
|
||||
28: 60 00 00 00 nop
|
||||
2c: 60 00 00 00 nop
|
||||
30: 60 00 00 00 nop
|
||||
34: 60 00 00 00 nop
|
||||
38: 60 00 00 00 nop
|
||||
3c: 60 00 00 00 nop
|
||||
40: 48 00 00 00 b 40 <_start+0x40>
|
||||
44: 48 00 00 1c b 60 <_start+0x60>
|
||||
48: 60 00 00 00 nop
|
||||
4c: 60 00 00 00 nop
|
||||
50: 60 00 00 00 nop
|
||||
54: 60 00 00 00 nop
|
||||
58: 60 00 00 00 nop
|
||||
5c: 60 00 00 00 nop
|
||||
60: 48 00 00 00 b 60 <_start+0x60>
|
||||
64: 48 00 00 1c b 80 <_start+0x80>
|
||||
68: 60 00 00 00 nop
|
||||
6c: 60 00 00 00 nop
|
||||
70: 60 00 00 00 nop
|
||||
74: 60 00 00 00 nop
|
||||
78: 60 00 00 00 nop
|
||||
7c: 60 00 00 00 nop
|
||||
80: 48 00 00 00 b 80 <_start+0x80>
|
||||
84: 48 00 00 1c b a0 <_start+0xa0>
|
||||
88: 60 00 00 00 nop
|
||||
8c: 60 00 00 00 nop
|
||||
90: 60 00 00 00 nop
|
||||
94: 60 00 00 00 nop
|
||||
98: 60 00 00 00 nop
|
||||
9c: 60 00 00 00 nop
|
||||
a0: 48 00 00 00 b a0 <_start+0xa0>
|
||||
a4: 48 00 00 1c b c0 <_start+0xc0>
|
||||
a8: 60 00 00 00 nop
|
||||
ac: 60 00 00 00 nop
|
||||
b0: 60 00 00 00 nop
|
||||
b4: 60 00 00 00 nop
|
||||
b8: 60 00 00 00 nop
|
||||
bc: 60 00 00 00 nop
|
||||
c0: 48 00 00 00 b c0 <_start+0xc0>
|
||||
c4: 48 00 00 1c b e0 <_start+0xe0>
|
||||
c8: 60 00 00 00 nop
|
||||
cc: 60 00 00 00 nop
|
||||
d0: 60 00 00 00 nop
|
||||
d4: 60 00 00 00 nop
|
||||
d8: 60 00 00 00 nop
|
||||
dc: 60 00 00 00 nop
|
||||
e0: 48 00 00 00 b e0 <_start+0xe0>
|
||||
e4: 48 00 00 1c b 100 <_start+0x100>
|
||||
e8: 60 00 00 00 nop
|
||||
ec: 60 00 00 00 nop
|
||||
f0: 60 00 00 00 nop
|
||||
f4: 60 00 00 00 nop
|
||||
f8: 60 00 00 00 nop
|
||||
fc: 60 00 00 00 nop
|
||||
100: 48 00 00 00 b 100 <_start+0x100>
|
||||
104: 48 00 00 1c b 120 <_start+0x120>
|
||||
108: 60 00 00 00 nop
|
||||
10c: 60 00 00 00 nop
|
||||
110: 60 00 00 00 nop
|
||||
114: 60 00 00 00 nop
|
||||
118: 60 00 00 00 nop
|
||||
11c: 60 00 00 00 nop
|
||||
120: 48 00 0c e0 b e00 <_start+0xe00>
|
||||
124: 48 00 00 1c b 140 <_start+0x140>
|
||||
128: 60 00 00 00 nop
|
||||
12c: 60 00 00 00 nop
|
||||
130: 60 00 00 00 nop
|
||||
134: 60 00 00 00 nop
|
||||
138: 60 00 00 00 nop
|
||||
13c: 60 00 00 00 nop
|
||||
140: 48 00 00 00 b 140 <_start+0x140>
|
||||
144: 48 00 00 1c b 160 <_start+0x160>
|
||||
148: 60 00 00 00 nop
|
||||
14c: 60 00 00 00 nop
|
||||
150: 60 00 00 00 nop
|
||||
154: 60 00 00 00 nop
|
||||
158: 60 00 00 00 nop
|
||||
15c: 60 00 00 00 nop
|
||||
160: 48 00 00 00 b 160 <_start+0x160>
|
||||
164: 48 00 00 1c b 180 <_start+0x180>
|
||||
168: 60 00 00 00 nop
|
||||
16c: 60 00 00 00 nop
|
||||
170: 60 00 00 00 nop
|
||||
174: 60 00 00 00 nop
|
||||
178: 60 00 00 00 nop
|
||||
17c: 60 00 00 00 nop
|
||||
180: 48 00 00 00 b 180 <_start+0x180>
|
||||
184: 48 00 00 1c b 1a0 <_start+0x1a0>
|
||||
188: 60 00 00 00 nop
|
||||
18c: 60 00 00 00 nop
|
||||
190: 60 00 00 00 nop
|
||||
194: 60 00 00 00 nop
|
||||
198: 60 00 00 00 nop
|
||||
19c: 60 00 00 00 nop
|
||||
1a0: 48 00 00 00 b 1a0 <_start+0x1a0>
|
||||
1a4: 48 00 00 1c b 1c0 <_start+0x1c0>
|
||||
1a8: 60 00 00 00 nop
|
||||
1ac: 60 00 00 00 nop
|
||||
1b0: 60 00 00 00 nop
|
||||
1b4: 60 00 00 00 nop
|
||||
1b8: 60 00 00 00 nop
|
||||
1bc: 60 00 00 00 nop
|
||||
1c0: 48 00 00 00 b 1c0 <_start+0x1c0>
|
||||
1c4: 48 00 00 1c b 1e0 <_start+0x1e0>
|
||||
1c8: 60 00 00 00 nop
|
||||
1cc: 60 00 00 00 nop
|
||||
1d0: 60 00 00 00 nop
|
||||
1d4: 60 00 00 00 nop
|
||||
1d8: 60 00 00 00 nop
|
||||
1dc: 60 00 00 00 nop
|
||||
1e0: 48 00 00 00 b 1e0 <_start+0x1e0>
|
||||
1e4: 48 00 00 1c b 200 <_start+0x200>
|
||||
1e8: 60 00 00 00 nop
|
||||
1ec: 60 00 00 00 nop
|
||||
1f0: 60 00 00 00 nop
|
||||
1f4: 60 00 00 00 nop
|
||||
1f8: 60 00 00 00 nop
|
||||
1fc: 60 00 00 00 nop
|
||||
200: 48 00 00 00 b 200 <_start+0x200>
|
||||
204: 48 00 00 1c b 220 <_start+0x220>
|
||||
208: 60 00 00 00 nop
|
||||
20c: 60 00 00 00 nop
|
||||
210: 60 00 00 00 nop
|
||||
214: 60 00 00 00 nop
|
||||
218: 60 00 00 00 nop
|
||||
21c: 60 00 00 00 nop
|
||||
220: 48 00 00 00 b 220 <_start+0x220>
|
||||
224: 48 00 00 1c b 240 <_start+0x240>
|
||||
228: 60 00 00 00 nop
|
||||
22c: 60 00 00 00 nop
|
||||
230: 60 00 00 00 nop
|
||||
234: 60 00 00 00 nop
|
||||
238: 60 00 00 00 nop
|
||||
23c: 60 00 00 00 nop
|
||||
240: 48 00 00 00 b 240 <_start+0x240>
|
||||
244: 48 00 00 1c b 260 <_start+0x260>
|
||||
248: 60 00 00 00 nop
|
||||
24c: 60 00 00 00 nop
|
||||
250: 60 00 00 00 nop
|
||||
254: 60 00 00 00 nop
|
||||
258: 60 00 00 00 nop
|
||||
25c: 60 00 00 00 nop
|
||||
260: 48 00 00 00 b 260 <_start+0x260>
|
||||
264: 48 00 00 1c b 280 <_start+0x280>
|
||||
268: 60 00 00 00 nop
|
||||
26c: 60 00 00 00 nop
|
||||
270: 60 00 00 00 nop
|
||||
274: 60 00 00 00 nop
|
||||
278: 60 00 00 00 nop
|
||||
27c: 60 00 00 00 nop
|
||||
280: 48 00 00 00 b 280 <_start+0x280>
|
||||
284: 48 00 00 1c b 2a0 <_start+0x2a0>
|
||||
288: 60 00 00 00 nop
|
||||
28c: 60 00 00 00 nop
|
||||
290: 60 00 00 00 nop
|
||||
294: 60 00 00 00 nop
|
||||
298: 60 00 00 00 nop
|
||||
29c: 60 00 00 00 nop
|
||||
2a0: 48 00 00 00 b 2a0 <_start+0x2a0>
|
||||
2a4: 48 00 00 1c b 2c0 <_start+0x2c0>
|
||||
2a8: 60 00 00 00 nop
|
||||
2ac: 60 00 00 00 nop
|
||||
2b0: 60 00 00 00 nop
|
||||
2b4: 60 00 00 00 nop
|
||||
2b8: 60 00 00 00 nop
|
||||
2bc: 60 00 00 00 nop
|
||||
2c0: 48 00 00 00 b 2c0 <_start+0x2c0>
|
||||
2c4: 48 00 00 1c b 2e0 <_start+0x2e0>
|
||||
2c8: 60 00 00 00 nop
|
||||
2cc: 60 00 00 00 nop
|
||||
2d0: 60 00 00 00 nop
|
||||
2d4: 60 00 00 00 nop
|
||||
2d8: 60 00 00 00 nop
|
||||
2dc: 60 00 00 00 nop
|
||||
2e0: 48 00 00 00 b 2e0 <_start+0x2e0>
|
||||
2e4: 48 00 00 1c b 300 <_start+0x300>
|
||||
2e8: 60 00 00 00 nop
|
||||
2ec: 60 00 00 00 nop
|
||||
2f0: 60 00 00 00 nop
|
||||
2f4: 60 00 00 00 nop
|
||||
2f8: 60 00 00 00 nop
|
||||
2fc: 60 00 00 00 nop
|
||||
300: 48 00 0a 00 b d00 <_start+0xd00>
|
||||
304: 48 00 00 1c b 320 <_start+0x320>
|
||||
308: 60 00 00 00 nop
|
||||
30c: 60 00 00 00 nop
|
||||
310: 60 00 00 00 nop
|
||||
314: 60 00 00 00 nop
|
||||
318: 60 00 00 00 nop
|
||||
31c: 60 00 00 00 nop
|
||||
320: 48 00 00 00 b 320 <_start+0x320>
|
||||
324: 48 00 00 1c b 340 <_start+0x340>
|
||||
328: 60 00 00 00 nop
|
||||
32c: 60 00 00 00 nop
|
||||
330: 60 00 00 00 nop
|
||||
334: 60 00 00 00 nop
|
||||
338: 60 00 00 00 nop
|
||||
33c: 60 00 00 00 nop
|
||||
340: 48 00 00 00 b 340 <_start+0x340>
|
||||
344: 48 00 00 bc b 400 <_start+0x400>
|
||||
348: 60 00 00 00 nop
|
||||
34c: 60 00 00 00 nop
|
||||
350: 60 00 00 00 nop
|
||||
354: 60 00 00 00 nop
|
||||
358: 60 00 00 00 nop
|
||||
35c: 60 00 00 00 nop
|
||||
360: 60 00 00 00 nop
|
||||
364: 60 00 00 00 nop
|
||||
368: 60 00 00 00 nop
|
||||
36c: 60 00 00 00 nop
|
||||
370: 60 00 00 00 nop
|
||||
374: 60 00 00 00 nop
|
||||
378: 60 00 00 00 nop
|
||||
37c: 60 00 00 00 nop
|
||||
380: 60 00 00 00 nop
|
||||
384: 60 00 00 00 nop
|
||||
388: 60 00 00 00 nop
|
||||
38c: 60 00 00 00 nop
|
||||
390: 60 00 00 00 nop
|
||||
394: 60 00 00 00 nop
|
||||
398: 60 00 00 00 nop
|
||||
39c: 60 00 00 00 nop
|
||||
3a0: 60 00 00 00 nop
|
||||
3a4: 60 00 00 00 nop
|
||||
3a8: 60 00 00 00 nop
|
||||
3ac: 60 00 00 00 nop
|
||||
3b0: 60 00 00 00 nop
|
||||
3b4: 60 00 00 00 nop
|
||||
3b8: 60 00 00 00 nop
|
||||
3bc: 60 00 00 00 nop
|
||||
3c0: 60 00 00 00 nop
|
||||
3c4: 60 00 00 00 nop
|
||||
3c8: 60 00 00 00 nop
|
||||
3cc: 60 00 00 00 nop
|
||||
3d0: 60 00 00 00 nop
|
||||
3d4: 60 00 00 00 nop
|
||||
3d8: 60 00 00 00 nop
|
||||
3dc: 60 00 00 00 nop
|
||||
3e0: 60 00 00 00 nop
|
||||
3e4: 60 00 00 00 nop
|
||||
3e8: 60 00 00 00 nop
|
||||
3ec: 60 00 00 00 nop
|
||||
3f0: 60 00 00 00 nop
|
||||
3f4: 60 00 00 00 nop
|
||||
3f8: 60 00 00 00 nop
|
||||
3fc: 60 00 00 00 nop
|
||||
400: 7c be 6a a6 mfspr r5,446
|
||||
404: 2c 25 00 00 cmpdi r5,0
|
||||
408: 40 82 00 ec bne 4f4 <_start+0x4f4>
|
||||
40c: 3c 60 8c 00 lis r3,-29696
|
||||
410: 38 00 00 1f li r0,31
|
||||
414: 38 40 00 15 li r2,21
|
||||
418: 38 80 00 00 li r4,0
|
||||
41c: 39 00 02 5f li r8,607
|
||||
420: 7c 7c fb a6 mtspr 1020,r3
|
||||
424: 7c 40 11 a6 eratwe r2,r0,2
|
||||
428: 7c 80 09 a6 eratwe r4,r0,1
|
||||
42c: 7d 00 01 a6 mtfprwa f8,r0
|
||||
430: 4c 00 01 2c isync
|
||||
434: 81 40 0a 08 lwz r10,2568(0)
|
||||
438: 38 00 00 1e li r0,30
|
||||
43c: 3c 80 10 00 lis r4,4096
|
||||
440: 39 00 02 5f li r8,607
|
||||
444: 65 08 10 00 oris r8,r8,4096
|
||||
448: 7d 40 11 a6 eratwe r10,r0,2
|
||||
44c: 7c 80 09 a6 eratwe r4,r0,1
|
||||
450: 7d 00 01 a6 mtfprwa f8,r0
|
||||
454: 4c 00 01 2c isync
|
||||
458: 3c 60 88 00 lis r3,-30720
|
||||
45c: 38 00 00 0f li r0,15
|
||||
460: 38 40 00 3f li r2,63
|
||||
464: 38 80 00 00 li r4,0
|
||||
468: 39 00 02 5f li r8,607
|
||||
46c: 7c 7c fb a6 mtspr 1020,r3
|
||||
470: 7c 40 11 a6 eratwe r2,r0,2
|
||||
474: 7c 80 09 a6 eratwe r4,r0,1
|
||||
478: 7d 00 01 a6 mtfprwa f8,r0
|
||||
47c: 4c 00 01 2c isync
|
||||
480: 38 00 00 0d li r0,13
|
||||
484: 3c 80 10 00 lis r4,4096
|
||||
488: 39 00 02 5f li r8,607
|
||||
48c: 65 08 10 00 oris r8,r8,4096
|
||||
490: 7d 40 11 a6 eratwe r10,r0,2
|
||||
494: 7c 80 09 a6 eratwe r4,r0,1
|
||||
498: 7d 00 01 a6 mtfprwa f8,r0
|
||||
49c: 4c 00 01 2c isync
|
||||
4a0: 81 40 0a 00 lwz r10,2560(0)
|
||||
4a4: 7d 40 01 24 mtmsr r10
|
||||
4a8: 4c 00 01 2c isync
|
||||
4ac: 3c 20 03 00 lis r1,768
|
||||
4b0: 7c 33 4b a6 mtspr 307,r1
|
||||
4b4: 38 20 00 00 li r1,0
|
||||
4b8: 7c 36 03 a6 mtdec r1
|
||||
4bc: 7c 3d 43 a6 mttbu r1
|
||||
4c0: 7c 3c 43 a6 mttbl r1
|
||||
4c4: 3c 40 fe 00 lis r2,-512
|
||||
4c8: 7c 50 53 a6 mtspr 336,r2
|
||||
4cc: 7c 56 fa a6 mfspr r2,1014
|
||||
4d0: 70 42 02 00 andi. r2,r2,512
|
||||
4d4: 7c 56 fb a6 mtspr 1014,r2
|
||||
4d8: 7c 30 53 a6 mtspr 336,r1
|
||||
4dc: 7c 34 53 a6 mtspr 340,r1
|
||||
4e0: 80 20 0a 04 lwz r1,2564(0)
|
||||
4e4: 70 21 00 0f andi. r1,r1,15
|
||||
4e8: 7c 36 6b a6 mtspr 438,r1
|
||||
4ec: 4c 00 01 2c isync
|
||||
4f0: 48 00 00 14 b 504 <_start+0x504>
|
||||
4f4: 81 40 0a 00 lwz r10,2560(0)
|
||||
4f8: 7d 40 01 24 mtmsr r10
|
||||
4fc: 4c 00 01 2c isync
|
||||
500: 48 00 00 04 b 504 <_start+0x504>
|
||||
504: 80 20 0a 04 lwz r1,2564(0)
|
||||
508: 74 21 80 00 andis. r1,r1,32768
|
||||
50c: 40 82 00 08 bne 514 <_start+0x514>
|
||||
510: 48 00 06 f1 bl c00 <_start+0xc00>
|
||||
514: 80 20 0a 04 lwz r1,2564(0)
|
||||
518: 3c 40 7f ff lis r2,32767
|
||||
51c: 60 42 ff ff ori r2,r2,65535
|
||||
520: 7c 21 10 38 and r1,r1,r2
|
||||
524: 90 20 0a 04 stw r1,2564(0)
|
||||
528: 7c be 6a a6 mfspr r5,446
|
||||
52c: 78 a5 36 64 rldicr r5,r5,6,57
|
||||
530: 38 a5 0a 80 addi r5,r5,2688
|
||||
534: 81 65 00 00 lwz r11,0(r5)
|
||||
538: e9 85 00 08 ld r12,8(r5)
|
||||
53c: e9 a5 00 10 ld r13,16(r5)
|
||||
540: 80 20 0a 04 lwz r1,2564(0)
|
||||
544: 70 21 00 10 andi. r1,r1,16
|
||||
548: 41 82 00 1c beq 564 <_start+0x564>
|
||||
54c: 80 40 0a 0c lwz r2,2572(0)
|
||||
550: 3c 20 44 00 lis r1,17408
|
||||
554: 60 21 00 12 ori r1,r1,18
|
||||
558: f8 22 00 00 std r1,0(r2)
|
||||
55c: 7c 28 03 a6 mtlr r1
|
||||
560: 48 00 00 14 b 574 <_start+0x574>
|
||||
564: 48 00 00 05 bl 568 <_start+0x568>
|
||||
568: 7c 28 02 a6 mflr r1
|
||||
56c: 38 21 00 30 addi r1,r1,48
|
||||
570: 7c 28 03 a6 mtlr r1
|
||||
574: 7d 7b 03 a6 mtsrr1 r11
|
||||
578: 7d ba 03 a6 mtsrr0 r13
|
||||
57c: 7d 81 63 78 mr r1,r12
|
||||
580: 7c 7e 6a a6 mfspr r3,446
|
||||
584: 7c 4c 42 a6 mftb r2
|
||||
588: f8 45 00 30 std r2,48(r5)
|
||||
58c: 4c 00 00 64 rfi
|
||||
590: 60 00 00 00 nop
|
||||
594: 60 00 00 00 nop
|
||||
598: 60 00 00 00 nop
|
||||
59c: 44 00 00 22 sc 1
|
||||
5a0: 7c be 6a a6 mfspr r5,446
|
||||
5a4: 78 a5 36 64 rldicr r5,r5,6,57
|
||||
5a8: 38 a5 0a 80 addi r5,r5,2688
|
||||
5ac: 7c 4c 42 a6 mftb r2
|
||||
5b0: f8 45 00 38 std r2,56(r5)
|
||||
5b4: 2c 23 00 00 cmpdi r3,0
|
||||
5b8: 41 82 01 48 beq 700 <_start+0x700>
|
||||
5bc: 48 00 00 44 b 600 <_start+0x600>
|
||||
5c0: 48 00 00 40 b 600 <_start+0x600>
|
||||
5c4: 60 00 00 00 nop
|
||||
5c8: 60 00 00 00 nop
|
||||
5cc: 60 00 00 00 nop
|
||||
5d0: 60 00 00 00 nop
|
||||
5d4: 60 00 00 00 nop
|
||||
5d8: 60 00 00 00 nop
|
||||
5dc: 60 00 00 00 nop
|
||||
5e0: 60 00 00 00 nop
|
||||
5e4: 60 00 00 00 nop
|
||||
5e8: 60 00 00 00 nop
|
||||
5ec: 60 00 00 00 nop
|
||||
5f0: 60 00 00 00 nop
|
||||
5f4: 60 00 00 00 nop
|
||||
5f8: 60 00 00 00 nop
|
||||
5fc: 60 00 00 00 nop
|
||||
600: 48 00 00 00 b 600 <_start+0x600>
|
||||
604: 48 00 00 fc b 700 <_start+0x700>
|
||||
608: 60 00 00 00 nop
|
||||
60c: 60 00 00 00 nop
|
||||
610: 60 00 00 00 nop
|
||||
614: 60 00 00 00 nop
|
||||
618: 60 00 00 00 nop
|
||||
61c: 60 00 00 00 nop
|
||||
620: 60 00 00 00 nop
|
||||
624: 60 00 00 00 nop
|
||||
628: 60 00 00 00 nop
|
||||
62c: 60 00 00 00 nop
|
||||
630: 60 00 00 00 nop
|
||||
634: 60 00 00 00 nop
|
||||
638: 60 00 00 00 nop
|
||||
63c: 60 00 00 00 nop
|
||||
640: 60 00 00 00 nop
|
||||
644: 60 00 00 00 nop
|
||||
648: 60 00 00 00 nop
|
||||
64c: 60 00 00 00 nop
|
||||
650: 60 00 00 00 nop
|
||||
654: 60 00 00 00 nop
|
||||
658: 60 00 00 00 nop
|
||||
65c: 60 00 00 00 nop
|
||||
660: 60 00 00 00 nop
|
||||
664: 60 00 00 00 nop
|
||||
668: 60 00 00 00 nop
|
||||
66c: 60 00 00 00 nop
|
||||
670: 60 00 00 00 nop
|
||||
674: 60 00 00 00 nop
|
||||
678: 60 00 00 00 nop
|
||||
67c: 60 00 00 00 nop
|
||||
680: 60 00 00 00 nop
|
||||
684: 60 00 00 00 nop
|
||||
688: 60 00 00 00 nop
|
||||
68c: 60 00 00 00 nop
|
||||
690: 60 00 00 00 nop
|
||||
694: 60 00 00 00 nop
|
||||
698: 60 00 00 00 nop
|
||||
69c: 60 00 00 00 nop
|
||||
6a0: 60 00 00 00 nop
|
||||
6a4: 60 00 00 00 nop
|
||||
6a8: 60 00 00 00 nop
|
||||
6ac: 60 00 00 00 nop
|
||||
6b0: 60 00 00 00 nop
|
||||
6b4: 60 00 00 00 nop
|
||||
6b8: 60 00 00 00 nop
|
||||
6bc: 60 00 00 00 nop
|
||||
6c0: 60 00 00 00 nop
|
||||
6c4: 60 00 00 00 nop
|
||||
6c8: 60 00 00 00 nop
|
||||
6cc: 60 00 00 00 nop
|
||||
6d0: 60 00 00 00 nop
|
||||
6d4: 60 00 00 00 nop
|
||||
6d8: 60 00 00 00 nop
|
||||
6dc: 60 00 00 00 nop
|
||||
6e0: 60 00 00 00 nop
|
||||
6e4: 60 00 00 00 nop
|
||||
6e8: 60 00 00 00 nop
|
||||
6ec: 60 00 00 00 nop
|
||||
6f0: 60 00 00 00 nop
|
||||
6f4: 60 00 00 00 nop
|
||||
6f8: 60 00 00 00 nop
|
||||
6fc: 60 00 00 00 nop
|
||||
700: 48 00 00 00 b 700 <_start+0x700>
|
||||
704: 48 00 00 fc b 800 <_start+0x800>
|
||||
708: 60 00 00 00 nop
|
||||
70c: 60 00 00 00 nop
|
||||
710: 60 00 00 00 nop
|
||||
714: 60 00 00 00 nop
|
||||
718: 60 00 00 00 nop
|
||||
71c: 60 00 00 00 nop
|
||||
720: 60 00 00 00 nop
|
||||
724: 60 00 00 00 nop
|
||||
728: 60 00 00 00 nop
|
||||
72c: 60 00 00 00 nop
|
||||
730: 60 00 00 00 nop
|
||||
734: 60 00 00 00 nop
|
||||
738: 60 00 00 00 nop
|
||||
73c: 60 00 00 00 nop
|
||||
740: 60 00 00 00 nop
|
||||
744: 60 00 00 00 nop
|
||||
748: 60 00 00 00 nop
|
||||
74c: 60 00 00 00 nop
|
||||
750: 60 00 00 00 nop
|
||||
754: 60 00 00 00 nop
|
||||
758: 60 00 00 00 nop
|
||||
75c: 60 00 00 00 nop
|
||||
760: 60 00 00 00 nop
|
||||
764: 60 00 00 00 nop
|
||||
768: 60 00 00 00 nop
|
||||
76c: 60 00 00 00 nop
|
||||
770: 60 00 00 00 nop
|
||||
774: 60 00 00 00 nop
|
||||
778: 60 00 00 00 nop
|
||||
77c: 60 00 00 00 nop
|
||||
780: 60 00 00 00 nop
|
||||
784: 60 00 00 00 nop
|
||||
788: 60 00 00 00 nop
|
||||
78c: 60 00 00 00 nop
|
||||
790: 60 00 00 00 nop
|
||||
794: 60 00 00 00 nop
|
||||
798: 60 00 00 00 nop
|
||||
79c: 60 00 00 00 nop
|
||||
7a0: 60 00 00 00 nop
|
||||
7a4: 60 00 00 00 nop
|
||||
7a8: 60 00 00 00 nop
|
||||
7ac: 60 00 00 00 nop
|
||||
7b0: 60 00 00 00 nop
|
||||
7b4: 60 00 00 00 nop
|
||||
7b8: 60 00 00 00 nop
|
||||
7bc: 60 00 00 00 nop
|
||||
7c0: 60 00 00 00 nop
|
||||
7c4: 60 00 00 00 nop
|
||||
7c8: 60 00 00 00 nop
|
||||
7cc: 60 00 00 00 nop
|
||||
7d0: 60 00 00 00 nop
|
||||
7d4: 60 00 00 00 nop
|
||||
7d8: 60 00 00 00 nop
|
||||
7dc: 60 00 00 00 nop
|
||||
7e0: 60 00 00 00 nop
|
||||
7e4: 60 00 00 00 nop
|
||||
7e8: 60 00 00 00 nop
|
||||
7ec: 60 00 00 00 nop
|
||||
7f0: 60 00 00 00 nop
|
||||
7f4: 60 00 00 00 nop
|
||||
7f8: 60 00 00 00 nop
|
||||
7fc: 60 00 00 00 nop
|
||||
800: 48 00 00 00 b 800 <_start+0x800>
|
||||
804: 48 00 00 1c b 820 <_start+0x820>
|
||||
808: 60 00 00 00 nop
|
||||
80c: 60 00 00 00 nop
|
||||
810: 60 00 00 00 nop
|
||||
814: 60 00 00 00 nop
|
||||
818: 60 00 00 00 nop
|
||||
81c: 60 00 00 00 nop
|
||||
820: 48 00 00 00 b 820 <_start+0x820>
|
||||
824: 48 00 01 dc b a00 <_start+0xa00>
|
||||
828: 60 00 00 00 nop
|
||||
82c: 60 00 00 00 nop
|
||||
830: 60 00 00 00 nop
|
||||
834: 60 00 00 00 nop
|
||||
838: 60 00 00 00 nop
|
||||
83c: 60 00 00 00 nop
|
||||
840: 60 00 00 00 nop
|
||||
844: 60 00 00 00 nop
|
||||
848: 60 00 00 00 nop
|
||||
84c: 60 00 00 00 nop
|
||||
850: 60 00 00 00 nop
|
||||
854: 60 00 00 00 nop
|
||||
858: 60 00 00 00 nop
|
||||
85c: 60 00 00 00 nop
|
||||
860: 60 00 00 00 nop
|
||||
864: 60 00 00 00 nop
|
||||
868: 60 00 00 00 nop
|
||||
86c: 60 00 00 00 nop
|
||||
870: 60 00 00 00 nop
|
||||
874: 60 00 00 00 nop
|
||||
878: 60 00 00 00 nop
|
||||
87c: 60 00 00 00 nop
|
||||
880: 60 00 00 00 nop
|
||||
884: 60 00 00 00 nop
|
||||
888: 60 00 00 00 nop
|
||||
88c: 60 00 00 00 nop
|
||||
890: 60 00 00 00 nop
|
||||
894: 60 00 00 00 nop
|
||||
898: 60 00 00 00 nop
|
||||
89c: 60 00 00 00 nop
|
||||
8a0: 60 00 00 00 nop
|
||||
8a4: 60 00 00 00 nop
|
||||
8a8: 60 00 00 00 nop
|
||||
8ac: 60 00 00 00 nop
|
||||
8b0: 60 00 00 00 nop
|
||||
8b4: 60 00 00 00 nop
|
||||
8b8: 60 00 00 00 nop
|
||||
8bc: 60 00 00 00 nop
|
||||
8c0: 60 00 00 00 nop
|
||||
8c4: 60 00 00 00 nop
|
||||
8c8: 60 00 00 00 nop
|
||||
8cc: 60 00 00 00 nop
|
||||
8d0: 60 00 00 00 nop
|
||||
8d4: 60 00 00 00 nop
|
||||
8d8: 60 00 00 00 nop
|
||||
8dc: 60 00 00 00 nop
|
||||
8e0: 60 00 00 00 nop
|
||||
8e4: 60 00 00 00 nop
|
||||
8e8: 60 00 00 00 nop
|
||||
8ec: 60 00 00 00 nop
|
||||
8f0: 60 00 00 00 nop
|
||||
8f4: 60 00 00 00 nop
|
||||
8f8: 60 00 00 00 nop
|
||||
8fc: 60 00 00 00 nop
|
||||
900: 60 00 00 00 nop
|
||||
904: 60 00 00 00 nop
|
||||
908: 60 00 00 00 nop
|
||||
90c: 60 00 00 00 nop
|
||||
910: 60 00 00 00 nop
|
||||
914: 60 00 00 00 nop
|
||||
918: 60 00 00 00 nop
|
||||
91c: 60 00 00 00 nop
|
||||
920: 60 00 00 00 nop
|
||||
924: 60 00 00 00 nop
|
||||
928: 60 00 00 00 nop
|
||||
92c: 60 00 00 00 nop
|
||||
930: 60 00 00 00 nop
|
||||
934: 60 00 00 00 nop
|
||||
938: 60 00 00 00 nop
|
||||
93c: 60 00 00 00 nop
|
||||
940: 60 00 00 00 nop
|
||||
944: 60 00 00 00 nop
|
||||
948: 60 00 00 00 nop
|
||||
94c: 60 00 00 00 nop
|
||||
950: 60 00 00 00 nop
|
||||
954: 60 00 00 00 nop
|
||||
958: 60 00 00 00 nop
|
||||
95c: 60 00 00 00 nop
|
||||
960: 60 00 00 00 nop
|
||||
964: 60 00 00 00 nop
|
||||
968: 60 00 00 00 nop
|
||||
96c: 60 00 00 00 nop
|
||||
970: 60 00 00 00 nop
|
||||
974: 60 00 00 00 nop
|
||||
978: 60 00 00 00 nop
|
||||
97c: 60 00 00 00 nop
|
||||
980: 60 00 00 00 nop
|
||||
984: 60 00 00 00 nop
|
||||
988: 60 00 00 00 nop
|
||||
98c: 60 00 00 00 nop
|
||||
990: 60 00 00 00 nop
|
||||
994: 60 00 00 00 nop
|
||||
998: 60 00 00 00 nop
|
||||
99c: 60 00 00 00 nop
|
||||
9a0: 60 00 00 00 nop
|
||||
9a4: 60 00 00 00 nop
|
||||
9a8: 60 00 00 00 nop
|
||||
9ac: 60 00 00 00 nop
|
||||
9b0: 60 00 00 00 nop
|
||||
9b4: 60 00 00 00 nop
|
||||
9b8: 60 00 00 00 nop
|
||||
9bc: 60 00 00 00 nop
|
||||
9c0: 60 00 00 00 nop
|
||||
9c4: 60 00 00 00 nop
|
||||
9c8: 60 00 00 00 nop
|
||||
9cc: 60 00 00 00 nop
|
||||
9d0: 60 00 00 00 nop
|
||||
9d4: 60 00 00 00 nop
|
||||
9d8: 60 00 00 00 nop
|
||||
9dc: 60 00 00 00 nop
|
||||
9e0: 60 00 00 00 nop
|
||||
9e4: 60 00 00 00 nop
|
||||
9e8: 60 00 00 00 nop
|
||||
9ec: 60 00 00 00 nop
|
||||
9f0: 60 00 00 00 nop
|
||||
9f4: 60 00 00 00 nop
|
||||
9f8: 60 00 00 00 nop
|
||||
9fc: 60 00 00 00 nop
|
||||
a00: 80 02 b0 00 lwz r0,-20480(r2)
|
||||
a04: 80 00 00 01 lwz r0,1(0)
|
||||
a08: 00 00 00 3f .long 0x3f
|
||||
a0c: 10 00 00 00 vaddubm v0,v0,v0
|
||||
a10: 48 00 00 70 b a80 <_start+0xa80>
|
||||
a14: 60 00 00 00 nop
|
||||
a18: 60 00 00 00 nop
|
||||
a1c: 60 00 00 00 nop
|
||||
a20: 60 00 00 00 nop
|
||||
a24: 60 00 00 00 nop
|
||||
a28: 60 00 00 00 nop
|
||||
a2c: 60 00 00 00 nop
|
||||
a30: 60 00 00 00 nop
|
||||
a34: 60 00 00 00 nop
|
||||
a38: 60 00 00 00 nop
|
||||
a3c: 60 00 00 00 nop
|
||||
a40: 60 00 00 00 nop
|
||||
a44: 60 00 00 00 nop
|
||||
a48: 60 00 00 00 nop
|
||||
a4c: 60 00 00 00 nop
|
||||
a50: 60 00 00 00 nop
|
||||
a54: 60 00 00 00 nop
|
||||
a58: 60 00 00 00 nop
|
||||
a5c: 60 00 00 00 nop
|
||||
a60: 60 00 00 00 nop
|
||||
a64: 60 00 00 00 nop
|
||||
a68: 60 00 00 00 nop
|
||||
a6c: 60 00 00 00 nop
|
||||
a70: 60 00 00 00 nop
|
||||
a74: 60 00 00 00 nop
|
||||
a78: 60 00 00 00 nop
|
||||
a7c: 60 00 00 00 nop
|
||||
a80: 80 02 f0 00 lwz r0,-4096(r2)
|
||||
...
|
||||
a8c: 10 0f ff fc vaddeuqm v0,v15,v31,v31
|
||||
a90: 00 00 00 00 .long 0x0
|
||||
a94: 10 00 00 00 vaddubm v0,v0,v0
|
||||
a98: 00 00 00 00 .long 0x0
|
||||
a9c: 10 03 00 00 vaddubm v0,v3,v0
|
||||
aa0: 00 00 00 00 .long 0x0
|
||||
aa4: 10 03 1f ff vsubecuq v0,v3,v3,v31
|
||||
aa8: 00 00 00 00 .long 0x0
|
||||
aac: 10 03 00 00 vaddubm v0,v3,v0
|
||||
...
|
||||
ac0: 80 02 f0 00 lwz r0,-4096(r2)
|
||||
...
|
||||
acc: 10 0e ff fc vaddeuqm v0,v14,v31,v31
|
||||
ad0: 00 00 00 00 .long 0x0
|
||||
ad4: 10 00 00 00 vaddubm v0,v0,v0
|
||||
ad8: 00 00 00 00 .long 0x0
|
||||
adc: 10 03 20 00 vaddubm v0,v3,v4
|
||||
ae0: 00 00 00 00 .long 0x0
|
||||
ae4: 10 03 3f ff vsubecuq v0,v3,v7,v31
|
||||
ae8: 00 00 00 00 .long 0x0
|
||||
aec: 10 03 20 00 vaddubm v0,v3,v4
|
||||
...
|
||||
b00: 80 02 f0 00 lwz r0,-4096(r2)
|
||||
...
|
||||
b14: 10 00 00 00 vaddubm v0,v0,v0
|
||||
b18: 00 00 00 00 .long 0x0
|
||||
b1c: 10 03 40 00 vaddubm v0,v3,v8
|
||||
b20: 00 00 00 00 .long 0x0
|
||||
b24: 10 03 5f ff vsubecuq v0,v3,v11,v31
|
||||
b28: 00 00 00 00 .long 0x0
|
||||
b2c: 10 03 40 00 vaddubm v0,v3,v8
|
||||
...
|
||||
b40: 80 02 f0 00 lwz r0,-4096(r2)
|
||||
...
|
||||
b54: 10 00 00 00 vaddubm v0,v0,v0
|
||||
b58: 00 00 00 00 .long 0x0
|
||||
b5c: 10 03 60 00 vaddubm v0,v3,v12
|
||||
b60: 00 00 00 00 .long 0x0
|
||||
b64: 10 03 7f ff vsubecuq v0,v3,v15,v31
|
||||
b68: 00 00 00 00 .long 0x0
|
||||
b6c: 10 03 60 00 vaddubm v0,v3,v12
|
||||
...
|
||||
b80: 48 00 00 80 b c00 <_start+0xc00>
|
||||
b84: 60 00 00 00 nop
|
||||
b88: 60 00 00 00 nop
|
||||
b8c: 60 00 00 00 nop
|
||||
b90: 60 00 00 00 nop
|
||||
b94: 60 00 00 00 nop
|
||||
b98: 60 00 00 00 nop
|
||||
b9c: 60 00 00 00 nop
|
||||
ba0: 60 00 00 00 nop
|
||||
ba4: 60 00 00 00 nop
|
||||
ba8: 60 00 00 00 nop
|
||||
bac: 60 00 00 00 nop
|
||||
bb0: 60 00 00 00 nop
|
||||
bb4: 60 00 00 00 nop
|
||||
bb8: 60 00 00 00 nop
|
||||
bbc: 60 00 00 00 nop
|
||||
bc0: 60 00 00 00 nop
|
||||
bc4: 60 00 00 00 nop
|
||||
bc8: 60 00 00 00 nop
|
||||
bcc: 60 00 00 00 nop
|
||||
bd0: 60 00 00 00 nop
|
||||
bd4: 60 00 00 00 nop
|
||||
bd8: 60 00 00 00 nop
|
||||
bdc: 60 00 00 00 nop
|
||||
be0: 60 00 00 00 nop
|
||||
be4: 60 00 00 00 nop
|
||||
be8: 60 00 00 00 nop
|
||||
bec: 60 00 00 00 nop
|
||||
bf0: 60 00 00 00 nop
|
||||
bf4: 60 00 00 00 nop
|
||||
bf8: 60 00 00 00 nop
|
||||
bfc: 60 00 00 00 nop
|
||||
c00: 7c be 6a a6 mfspr r5,446
|
||||
c04: 78 a5 36 64 rldicr r5,r5,6,57
|
||||
c08: 38 a5 0a 80 addi r5,r5,2688
|
||||
c0c: 38 c5 00 18 addi r6,r5,24
|
||||
c10: e8 e6 00 00 ld r7,0(r6)
|
||||
c14: 38 c5 00 20 addi r6,r5,32
|
||||
c18: e9 06 00 00 ld r8,0(r6)
|
||||
c1c: 7d 07 40 50 subf r8,r7,r8
|
||||
c20: 39 08 00 01 addi r8,r8,1
|
||||
c24: 7d 09 03 a6 mtctr r8
|
||||
c28: 38 c0 00 00 li r6,0
|
||||
c2c: 7c e8 3b 78 mr r8,r7
|
||||
c30: 98 c8 00 00 stb r6,0(r8)
|
||||
c34: 39 08 00 01 addi r8,r8,1
|
||||
c38: 42 00 ff f8 bdnz c30 <_start+0xc30>
|
||||
c3c: 39 05 00 28 addi r8,r5,40
|
||||
c40: f8 e8 00 00 std r7,0(r8)
|
||||
c44: 4e 80 00 20 blr
|
||||
c48: 48 00 00 b8 b d00 <_start+0xd00>
|
||||
c4c: 60 00 00 00 nop
|
||||
c50: 60 00 00 00 nop
|
||||
c54: 60 00 00 00 nop
|
||||
c58: 60 00 00 00 nop
|
||||
c5c: 60 00 00 00 nop
|
||||
c60: 60 00 00 00 nop
|
||||
c64: 60 00 00 00 nop
|
||||
c68: 60 00 00 00 nop
|
||||
c6c: 60 00 00 00 nop
|
||||
c70: 60 00 00 00 nop
|
||||
c74: 60 00 00 00 nop
|
||||
c78: 60 00 00 00 nop
|
||||
c7c: 60 00 00 00 nop
|
||||
c80: 60 00 00 00 nop
|
||||
c84: 60 00 00 00 nop
|
||||
c88: 60 00 00 00 nop
|
||||
c8c: 60 00 00 00 nop
|
||||
c90: 60 00 00 00 nop
|
||||
c94: 60 00 00 00 nop
|
||||
c98: 60 00 00 00 nop
|
||||
c9c: 60 00 00 00 nop
|
||||
ca0: 60 00 00 00 nop
|
||||
ca4: 60 00 00 00 nop
|
||||
ca8: 60 00 00 00 nop
|
||||
cac: 60 00 00 00 nop
|
||||
cb0: 60 00 00 00 nop
|
||||
cb4: 60 00 00 00 nop
|
||||
cb8: 60 00 00 00 nop
|
||||
cbc: 60 00 00 00 nop
|
||||
cc0: 60 00 00 00 nop
|
||||
cc4: 60 00 00 00 nop
|
||||
cc8: 60 00 00 00 nop
|
||||
ccc: 60 00 00 00 nop
|
||||
cd0: 60 00 00 00 nop
|
||||
cd4: 60 00 00 00 nop
|
||||
cd8: 60 00 00 00 nop
|
||||
cdc: 60 00 00 00 nop
|
||||
ce0: 60 00 00 00 nop
|
||||
ce4: 60 00 00 00 nop
|
||||
ce8: 60 00 00 00 nop
|
||||
cec: 60 00 00 00 nop
|
||||
cf0: 60 00 00 00 nop
|
||||
cf4: 60 00 00 00 nop
|
||||
cf8: 60 00 00 00 nop
|
||||
cfc: 60 00 00 00 nop
|
||||
d00: 80 00 0a 00 lwz r0,2560(0)
|
||||
d04: 7c 00 01 24 mtmsr r0
|
||||
d08: 4c 00 01 2c isync
|
||||
d0c: 4b ff f8 94 b 5a0 <_start+0x5a0>
|
||||
d10: 48 00 00 f0 b e00 <_start+0xe00>
|
||||
d14: 60 00 00 00 nop
|
||||
d18: 60 00 00 00 nop
|
||||
d1c: 60 00 00 00 nop
|
||||
d20: 60 00 00 00 nop
|
||||
d24: 60 00 00 00 nop
|
||||
d28: 60 00 00 00 nop
|
||||
d2c: 60 00 00 00 nop
|
||||
d30: 60 00 00 00 nop
|
||||
d34: 60 00 00 00 nop
|
||||
d38: 60 00 00 00 nop
|
||||
d3c: 60 00 00 00 nop
|
||||
d40: 60 00 00 00 nop
|
||||
d44: 60 00 00 00 nop
|
||||
d48: 60 00 00 00 nop
|
||||
d4c: 60 00 00 00 nop
|
||||
d50: 60 00 00 00 nop
|
||||
d54: 60 00 00 00 nop
|
||||
d58: 60 00 00 00 nop
|
||||
d5c: 60 00 00 00 nop
|
||||
d60: 60 00 00 00 nop
|
||||
d64: 60 00 00 00 nop
|
||||
d68: 60 00 00 00 nop
|
||||
d6c: 60 00 00 00 nop
|
||||
d70: 60 00 00 00 nop
|
||||
d74: 60 00 00 00 nop
|
||||
d78: 60 00 00 00 nop
|
||||
d7c: 60 00 00 00 nop
|
||||
d80: 60 00 00 00 nop
|
||||
d84: 60 00 00 00 nop
|
||||
d88: 60 00 00 00 nop
|
||||
d8c: 60 00 00 00 nop
|
||||
d90: 60 00 00 00 nop
|
||||
d94: 60 00 00 00 nop
|
||||
d98: 60 00 00 00 nop
|
||||
d9c: 60 00 00 00 nop
|
||||
da0: 60 00 00 00 nop
|
||||
da4: 60 00 00 00 nop
|
||||
da8: 60 00 00 00 nop
|
||||
dac: 60 00 00 00 nop
|
||||
db0: 60 00 00 00 nop
|
||||
db4: 60 00 00 00 nop
|
||||
db8: 60 00 00 00 nop
|
||||
dbc: 60 00 00 00 nop
|
||||
dc0: 60 00 00 00 nop
|
||||
dc4: 60 00 00 00 nop
|
||||
dc8: 60 00 00 00 nop
|
||||
dcc: 60 00 00 00 nop
|
||||
dd0: 60 00 00 00 nop
|
||||
dd4: 60 00 00 00 nop
|
||||
dd8: 60 00 00 00 nop
|
||||
ddc: 60 00 00 00 nop
|
||||
de0: 60 00 00 00 nop
|
||||
de4: 60 00 00 00 nop
|
||||
de8: 60 00 00 00 nop
|
||||
dec: 60 00 00 00 nop
|
||||
df0: 60 00 00 00 nop
|
||||
df4: 60 00 00 00 nop
|
||||
df8: 60 00 00 00 nop
|
||||
dfc: 60 00 00 00 nop
|
||||
e00: 7c 08 02 a6 mflr r0
|
||||
e04: 2c 23 00 01 cmpdi r3,1
|
||||
e08: 41 82 00 38 beq e40 <_start+0xe40>
|
||||
e0c: 2c 23 00 10 cmpdi r3,16
|
||||
e10: 41 82 00 70 beq e80 <_start+0xe80>
|
||||
e14: 2c 23 01 00 cmpdi r3,256
|
||||
e18: 41 82 00 a8 beq ec0 <_start+0xec0>
|
||||
e1c: 2c 23 01 07 cmpdi r3,263
|
||||
e20: 41 82 01 20 beq f40 <_start+0xf40>
|
||||
e24: 38 60 ff ff li r3,-1
|
||||
e28: 7c 08 03 a6 mtlr r0
|
||||
e2c: 4c 00 00 64 rfi
|
||||
e30: 60 00 00 00 nop
|
||||
e34: 60 00 00 00 nop
|
||||
e38: 60 00 00 00 nop
|
||||
e3c: 60 00 00 00 nop
|
||||
e40: 7c 7e 6a a6 mfspr r3,446
|
||||
e44: 4c 00 00 64 rfi
|
||||
e48: 48 00 00 38 b e80 <_start+0xe80>
|
||||
e4c: 60 00 00 00 nop
|
||||
e50: 60 00 00 00 nop
|
||||
e54: 60 00 00 00 nop
|
||||
e58: 60 00 00 00 nop
|
||||
e5c: 60 00 00 00 nop
|
||||
e60: 60 00 00 00 nop
|
||||
e64: 60 00 00 00 nop
|
||||
e68: 60 00 00 00 nop
|
||||
e6c: 60 00 00 00 nop
|
||||
e70: 60 00 00 00 nop
|
||||
e74: 60 00 00 00 nop
|
||||
e78: 60 00 00 00 nop
|
||||
e7c: 60 00 00 00 nop
|
||||
e80: 7c 6c 42 a6 mftb r3
|
||||
e84: 4c 00 00 64 rfi
|
||||
e88: 48 00 00 38 b ec0 <_start+0xec0>
|
||||
e8c: 60 00 00 00 nop
|
||||
e90: 60 00 00 00 nop
|
||||
e94: 60 00 00 00 nop
|
||||
e98: 60 00 00 00 nop
|
||||
e9c: 60 00 00 00 nop
|
||||
ea0: 60 00 00 00 nop
|
||||
ea4: 60 00 00 00 nop
|
||||
ea8: 60 00 00 00 nop
|
||||
eac: 60 00 00 00 nop
|
||||
eb0: 60 00 00 00 nop
|
||||
eb4: 60 00 00 00 nop
|
||||
eb8: 60 00 00 00 nop
|
||||
ebc: 60 00 00 00 nop
|
||||
ec0: 7c be 6a a6 mfspr r5,446
|
||||
ec4: 78 a5 36 64 rldicr r5,r5,6,57
|
||||
ec8: 38 a5 0a 80 addi r5,r5,2688
|
||||
ecc: 38 c5 00 28 addi r6,r5,40
|
||||
ed0: e8 e6 00 00 ld r7,0(r6)
|
||||
ed4: 98 87 00 00 stb r4,0(r7)
|
||||
ed8: 38 e7 00 01 addi r7,r7,1
|
||||
edc: 39 05 00 20 addi r8,r5,32
|
||||
ee0: e9 08 00 00 ld r8,0(r8)
|
||||
ee4: 7c 27 40 00 cmpd r7,r8
|
||||
ee8: 38 60 00 00 li r3,0
|
||||
eec: 40 81 00 10 ble efc <_start+0xefc>
|
||||
ef0: 39 05 00 18 addi r8,r5,24
|
||||
ef4: e8 e8 00 00 ld r7,0(r8)
|
||||
ef8: 38 60 ff ff li r3,-1
|
||||
efc: f8 e6 00 00 std r7,0(r6)
|
||||
f00: 4c 00 00 64 rfi
|
||||
f04: 48 00 00 3c b f40 <_start+0xf40>
|
||||
f08: 60 00 00 00 nop
|
||||
f0c: 60 00 00 00 nop
|
||||
f10: 60 00 00 00 nop
|
||||
f14: 60 00 00 00 nop
|
||||
f18: 60 00 00 00 nop
|
||||
f1c: 60 00 00 00 nop
|
||||
f20: 60 00 00 00 nop
|
||||
f24: 60 00 00 00 nop
|
||||
f28: 60 00 00 00 nop
|
||||
f2c: 60 00 00 00 nop
|
||||
f30: 60 00 00 00 nop
|
||||
f34: 60 00 00 00 nop
|
||||
f38: 60 00 00 00 nop
|
||||
f3c: 60 00 00 00 nop
|
||||
f40: 7c 69 02 a6 mfctr r3
|
||||
f44: 4b ff fc bd bl c00 <_start+0xc00>
|
||||
f48: 7c 69 03 a6 mtctr r3
|
||||
f4c: 7c 08 03 a6 mtlr r0
|
||||
f50: 38 60 00 00 li r3,0
|
||||
f54: 4c 00 00 64 rfi
|
||||
@ -0,0 +1,982 @@
|
||||
48000400
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000CE0
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
48000000
|
||||
4800001C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
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|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7C0802A6
|
||||
2C230001
|
||||
41820038
|
||||
2C230010
|
||||
41820070
|
||||
2C230100
|
||||
418200A8
|
||||
2C230107
|
||||
41820120
|
||||
3860FFFF
|
||||
7C0803A6
|
||||
4C000064
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7C7E6AA6
|
||||
4C000064
|
||||
48000038
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7C6C42A6
|
||||
4C000064
|
||||
48000038
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7CBE6AA6
|
||||
78A53664
|
||||
38A50A80
|
||||
38C50028
|
||||
E8E60000
|
||||
98870000
|
||||
38E70001
|
||||
39050020
|
||||
E9080000
|
||||
7C274000
|
||||
38600000
|
||||
40810010
|
||||
39050018
|
||||
E8E80000
|
||||
3860FFFF
|
||||
F8E60000
|
||||
4C000064
|
||||
4800003C
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
60000000
|
||||
7C6902A6
|
||||
4BFFFCBD
|
||||
7C6903A6
|
||||
7C0803A6
|
||||
38600000
|
||||
4C000064
|
||||
@ -0,0 +1,250 @@
|
||||
|
||||
rom: file format elf64-powerpc
|
||||
|
||||
Contents of section .kernel:
|
||||
0000 48000400 4800001c 60000000 60000000 H...H...`...`...
|
||||
0010 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0020 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0030 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0040 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0050 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0060 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0070 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0080 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0090 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
00a0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
00b0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
00c0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
00d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
00e0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
00f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0100 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0110 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0120 48000ce0 4800001c 60000000 60000000 H...H...`...`...
|
||||
0130 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0140 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0150 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0160 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0170 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0180 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0190 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
01a0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
01b0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
01c0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
01d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
01e0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
01f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0200 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0210 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0220 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0230 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0240 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0250 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0260 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0270 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0280 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0290 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
02a0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
02b0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
02c0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
02d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
02e0 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
02f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0300 48000a00 4800001c 60000000 60000000 H...H...`...`...
|
||||
0310 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0320 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0330 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0340 48000000 480000bc 60000000 60000000 H...H...`...`...
|
||||
0350 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0360 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0370 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0380 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0390 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
03a0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
03b0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
03c0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
03d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
03e0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
03f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0400 7cbe6aa6 2c250000 408200ec 3c608c00 |.j.,%..@...<`..
|
||||
0410 3800001f 38400015 38800000 3900025f 8...8@..8...9.._
|
||||
0420 7c7cfba6 7c4011a6 7c8009a6 7d0001a6 ||..|@..|...}...
|
||||
0430 4c00012c 81400a08 3800001e 3c801000 L..,.@..8...<...
|
||||
0440 3900025f 65081000 7d4011a6 7c8009a6 9.._e...}@..|...
|
||||
0450 7d0001a6 4c00012c 3c608800 3800000f }...L..,<`..8...
|
||||
0460 3840003f 38800000 3900025f 7c7cfba6 8@.?8...9.._||..
|
||||
0470 7c4011a6 7c8009a6 7d0001a6 4c00012c |@..|...}...L..,
|
||||
0480 3800000d 3c801000 3900025f 65081000 8...<...9.._e...
|
||||
0490 7d4011a6 7c8009a6 7d0001a6 4c00012c }@..|...}...L..,
|
||||
04a0 81400a00 7d400124 4c00012c 3c200300 .@..}@.$L..,< ..
|
||||
04b0 7c334ba6 38200000 7c3603a6 7c3d43a6 |3K.8 ..|6..|=C.
|
||||
04c0 7c3c43a6 3c40fe00 7c5053a6 7c56faa6 |<C.<@..|PS.|V..
|
||||
04d0 70420200 7c56fba6 7c3053a6 7c3453a6 pB..|V..|0S.|4S.
|
||||
04e0 80200a04 7021000f 7c366ba6 4c00012c . ..p!..|6k.L..,
|
||||
04f0 48000014 81400a00 7d400124 4c00012c H....@..}@.$L..,
|
||||
0500 48000004 80200a04 74218000 40820008 H.... ..t!..@...
|
||||
0510 480006f1 80200a04 3c407fff 6042ffff H.... ..<@..`B..
|
||||
0520 7c211038 90200a04 7cbe6aa6 78a53664 |!.8. ..|.j.x.6d
|
||||
0530 38a50a80 81650000 e9850008 e9a50010 8....e..........
|
||||
0540 80200a04 70210010 4182001c 80400a0c . ..p!..A....@..
|
||||
0550 3c204400 60210012 f8220000 7c2803a6 < D.`!..."..|(..
|
||||
0560 48000014 48000005 7c2802a6 38210030 H...H...|(..8!.0
|
||||
0570 7c2803a6 7d7b03a6 7dba03a6 7d816378 |(..}{..}...}.cx
|
||||
0580 7c7e6aa6 7c4c42a6 f8450030 4c000064 |~j.|LB..E.0L..d
|
||||
0590 60000000 60000000 60000000 44000022 `...`...`...D.."
|
||||
05a0 7cbe6aa6 78a53664 38a50a80 7c4c42a6 |.j.x.6d8...|LB.
|
||||
05b0 f8450038 2c230000 41820148 48000044 .E.8,#..A..HH..D
|
||||
05c0 48000040 60000000 60000000 60000000 H..@`...`...`...
|
||||
05d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
05e0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
05f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0600 48000000 480000fc 60000000 60000000 H...H...`...`...
|
||||
0610 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0620 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0630 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0640 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0650 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0660 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0670 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0680 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0690 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
06a0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
06b0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
06c0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
06d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
06e0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
06f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0700 48000000 480000fc 60000000 60000000 H...H...`...`...
|
||||
0710 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0720 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0730 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0740 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0750 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0760 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0770 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0780 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0790 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
07a0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
07b0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
07c0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
07d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
07e0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
07f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0800 48000000 4800001c 60000000 60000000 H...H...`...`...
|
||||
0810 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0820 48000000 480001dc 60000000 60000000 H...H...`...`...
|
||||
0830 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0840 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0850 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0860 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0870 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0880 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0890 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
08a0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
08b0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
08c0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
08d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
08e0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
08f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0900 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0910 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0920 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0930 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0940 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0950 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0960 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0970 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0980 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0990 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
09a0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
09b0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
09c0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
09d0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
09e0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
09f0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0a00 8002b000 80000001 0000003f 10000000 ...........?....
|
||||
0a10 48000070 60000000 60000000 60000000 H..p`...`...`...
|
||||
0a20 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0a30 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0a40 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0a50 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0a60 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0a70 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0a80 8002f000 00000000 00000000 100ffffc ................
|
||||
0a90 00000000 10000000 00000000 10030000 ................
|
||||
0aa0 00000000 10031fff 00000000 10030000 ................
|
||||
0ab0 00000000 00000000 00000000 00000000 ................
|
||||
0ac0 8002f000 00000000 00000000 100efffc ................
|
||||
0ad0 00000000 10000000 00000000 10032000 .............. .
|
||||
0ae0 00000000 10033fff 00000000 10032000 ......?....... .
|
||||
0af0 00000000 00000000 00000000 00000000 ................
|
||||
0b00 8002f000 00000000 00000000 00000000 ................
|
||||
0b10 00000000 10000000 00000000 10034000 ..............@.
|
||||
0b20 00000000 10035fff 00000000 10034000 ......_.......@.
|
||||
0b30 00000000 00000000 00000000 00000000 ................
|
||||
0b40 8002f000 00000000 00000000 00000000 ................
|
||||
0b50 00000000 10000000 00000000 10036000 ..............`.
|
||||
0b60 00000000 10037fff 00000000 10036000 ..............`.
|
||||
0b70 00000000 00000000 00000000 00000000 ................
|
||||
0b80 48000080 60000000 60000000 60000000 H...`...`...`...
|
||||
0b90 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0ba0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0bb0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0bc0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0bd0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0be0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0bf0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0c00 7cbe6aa6 78a53664 38a50a80 38c50018 |.j.x.6d8...8...
|
||||
0c10 e8e60000 38c50020 e9060000 7d074050 ....8.. ....}.@P
|
||||
0c20 39080001 7d0903a6 38c00000 7ce83b78 9...}...8...|.;x
|
||||
0c30 98c80000 39080001 4200fff8 39050028 ....9...B...9..(
|
||||
0c40 f8e80000 4e800020 480000b8 60000000 ....N.. H...`...
|
||||
0c50 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0c60 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0c70 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0c80 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0c90 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0ca0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0cb0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0cc0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0cd0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0ce0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0cf0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0d00 80000a00 7c000124 4c00012c 4bfff894 ....|..$L..,K...
|
||||
0d10 480000f0 60000000 60000000 60000000 H...`...`...`...
|
||||
0d20 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0d30 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0d40 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0d50 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0d60 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0d70 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0d80 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0d90 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0da0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0db0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0dc0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0dd0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0de0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0df0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0e00 7c0802a6 2c230001 41820038 2c230010 |...,#..A..8,#..
|
||||
0e10 41820070 2c230100 418200a8 2c230107 A..p,#..A...,#..
|
||||
0e20 41820120 3860ffff 7c0803a6 4c000064 A.. 8`..|...L..d
|
||||
0e30 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0e40 7c7e6aa6 4c000064 48000038 60000000 |~j.L..dH..8`...
|
||||
0e50 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0e60 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0e70 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0e80 7c6c42a6 4c000064 48000038 60000000 |lB.L..dH..8`...
|
||||
0e90 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0ea0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0eb0 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0ec0 7cbe6aa6 78a53664 38a50a80 38c50028 |.j.x.6d8...8..(
|
||||
0ed0 e8e60000 98870000 38e70001 39050020 ........8...9..
|
||||
0ee0 e9080000 7c274000 38600000 40810010 ....|'@.8`..@...
|
||||
0ef0 39050018 e8e80000 3860ffff f8e60000 9.......8`......
|
||||
0f00 4c000064 4800003c 60000000 60000000 L..dH..<`...`...
|
||||
0f10 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0f20 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0f30 60000000 60000000 60000000 60000000 `...`...`...`...
|
||||
0f40 7c6902a6 4bfffcbd 7c6903a6 7c0803a6 |i..K...|i..|...
|
||||
0f50 38600000 4c000064 8`..L..d
|
||||
Binary file not shown.
Binary file not shown.
@ -0,0 +1,13 @@
|
||||
#include <stdint.h>
|
||||
|
||||
uint32_t main(uint32_t tid) {
|
||||
uint32_t i, a = tid;
|
||||
for (i = 0; i < 10; i++) {
|
||||
a = a + i + 1;
|
||||
}
|
||||
if (a == 55+tid) {
|
||||
return 0;
|
||||
} else {
|
||||
return 0x8000000 + a;
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,37 @@
|
||||
|
||||
test: file format elf64-powerpc
|
||||
|
||||
|
||||
Disassembly of section .test:
|
||||
|
||||
0000000010000000 <main>:
|
||||
10000000: 94 21 ff e0 stwu r1,-32(r1)
|
||||
10000004: 90 61 00 18 stw r3,24(r1)
|
||||
10000008: 81 21 00 18 lwz r9,24(r1)
|
||||
1000000c: 91 21 00 0c stw r9,12(r1)
|
||||
10000010: 39 20 00 00 li r9,0
|
||||
10000014: 91 21 00 08 stw r9,8(r1)
|
||||
10000018: 48 00 00 24 b 1000003c <main+0x3c>
|
||||
1000001c: 81 41 00 0c lwz r10,12(r1)
|
||||
10000020: 81 21 00 08 lwz r9,8(r1)
|
||||
10000024: 7d 2a 4a 14 add r9,r10,r9
|
||||
10000028: 39 29 00 01 addi r9,r9,1
|
||||
1000002c: 91 21 00 0c stw r9,12(r1)
|
||||
10000030: 81 21 00 08 lwz r9,8(r1)
|
||||
10000034: 39 29 00 01 addi r9,r9,1
|
||||
10000038: 91 21 00 08 stw r9,8(r1)
|
||||
1000003c: 81 21 00 08 lwz r9,8(r1)
|
||||
10000040: 28 09 00 09 cmplwi r9,9
|
||||
10000044: 40 81 ff d8 ble 1000001c <main+0x1c>
|
||||
10000048: 81 21 00 18 lwz r9,24(r1)
|
||||
1000004c: 39 29 00 37 addi r9,r9,55
|
||||
10000050: 81 41 00 0c lwz r10,12(r1)
|
||||
10000054: 7c 0a 48 00 cmpw r10,r9
|
||||
10000058: 40 82 00 0c bne 10000064 <main+0x64>
|
||||
1000005c: 39 20 00 00 li r9,0
|
||||
10000060: 48 00 00 0c b 1000006c <main+0x6c>
|
||||
10000064: 81 21 00 0c lwz r9,12(r1)
|
||||
10000068: 3d 29 08 00 addis r9,r9,2048
|
||||
1000006c: 7d 23 4b 78 mr r3,r9
|
||||
10000070: 38 21 00 20 addi r1,r1,32
|
||||
10000074: 4e 80 00 20 blr
|
||||
@ -0,0 +1,30 @@
|
||||
9421FFE0
|
||||
90610018
|
||||
81210018
|
||||
9121000C
|
||||
39200000
|
||||
91210008
|
||||
48000024
|
||||
8141000C
|
||||
81210008
|
||||
7D2A4A14
|
||||
39290001
|
||||
9121000C
|
||||
81210008
|
||||
39290001
|
||||
91210008
|
||||
81210008
|
||||
28090009
|
||||
4081FFD8
|
||||
81210018
|
||||
39290037
|
||||
8141000C
|
||||
7C0A4800
|
||||
4082000C
|
||||
39200000
|
||||
4800000C
|
||||
8121000C
|
||||
3D290800
|
||||
7D234B78
|
||||
38210020
|
||||
4E800020
|
||||
Binary file not shown.
@ -0,0 +1,12 @@
|
||||
|
||||
test: file format elf64-powerpc
|
||||
|
||||
Contents of section .test:
|
||||
10000000 9421ffe0 90610018 81210018 9121000c .!...a...!...!..
|
||||
10000010 39200000 91210008 48000024 8141000c 9 ...!..H..$.A..
|
||||
10000020 81210008 7d2a4a14 39290001 9121000c .!..}*J.9)...!..
|
||||
10000030 81210008 39290001 91210008 81210008 .!..9)...!...!..
|
||||
10000040 28090009 4081ffd8 81210018 39290037 (...@....!..9).7
|
||||
10000050 8141000c 7c0a4800 4082000c 39200000 .A..|.H.@...9 ..
|
||||
10000060 4800000c 8121000c 3d290800 7d234b78 H....!..=)..}#Kx
|
||||
10000070 38210020 4e800020 8!. N..
|
||||
@ -0,0 +1 @@
|
||||
../../sim/mem/test1
|
||||
Loading…
Reference in New Issue