litex vivado build
openpowerwtf
2 years ago
parent
592b55cc02
commit
2ec8bc211e
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__pycache__/
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vivado*
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#!/usr/bin/python3
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# A2O Test - build with core.py
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# a2o.py --csr-csv csr.csv --no-compile-software --build --sys-clk-freq 10e6
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#
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import os
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import argparse
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from migen import *
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# wtf - use local platform
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from platforms import cmod7
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# wtf - use local core (not built into litex)
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# help python find package
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import sys
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binPath = os.path.dirname(os.path.realpath(__file__))
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sys.path.append(os.path.join(binPath, 'a2p')) # dir with core package; core.py defines core source location
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# get core def
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from a2o import A2O
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# add to litex dict
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from litex.soc.cores import cpu
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cpu.CPUS['a2o'] = A2O
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores import dna, xadc
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from litex.soc.cores.gpio import GPIOIn
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from litex.soc.cores.gpio import GPIOOut
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.interconnect import wishbone
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from litex.soc.cores import uart
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from litex.soc.cores.uart import UART
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from litex.soc.cores.uart import UARTPHY
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from litex.soc.cores.uart import UARTWishboneBridge
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from litescope import LiteScopeAnalyzer
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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#wtf if you do this it crashes later..request() takes the pin off 'available' list i think; so can't put to csr reg
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#no idea how to modify the reset signal later
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#maybe have to change this class to take a signal you create first?
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#x = platform.request('user_btn',0)
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self.comb += pll.reset.eq(self.rst)
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#self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request('clk12'), 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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def _to_signal(obj):
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return obj.raw_bits() if isinstance(obj, Record) else obj
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6),
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with_analyzer=False,
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uart_baudrate=115200,
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**kwargs):
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coreUART = True
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# try build using different fpga's
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#platform = cmod7.Platform()
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platform = cmod7.Platform(fpga='xc7a200t-SBG484-1') # arty-200
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#platform = cmod7.Platform(fpga='xc7k325t-FFG676-1') #xc7k325t-ffv676-1 ?? need to try it on machine with license
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SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
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with_uart=coreUART, integrated_sram_size=0, integrated_rom_size=0,
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ident='A2O Test', ident_version=True, uart_baudrate=uart_baudrate,
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cpu_type='a2o')
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print(f'Building variant={self.cpu.variant}.')
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# no irq yet? should be able to connect
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#self.add_constant('UART_POLLING')
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#!!!!!!!!!!!!!!!!!!
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# any hints here on using uarts (to get the gpio one working)?
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# cult-soft.de/2920/05/24/litex-uart-hub
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# played a little below but didnt try if it works
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#!!!!!!!!!!!!!!!!!!
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# this appears to be how to set up fixed csr order but not sure it works this way. https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py
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#SoCCore.csr_map
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#self.csr_map = {**SoCCore.csr_map, **{
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#self.csr_map = {
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# 'ctrl': 0,
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# 'dna' : 1,
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# 'uart': 2,
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# 'i2c': 3,
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# 'leds': 4
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#}}
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#interrupt_map = {**soc_cls.interrupt_map, **{
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# 'uart': 0,
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# 'timer0': 1,
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#}}
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self.mem_map = {
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'csr': 0xFFF00000,
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'main_ram': 0x00100000,
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'rom': 0x00000000,
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'ram': 0x00010000,
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}
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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if not coreUART:
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self.submodules.serial_bridge = UARTWishboneBridge(platform.request('serial'), sys_clk_freq)
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self.add_wb_master(self.serial_bridge.wishbone)
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self.add_csr('node_ctl')
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self.add_csr('node_config')
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self.add_csr('node_status')
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# ON-BOARD MEM ------------------------------------------------------------------------------
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with open('rom.init', 'r') as file:
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hexdata = file.read().replace('\n', '')
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#a2o how will this work for a2o? should allow 32BE or 64LE to load kernel+bios
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# 1. core resets to 32BE
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# 2. probably want to link kernel+bios in same mode, so have kernel deal with possible mode switch
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# 3. load mem here in proper mode based on variant (A2O_32BE or A2O64_LE)
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outFile = open('mem_init', 'w') # write data immediately so available even if not building (sim)
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# this seems to work (specified in BE in rom.init, instructions are decoded properly)
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# BUT, vivado wants each line to be 4B to match width (at least for sim)
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bytedata = []
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for i in range(0, len(hexdata), 8):
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data = int(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2], 16) # BE->LE
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bytedata.append(data)
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outFile.write(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2] + '\n')
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#bytedata.append(int(hexdata[i:i+2] + hexdata[i+2:i+4] + hexdata[i+4:i+6] + hexdata[i+6:i+8], 16))
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romdata = bytedata
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print('Read ' + str(len(romdata)) + ' bytes for ROM data.')
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outFile.close()
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print('Wrote mem.init')
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self.add_rom('rom', origin=self.mem_map['rom'], size=0x10000, contents=romdata) # name, origin, size, contents=[], mode='r'
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# make this sram to match what linker expects
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self.add_ram('sram', origin=self.mem_map['ram'], size=0x10000) # name, origin, size, contents=[], mode='rw'
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all('user_led'),
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sys_clk_freq = sys_clk_freq
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)
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self.add_csr('leds')
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# Buttons
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self.submodules.buttons = GPIOIn(
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pads = platform.request_all('user_btn')
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)
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self.add_csr('buttons')
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# SRAM -------------------------------------------------------------------------------------
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self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=0x100)
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# Analyzer ---------------------------------------------------------------------------------
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if with_analyzer:
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analyzer_signals = [
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self.cpu.dbus.stb,
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self.cpu.dbus.cyc,
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self.cpu.dbus.adr,
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self.cpu.dbus.we,
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self.cpu.dbus.ack,
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self.cpu.dbus.sel,
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self.cpu.dbus.dat_w,
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self.cpu.dbus.dat_r,
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]
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
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depth = 512,
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clock_domain = 'sys',
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csr_csv = 'analyzer.csv')
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self.add_csr('analyzer')
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description='A2O Test')
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parser.add_argument('--build', action='store_true', help='Build bitstream')
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parser.add_argument('--load', action='store_true', help='Load bitstream')
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parser.add_argument('--sys-clk-freq', default=100e6, help='System clock frequency (default: 100MHz)')
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parser.add_argument('--with-analyzer', action='store_true', help='Include analyzer')
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builder_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_analyzer = args.with_analyzer,
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if __name__ == '__main__':
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main()
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from .core import A2O
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# A2O variants
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import os
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from migen import *
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.cpu import CPU
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dir = os.path.dirname(os.path.realpath(__file__))
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# these select the top RTL file for each variant name
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CPU_VARIANTS = {
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'WB_32BE' : 'a2owb',
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'WB_64LE' : 'a2owb',
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'standard' : 'a2owb'
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}
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# 32 is from a2p plus -ma2; can get rid of some of them
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GCC_FLAGS = {
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'WB_32BE' : '-ma2 -m32 -mbig-endian fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes',
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'WB_64LE' : '-ma2 -m64 -mlittle-endian -mabi=elfv2 -fnostack-protector'
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}
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class A2O(CPU, AutoCSR):
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name = 'a2o'
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human_name = 'a2o'
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variants = CPU_VARIANTS
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family = 'ppc64'
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data_width = 64
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endianness = 'little'
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gcc_triple = ('powerpc64le-linux', 'powerpc64le-linux-gnu')
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linker_output_format = 'elf64-powerpcle'
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nop = 'nop'
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io_regions = {0xF0000000: 0x10000000} # origin, length
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@property
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def mem_map(self):
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return {
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'rom': 0x00000000, # on-board
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'sram': 0x00004000, # on-board
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'main_ram': 0x00100000, # external 1M+
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'csr': 0xF0000000,
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}
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@property
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def gcc_flags(self):
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flags = GCC_FLAGS[self.variant]
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flags += ' -D__a2o__'
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return flags
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def __init__(self, platform, variant='WB'):
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if variant == 'standard':
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variant = 'WB_64LE'
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if variant == 'WB_32LE':
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self.family = 'ppc32'
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self.data_width = 32
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self.endianness = 'big'
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self.gcc_triple = 'powerpc-linux-gnu'
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self.linker_output_format = 'elf32-powerpc'
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self.platform = platform
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self.variant = variant
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self.human_name = CPU_VARIANTS.get(variant, 'a2o')
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self.external_variant = None
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self.reset = Signal()
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self.interrupt = Signal(3)
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self.interruptS = Signal()
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self.dbus = dbus = wishbone.Interface()
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self.periph_buses = [dbus]
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self.memory_buses = []
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self.enableDebug = False
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self.enableJTAG = False
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self.reset_address = 0x00000000
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self.cpu_params = dict(
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i_clk_1x = ClockSignal('sys'),
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i_clk_2x = ClockSignal('sys2x'),
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i_rst = ResetSignal() | self.reset,
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# how do i connect these to csr?
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#i_cfg_wr = csr_0[0], # wr command - will be 3+ bit cmd
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#i_cfg_dat = csr_1, # wr data
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#o_status = status, # should update csr continuously
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i_cfg_wr = 0,
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i_externalInterrupt = self.interrupt[0],
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i_timerInterrupt = self.interrupt[1],
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i_softwareInterrupt = self.interrupt[2],
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i_externalInterruptS = self.interruptS,
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#wtf i guess you get these names from the Inteface() def - but what about other sigs?
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o_wb_cyc = dbus.cyc,
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o_wb_stb = dbus.stb,
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o_wb_adr = Cat(dbus.adr,Signal(2)),
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o_wb_we = dbus.we,
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o_wb_sel = dbus.sel,
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o_wb_datw = dbus.dat_w,
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i_wb_ack = dbus.ack,
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i_wb_datr = dbus.dat_r
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)
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def set_reset_address(self, reset_address):
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if reset_address != self.reset_address:
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print(f'Reset address = {self.reset_address} and cannot be changed here!')
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assert False
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@staticmethod
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def add_sources(platform, variant='WB_64LE'):
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dir = os.path.dirname(os.path.realpath(__file__))
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# unfortunately, vivado doesn't do the right thing and skip modules already analyzed, so overrides dirs don't work; rearrange override after
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platform.add_source(os.path.join(dir, 'verilog/a2o_litex/')) # node, wrapper
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platform.add_source(os.path.join(dir, 'verilog/trilib/')) # array, ff
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platform.add_source(os.path.join(dir, 'verilog/trilib_clk1x/')) # 2r4w override
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#platform.add_source(os.path.join(dir, 'verilog/unisims/')) # xil array
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platform.add_source(os.path.join(dir, 'verilog/work/')) # core
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def use_external_variant(self, variant_filename):
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self.external_variant = True
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self.platform.add_source(variant_filename)
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def do_finalize(self):
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if not self.external_variant:
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self.add_sources(self.platform, self.variant)
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self.specials += Instance('a2owb', **self.cpu_params)
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../../verilog
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#--------------------------------------------------------------------------------
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# Auto-generated by LiteX (6932fc51) on 2022-08-03 07:06:41
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#--------------------------------------------------------------------------------
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csr_base,leds,0xfff01800,,
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csr_base,buttons,0xfff02000,,
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csr_base,ctrl,0xfff02800,,
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csr_base,identifier_mem,0xfff03000,,
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csr_base,timer0,0xfff03800,,
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csr_base,uart,0xfff04000,,
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csr_register,leds_out,0xfff01800,1,rw
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csr_register,buttons_in,0xfff02000,1,ro
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csr_register,ctrl_reset,0xfff02800,1,rw
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csr_register,ctrl_scratch,0xfff02804,1,rw
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csr_register,ctrl_bus_errors,0xfff02808,1,ro
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csr_register,timer0_load,0xfff03800,1,rw
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csr_register,timer0_reload,0xfff03804,1,rw
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csr_register,timer0_en,0xfff03808,1,rw
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csr_register,timer0_update_value,0xfff0380c,1,rw
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csr_register,timer0_value,0xfff03810,1,ro
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csr_register,timer0_ev_status,0xfff03814,1,ro
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csr_register,timer0_ev_pending,0xfff03818,1,rw
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csr_register,timer0_ev_enable,0xfff0381c,1,rw
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csr_register,uart_rxtx,0xfff04000,1,rw
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csr_register,uart_txfull,0xfff04004,1,ro
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csr_register,uart_rxempty,0xfff04008,1,ro
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csr_register,uart_ev_status,0xfff0400c,1,ro
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csr_register,uart_ev_pending,0xfff04010,1,rw
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csr_register,uart_ev_enable,0xfff04014,1,rw
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csr_register,uart_txempty,0xfff04018,1,ro
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csr_register,uart_rxfull,0xfff0401c,1,ro
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constant,config_clock_frequency,50000000,,
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constant,config_cpu_has_interrupt,None,,
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constant,config_cpu_reset_addr,0,,
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constant,config_cpu_type_a2o,None,,
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constant,config_cpu_variant_standard,None,,
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constant,config_cpu_human_name,a2owb,,
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constant,config_cpu_nop,nop,,
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constant,config_rom_init,1,,
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constant,config_csr_data_width,32,,
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constant,config_csr_alignment,32,,
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constant,config_bus_standard,wishbone,,
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constant,config_bus_data_width,32,,
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constant,config_bus_address_width,32,,
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constant,config_bus_bursting,0,,
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constant,timer0_interrupt,1,,
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constant,uart_interrupt,0,,
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memory_region,rom,0x00000000,65536,cached
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memory_region,sram,0x00010000,65536,cached
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memory_region,main_ram,0x00100000,256,cached
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memory_region,csr,0xfff00000,65536,io
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/home/wtf/projects/litex/litex
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||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,172 @@
|
||||
#wtf from litex-boards; added some stuff from https://github.com/litex-hub/fpga_101
|
||||
|
||||
#
|
||||
# This file is part of LiteX-Boards.
|
||||
#
|
||||
# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
from litex.build.generic_platform import *
|
||||
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
|
||||
from litex.build.openocd import OpenOCD
|
||||
|
||||
# IOs ----------------------------------------------------------------------------------------------
|
||||
|
||||
_io = [
|
||||
# Clk / Rst
|
||||
('clk12', 0, Pins('L17'), IOStandard('LVCMOS33')),
|
||||
|
||||
# Leds
|
||||
('user_led', 0, Pins('A17'), IOStandard('LVCMOS33')), # LD1
|
||||
('user_led', 1, Pins('C16'), IOStandard('LVCMOS33')), # LD2
|
||||
|
||||
# RGB
|
||||
('user_rgb_led', 0,
|
||||
Subsignal('r', Pins('C17')),
|
||||
Subsignal('g', Pins('B16')),
|
||||
Subsignal('b', Pins('B17')),
|
||||
IOStandard('LVCMOS33'),
|
||||
),
|
||||
|
||||
# Buttons
|
||||
('user_btn', 0, Pins('A18'), IOStandard('LVCMOS33')), # B0
|
||||
('user_btn', 1, Pins('B18'), IOStandard('LVCMOS33')), # B1
|
||||
|
||||
#### test to see if can add uart by changing platform
|
||||
('uart_0', 0,
|
||||
Subsignal('tx', Pins('J3')), # 10
|
||||
Subsignal('rx', Pins('J1')), # 11
|
||||
IOStandard('LVCMOS33'),
|
||||
),
|
||||
|
||||
# GPIO
|
||||
('digital', 0, Pins('M3'), IOStandard('LVCMOS33')), # 1
|
||||
('digital', 1, Pins('L3'), IOStandard('LVCMOS33')), # 2
|
||||
('digital', 2, Pins('A16'), IOStandard('LVCMOS33')), # 3
|
||||
('digital', 3, Pins('K3'), IOStandard('LVCMOS33')), # 4
|
||||
('digital', 4, Pins('C15'), IOStandard('LVCMOS33')), # 5
|
||||
('digital', 5, Pins('H1'), IOStandard('LVCMOS33')), # 6
|
||||
('digital', 6, Pins('A15'), IOStandard('LVCMOS33')), # 7
|
||||
('digital', 7, Pins('B15'), IOStandard('LVCMOS33')), # 8
|
||||
('digital', 8, Pins('A14'), IOStandard('LVCMOS33')), # 9
|
||||
('digital', 9, Pins('J3'), IOStandard('LVCMOS33')), # 10
|
||||
('digital', 10, Pins('J1'), IOStandard('LVCMOS33')), # 11
|
||||
('digital', 11, Pins('K2'), IOStandard('LVCMOS33')), # 12
|
||||
('digital', 12, Pins('L1'), IOStandard('LVCMOS33')), # 13
|
||||
('digital', 13, Pins('L2'), IOStandard('LVCMOS33')), # 14
|
||||
('digital', 14, Pins('M1'), IOStandard('LVCMOS33')), # 17
|
||||
('digital', 15, Pins('N3'), IOStandard('LVCMOS33')), # 18
|
||||
('digital', 16, Pins('P3'), IOStandard('LVCMOS33')), # 19
|
||||
('digital', 17, Pins('M2'), IOStandard('LVCMOS33')), # 20
|
||||
('digital', 18, Pins('N1'), IOStandard('LVCMOS33')), # 21
|
||||
('digital', 19, Pins('N2'), IOStandard('LVCMOS33')), # 22
|
||||
('digital', 20, Pins('P1'), IOStandard('LVCMOS33')), # 23
|
||||
('digital', 21, Pins('R3'), IOStandard('LVCMOS33')), # 26
|
||||
('digital', 22, Pins('T3'), IOStandard('LVCMOS33')), # 27
|
||||
('digital', 23, Pins('R2'), IOStandard('LVCMOS33')), # 28
|
||||
('digital', 24, Pins('T1'), IOStandard('LVCMOS33')), # 29
|
||||
('digital', 25, Pins('T2'), IOStandard('LVCMOS33')), # 30
|
||||
('digital', 26, Pins('U1'), IOStandard('LVCMOS33')), # 31
|
||||
('digital', 27, Pins('W2'), IOStandard('LVCMOS33')), # 32
|
||||
('digital', 28, Pins('V2'), IOStandard('LVCMOS33')), # 33
|
||||
('digital', 29, Pins('W3'), IOStandard('LVCMOS33')), # 34
|
||||
('digital', 30, Pins('V3'), IOStandard('LVCMOS33')), # 35
|
||||
('digital', 31, Pins('W5'), IOStandard('LVCMOS33')), # 36
|
||||
('digital', 32, Pins('V4'), IOStandard('LVCMOS33')), # 37
|
||||
('digital', 33, Pins('U4'), IOStandard('LVCMOS33')), # 38
|
||||
('digital', 34, Pins('V5'), IOStandard('LVCMOS33')), # 39
|
||||
('digital', 35, Pins('W4'), IOStandard('LVCMOS33')), # 40
|
||||
('digital', 36, Pins('U5'), IOStandard('LVCMOS33')), # 41
|
||||
('digital', 37, Pins('U2'), IOStandard('LVCMOS33')), # 42
|
||||
('digital', 38, Pins('W6'), IOStandard('LVCMOS33')), # 43
|
||||
('digital', 39, Pins('U3'), IOStandard('LVCMOS33')), # 44
|
||||
('digital', 40, Pins('U7'), IOStandard('LVCMOS33')), # 45
|
||||
('digital', 41, Pins('W7'), IOStandard('LVCMOS33')), # 46
|
||||
('digital', 42, Pins('U8'), IOStandard('LVCMOS33')), # 47
|
||||
('digital', 43, Pins('V8'), IOStandard('LVCMOS33')), # 48
|
||||
|
||||
# declare these to use GPIO 15/16 as analog to xadc
|
||||
('analog', 0,
|
||||
Subsignal('n'), Pins('G2'),
|
||||
Subsignal('p'), Pins('G3'),
|
||||
IOStandard('LVCMOS33')
|
||||
),
|
||||
|
||||
('analog', 1,
|
||||
Subsignal('n'), Pins('J2'),
|
||||
Subsignal('p'), Pins('H2'),
|
||||
IOStandard('LVCMOS33')
|
||||
),
|
||||
|
||||
# PMOD
|
||||
('pmod', 0, Pins('G17'), IOStandard('LVCMOS33')), # 1
|
||||
('pmod', 1, Pins('G19'), IOStandard('LVCMOS33')), # 2
|
||||
('pmod', 2, Pins('N18'), IOStandard('LVCMOS33')), # 3
|
||||
('pmod', 3, Pins('L18'), IOStandard('LVCMOS33')), # 4
|
||||
('pmod', 4, Pins('H17'), IOStandard('LVCMOS33')), # 7
|
||||
('pmod', 5, Pins('H19'), IOStandard('LVCMOS33')), # 8
|
||||
('pmod', 6, Pins('J19'), IOStandard('LVCMOS33')), # 9
|
||||
('pmod', 7, Pins('K18'), IOStandard('LVCMOS33')), # 10
|
||||
|
||||
# Serial
|
||||
('serial', 0,
|
||||
Subsignal('tx', Pins('J18')),
|
||||
Subsignal('rx', Pins('J17')),
|
||||
IOStandard('LVCMOS33'),
|
||||
),
|
||||
|
||||
# JTAG: TMS(W9),TCK(C8),TDI(W10),TDO(W8)
|
||||
|
||||
# Crypto 1-Wire (?) - goes to ATSHA204A-MAHCZ-T
|
||||
('crypto_sda', 0, Pins('D17'), IOStandard('LVCMOS33')),
|
||||
|
||||
# QSPI
|
||||
('mx25l3233_spi', 0,
|
||||
Subsignal('cs', Pins('K19')),
|
||||
Subsignal('mosi', Pins('D18')), # DQ0
|
||||
Subsignal('miso', Pins('D19')), # DQ1
|
||||
#Subsignal('clk', Pins('E19')), # ref says E19; doesn't show in xdc; C11 in schematic
|
||||
# ref: On other boards, SCK is an exception because it remains a dedicated pin even after configuration,
|
||||
# however, on the Cmod A7 the SCK signal is routed to an additional general purpose pin that can be
|
||||
# accessed after configuration (pin E19). This allows access to this pin without having to instantiate
|
||||
# the special FPGA primitive called STARTUPE2.
|
||||
Subsignal('wp', Pins('G18')), # DQ2
|
||||
Subsignal('hld', Pins('F18')), # DQ3
|
||||
IOStandard('LVCMOS33')
|
||||
),
|
||||
|
||||
# SRAM
|
||||
('issiram', 0,
|
||||
Subsignal('addr', Pins('M18 M19 K17 N17 P17 P18 R18 W19 U19 V19 W18 T17 T18 U17 U18 V16 W16 W17 V15'),
|
||||
IOStandard('LVCMOS33')
|
||||
),
|
||||
Subsignal('data', Pins('W15 W13 W14 U15 U16 V13 V14 U14'),
|
||||
IOStandard('LVCMOS33')
|
||||
),
|
||||
#this shows up as input! issiram_oen
|
||||
Subsignal('oen', Pins('P19'), IOStandard('LVCMOS33')),
|
||||
Subsignal('wen', Pins('R19'), IOStandard('LVCMOS33')),
|
||||
Subsignal('cen', Pins('N19'), IOStandard('LVCMOS33')),
|
||||
Misc('SLEW=FAST')
|
||||
),
|
||||
|
||||
]
|
||||
|
||||
# Platform -----------------------------------------------------------------------------------------
|
||||
|
||||
class Platform(XilinxPlatform):
|
||||
default_clk_name = 'clk12'
|
||||
default_clk_period = 1e9/12e6
|
||||
|
||||
def __init__(self, fpga=None):
|
||||
if fpga is None: # real cmod7
|
||||
XilinxPlatform.__init__(self, 'xc7a35t-CPG236-1', _io, toolchain='vivado')
|
||||
else: # phony for build
|
||||
XilinxPlatform.__init__(self, fpga, _io, toolchain='vivado')
|
||||
|
||||
#def create_programmer(self):
|
||||
# return OpenOCD('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a100t.bit')
|
||||
|
||||
def do_finalize(self, fragment):
|
||||
XilinxPlatform.do_finalize(self, fragment)
|
||||
self.add_period_constraint(self.lookup_request('clk12', loose=True), self.default_clk_period)
|
||||
@ -0,0 +1,181 @@
|
||||
#wtf from litex-boards; added some stuff from https://github.com/litex-hub/fpga_101
|
||||
|
||||
#
|
||||
# This file is part of LiteX-Boards.
|
||||
#
|
||||
# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
|
||||
# SPDX-License-Identifier: BSD-2-Clause
|
||||
|
||||
from litex.build.generic_platform import *
|
||||
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
|
||||
from litex.build.openocd import OpenOCD
|
||||
|
||||
# IOs ----------------------------------------------------------------------------------------------
|
||||
|
||||
_io = [
|
||||
# Clk / Rst
|
||||
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
|
||||
("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
|
||||
|
||||
# Leds
|
||||
("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
|
||||
("user_led", 1, Pins("K15"), IOStandard("LVCMOS33")),
|
||||
("user_led", 2, Pins("J13"), IOStandard("LVCMOS33")),
|
||||
("user_led", 3, Pins("N14"), IOStandard("LVCMOS33")),
|
||||
("user_led", 4, Pins("R18"), IOStandard("LVCMOS33")),
|
||||
("user_led", 5, Pins("V17"), IOStandard("LVCMOS33")),
|
||||
("user_led", 6, Pins("U17"), IOStandard("LVCMOS33")),
|
||||
("user_led", 7, Pins("U16"), IOStandard("LVCMOS33")),
|
||||
("user_led", 8, Pins("V16"), IOStandard("LVCMOS33")),
|
||||
("user_led", 9, Pins("T15"), IOStandard("LVCMOS33")),
|
||||
("user_led", 10, Pins("U14"), IOStandard("LVCMOS33")),
|
||||
("user_led", 11, Pins("T16"), IOStandard("LVCMOS33")),
|
||||
("user_led", 12, Pins("V15"), IOStandard("LVCMOS33")),
|
||||
("user_led", 13, Pins("V14"), IOStandard("LVCMOS33")),
|
||||
("user_led", 14, Pins("V12"), IOStandard("LVCMOS33")),
|
||||
("user_led", 15, Pins("V11"), IOStandard("LVCMOS33")),
|
||||
|
||||
# Switches
|
||||
("user_sw", 0, Pins("J15"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 1, Pins("L16"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 2, Pins("M13"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 3, Pins("R15"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 4, Pins("R17"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 5, Pins("T18"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 6, Pins("U18"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 7, Pins("R13"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 8, Pins("T8"), IOStandard("LVCMOS18")),
|
||||
("user_sw", 9, Pins("U8"), IOStandard("LVCMOS18")),
|
||||
("user_sw", 10, Pins("R16"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 11, Pins("T13"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 12, Pins("H6"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 13, Pins("U12"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 14, Pins("U11"), IOStandard("LVCMOS33")),
|
||||
("user_sw", 15, Pins("V10"), IOStandard("LVCMOS33")),
|
||||
|
||||
# Buttons
|
||||
("user_btn", 0, Pins("N17"), IOStandard("LVCMOS33")), # C
|
||||
("user_btn", 1, Pins("P17"), IOStandard("LVCMOS33")), # L
|
||||
("user_btn", 2, Pins("M17"), IOStandard("LVCMOS33")), # R
|
||||
("user_btn", 3, Pins("M18"), IOStandard("LVCMOS33")), # U
|
||||
("user_btn", 4, Pins("P18"), IOStandard("LVCMOS33")), # D
|
||||
|
||||
("user_rgb_led", 0,
|
||||
Subsignal("r", Pins("N16")),
|
||||
Subsignal("g", Pins("R11")),
|
||||
Subsignal("b", Pins("G14")),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
|
||||
("display_cs_n", 0, Pins("J17 J18 J14 P14 K2 U13 T9 T14"), IOStandard("LVCMOS33")),
|
||||
("display_abcdefg", 0, Pins("T10 R10 K16 K13 P15 T11 L18 H15"), IOStandard("LVCMOS33")),
|
||||
|
||||
# Serial
|
||||
("serial", 0,
|
||||
Subsignal("tx", Pins("D4")),
|
||||
Subsignal("rx", Pins("C4")),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
|
||||
# SPI
|
||||
("adxl362_spi", 0,
|
||||
Subsignal("cs_n", Pins("D15")),
|
||||
Subsignal("clk", Pins("F15")),
|
||||
Subsignal("mosi", Pins("F14")),
|
||||
Subsignal("miso", Pins("E15")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
|
||||
# SDCard
|
||||
("spisdcard", 0,
|
||||
Subsignal("rst", Pins("E2")),
|
||||
Subsignal("clk", Pins("B1")),
|
||||
Subsignal("mosi", Pins("C1"), Misc("PULLUP True")),
|
||||
Subsignal("cs_n", Pins("D2"), Misc("PULLUP True")),
|
||||
Subsignal("miso", Pins("C2"), Misc("PULLUP True")),
|
||||
Misc("SLEW=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
("sdcard", 0,
|
||||
Subsignal("rst", Pins("E2"), Misc("PULLUP True")),
|
||||
Subsignal("data", Pins("C2 E1 F1 D2"), Misc("PULLUP True")),
|
||||
Subsignal("cmd", Pins("C1"), Misc("PULLUP True")),
|
||||
Subsignal("clk", Pins("B1")),
|
||||
Subsignal("cd", Pins("A1")),
|
||||
Misc("SLEW=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
|
||||
# DDR2 SDRAM
|
||||
("ddram", 0,
|
||||
Subsignal("a", Pins(
|
||||
"M4 P4 M6 T1 L3 P5 M2 N1",
|
||||
"L4 N5 R2 K5 N6"),
|
||||
IOStandard("SSTL18_II")),
|
||||
Subsignal("ba", Pins("P2 P3 R1"), IOStandard("SSTL18_II")),
|
||||
Subsignal("ras_n", Pins("N4"), IOStandard("SSTL18_II")),
|
||||
Subsignal("cas_n", Pins("L1"), IOStandard("SSTL18_II")),
|
||||
Subsignal("we_n", Pins("N2"), IOStandard("SSTL18_II")),
|
||||
Subsignal("dm", Pins("T6 U1"), IOStandard("SSTL18_II")),
|
||||
Subsignal("dq", Pins(
|
||||
"R7 V6 R8 U7 V7 R6 U6 R5",
|
||||
"T5 U3 V5 U4 V4 T4 V1 T3"),
|
||||
IOStandard("SSTL18_II"),
|
||||
Misc("IN_TERM=UNTUNED_SPLIT_50")),
|
||||
Subsignal("dqs_p", Pins("U9 U2"), IOStandard("DIFF_SSTL18_II")),
|
||||
Subsignal("dqs_n", Pins("V9 V2"), IOStandard("DIFF_SSTL18_II")),
|
||||
Subsignal("clk_p", Pins("L6"), IOStandard("DIFF_SSTL18_II")),
|
||||
Subsignal("clk_n", Pins("L5"), IOStandard("DIFF_SSTL18_II")),
|
||||
Subsignal("cke", Pins("M1"), IOStandard("SSTL18_II")),
|
||||
Subsignal("odt", Pins("M3"), IOStandard("SSTL18_II")),
|
||||
Subsignal("cs_n", Pins("K6"), IOStandard("SSTL18_II")),
|
||||
Misc("SLEW=FAST"),
|
||||
),
|
||||
|
||||
# RMII Ethernet
|
||||
("eth_clocks", 0,
|
||||
Subsignal("ref_clk", Pins("D5")),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
|
||||
("eth", 0,
|
||||
Subsignal("rst_n", Pins("B3")),
|
||||
Subsignal("rx_data", Pins("C11 D10")),
|
||||
Subsignal("crs_dv", Pins("D9")),
|
||||
Subsignal("tx_en", Pins("B9")),
|
||||
Subsignal("tx_data", Pins("A10 A8")),
|
||||
Subsignal("mdc", Pins("C9")),
|
||||
Subsignal("mdio", Pins("A9")),
|
||||
Subsignal("rx_er", Pins("C10")),
|
||||
Subsignal("int_n", Pins("B8")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
|
||||
# VGA
|
||||
("vga", 0,
|
||||
Subsignal("hsync_n", Pins("B11")),
|
||||
Subsignal("vsync_n", Pins("B12")),
|
||||
Subsignal("r", Pins("A4 C5 B4 A3")),
|
||||
Subsignal("g", Pins("A6 B6 A5 C6")),
|
||||
Subsignal("b", Pins("D7 C7 B7 D8")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
]
|
||||
|
||||
# Platform -----------------------------------------------------------------------------------------
|
||||
|
||||
class Platform(XilinxPlatform):
|
||||
default_clk_name = "clk100"
|
||||
default_clk_period = 1e9/100e6
|
||||
|
||||
def __init__(self):
|
||||
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, toolchain="vivado")
|
||||
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
|
||||
|
||||
def create_programmer(self):
|
||||
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit")
|
||||
|
||||
def do_finalize(self, fragment):
|
||||
XilinxPlatform.do_finalize(self, fragment)
|
||||
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
|
||||
self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/50e6)
|
||||
@ -0,0 +1,51 @@
|
||||
# Build Targets
|
||||
|
||||
## Litex
|
||||
|
||||
#### Core and wishbone wrapper with extra stuff for Litex integration
|
||||
|
||||
* create a2o/core.py and a2o.py (SOC) from a2p
|
||||
* makes it through vivado compile
|
||||
* cleaned up some various minor rtl warnings
|
||||
* added parm to cmod7 platform to allow replacing the target fpga device; trying arty-200 to see if it fits as-is - no, but can override?
|
||||
|
||||
```
|
||||
ERROR: [DRC UTLZ-1] Resource utilization: Slice LUTs over-utilized in Top Level Design (This design requires more Slice LUTs cells than are available in the target device. This design requires 212846 of such cell types but only 134600 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
|
||||
```
|
||||
|
||||
* try adding ```set drc.disableLUTOverUtilError 1``` to build script and running...
|
||||
```
|
||||
cd build/cmod7/gateware
|
||||
vivado -mode tcl -source cmod7.tcl
|
||||
```
|
||||
|
||||
* doesn't change results
|
||||
* try in gui:
|
||||
```
|
||||
set_property SEVERITY WARNING [get_drc_checks {DRC UTLZ-1}]
|
||||
WARNING: [Vivado 12-4383] DRC UTLZ-1 may not change severity
|
||||
```
|
||||
* do get the synth util report; iu=25% lq=28% xu=12% rv=16% fu=9% mmu=8%
|
||||
|
||||
```
|
||||
+-----------------------------------------+--------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+
|
||||
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks |
|
||||
+-----------------------------------------+--------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+
|
||||
| cmod7 | (top) | 212875 | 210949 | 1924 | 2 | 83329 | 116 | 13 | 0 |
|
||||
| (cmod7) | (top) | 162 | 146 | 16 | 0 | 312 | 20 | 1 | 0 |
|
||||
| a2owb | a2owb | 212713 | 210803 | 1908 | 2 | 83017 | 96 | 12 | 0 |
|
||||
| c0 | c | 212222 | 210312 | 1908 | 2 | 82296 | 96 | 12 | 0 |
|
||||
| fupc | c_fu_pc | 20918 | 20317 | 600 | 1 | 7726 | 0 | 0 | 0 |
|
||||
| iuq0 | iuq | 54334 | 53794 | 540 | 0 | 19339 | 25 | 6 | 0 |
|
||||
| lq0 | lq | 60745 | 60744 | 0 | 1 | 26090 | 49 | 6
|
||||
| mmu0 | mmq | 16032 | 16032 | 0 | 0 | 8151 | 21 |
|
||||
| rv0 | rv | 34548 | 34292 | 256 | 0 | 9989 | 0 | 0 | 0 |
|
||||
| xu0 | xu | 25469 | 24957 | 512 | 0 | 10997 | 1 |
|
||||
| n0 | a2l2wb | 491 | 491 | 0 | 0 | 721 | 0 | 0 | 0 |
|
||||
+-----------------------------------------+--------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+
|
||||
|
||||
```
|
||||
|
||||
* errors to check in source: a lot of critical warnings are vdd vs VCC and gnd vs GND; are these inouts and ties missing?
|
||||
|
||||
|
||||
@ -0,0 +1,19 @@
|
||||
## Current build
|
||||
|
||||
```
|
||||
python3 a2o.py --csr-csv csr.csv --no-compile-software --build
|
||||
```
|
||||
|
||||
```
|
||||
# build and program
|
||||
make c # copy code, build, program
|
||||
make # build and program
|
||||
make p # program only
|
||||
```
|
||||
|
||||
start terminal...
|
||||
|
||||
```
|
||||
# start in separate terminal (if running core uart terminal)
|
||||
python3 litex-install/tools/litex_term.py /dev/ttyUSB0
|
||||
```
|
||||
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Reference in New Issue