assign ex6_load_addr[0:7] = f_fpr_ex6_load_addr[0:7]; // no tid bit
assign ex6_load_addr[0:7] = f_fpr_ex6_load_addr[0:7]; // no tid bit
assign ex6_reload_addr[0:7] = f_fpr_ex6_reload_addr[0:7]; // no tid bit
assign ex6_reload_addr[0:7] = f_fpr_ex6_reload_addr[0:7]; // no tid bit
@ -2135,7 +2135,7 @@ module fu_dcd(
endgenerate
endgenerate
generate
generate
if (THREADS == 2)
if (`THREADS == 2)
begin : dcd_loadaddr_thr_2
begin : dcd_loadaddr_thr_2
assign ex6_load_addr[0:7] = {f_fpr_ex6_load_addr[0], f_fpr_ex6_load_addr[7], f_fpr_ex6_load_addr[1:6]}; // bit 7 is the tid but only in the 2 thread model
assign ex6_load_addr[0:7] = {f_fpr_ex6_load_addr[0], f_fpr_ex6_load_addr[7], f_fpr_ex6_load_addr[1:6]}; // bit 7 is the tid but only in the 2 thread model
assign ex6_reload_addr[0:7] = {f_fpr_ex6_reload_addr[0], f_fpr_ex6_reload_addr[7], f_fpr_ex6_reload_addr[1:6]}; // bit 7 is the tid but only in the 2 thread model
assign ex6_reload_addr[0:7] = {f_fpr_ex6_reload_addr[0], f_fpr_ex6_reload_addr[7], f_fpr_ex6_reload_addr[1:6]}; // bit 7 is the tid but only in the 2 thread model
always @(iu4_stall or buffer_valid_flush or iu4_uc_mode_din or iu4_0_valid_din or iu4_0_instr_din or iu4_0_bta_din or iu4_0_ifar_din or iu4_0_ucode_din or iu4_0_ucode_ext_din or iu4_0_isram_din or iu4_0_fuse_val_din or iu4_0_fuse_data_din or iu4_1_valid_din or iu4_1_instr_din or iu4_1_bta_din or iu4_1_ifar_din or iu4_1_ucode_din or iu4_1_ucode_ext_din or iu4_1_isram_din or iu4_1_fuse_val_din or iu4_1_fuse_data_din or iu4_uc_mode_q or iu4_0_valid_q or iu4_0_instr_q or iu4_0_bta_q or iu4_0_ifar_q or iu4_0_ucode_q or iu4_0_ucode_ext_q or iu4_0_isram_q or iu4_0_fuse_val_q or iu4_0_fuse_data_q or iu4_1_valid_q or iu4_1_instr_q or iu4_1_bta_q or iu4_1_ifar_q or iu4_1_ucode_q or iu4_1_ucode_ext_q or iu4_1_isram_q or iu4_1_fuse_val_q or iu4_1_fuse_data_q)
always @(iu5_vld_q or cp_flush_q or frn_fdec_iu5_stall or iu5_vld_din or iu5_ucode_din or iu5_2ucode_din or iu5_fuse_nop_din or iu5_error_din or iu5_btb_entry_din or iu5_btb_hist_din or iu5_bta_val_din or iu5_fusion_din or iu5_rte_lq_din or iu5_rte_sq_din or iu5_rte_fx0_din or iu5_rte_fx1_din or iu5_rte_axu0_din or iu5_rte_axu1_din or iu5_valop_din or iu5_ord_din or iu5_cord_din or iu5_spec_din or iu5_isram_din or iu5_isload_din or iu5_isstore_din or iu5_instr_din or iu5_ifar_din or iu5_bta_din or iu5_ilat_din or iu5_t1_v_din or iu5_t1_t_din or iu5_t1_a_din or iu5_t2_v_din or iu5_t2_a_din or iu5_t2_t_din or iu5_t3_v_din or iu5_t3_a_din or iu5_t3_t_din or iu5_s1_v_din or iu5_s1_a_din or iu5_s1_t_din or iu5_s2_v_din or iu5_s2_a_din or iu5_s2_t_din or iu5_s3_v_din or iu5_s3_a_din or iu5_s3_t_din or iu5_br_pred_din or iu5_bh_update_din or iu5_bh0_hist_din or iu5_bh1_hist_din or iu5_bh2_hist_din or iu5_gshare_din or iu5_ls_ptr_din or iu5_match_din or iu5_async_block_din or iu5_np1_flush_din or iu5_core_block_din or iu5_type_fp_din or iu5_type_ap_din or iu5_type_spv_din or iu5_type_st_din or iu5_ucode_q or iu5_2ucode_q or iu5_fuse_nop_q or iu5_error_q or iu5_btb_hist_q or iu5_btb_entry_q or iu5_bta_val_q or iu5_fusion_q or iu5_rte_lq_q or iu5_rte_sq_q or iu5_rte_fx0_q or iu5_rte_fx1_q or iu5_rte_axu0_q or iu5_rte_axu1_q or iu5_valop_q or iu5_ord_q or iu5_cord_q or iu5_spec_q or iu5_isram_q or iu5_isload_q or iu5_isstore_q or iu5_instr_q or iu5_ifar_q or iu5_bta_q or iu5_ilat_q or iu5_t1_v_q or iu5_t1_t_q or iu5_t1_a_q or iu5_t2_v_q or iu5_t2_a_q or iu5_t2_t_q or iu5_t3_v_q or iu5_t3_a_q or iu5_t3_t_q or iu5_s1_v_q or iu5_s1_a_q or iu5_s1_t_q or iu5_s2_v_q or iu5_s2_a_q or iu5_s2_t_q or iu5_s3_v_q or iu5_s3_a_q or iu5_s3_t_q or iu5_br_pred_q or iu5_bh_update_q or iu5_bh0_hist_q or iu5_bh1_hist_q or iu5_bh2_hist_q or iu5_gshare_q or iu5_ls_ptr_q or iu5_match_q or iu5_async_block_q or iu5_np1_flush_q or iu5_core_block_q or iu5_type_fp_q or iu5_type_ap_q or iu5_type_spv_q or iu5_type_st_q)
always @(fdec_frn_iu5_i0_t1_v or fdec_frn_iu5_i0_t1_t or fdec_frn_iu5_i1_t1_t or fdec_frn_iu5_i1_t1_a or next_gpr_0 or next_gpr_1 or next_cr_1 or next_cr_0 or au_iu_iu5_i0_t1_p or au_iu_iu5_i1_t1_p)
always @(fdec_frn_iu5_i0_t2_v or fdec_frn_iu5_i0_t2_t or fdec_frn_iu5_i1_t2_t or fdec_frn_iu5_i1_t2_a or next_ctr_1 or next_xer_1 or next_ctr_0 or next_xer_0 or au_iu_iu5_i0_t2_p or au_iu_iu5_i1_t2_p)
always @(fdec_frn_iu5_i0_t3_v or fdec_frn_iu5_i0_t3_t or fdec_frn_iu5_i1_t3_t or fdec_frn_iu5_i1_t3_a or next_lr_1 or next_lr_0 or next_cr_1 or next_cr_0 or fdec_frn_iu5_i0_t1_v or fdec_frn_iu5_i0_t1_t)
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1)
begin : map_set0
begin : map_set0
always @(flush_map or spec_0_wr_val or spec_0_wr_arc or spec_0_wr_rename or spec_1_wr_val or spec_1_wr_arc or spec_1_wr_rename or spec_map_arc_l2[i] or comp_map_l2[i])
always @*
begin: set_spec_map_arc_proc
begin: set_spec_map_arc_proc
spec_map_arc_d[i] = spec_map_arc_l2[i];
spec_map_arc_d[i] = spec_map_arc_l2[i];
if (flush_map == 1'b1)
if (flush_map == 1'b1)
@ -310,7 +310,7 @@ module iuq_rn_map #(
spec_map_arc_d[i] = spec_0_wr_rename;
spec_map_arc_d[i] = spec_0_wr_rename;
end
end
always @(flush_map or spec_0_wr_val or spec_0_wr_arc or spec_0_wr_itag or spec_1_wr_val or spec_1_wr_arc or spec_1_wr_itag or spec_map_itag_l2[i] or comp_0_wr_val or comp_0_wr_itag or comp_1_wr_val or comp_1_wr_itag)
always @(iu4_ov_valid_l2 or iu4_ifar_l2 or iu4_instr0_l2 or iu4_instr1_l2 or iu4_valid_l2 or iu4_ext0_l2 or iu4_ext1_l2 or iu4_done_l2 or iu4_ov_ifar_l2 or iu4_ov_instr0_l2 or iu4_ov_instr1_l2 or iu4_ov_ext0_l2 or iu4_ov_ext1_l2 or iu4_ov_done_l2)
// HTW sequencer for servicing indirect tlb entry hits
// HTW sequencer for servicing indirect tlb entry hits
always @(htw_seq_q or tlb_htw_req_valid_vec or tlb_htw_pte_machines_full or htw_lsu_req_taken)
always @*
begin: Htw_Sequencer
begin: Htw_Sequencer
htw_seq_load_pteaddr = 1'b0;
htw_seq_load_pteaddr = 1'b0;
htw_lsu_req_valid = 1'b0;
htw_lsu_req_valid = 1'b0;
@ -604,7 +604,7 @@ module mmq_htw(
// PTE sequencer for servicing pte data reloads
// PTE sequencer for servicing pte data reloads
always @(pte0_seq_q or pte_load_ptr_q or ptereload_ptr_q or htw_lsu_req_taken or ptereload_req_taken or pte0_score_pending_q or pte0_score_dataval_q or pte0_score_error_q or pte0_score_qwbeat_q or pte0_score_ibit_q)
always @*
begin: Pte0_Sequencer
begin: Pte0_Sequencer
pte0_reload_req_valid = 1'b0;
pte0_reload_req_valid = 1'b0;
pte0_reload_req_taken = 1'b0;
pte0_reload_req_taken = 1'b0;
@ -683,7 +683,7 @@ module mmq_htw(
1'b0;
1'b0;
// PTE sequencer for servicing pte data reloads
// PTE sequencer for servicing pte data reloads
always @(pte1_seq_q or pte_load_ptr_q or ptereload_ptr_q or htw_lsu_req_taken or ptereload_req_taken or pte1_score_pending_q or pte1_score_dataval_q or pte1_score_error_q or pte1_score_qwbeat_q or pte1_score_ibit_q)
//Inv_Sequencer: PROCESS (inv_seq_q, por_seq_q, an_ac_back_inv, an_ac_back_inv_target,
//Inv_Sequencer: PROCESS (inv_seq_q, por_seq_q, an_ac_back_inv, an_ac_back_inv_target,
// ex6_valid_q, ex6_ttype_q)
// ex6_valid_q, ex6_ttype_q)
always @(inv_seq_q or xu_mm_lmq_stq_empty or iu_mm_lmq_empty or hold_ack_q or lsu_tokens_q or xu_mm_ccr2_notlb_q[0] or snoop_ack_q or ex6_valid_q or ex6_ttype_q[0:3] or ex6_ind_q or ex6_isel_q or bus_snoop_seq_ready or mmucsr0_tlb0fi or tlbwe_back_inv_q[`MM_THREADS+1] or an_ac_back_inv_q[6] or an_ac_back_inv_addr_q[54:55] or htw_lsu_req_valid or lsu_req_q or cswitch_q[0:1] or cswitch_q[3] or power_managed_q[0] or power_managed_q[2] or power_managed_q[3])
always @*
begin: Inv_Sequencer
begin: Inv_Sequencer
inv_seq_idle = 1'b0;
inv_seq_idle = 1'b0;
inv_seq_snoop_inprogress = 1'b0;
inv_seq_snoop_inprogress = 1'b0;
@ -1441,7 +1441,7 @@ module mmq_inval(
hold_ack_q[1];
hold_ack_q[1];
`endif
`endif
always @(bus_snoop_seq_q or inval_snoop_forme or bus_snoop_hold_ack_q or inv_seq_snoop_done or power_managed_q)
openpowerwtf
2 years ago