pd
openpowerwtf
parent 1cefef0726
commit 200551679c

@ -86,6 +86,7 @@ module tri_144x78_2r4w(
input [64-`GPR_WIDTH:77] w_data_in_4 input [64-`GPR_WIDTH:77] w_data_in_4
); );


wire unused;
// sim array // sim array
reg [64-`GPR_WIDTH:77] mem[0:143]; reg [64-`GPR_WIDTH:77] mem[0:143];



@ -27,7 +27,7 @@ module bram_model (DIA, DIB, ENA, ENB, WEA, WEB, SSRA, SSRB, CLKA, CLKB, ADDRA,
initial begin initial begin
integer i; integer i;
for (i = 0; i < 2**addr_w; i = i + 1) for (i = 0; i < 2**addr_w; i = i + 1)
MEM[i] <= 0; MEM[i] = 0;
end end


always @(posedge CLKA, posedge CLKB) begin: BRAM_MODEL always @(posedge CLKA, posedge CLKB) begin: BRAM_MODEL

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