68 lines
2.3 KiB
Verilog
68 lines
2.3 KiB
Verilog
3 years ago
|
// © IBM Corp. 2020
|
||
|
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
|
||
|
// the terms below; you may not use the files in this repository except in
|
||
|
// compliance with the License as modified.
|
||
|
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
|
||
|
//
|
||
|
// Modified Terms:
|
||
|
//
|
||
|
// 1) For the purpose of the patent license granted to you in Section 3 of the
|
||
|
// License, the "Work" hereby includes implementations of the work of authorship
|
||
|
// in physical form.
|
||
|
//
|
||
|
// 2) Notwithstanding any terms to the contrary in the License, any licenses
|
||
|
// necessary for implementation of the Work that are available from OpenPOWER
|
||
|
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
|
||
|
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
|
||
|
// of the EULA.
|
||
|
//
|
||
|
// Unless required by applicable law or agreed to in writing, the reference design
|
||
|
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||
|
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
|
||
|
// for the specific language governing permissions and limitations under the License.
|
||
|
//
|
||
|
// Additional rights, including the ability to physically implement a softcore that
|
||
|
// is compliant with the required sections of the Power ISA Specification, are
|
||
|
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
|
||
|
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
|
||
|
|
||
|
// Description: XU Multiplier Top
|
||
|
//
|
||
|
//*****************************************************************************
|
||
|
|
||
|
`timescale 1 ns / 1 ns
|
||
|
|
||
|
module tri_bthmx(x, sneg, sx, sx2, right, left, q, vd, gd);
|
||
|
|
||
|
input x;
|
||
|
input sneg;
|
||
|
input sx;
|
||
|
input sx2;
|
||
|
input right;
|
||
|
output left;
|
||
|
output q;
|
||
|
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
|
||
|
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
|
||
|
inout vd;
|
||
|
(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
|
||
|
(* ANALYSIS_NOT_REFERENCED="TRUE" *)
|
||
|
inout gd;
|
||
|
|
||
|
|
||
|
|
||
|
wire center, xn, spos;
|
||
|
|
||
|
assign xn = ~x;
|
||
|
assign spos = ~sneg;
|
||
|
|
||
|
assign center = ~(( xn & spos ) |
|
||
|
( x & sneg ));
|
||
|
|
||
|
assign left = center; // output
|
||
|
|
||
|
|
||
|
assign q = ( center & sx ) |
|
||
|
( right & sx2 ) ;
|
||
|
|
||
|
endmodule
|