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87 lines
2.6 KiB
Verilog
87 lines
2.6 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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module tri_csa42(
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a,
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b,
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c,
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d,
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ki,
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ko,
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car,
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sum,
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vd,
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gd
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);
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input a;
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input b;
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input c;
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input d;
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input ki;
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output ko;
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output car;
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output sum;
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(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
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(* ANALYSIS_NOT_REFERENCED="TRUE" *)
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inout vd;
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(* ANALYSIS_NOT_ASSIGNED="TRUE" *)
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(* ANALYSIS_NOT_REFERENCED="TRUE" *)
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inout gd;
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wire s1;
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wire carn1;
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wire carn2;
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wire carn3;
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wire kon1;
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wire kon2;
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wire kon3;
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// assign s1 = b ^ c ^ d;
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tri_xor3 CSA42_XOR3_1(s1,b,c,d);
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// assign sum = s1 ^ a ^ ki;
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tri_xor3 CSA42_XOR3_2(sum,s1,a,ki);
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// assign car = (s1 & a) | (s1 & ki) | (a & ki);
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tri_nand2 CSA42_NAND2_1(carn1,s1,a);
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tri_nand2 CSA42_NAND2_2(carn2,s1,ki);
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tri_nand2 CSA42_NAND2_3(carn3,a,ki);
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tri_nand3 CSA42_NAND3_4(car,carn1,carn2,carn3);
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// assign ko = (b & c) | (b & d) | (c & d);
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tri_nand2 CSA42_NAND2_5(kon1,b,c);
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tri_nand2 CSA42_NAND2_6(kon2,b,d);
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tri_nand2 CSA42_NAND2_7(kon3,c,d);
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tri_nand3 CSA42_NAND3_8(ko,kon1,kon2,kon3);
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endmodule
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