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15 lines
265 B
Verilog
15 lines
265 B
Verilog
3 years ago
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(* blackbox *)
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module RAM64X1D #(
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parameter [63:0] INIT = 64'h0
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)
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(
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5,
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input D,
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output SPO,
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output DPO
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);
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endmodule
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