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61 lines
2.1 KiB
Verilog
61 lines
2.1 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: Prioritizer
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//
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//*****************************************************************************
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module tri_agecmp(
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a,
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b,
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a_newer_b
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);
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parameter SIZE = 8;
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input [0:SIZE-1] a;
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input [0:SIZE-1] b;
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output a_newer_b;
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// tri_agecmp
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wire a_lt_b;
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wire a_gte_b;
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wire cmp_sel;
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assign a_lt_b = (a[1:SIZE - 1] < b[1:SIZE - 1]) ? 1'b1 :
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1'b0;
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assign a_gte_b = (~a_lt_b);
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assign cmp_sel = a[0] ~^ b[0];
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assign a_newer_b = (a_lt_b & (~cmp_sel)) | (a_gte_b & cmp_sel);
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endmodule
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