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# RTL Notes
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### set up ERAT autoload at reset
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* iuq_ic_ierat and lq_derat, bcfg_q (2 entries I & D)
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```
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//------------------------------------------------
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// scan only latches for boot config
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//------------------------------------------------
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// epn rpn u0:3 E
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// 0 31 32 51 52 54 61 62 81 86
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// 0 31 32 51 22 24 31 32 51
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//init => "0000_0000_0000_0000_0000_0000_0000_0000_1111_1111_1111_1111_1111_11_1111_1111_1111_1111_1111_1111_1111_0000_0",
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```
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### special rings
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* tri_slat_scan's seem to be the comps used for core config and boot config
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### reg bits
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* erat-only
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* These two modes are termed “MMU mode” and “ERAT-only mode”. This mode controlled by the CCR2[NOTLB] bit.
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* mmu may be configurable to table-walk but not have a TLB(?) This would allow the erats and htw to be changed for radix before implementing
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the TLB logic.
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### translation
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* ERAT holes (UM 6.2.3)
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The rules for configuring an exclusion range “hole” for a given TLB entry and placing one or more pages
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within the “hole” are as follows:
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1. Only TLB entries with page sizes greater than 4 KB can have an exclusion range hole enabled via X = 1.
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2. A virtual address to be translated that falls within the hole will not match this TLB entry.
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3. The size of the hole configured must be smaller than the page size of this TLB entry.
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4. The size of the hole is configurable to 2 n 4 KB, where n = 0 to log 2 (entry size in bytes) - 13.
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5. The legal binary values of the unused EPN bits of a given TLB entry are contained in the set defined by
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2 n - 1, where n = 0 to log 2 (entry size in bytes) - 13.
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6. Other TLB entries of valid page sizes (less than or equal to the hole size) can be mapped into the hole.
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7. Multiple other TLB entries can be mapped into the hole simultaneously.
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8. Not all of the address space defined by the hole needs to be mapped by other entries.
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9. Pages mapped in the hole must be page-size aligned.
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10. Pages mapped in the hole must not overlap.
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11. Pages mapped in the hole must be collectively fully contained within the hole.
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* Page sizes
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* UM 6.17.3 says
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> Supported values of the PS field for this implementation include:
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0b0010 (4 KB for sub-page size of 4 KB only), 0b0110 (64 KB), 0b1010 (1 MB), and
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0b1110 (16 MB).
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Is this correct? No 1G size? The logic (iuq_ic_ierat) says:
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```
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parameter [0:2] CAM_PgSize_1GB = 3'b110;
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parameter [0:2] CAM_PgSize_16MB = 3'b111;
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parameter [0:2] CAM_PgSize_1MB = 3'b101;
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parameter [0:2] CAM_PgSize_64KB = 3'b011;
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parameter [0:2] CAM_PgSize_4KB = 3'b001;
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```
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* UM also says:
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>Variable page sizes for direct (IND=0) entries (4KB, 64KB, 1MB, 16MB, 1GB), simultaneously resi-
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dent in TLB and/or ERAT, and indirect (IND=1) entries (1 MB and 256 MB) in TLB
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>The MMU divides the address space into pages. Five direct (IND=0) page sizes (4KB, 64KB, 1MB, 16MB,
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1GB) are simultaneously supported,
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### implementing radix
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Possible:
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1. toss all of MMU and rewrite using MMU interface; update ERAT entries as necessary
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2. keep everything and change HTW/TLB for radix (plus ERATs)
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3. do in steps; get ERATS+HTW working and then add TLB logic
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