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452 lines
21 KiB
Verilog
452 lines
21 KiB
Verilog
2 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//
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// Description: XU LSU L1 Data Directory Tag Array
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//
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//*****************************************************************************
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// ##########################################################################################
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// Tag Compare
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// 1) Contains an Array of Tags
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// 2) Updates Tag on Reload
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// ##########################################################################################
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module lq_dir_tag_arr(
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wdata,
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dir_arr_rd_data0,
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dir_arr_rd_data1,
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inj_ddir_p0_parity,
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inj_ddir_p1_parity,
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dir_arr_wr_data,
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p0_way_tag_a,
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p0_way_tag_b,
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p0_way_tag_c,
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p0_way_tag_d,
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p0_way_tag_e,
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p0_way_tag_f,
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p0_way_tag_g,
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p0_way_tag_h,
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p1_way_tag_a,
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p1_way_tag_b,
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p1_way_tag_c,
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p1_way_tag_d,
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p1_way_tag_e,
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p1_way_tag_f,
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p1_way_tag_g,
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p1_way_tag_h,
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p0_way_par_a,
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p0_way_par_b,
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p0_way_par_c,
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p0_way_par_d,
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p0_way_par_e,
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p0_way_par_f,
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p0_way_par_g,
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p0_way_par_h,
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p0_par_err_det_a,
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p0_par_err_det_b,
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p0_par_err_det_c,
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p0_par_err_det_d,
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p0_par_err_det_e,
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p0_par_err_det_f,
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p0_par_err_det_g,
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p0_par_err_det_h,
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p1_par_err_det_a,
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p1_par_err_det_b,
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p1_par_err_det_c,
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p1_par_err_det_d,
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p1_par_err_det_e,
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p1_par_err_det_f,
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p1_par_err_det_g,
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p1_par_err_det_h
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);
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//-------------------------------------------------------------------
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// Generics
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//-------------------------------------------------------------------
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parameter WAYDATASIZE = 34; // TagSize + Parity Bits
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parameter PARBITS = 4; // Parity Bits
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// Write Path
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input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] wdata;
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// Directory Array Read Data
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input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data0;
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input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data1;
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// Parity Error Injection
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input inj_ddir_p0_parity;
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input inj_ddir_p1_parity;
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// Directory Array Write Controls
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output [64-`REAL_IFAR_WIDTH:64-`REAL_IFAR_WIDTH+WAYDATASIZE-1] dir_arr_wr_data;
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// Way Tag Data
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_a;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_b;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_c;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_d;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_e;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_f;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_g;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p0_way_tag_h;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_a;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_b;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_c;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_d;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_e;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_f;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_g;
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output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] p1_way_tag_h;
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// Way Tag Parity
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output [0:PARBITS-1] p0_way_par_a;
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output [0:PARBITS-1] p0_way_par_b;
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output [0:PARBITS-1] p0_way_par_c;
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output [0:PARBITS-1] p0_way_par_d;
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output [0:PARBITS-1] p0_way_par_e;
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output [0:PARBITS-1] p0_way_par_f;
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output [0:PARBITS-1] p0_way_par_g;
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output [0:PARBITS-1] p0_way_par_h;
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// Parity Error Detected
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output p0_par_err_det_a;
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output p0_par_err_det_b;
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output p0_par_err_det_c;
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output p0_par_err_det_d;
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output p0_par_err_det_e;
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output p0_par_err_det_f;
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output p0_par_err_det_g;
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output p0_par_err_det_h;
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output p1_par_err_det_a;
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output p1_par_err_det_b;
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output p1_par_err_det_c;
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output p1_par_err_det_d;
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output p1_par_err_det_e;
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output p1_par_err_det_f;
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output p1_par_err_det_g;
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output p1_par_err_det_h;
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//--------------------------
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// components
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//--------------------------
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//--------------------------
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// constants
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//--------------------------
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parameter uprTagBit = 64 - `REAL_IFAR_WIDTH;
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parameter lwrTagBit = 63 - (`DC_SIZE - 3);
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parameter tagSize = lwrTagBit - uprTagBit + 1;
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parameter numWays = 8;
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//--------------------------
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// signals
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//--------------------------
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wire [uprTagBit:lwrTagBit] wr_data;
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wire [uprTagBit:lwrTagBit] p0_rd_way[0:numWays-1];
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wire [uprTagBit:lwrTagBit] p1_rd_way[0:numWays-1];
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wire [0:(8*WAYDATASIZE)-1] arr_rd_data0;
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wire [0:(8*WAYDATASIZE)-1] arr_rd_data1;
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wire [0:PARBITS-1] arr_parity;
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wire [0:7] extra_byte_par;
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wire [uprTagBit:lwrTagBit+PARBITS] arr_wr_data;
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wire [0:PARBITS-1] p0_rd_par_arr;
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wire [0:PARBITS-1] p1_rd_par_arr;
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wire [0:PARBITS-1] p0_rd_par[0:numWays-1];
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wire [0:PARBITS-1] p1_rd_par[0:numWays-1];
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wire [0:7] p0_extra_tag_par[0:numWays-1];
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wire [0:7] p1_extra_tag_par[0:numWays-1];
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wire [0:PARBITS-1] p0_par_err_det[0:numWays-1];
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wire [0:PARBITS-1] p1_par_err_det[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p0_par_gen_1stlvla[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p0_par_gen_1stlvlb[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p0_par_gen_1stlvlc[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p0_par_gen_1stlvld[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p0_parity_gen_1b[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p0_parity_gen_2b[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p1_par_gen_1stlvla[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p1_par_gen_1stlvlb[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p1_par_gen_1stlvlc[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p1_par_gen_1stlvld[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p1_parity_gen_1b[0:numWays-1];
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(* NO_MODIFICATION="TRUE" *)
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wire [0:PARBITS-1] p1_parity_gen_2b[0:numWays-1];
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// ####################################################
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// Inputs
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// ####################################################
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assign arr_rd_data0 = dir_arr_rd_data0;
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assign arr_rd_data1 = dir_arr_rd_data1;
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assign wr_data = wdata;
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// ####################################################
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// Array Parity Generation
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// ####################################################
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generate begin : extra_byte
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genvar t;
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for (t = 0; t <= 7; t = t + 1) begin : extra_byte
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if (t < (tagSize % 8)) begin : R0
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assign extra_byte_par[t] = wr_data[uprTagBit+(8*(tagSize/8)) + t];
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end
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if (t >= (tagSize % 8)) begin : R1
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assign extra_byte_par[t] = 1'b0;
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end
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end
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end
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endgenerate
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generate begin : par_gen
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genvar i;
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for (i = 0; i <= (tagSize/8) - 1; i = i + 1) begin : par_gen
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assign arr_parity[i] = ^(wr_data[8*i+uprTagBit:8*i+uprTagBit+7]);
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end
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end
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endgenerate
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generate
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if ((tagSize % 8) != 0) begin : par_gen_x
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assign arr_parity[tagSize/8] = ^(extra_byte_par);
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end
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endgenerate
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assign arr_wr_data = {wr_data, arr_parity};
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// ####################################################
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// Tag Array Read
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// ####################################################
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generate begin : tagRead
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genvar way;
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for (way=0; way<numWays; way=way+1) begin : tagRead
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assign p0_rd_way[way] = arr_rd_data0[(way*WAYDATASIZE):(way*WAYDATASIZE) + tagSize - 1];
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assign p1_rd_way[way] = arr_rd_data1[(way*WAYDATASIZE):(way*WAYDATASIZE) + tagSize - 1];
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if (way == 0) begin :injErr
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assign p0_rd_par_arr = arr_rd_data0[(way*WAYDATASIZE) + tagSize:(way*WAYDATASIZE) + tagSize + PARBITS - 1];
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assign p0_rd_par[way] = {(p0_rd_par_arr[0] ^ inj_ddir_p0_parity), p0_rd_par_arr[1:PARBITS - 1]};
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assign p1_rd_par_arr = arr_rd_data1[(way*WAYDATASIZE) + tagSize:(way*WAYDATASIZE) + tagSize + PARBITS - 1];
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assign p1_rd_par[way] = {(p1_rd_par_arr[0] ^ inj_ddir_p1_parity), p1_rd_par_arr[1:PARBITS - 1]};
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end
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if (way != 0) begin :noErr
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assign p0_rd_par[way] = arr_rd_data0[(way*WAYDATASIZE) + tagSize:(way*WAYDATASIZE) + tagSize + PARBITS - 1];
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assign p1_rd_par[way] = arr_rd_data1[(way*WAYDATASIZE) + tagSize:(way*WAYDATASIZE) + tagSize + PARBITS - 1];
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end
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end
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end
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endgenerate
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// ####################################################
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// Tag Parity Generation
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// ####################################################
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generate begin : rdExtraByte
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genvar way;
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for (way=0; way<numWays; way=way+1) begin : rdExtraByte
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genvar t;
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for (t=0; t<8; t=t+1) begin : rdExtraByte
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if (t < (tagSize % 8)) begin : R0
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assign p0_extra_tag_par[way][t] = p0_rd_way[way][uprTagBit + (8 * (tagSize/8)) + t];
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assign p1_extra_tag_par[way][t] = p1_rd_way[way][uprTagBit + (8 * (tagSize/8)) + t];
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end
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if (t >= (tagSize % 8)) begin : R1
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assign p0_extra_tag_par[way][t] = 1'b0;
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assign p1_extra_tag_par[way][t] = 1'b0;
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end
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end
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end
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end
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endgenerate
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generate begin : rdParGen
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genvar way;
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for (way=0; way<numWays; way=way+1) begin : rdParGen
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genvar i;
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for (i = 0; i <= (tagSize/8) - 1; i = i + 1) begin : rdParGen
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// Port 0
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//assign p0_par_gen_1stlvla[way][i] = (~(p0_rd_way[way][8 * i + uprTagBit + 0] ^ p0_rd_way[way][8 * i + uprTagBit + 1]));
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tri_xnor2 p0_par_gen_1stlvla_0 (.y(p0_par_gen_1stlvla[way][i]), .a(p0_rd_way[way][8*i + uprTagBit+0]), .b(p0_rd_way[way][8*i + uprTagBit+1]));
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//assign p0_par_gen_1stlvlb[way][i] = (~(p0_rd_way[way][8 * i + uprTagBit + 2] ^ p0_rd_way[way][8 * i + uprTagBit + 3]));
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tri_xnor2 p0_par_gen_1stlvlb_0 (.y(p0_par_gen_1stlvlb[way][i]), .a(p0_rd_way[way][8*i + uprTagBit+2]), .b(p0_rd_way[way][8*i + uprTagBit+3]));
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//assign p0_par_gen_1stlvlc[way][i] = (~(p0_rd_way[way][8 * i + uprTagBit + 4] ^ p0_rd_way[way][8 * i + uprTagBit + 5]));
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tri_xnor2 p0_par_gen_1stlvlc_0 (.y(p0_par_gen_1stlvlc[way][i]), .a(p0_rd_way[way][8*i + uprTagBit+4]), .b(p0_rd_way[way][8*i + uprTagBit+5]));
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//assign p0_par_gen_1stlvld[way][i] = (~(p0_rd_way[way][8 * i + uprTagBit + 6] ^ p0_rd_way[way][8 * i + uprTagBit + 7]));
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tri_xnor2 p0_par_gen_1stlvld_0 (.y(p0_par_gen_1stlvld[way][i]), .a(p0_rd_way[way][8*i + uprTagBit+6]), .b(p0_rd_way[way][8*i + uprTagBit+7]));
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//assign p0_parity_gen_1b[way][i] = (~(p0_par_gen_1stlvla[way][i] ^ p0_par_gen_1stlvlb[way][i]));
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tri_xnor2 p0_parity_gen_1b_0 (.y(p0_parity_gen_1b[way][i]), .a(p0_par_gen_1stlvla[way][i]), .b(p0_par_gen_1stlvlb[way][i]));
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//assign p0_parity_gen_2b[way][i] = (~(p0_par_gen_1stlvlc[way][i] ^ p0_par_gen_1stlvld[way][i]));
|
||
|
tri_xnor2 p0_parity_gen_2b_0 (.y(p0_parity_gen_2b[way][i]), .a(p0_par_gen_1stlvlc[way][i]), .b(p0_par_gen_1stlvld[way][i]));
|
||
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|
||
|
// Port 1
|
||
|
//assign p1_par_gen_1stlvla[way][i] = (~(p1_rd_way[way][8 * i + uprTagBit + 0] ^ p1_rd_way[way][8 * i + uprTagBit + 1]));
|
||
|
tri_xnor2 p1_par_gen_1stlvla_0 (.y(p1_par_gen_1stlvla[way][i]), .a(p1_rd_way[way][8*i + uprTagBit+0]), .b(p1_rd_way[way][8*i + uprTagBit+1]));
|
||
|
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||
|
//assign p1_par_gen_1stlvlb[way][i] = (~(p1_rd_way[way][8 * i + uprTagBit + 2] ^ p1_rd_way[way][8 * i + uprTagBit + 3]));
|
||
|
tri_xnor2 p1_par_gen_1stlvlb_0 (.y(p1_par_gen_1stlvlb[way][i]), .a(p1_rd_way[way][8*i + uprTagBit+2]), .b(p1_rd_way[way][8*i + uprTagBit+3]));
|
||
|
|
||
|
//assign p1_par_gen_1stlvlc[way][i] = (~(p1_rd_way[way][8 * i + uprTagBit + 4] ^ p1_rd_way[way][8 * i + uprTagBit + 5]));
|
||
|
tri_xnor2 p1_par_gen_1stlvlc_0 (.y(p1_par_gen_1stlvlc[way][i]), .a(p1_rd_way[way][8*i + uprTagBit+4]), .b(p1_rd_way[way][8*i + uprTagBit+5]));
|
||
|
|
||
|
//assign p1_par_gen_1stlvld[way][i] = (~(p1_rd_way[way][8 * i + uprTagBit + 6] ^ p1_rd_way[way][8 * i + uprTagBit + 7]));
|
||
|
tri_xnor2 p1_par_gen_1stlvld_0 (.y(p1_par_gen_1stlvld[way][i]), .a(p1_rd_way[way][8*i + uprTagBit+6]), .b(p1_rd_way[way][8*i + uprTagBit+7]));
|
||
|
|
||
|
//assign p1_parity_gen_1b[way][i] = (~(p1_par_gen_1stlvla[way][i] ^ p1_par_gen_1stlvlb[way][i]));
|
||
|
tri_xnor2 p1_parity_gen_1b_0 (.y(p1_parity_gen_1b[way][i]), .a(p1_par_gen_1stlvla[way][i]), .b(p1_par_gen_1stlvlb[way][i]));
|
||
|
|
||
|
//assign p1_parity_gen_2b[way][i] = (~(p1_par_gen_1stlvlc[way][i] ^ p1_par_gen_1stlvld[way][i]));
|
||
|
tri_xnor2 p1_parity_gen_2b_0 (.y(p1_parity_gen_2b[way][i]), .a(p1_par_gen_1stlvlc[way][i]), .b(p1_par_gen_1stlvld[way][i]));
|
||
|
end
|
||
|
end
|
||
|
end
|
||
|
endgenerate
|
||
|
|
||
|
generate
|
||
|
if ((tagSize % 8) != 0) begin : rdParGenx
|
||
|
genvar way;
|
||
|
for (way=0; way<numWays; way=way+1) begin : rdParGenx
|
||
|
|
||
|
// Port 0
|
||
|
assign p0_par_gen_1stlvla[way][PARBITS - 1] = (~(p0_extra_tag_par[way][0] ^ p0_extra_tag_par[way][1]));
|
||
|
assign p0_par_gen_1stlvlb[way][PARBITS - 1] = (~(p0_extra_tag_par[way][2] ^ p0_extra_tag_par[way][3]));
|
||
|
assign p0_par_gen_1stlvlc[way][PARBITS - 1] = (~(p0_extra_tag_par[way][4] ^ p0_extra_tag_par[way][5]));
|
||
|
assign p0_par_gen_1stlvld[way][PARBITS - 1] = (~(p0_extra_tag_par[way][6] ^ p0_extra_tag_par[way][7]));
|
||
|
assign p0_parity_gen_1b[way][PARBITS - 1] = (~(p0_par_gen_1stlvla[way][PARBITS - 1] ^ p0_par_gen_1stlvlb[way][PARBITS - 1]));
|
||
|
assign p0_parity_gen_2b[way][PARBITS - 1] = (~(p0_par_gen_1stlvlc[way][PARBITS - 1] ^ p0_par_gen_1stlvld[way][PARBITS - 1]));
|
||
|
|
||
|
// Port 1
|
||
|
assign p1_par_gen_1stlvla[way][PARBITS - 1] = (~(p1_extra_tag_par[way][0] ^ p1_extra_tag_par[way][1]));
|
||
|
assign p1_par_gen_1stlvlb[way][PARBITS - 1] = (~(p1_extra_tag_par[way][2] ^ p1_extra_tag_par[way][3]));
|
||
|
assign p1_par_gen_1stlvlc[way][PARBITS - 1] = (~(p1_extra_tag_par[way][4] ^ p1_extra_tag_par[way][5]));
|
||
|
assign p1_par_gen_1stlvld[way][PARBITS - 1] = (~(p1_extra_tag_par[way][6] ^ p1_extra_tag_par[way][7]));
|
||
|
assign p1_parity_gen_1b[way][PARBITS - 1] = (~(p1_par_gen_1stlvla[way][PARBITS - 1] ^ p1_par_gen_1stlvlb[way][PARBITS - 1]));
|
||
|
assign p1_parity_gen_2b[way][PARBITS - 1] = (~(p1_par_gen_1stlvlc[way][PARBITS - 1] ^ p1_par_gen_1stlvld[way][PARBITS - 1]));
|
||
|
end
|
||
|
end
|
||
|
endgenerate
|
||
|
|
||
|
// ####################################################
|
||
|
// Parity Error Detect
|
||
|
// ####################################################
|
||
|
|
||
|
generate begin : parDet
|
||
|
genvar way;
|
||
|
for (way=0; way<numWays; way=way+1) begin : parDet
|
||
|
assign p0_par_err_det[way] = p0_parity_gen_1b[way] ^ p0_parity_gen_2b[way] ^ p0_rd_par[way];
|
||
|
assign p1_par_err_det[way] = p1_parity_gen_1b[way] ^ p1_parity_gen_2b[way] ^ p1_rd_par[way];
|
||
|
end
|
||
|
end
|
||
|
endgenerate
|
||
|
|
||
|
// ####################################################
|
||
|
// Outputs
|
||
|
// ####################################################
|
||
|
|
||
|
// Directory Array Write Data
|
||
|
assign dir_arr_wr_data = arr_wr_data;
|
||
|
|
||
|
// Directory Array Read Tags
|
||
|
assign p0_way_tag_a = p0_rd_way[0];
|
||
|
assign p0_way_tag_b = p0_rd_way[1];
|
||
|
assign p0_way_tag_c = p0_rd_way[2];
|
||
|
assign p0_way_tag_d = p0_rd_way[3];
|
||
|
assign p0_way_tag_e = p0_rd_way[4];
|
||
|
assign p0_way_tag_f = p0_rd_way[5];
|
||
|
assign p0_way_tag_g = p0_rd_way[6];
|
||
|
assign p0_way_tag_h = p0_rd_way[7];
|
||
|
assign p1_way_tag_a = p1_rd_way[0];
|
||
|
assign p1_way_tag_b = p1_rd_way[1];
|
||
|
assign p1_way_tag_c = p1_rd_way[2];
|
||
|
assign p1_way_tag_d = p1_rd_way[3];
|
||
|
assign p1_way_tag_e = p1_rd_way[4];
|
||
|
assign p1_way_tag_f = p1_rd_way[5];
|
||
|
assign p1_way_tag_g = p1_rd_way[6];
|
||
|
assign p1_way_tag_h = p1_rd_way[7];
|
||
|
|
||
|
// Directory Array Read Parity
|
||
|
assign p0_way_par_a = p0_rd_par[0];
|
||
|
assign p0_way_par_b = p0_rd_par[1];
|
||
|
assign p0_way_par_c = p0_rd_par[2];
|
||
|
assign p0_way_par_d = p0_rd_par[3];
|
||
|
assign p0_way_par_e = p0_rd_par[4];
|
||
|
assign p0_way_par_f = p0_rd_par[5];
|
||
|
assign p0_way_par_g = p0_rd_par[6];
|
||
|
assign p0_way_par_h = p0_rd_par[7];
|
||
|
|
||
|
// Directory Parity Error Detected
|
||
|
assign p0_par_err_det_a = |(p0_par_err_det[0]);
|
||
|
assign p0_par_err_det_b = |(p0_par_err_det[1]);
|
||
|
assign p0_par_err_det_c = |(p0_par_err_det[2]);
|
||
|
assign p0_par_err_det_d = |(p0_par_err_det[3]);
|
||
|
assign p0_par_err_det_e = |(p0_par_err_det[4]);
|
||
|
assign p0_par_err_det_f = |(p0_par_err_det[5]);
|
||
|
assign p0_par_err_det_g = |(p0_par_err_det[6]);
|
||
|
assign p0_par_err_det_h = |(p0_par_err_det[7]);
|
||
|
assign p1_par_err_det_a = |(p1_par_err_det[0]);
|
||
|
assign p1_par_err_det_b = |(p1_par_err_det[1]);
|
||
|
assign p1_par_err_det_c = |(p1_par_err_det[2]);
|
||
|
assign p1_par_err_det_d = |(p1_par_err_det[3]);
|
||
|
assign p1_par_err_det_e = |(p1_par_err_det[4]);
|
||
|
assign p1_par_err_det_f = |(p1_par_err_det[5]);
|
||
|
assign p1_par_err_det_g = |(p1_par_err_det[6]);
|
||
|
assign p1_par_err_det_h = |(p1_par_err_det[7]);
|
||
|
|
||
|
endmodule
|