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177 lines
7.3 KiB
Verilog
177 lines
7.3 KiB
Verilog
2 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// Description: Adder Component
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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// input phase is importent
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// (change X (B) by switching xor/xnor )
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module tri_st_add_loc(
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g01_b,
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t01_b,
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sum_0,
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sum_1
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);
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input [0:7] g01_b; // after xor
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input [0:7] t01_b;
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output [0:7] sum_0;
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output [0:7] sum_1;
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wire [0:7] g01_t;
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wire [0:7] g01_not;
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wire [0:7] z01_b;
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wire [0:7] p01;
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wire [0:7] p01_b;
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wire [0:7] g02;
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wire [0:7] t02;
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wire [0:7] g04_b;
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wire [0:7] t04_b;
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wire [0:7] g08;
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wire [0:7] t08;
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(* ANALYSIS_NOT_REFERENCED="<0>TRUE" *)
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wire [0:7] g08_b;
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(* ANALYSIS_NOT_REFERENCED="<0>TRUE" *)
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wire [0:7] t08_b;
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//####################################################################
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//# funny way to make xor
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//####################################################################
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assign g01_t[0:7] = (~g01_b[0:7]); //small (buffer off)
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assign g01_not[0:7] = (~g01_t[0:7]); //small (buffer off)
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assign z01_b[0:7] = (~t01_b[0:7]);
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assign p01_b[0:7] = (~(g01_not[0:7] & z01_b[0:7]));
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assign p01[0:7] = (~(p01_b[0:7]));
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//####################################################################
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//# conditional sums // may need to make NON-xor implementation
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//####################################################################
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//xx u_sum_0: sum_0(0 to 7) <= not( p01_b(0 to 7) xor g08(0 to 7) ); --output--
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//xx u_sum_1: sum_1(0 to 7) <= not( p01_b(0 to 7) xor t08(0 to 7) ); --output--
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assign g08_b[0] = (~g08[0]);
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assign g08_b[1] = (~g08[1]);
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assign g08_b[2] = (~g08[2]);
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assign g08_b[3] = (~g08[3]);
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assign g08_b[4] = (~g08[4]);
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assign g08_b[5] = (~g08[5]);
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assign g08_b[6] = (~g08[6]);
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assign g08_b[7] = (~g08[7]);
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assign t08_b[0] = (~t08[0]);
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assign t08_b[1] = (~t08[1]);
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assign t08_b[2] = (~t08[2]);
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assign t08_b[3] = (~t08[3]);
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assign t08_b[4] = (~t08[4]);
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assign t08_b[5] = (~t08[5]);
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assign t08_b[6] = (~t08[6]);
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assign t08_b[7] = (~t08[7]);
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assign sum_0[0] = (~((p01[0] & g08[1]) | (p01_b[0] & g08_b[1]))); //output--
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assign sum_0[1] = (~((p01[1] & g08[2]) | (p01_b[1] & g08_b[2]))); //output--
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assign sum_0[2] = (~((p01[2] & g08[3]) | (p01_b[2] & g08_b[3]))); //output--
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assign sum_0[3] = (~((p01[3] & g08[4]) | (p01_b[3] & g08_b[4]))); //output--
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assign sum_0[4] = (~((p01[4] & g08[5]) | (p01_b[4] & g08_b[5]))); //output--
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assign sum_0[5] = (~((p01[5] & g08[6]) | (p01_b[5] & g08_b[6]))); //output--
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assign sum_0[6] = (~((p01[6] & g08[7]) | (p01_b[6] & g08_b[7]))); //output--
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assign sum_0[7] = (~(p01_b[7])); //output--
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assign sum_1[0] = (~((p01[0] & t08[1]) | (p01_b[0] & t08_b[1]))); //output--
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assign sum_1[1] = (~((p01[1] & t08[2]) | (p01_b[1] & t08_b[2]))); //output--
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assign sum_1[2] = (~((p01[2] & t08[3]) | (p01_b[2] & t08_b[3]))); //output--
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assign sum_1[3] = (~((p01[3] & t08[4]) | (p01_b[3] & t08_b[4]))); //output--
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assign sum_1[4] = (~((p01[4] & t08[5]) | (p01_b[4] & t08_b[5]))); //output--
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assign sum_1[5] = (~((p01[5] & t08[6]) | (p01_b[5] & t08_b[6]))); //output--
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assign sum_1[6] = (~((p01[6] & t08[7]) | (p01_b[6] & t08_b[7]))); //output--
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assign sum_1[7] = (~(p01[7])); //output--
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//####################################################################
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//# local carry
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//####################################################################
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assign g02[0] = (~(g01_b[0] & (t01_b[0] | g01_b[1])));
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assign g02[1] = (~(g01_b[1] & (t01_b[1] | g01_b[2])));
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assign g02[2] = (~(g01_b[2] & (t01_b[2] | g01_b[3])));
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assign g02[3] = (~(g01_b[3] & (t01_b[3] | g01_b[4])));
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assign g02[4] = (~(g01_b[4] & (t01_b[4] | g01_b[5])));
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assign g02[5] = (~(g01_b[5] & (t01_b[5] | g01_b[6])));
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assign g02[6] = (~(g01_b[6] & (t01_b[6] | g01_b[7]))); //final--
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assign g02[7] = (~(g01_b[7]));
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assign t02[0] = (~(t01_b[0] | t01_b[1]));
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assign t02[1] = (~(t01_b[1] | t01_b[2]));
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assign t02[2] = (~(t01_b[2] | t01_b[3]));
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assign t02[3] = (~(t01_b[3] | t01_b[4]));
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assign t02[4] = (~(t01_b[4] | t01_b[5]));
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assign t02[5] = (~(t01_b[5] | t01_b[6]));
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assign t02[6] = (~(g01_b[6] & (t01_b[6] | t01_b[7]))); //final--
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assign t02[7] = (~(t01_b[7]));
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assign g04_b[0] = (~(g02[0] | (t02[0] & g02[2])));
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assign g04_b[1] = (~(g02[1] | (t02[1] & g02[3])));
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assign g04_b[2] = (~(g02[2] | (t02[2] & g02[4])));
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assign g04_b[3] = (~(g02[3] | (t02[3] & g02[5])));
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assign g04_b[4] = (~(g02[4] | (t02[4] & g02[6]))); //final--
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assign g04_b[5] = (~(g02[5] | (t02[5] & g02[7]))); //final--
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assign g04_b[6] = (~(g02[6]));
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assign g04_b[7] = (~(g02[7]));
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assign t04_b[0] = (~(t02[0] & t02[2]));
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assign t04_b[1] = (~(t02[1] & t02[3]));
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assign t04_b[2] = (~(t02[2] & t02[4]));
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assign t04_b[3] = (~(t02[3] & t02[5]));
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assign t04_b[4] = (~(g02[4] | (t02[4] & t02[6]))); //final--
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assign t04_b[5] = (~(g02[5] | (t02[5] & t02[7]))); //final--
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assign t04_b[6] = (~(t02[6]));
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assign t04_b[7] = (~(t02[7]));
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assign g08[0] = (~(g04_b[0] & (t04_b[0] | g04_b[4]))); //final--
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assign g08[1] = (~(g04_b[1] & (t04_b[1] | g04_b[5]))); //final--
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assign g08[2] = (~(g04_b[2] & (t04_b[2] | g04_b[6]))); //final--
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assign g08[3] = (~(g04_b[3] & (t04_b[3] | g04_b[7]))); //final--
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assign g08[4] = (~(g04_b[4]));
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assign g08[5] = (~(g04_b[5]));
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assign g08[6] = (~(g04_b[6]));
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assign g08[7] = (~(g04_b[7]));
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assign t08[0] = (~(g04_b[0] & (t04_b[0] | t04_b[4]))); //final--
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assign t08[1] = (~(g04_b[1] & (t04_b[1] | t04_b[5]))); //final--
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assign t08[2] = (~(g04_b[2] & (t04_b[2] | t04_b[6]))); //final--
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assign t08[3] = (~(g04_b[3] & (t04_b[3] | t04_b[7]))); //final--
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assign t08[4] = (~(t04_b[4]));
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assign t08[5] = (~(t04_b[5]));
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assign t08[6] = (~(t04_b[6]));
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assign t08[7] = (~(t04_b[7]));
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endmodule
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