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125 lines
6.9 KiB
Verilog
125 lines
6.9 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// VHDL 1076 Macro Expander C version 07/11/00
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// job was run on Tue Mar 29 10:19:33 2011
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//***************************************************************************************************
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//*
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//* TITLE:
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//*
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//* NAME: rv_decode.vhdl
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//*
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//***************************************************************************************************
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module rv_decode(
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instr,
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is_brick,
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brick_cycles
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);
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input [0:31] instr;
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output is_brick;
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output [0:2] brick_cycles;
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//@@ Signal Declarations
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wire [1:8] RV_INSTRUCTION_DECODER_PT;
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wire [0:5] instr_0_5;
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wire [0:10] instr_21_31;
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(* analysis_not_referenced="true" *)
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wire unused;
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assign unused = |instr[6:20] | instr_21_31[10];
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//@@ START OF EXECUTABLE CODE FOR RTL
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assign instr_0_5 = instr[0:5];
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assign instr_21_31 = instr[21:31];
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//table_start
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//?TABLE rv_instruction_decoder LISTING(final) OPTIMIZE PARMS(ON-SET);
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//*INPUTS*===============*OUTPUTS*==========*
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//| | |
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//| instr_0_5 | is_brick |
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//| | instr_21_31 | | brick_cycles |
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//| | | | | | |
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//| | | | | | |
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//| | | 1 | | | |
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//| 012345 01234567890 | | 012 |
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//*TYPE*=================+==================+
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//| SSSSSS SSSSSSSSSSS | P PPP | INSTR
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//*TERMS*=*=*============+==================+
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//| 000111 ........... | 1 000 | mulli 2
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//| 011111 0011101001. | 1 001 | mulld 3
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//| 011111 1011101001. | 1 010 | mulldo 4
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//| 011111 .001001001. | 1 010 | mulhd 4
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//| 011111 .000001001. | 1 010 | mulhdu 4
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//| 011111 1100110011. | 1 000 | erativax 2
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//| 011111 0011010100. | 1 000 | ldawx
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//| 011111 0010100110. | 1 000 | dcbtls
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//| 011111 0010000110. | 1 000 | dcbtstls
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//| 011111 0000110100. | 1 000 | lbarx
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//| 011111 0001010100. | 1 000 | ldarx
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//| 011111 0001110100. | 1 000 | lharx
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//| 011111 0000010100. | 1 000 | lwarx
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//*END*==================+==================+
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//?TABLE END rv_instruction_decoder ;
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//table_end
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//assign_start
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assign RV_INSTRUCTION_DECODER_PT[1] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111111100110011);
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assign RV_INSTRUCTION_DECODER_PT[2] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 15'b011111001000110);
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assign RV_INSTRUCTION_DECODER_PT[3] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111111011101001);
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assign RV_INSTRUCTION_DECODER_PT[4] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111110011101001);
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assign RV_INSTRUCTION_DECODER_PT[5] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 14'b01111100010100);
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assign RV_INSTRUCTION_DECODER_PT[6] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 15'b011111001010100);
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assign RV_INSTRUCTION_DECODER_PT[7] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[1], instr_21_31[2], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 14'b01111100001001);
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assign RV_INSTRUCTION_DECODER_PT[8] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5]}) == 6'b000111);
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// Table RV_INSTRUCTION_DECODER Signal Assignments for Outputs
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assign is_brick = (RV_INSTRUCTION_DECODER_PT[1] | RV_INSTRUCTION_DECODER_PT[2] | RV_INSTRUCTION_DECODER_PT[3] | RV_INSTRUCTION_DECODER_PT[4] | RV_INSTRUCTION_DECODER_PT[5] | RV_INSTRUCTION_DECODER_PT[6] | RV_INSTRUCTION_DECODER_PT[7] | RV_INSTRUCTION_DECODER_PT[8]);
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assign brick_cycles[0] = (1'b0);
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assign brick_cycles[1] = (RV_INSTRUCTION_DECODER_PT[3] | RV_INSTRUCTION_DECODER_PT[7]);
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assign brick_cycles[2] = (RV_INSTRUCTION_DECODER_PT[4]);
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//assign_end
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endmodule
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