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# © IBM Corp. 2022
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# Licensed under and subject to the terms of the CC-BY 4.0
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# license (https://creativecommons.org/licenses/by/4.0/legalcode).
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# Additional rights, including the right to physically implement a softcore
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# that is compliant with the required sections of the Power ISA
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# Specification, will be available at no cost via the OpenPOWER Foundation.
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# This README will be updated with additional information when OpenPOWER's
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# license is available.
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# litex boot kernel (original ppc-embedded architecture)
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# resets to 32BE
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# set up translations for starting bios (inc. BE/LE)
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# copy modifiable rom data to ram
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# set up msr for running bios (inc. 32/64)
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# jump to bios
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.include "defines.s"
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# pass in with -defsym
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;# if neither defined, it's 64BE!
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# BE/LE
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#.set BIOS_LE,1
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# 32/64
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#.set BIOS_32,1
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# this is for i/d xlate setup of 2nd entry; it should be related to _fdata i think
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.set BIOS_START,0x10000
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# this is for d xlate setup of 3rd entry; it needs to be defined by memory map; it could be done by bios code,
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# but has to be done before uart_init is called
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.set CSR_START,0xFFF00000
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# needed for litex
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.set ROM_INIT,1
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# not needed for litex
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.set BIOS_STACK_0,_fstack-8
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.set BIOS_STACK_1,_fstack-8
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.macro load32 rx,v
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li \rx,0
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oris \rx,\rx,\v>>16
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ori \rx,\rx,\v&0x0000FFFF
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.endm
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.macro load16swiz rx,v
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li \rx,0
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ori \rx,\rx,(\v<<8)&0xFF00
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ori \rx,\rx,(\v>>8)&0x00FF
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.endm
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# constants from linker script, or defsym
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.ifndef THREAD_ENABLES
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.set THREAD_ENABLES,0x1
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.endif
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.ifdef BIOS_32
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# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
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.set BIOS_MSR,0x0002B000
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.else
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# sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
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.set BIOS_MSR,0x8002B000
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.endif
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#wtf this should to be done in bios based on the tst
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# erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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.ifdef BIOS_LE
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.set BIOS_ERATW2,0x000000BF
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.else
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.set BIOS_ERATW2,0x0000003F
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.endif
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# bios might be able to use one stack during thread startup if careful
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.ifndef BIOS_STACK_0
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.set BIOS_STACK_0,_stack_0
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.endif
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#.ifndef BIOS_STACK_1
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#.set BIOS_STACK_1,_stack_1
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#.endif
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.section .text
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.global _start
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.org 0x000
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_start:
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int_000:
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b boot_start
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# ints need to handle save/restore and call to isr (like uart_isr())
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# enable in a2node when it's safe (stack set up, etc.)
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# critical input
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.org 0x020
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int_020:
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.ifdef INT_UNHANDLED
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b int_unhandled
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.else
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b .
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.endif
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# debug
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.org 0x040
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int_040:
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b .
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# dsi
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.org 0x060
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int_060:
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b .
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# isi
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.org 0x080
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int_080:
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b .
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# external
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.org 0x0A0
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int_0A0:
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b .
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# alignment
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.org 0x0C0
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int_0C0:
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b .
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# program
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.org 0x0E0
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int_0E0:
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b .
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# fp unavailable
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.org 0x100
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int_100:
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b .
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# sc
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.org 0x120
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int_120:
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.ifdef TST_END
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# tst results haven't been saved yet; if want to call bios, need to save r1, then restore or set stack
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b tst_end
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.else
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.ifdef INT_SC
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# lev is in 20:26, but supposed to use scv now
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li r3,0
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mfsrr0 r4
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b int_sc
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.else
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.ifdef INT_UNHANDLED
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b int_unhandled
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.else
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b .
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.endif
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.endif
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.endif
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# apu unavailable
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.org 0x140
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int_140:
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b .
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# decrementer
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.org 0x160
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int_160:
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b .
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# fit
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.org 0x180
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int_180:
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b .
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# watchdog
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.org 0x1A0
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int_1A0:
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b .
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# dtlb
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.org 0x1C0
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int_1C0:
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b .
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# itlb
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.org 0x1E0
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int_1E0:
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b .
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# vector unavailable
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.org 0x200
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int_200:
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b .
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#
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.org 0x220
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int_220:
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b .
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#
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.org 0x240
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int_240:
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b .
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#
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.org 0x260
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int_260:
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b .
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# doorbell
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.org 0x280
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int_280:
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b .
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# doorbell critical
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.org 0x2A0
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int_2A0:
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b .
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# doorbell guest
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.org 0x2C0
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int_2C0:
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b .
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# doorbell guest critical
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.org 0x2E0
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int_2E0:
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b .
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# hvsc
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.org 0x300
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int_300:
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b .
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# hvpriv
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.org 0x320
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int_320:
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b .
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# lrat
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.org 0x340
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int_340:
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b .
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# ------------------------------------------------------------------------------------------------------------------------------
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# initial translation
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#
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.org 0x400
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boot_start:
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mfspr r5,tir # who am i?
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cmpdi r5,0x00 # skip unless T0
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bne init_t123
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lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
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# derat 31 @00000000
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li r0,0x001F # entry #31
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li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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mtspr mmucr0,r3
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eratwe r2,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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load32 r10,BIOS_ERATW2 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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# derat 30 @<BIOS_START>
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li r0,0x001E # entry #30
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load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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load32 r8,BIOS_START
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ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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eratwe r10,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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# derat 29 @<CSR_START> I=1!!!
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li r0,0x001D # entry #29
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ori r10,r10,0x0F00 # word 2 with WIMG=F
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load32 r4,CSR_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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load32 r8,CSR_START
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ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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eratwe r10,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
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# ierat 15 @00000000
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li r0,0x000F # entry #15
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li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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li r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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mtspr mmucr0,r3
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eratwe r2,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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# *** leave the init'd entry 14 for MT access to FFFFFFC0
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# ierat 13 @<BIOS_START>
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li r0,0x000D # entry #13
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load32 r4,BIOS_START # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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load32 r8,BIOS_START
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ori r8,r8,0x023F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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eratwe r10,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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b init_t0
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# ------------------------------------------------------------------------------------------------------------------------------
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# init
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#
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# T0
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init_t0:
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.ifdef ROM_INIT
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########################################################################################################################################
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# VMA/LMA: copy .data, clear .bss
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rominit:
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lis r1,_fdata_rom@h
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ori r1,r1,_fdata_rom@l
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lis r2,_fdata@h
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ori r2,r2,_fdata@l
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lis r3,_edata_rom@h
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ori r3,r3,_edata_rom@l
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lis r4,_fbss@h
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ori r4,r4,_fbss@l
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lis r5,_ebss@h
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ori r5,r5,_ebss@l
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subf r9,r1,r3
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srwi. r9,r9,2
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beq romcopy_done
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mtctr r9
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addi r1,r1,-4
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addi r2,r2,-4
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romcopy:
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lwzu r9,4(r1)
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stwu r9,4(r2)
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bdnz romcopy
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romcopy_done:
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subf r9,r4,r5
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srwi. r9,r9,2
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beq romclear_done
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mtctr r9
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addi r4,r4,-4
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li r9,0
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romclear:
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stwu r9,4(r4)
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bdnz romclear
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romclear_done:
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.endif
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# set up threads
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# set thread configuration
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li r1,THREAD_ENABLES
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mtspr tens,r1 # 60:63 = tid 3:0 enabled
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not r1,r1
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mtspr tenc,r1 # in case T0 is marked disabled
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isync
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# set up BIOS msr
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load32 r10,BIOS_MSR
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mtmsr r10
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isync
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# can't use load32 unless you can .set BIOS_STACK_0 to the linked value
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# load32 r1,BIOS_STACK_0 # @stack_0
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# this ignores def
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|
|
# lis r1,_stack_0@h
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|
|
# ori r1,r1,_stack_0@l
|
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|
|
# this requires data load
|
|
|
|
lwz r1,stack_0(r0)
|
|
|
|
|
|
|
|
b boot_complete
|
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|
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|
|
# except T0
|
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|
|
|
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|
|
init_t123:
|
|
|
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|
|
|
# set up BIOS msr
|
|
|
|
|
|
|
|
load32 r10,BIOS_MSR
|
|
|
|
mtmsr r10
|
|
|
|
isync
|
|
|
|
# check tir if more than 2 threads possible
|
|
|
|
lwz r1,stack_1(r0)
|
|
|
|
|
|
|
|
b boot_complete
|
|
|
|
|
|
|
|
# ------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
boot_complete:
|
|
|
|
|
|
|
|
# set up thread and hop to it
|
|
|
|
|
|
|
|
lis r3,main@h
|
|
|
|
ori r3,r3,main@l
|
|
|
|
mtctr r3
|
|
|
|
mfspr r3,tir # who am i?
|
|
|
|
bctrl
|
|
|
|
b kernel_return
|
|
|
|
|
|
|
|
# ------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
.ifdef BIOS_32
|
|
|
|
.align 4
|
|
|
|
.include "crtsavres.s"
|
|
|
|
.endif
|
|
|
|
|
|
|
|
.ifdef TST_PASSFAIL
|
|
|
|
.global tst_pass
|
|
|
|
.global tst_fail
|
|
|
|
|
|
|
|
.org 0x7F0
|
|
|
|
tst_pass:
|
|
|
|
b .
|
|
|
|
|
|
|
|
.org 0x7F4
|
|
|
|
tst_fail:
|
|
|
|
b .
|
|
|
|
.endif
|
|
|
|
|
|
|
|
.org 0x7FC
|
|
|
|
kernel_return:
|
|
|
|
b .
|
|
|
|
|
|
|
|
# dec
|
|
|
|
.org 0x800
|
|
|
|
int_800:
|
|
|
|
b .
|
|
|
|
|
|
|
|
# perf
|
|
|
|
.org 0x820
|
|
|
|
int_820:
|
|
|
|
b .
|
|
|
|
|
|
|
|
.org 0x8F0
|
|
|
|
.section .rodata
|
|
|
|
stack_0: .long BIOS_STACK_0
|
|
|
|
stack_1: .long BIOS_STACK_1
|