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25 lines
341 B
Verilog
25 lines
341 B
Verilog
2 years ago
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`timescale 1 ps / 1 ps
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module FDPE (Q, C, CE, D, PRE);
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parameter INIT = 1'b1;
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output Q;
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input C, CE, D, PRE;
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wire Q;
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reg q_out;
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initial q_out = INIT;
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assign Q = q_out;
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always @(posedge C or posedge PRE)
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if (PRE)
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q_out <= 1;
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else if (CE)
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q_out <= D;
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endmodule
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