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250 lines
6.5 KiB
C++
250 lines
6.5 KiB
C++
3 years ago
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// simple verilator top
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/*
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doesn't build on 4.106 (at least)
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*/
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#define TRACING
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#include <cstddef>
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#include <iostream>
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#include <iomanip>
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#include "verilated.h"
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#include "Vc.h"
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#ifdef TRACING
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#include "verilated_vcd_c.h"
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VerilatedVcdC *t;
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#else
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unsigned int t = 0;
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#endif
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/*
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#include "uart/uartsim.h"
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*/
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Vc* m;
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vluint64_t main_time = 0; // in units of timeprecision used in verilog or --timescale-override
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// what is it? it changed to 941621251 after calling loadmem()
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double sc_time_stamp() { // $time in verilog
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return main_time;
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}
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const int resetCycle = 10;
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const int threadRunCycle = 200;
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const int runCycles = 1000;
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const int hbCycles = 500;
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const int threads = 1; // needs a more realistic a2l2 data return to work in smt
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/*
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143 # -------------------------------------------------------------------------------------------------
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144 # enable smt2 and branch in different locs (driver returns b +64 if doesnt hit actual ops)
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145 # 32b mode until msr[32]=1
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146
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147 0344 480000BC .align 8
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147 60000000
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147 60000000
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147 60000000
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147 60000000
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148 boot_start:
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149
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150 0400 38200003 li r1,0x3
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151 0404 7C366BA6 mtspr tens,r1 # 62:63 = tid 1:0 enabled
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152 0408 7C3E6AA6 mfspr r1,tir # who am i?
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*** appears to need an isync here! cr is not correct w/o it (old r1?)
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153 040c 2C010000 cmpwi r1,0x00
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154 0410 38202000 li r1,0x2000 # change to use 660 so stay in page 0
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155 0414 41820008 beq t0
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156 t1:
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157 0418 5421103A slwi r1,r1,2 # change to addi so stay in page 0
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158 t0:
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160 041c 7C2903A6 mtctr r1
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161 0420 4E800420 bctr # off to neverneverland
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162 041c 7C2FCBA6 mtspr tar,r1
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163 0420 4E800460 bctar 0x14,0,0
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4C00012C isync
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*/
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int mem[1024]; // 4B*1K
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void loadmem(void) {
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int adr;
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mem[0x0000/4] = 0x48000400;
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adr = 0x400/4;
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mem[adr++] = threads == 1 ? 0x38200001 : 0x38200003;
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mem[adr++] = 0x7C366BA6;
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mem[adr++] = 0x7C366BA6;
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mem[adr++] = 0x7C3E6AA6;
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mem[adr++] = 0x4C00012C;
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mem[adr++] = 0x2C010000;
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mem[adr++] = 0x38200660;
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mem[adr++] = 0x41820008;
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mem[adr++] = 0x38210100;
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mem[adr++] = 0x7C2903A6;
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mem[adr++] = 0x4E800420;
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}
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// nclk = (clk,reset,clk2x,clk4x,-,-)
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int main(int argc, char **argv) {
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using namespace std;
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loadmem();
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cout << setfill('0');
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Verilated::commandArgs(argc, argv);
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m = new Vc;
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#ifdef TRACING
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Verilated::traceEverOn(true);
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t = new VerilatedVcdC;
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m->trace(t, 99);
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t->open("wtf.vcd");
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cout << "Tracing enabled." << endl;
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#endif
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bool resetDone = false;
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unsigned int threadStop = 0x3;
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unsigned int tick = 0;
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unsigned int cycle = 1;
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unsigned int readPending = 0;
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unsigned int readAddr = 0;
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unsigned int readTag = 0;
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unsigned int readTID = 0;
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unsigned int countReads = 0;
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m->nclk = 0x3C; // run 2x,4x = 1x
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cout << setw(8) << cycle << "Resetting..." << endl;
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m->an_ac_pm_thread_stop = threadStop;
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cout << setw(8) << cycle << "Thread stop=" << threadStop << endl;
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// can skip 4x with new gpr array
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// 1x=4/4 2x=2/2 4x=1/1
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// 1 1 1 7
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// 1 1 0 6
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// 1 0 1 5
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// 1 0 0 4
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// 0 1 1 3
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// 0 1 0 2
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// 0 0 1 1
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// 0 0 0 0
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// (insert reset)
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//const int clocks[8] = {11, 0, 11, 0, 11, 0, 11, 0}; // 2x,4x == 1x
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const int clocks[8] = {11, 10, 9, 8, 3, 2, 1, 0}; // 1x, 2x, 4x
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const int ticks1x = 8;
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while (!Verilated::gotFinish()) {
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if (!resetDone && (cycle > resetCycle)) {
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m->nclk &= 0x2F;
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cout << setw(8) << cycle << "Releasing reset." << endl;
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resetDone = true;
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}
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if (threadStop && (cycle > threadRunCycle)) {
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threadStop = 0x0;
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m->an_ac_pm_thread_stop = threadStop;
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cout << setw(8) << cycle << "Thread stop=" << threadStop << endl;
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}
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m->nclk = (m->nclk & 0x10) | (clocks[tick % 8] << 2);
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tick++;
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m->eval();
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// bus is 1x clock
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if ((tick % ticks1x) == 0) {
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if (readPending == cycle) { // i=1
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m->an_ac_reld_data_vld = 1;
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m->an_ac_reld_core_tag = readTag;
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m->an_ac_reld_qw = 0;
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m->an_ac_reld_crit_qw = 1;
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if (readAddr == 0xFFFFFFF0) {
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m->an_ac_reld_data[3]= 0x00000000; // 0
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m->an_ac_reld_data[2]= 0x00000000; // 4
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m->an_ac_reld_data[1]= 0x00000000; // 8
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m->an_ac_reld_data[0]= 0x48000002; // C
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} else if (readAddr < 0x0500) {
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m->an_ac_reld_data[3]= mem[readAddr/4+0];
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m->an_ac_reld_data[2]= mem[readAddr/4+1];
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m->an_ac_reld_data[1]= mem[readAddr/4+2];
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m->an_ac_reld_data[0]= mem[readAddr/4+3];
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} else {
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m->an_ac_reld_data[3]= 0x48000040;
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m->an_ac_reld_data[2]= 0x00000000;
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m->an_ac_reld_data[1]= 0x00000000;
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m->an_ac_reld_data[0]= 0x00000000;
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}
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readPending = 0;
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countReads++;
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cout << setw(8) << cycle << " an_ac_rsp: data="<< hex << uppercase << setw(8) << m->an_ac_reld_data[3]
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<< hex << uppercase << setw(8) << m->an_ac_reld_data[2]
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<< hex << uppercase << setw(8) << m->an_ac_reld_data[1]
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<< hex << uppercase << setw(8) << m->an_ac_reld_data[0]
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<< dec << nouppercase << endl;
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} else {
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m->an_ac_reld_data_vld = 0;
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}
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m->an_ac_req_ld_pop = 0;
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if (!readPending && m->ac_an_req) {
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readAddr = m->ac_an_req_ra;
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readTag = m->ac_an_req_ld_core_tag;
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readTID = m->ac_an_req_thread;
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readPending = cycle + 3;
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cout << setw(8) << cycle << " ac_an_req: T" << readTID << " ra=" << hex << uppercase << setw(8) << readAddr << dec << nouppercase << endl;
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m->an_ac_req_ld_pop = 1;
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}
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}
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// finish clock stuff
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if ((tick % ticks1x) == 0) {
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cycle++;
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if ((cycle % hbCycles) == 0) {
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cout << setw(8) << cycle << " ...tick..." << endl;
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}
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}
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#ifdef TRACING
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t->dump(tick);
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t->flush();
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#endif
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// check for fails
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// hit limit
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if (cycle > runCycles) {
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break;
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}
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}
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#ifdef TRACING
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t->close();
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#endif
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m->final();
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exit(EXIT_SUCCESS);
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}
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