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556 lines
19 KiB
Verilog
556 lines
19 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: XU_FX ALU Top
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module xu_alu(
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//-------------------------------------------------------------------
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// Clocks & Power
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//-------------------------------------------------------------------
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input [0:`NCLK_WIDTH-1] nclk,
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inout vdd,
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inout gnd,
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//-------------------------------------------------------------------
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// Pervasive
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//-------------------------------------------------------------------
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input d_mode_dc,
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input delay_lclkr_dc,
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input mpw1_dc_b,
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input mpw2_dc_b,
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input func_sl_force,
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input func_sl_thold_0_b,
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input sg_0,
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input scan_in,
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output scan_out,
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//-------------------------------------------------------------------
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// Decode Interface
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//-------------------------------------------------------------------
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input dec_alu_ex1_act,
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input [0:31] dec_alu_ex1_instr,
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input dec_alu_ex1_sel_isel, // Critical!
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input [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv,
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input [0:1] dec_alu_ex2_add_ci_sel,
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input dec_alu_ex1_sel_trap,
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input dec_alu_ex1_sel_cmpl,
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input dec_alu_ex1_sel_cmp,
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input dec_alu_ex1_msb_64b_sel,
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input dec_alu_ex1_xer_ov_en,
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input dec_alu_ex1_xer_ca_en,
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//-------------------------------------------------------------------
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// Bypass Inputs
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//-------------------------------------------------------------------
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input [64-`GPR_WIDTH:63] byp_alu_ex2_rs1, // Source Data
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input [64-`GPR_WIDTH:63] byp_alu_ex2_rs2,
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input byp_alu_ex2_cr_bit, // CR bit for isel
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input [0:9] byp_alu_ex2_xer,
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//-------------------------------------------------------------------
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// Bypass Outputs
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//-------------------------------------------------------------------
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output [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt,
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output [64-`GPR_WIDTH:63] alu_byp_ex3_rt,
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output [0:3] alu_byp_ex3_cr,
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output [0:9] alu_byp_ex3_xer,
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output alu_dec_ex3_trap_val
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);
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localparam msb = 64 - `GPR_WIDTH;
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// Latches
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wire ex2_act_q; // input=>dec_alu_ex1_act ,act=>1'b1
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wire ex2_sel_isel_q; // input=>dec_alu_ex1_sel_isel ,act=>dec_alu_ex1_act
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wire ex2_msb_64b_sel_q; // input=>dec_alu_ex1_msb_64b_sel ,act=>dec_alu_ex1_act
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wire ex2_sel_trap_q; // input=>dec_alu_ex1_sel_trap ,act=>dec_alu_ex1_act
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wire ex2_sel_cmpl_q; // input=>dec_alu_ex1_sel_cmpl ,act=>dec_alu_ex1_act
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wire ex2_sel_cmp_q; // input=>dec_alu_ex1_sel_cmp ,act=>dec_alu_ex1_act
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wire [6:10] ex2_instr_6to10_q; // input=>dec_alu_ex1_instr(6 to 10) ,act=>dec_alu_ex1_act
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wire ex2_xer_ov_en_q; // input=>dec_alu_ex1_xer_ov_en ,act=>dec_alu_ex1_act
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wire ex2_xer_ca_en_q; // input=>dec_alu_ex1_xer_ca_en ,act=>dec_alu_ex1_act
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wire ex3_add_ca_q; // input=>ex2_add_ca ,act=>ex2_act_q
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wire ex2_add_ca;
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wire ex3_add_ovf_q; // input=>ex2_add_ovf ,act=>ex2_act_q
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wire ex2_add_ovf;
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wire ex3_sel_rot_log_q; // input=>ex2_sel_rot_log ,act=>ex2_act_q
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wire ex2_sel_rot_log;
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wire [0:9] ex3_xer_q; // input=>byp_alu_ex2_xer(0 to 9) ,act=>ex2_act_q
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wire ex3_xer_ov_en_q; // input=>ex2_xer_ov_en_q ,act=>ex2_act_q
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wire ex3_xer_ca_en_q; // input=>ex2_xer_ca_en_q ,act=>ex2_act_q
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// Scanchains
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localparam ex2_act_offset = 3;
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localparam ex2_sel_isel_offset = ex2_act_offset + 1;
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localparam ex2_msb_64b_sel_offset = ex2_sel_isel_offset + 1;
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localparam ex2_sel_trap_offset = ex2_msb_64b_sel_offset + 1;
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localparam ex2_sel_cmpl_offset = ex2_sel_trap_offset + 1;
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localparam ex2_sel_cmp_offset = ex2_sel_cmpl_offset + 1;
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localparam ex2_instr_6to10_offset = ex2_sel_cmp_offset + 1;
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localparam ex2_xer_ov_en_offset = ex2_instr_6to10_offset + 5;
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localparam ex2_xer_ca_en_offset = ex2_xer_ov_en_offset + 1;
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localparam ex3_add_ca_offset = ex2_xer_ca_en_offset + 1;
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localparam ex3_add_ovf_offset = ex3_add_ca_offset + 1;
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localparam ex3_sel_rot_log_offset = ex3_add_ovf_offset + 1;
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localparam ex3_xer_offset = ex3_sel_rot_log_offset + 1;
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localparam ex3_xer_ov_en_offset = ex3_xer_offset + 10;
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localparam ex3_xer_ca_en_offset = ex3_xer_ov_en_offset + 1;
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localparam scan_right = ex3_xer_ca_en_offset + 1;
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wire [0:scan_right-1] siv;
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wire [0:scan_right-1] sov;
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//!! bugspray include: xu_alu.bil;
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// Signals
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wire [msb:63] ex2_add_rs1;
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wire [msb:63] ex2_add_rs2;
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wire [msb:63] ex2_rot_rs0_b;
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wire [msb:63] ex2_rot_rs1_b;
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wire [msb:63] ex2_add_rt;
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wire [msb:63] ex3_alu_rt;
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wire ex3_rot_ca;
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wire ex3_alu_ca;
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wire ex2_add_ci;
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wire [0:3] ex2_isel_fcn;
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wire [0:3] ex2_isel_type;
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wire ex3_alu_so;
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//---------------------------------------------------------------
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// Source Buffering
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//---------------------------------------------------------------
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assign ex2_add_rs1 = byp_alu_ex2_rs1;
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assign ex2_add_rs2 = byp_alu_ex2_rs2;
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assign ex2_rot_rs0_b = (~byp_alu_ex2_rs1);
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assign ex2_rot_rs1_b = (~byp_alu_ex2_rs2);
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//---------------------------------------------------------------
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// Target Muxing/Buffering
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//---------------------------------------------------------------
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assign alu_byp_ex3_rt = ex3_alu_rt;
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assign ex3_alu_ca = (ex3_sel_rot_log_q == 1'b1) ? ex3_rot_ca :
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ex3_add_ca_q;
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assign alu_byp_ex3_cr[3] = ex3_alu_so;
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assign alu_byp_ex3_xer[0] = ex3_alu_so;
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assign ex3_alu_so = (ex3_xer_ov_en_q == 1'b1) ? ex3_add_ovf_q | ex3_xer_q[0] :
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ex3_xer_q[0];
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assign alu_byp_ex3_xer[1] = (ex3_xer_ov_en_q == 1'b1) ? ex3_add_ovf_q :
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ex3_xer_q[1];
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assign alu_byp_ex3_xer[2] = (ex3_xer_ca_en_q == 1'b1) ? ex3_alu_ca :
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ex3_xer_q[2];
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assign alu_byp_ex3_xer[3:9] = ex3_xer_q[3:9];
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assign alu_byp_ex2_add_rt = ex2_add_rt;
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//---------------------------------------------------------------
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// Add
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//---------------------------------------------------------------
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xu_alu_add add(
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.nclk(nclk),
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.vdd(vdd),
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.gnd(gnd),
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.delay_lclkr_dc(delay_lclkr_dc),
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.mpw1_dc_b(mpw1_dc_b),
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.mpw2_dc_b(mpw2_dc_b),
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.func_sl_force(func_sl_force),
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.func_sl_thold_0_b(func_sl_thold_0_b),
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.sg_0(sg_0),
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.scan_in(siv[0]),
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.scan_out(sov[0]),
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.ex1_act(dec_alu_ex1_act),
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.ex2_msb_64b_sel(ex2_msb_64b_sel_q),
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.dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv),
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.dec_alu_ex2_add_ci(ex2_add_ci),
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.ex2_rs1(ex2_add_rs1),
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.ex2_rs2(ex2_add_rs2),
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.ex2_add_rt(ex2_add_rt),
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.ex2_add_ovf(ex2_add_ovf),
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.ex2_add_ca(ex2_add_ca)
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);
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//---------------------------------------------------------------
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// Rotate / Logical
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//---------------------------------------------------------------
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assign ex2_add_ci = (dec_alu_ex2_add_ci_sel == 2'b10) ? byp_alu_ex2_xer[2] :
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(dec_alu_ex2_add_ci_sel == 2'b01) ? 1'b1 :
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1'b0;
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tri_st_rot rot(
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.nclk(nclk),
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.vdd(vdd),
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.gnd(gnd),
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.d_mode_dc(d_mode_dc),
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.delay_lclkr_dc(delay_lclkr_dc),
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.mpw1_dc_b(mpw1_dc_b),
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.mpw2_dc_b(mpw2_dc_b),
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.func_sl_force(func_sl_force),
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.func_sl_thold_0_b(func_sl_thold_0_b),
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.sg_0(sg_0),
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.scan_in(siv[1]),
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.scan_out(sov[1]),
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.ex1_act(dec_alu_ex1_act),
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.ex1_instr(dec_alu_ex1_instr),
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.ex2_isel_fcn(ex2_isel_fcn),
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.ex2_sel_rot_log(ex2_sel_rot_log),
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// Source Inputs
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.ex2_rs0_b(ex2_rot_rs0_b),
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.ex2_rs1_b(ex2_rot_rs1_b),
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// Other ALU Inputs for muxing
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.ex2_alu_rt(ex2_add_rt),
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// EX3 Bypass Tap
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.ex3_rt(ex3_alu_rt),
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.ex2_log_rt(),
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// EX2 Bypass Tap (logicals only)
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.ex3_xer_ca(ex3_rot_ca),
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.ex3_cr_eq()
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);
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assign ex2_isel_type = {1'b0, (~(byp_alu_ex2_cr_bit)), byp_alu_ex2_cr_bit, 1'b1};
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assign ex2_isel_fcn = ex2_sel_isel_q==1'b1 ? ex2_isel_type : 4'b0;
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//---------------------------------------------------------------
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// Compare / Trap
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//---------------------------------------------------------------
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xu_alu_cmp cmp(
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.nclk(nclk),
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.vdd(vdd),
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.gnd(gnd),
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.d_mode_dc(d_mode_dc),
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.delay_lclkr_dc(delay_lclkr_dc),
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.mpw1_dc_b(mpw1_dc_b),
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.mpw2_dc_b(mpw2_dc_b),
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.func_sl_force(func_sl_force),
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.func_sl_thold_0_b(func_sl_thold_0_b),
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.sg_0(sg_0),
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.scan_in(siv[2]),
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.scan_out(sov[2]),
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.ex2_act(ex2_act_q),
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.ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel),
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.ex2_instr(ex2_instr_6to10_q),
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.ex2_sel_trap(ex2_sel_trap_q),
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.ex2_sel_cmpl(ex2_sel_cmpl_q),
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.ex2_sel_cmp(ex2_sel_cmp_q),
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.ex2_rs1_00(ex2_add_rs1[msb]),
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.ex2_rs1_32(ex2_add_rs1[32]),
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.ex2_rs2_00(ex2_add_rs2[msb]),
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.ex2_rs2_32(ex2_add_rs2[32]),
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.ex3_alu_rt(ex3_alu_rt),
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.ex3_add_ca(ex3_add_ca_q),
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.ex3_alu_cr(alu_byp_ex3_cr[0:2]),
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.ex3_trap_val(alu_dec_ex3_trap_val)
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);
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//---------------------------------------------------------------
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// Latches
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//---------------------------------------------------------------
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tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_act_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(1'b1),
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.force_t(func_sl_force),
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.d_mode(d_mode_dc),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.scin(siv[ex2_act_offset]),
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.scout(sov[ex2_act_offset]),
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.din(dec_alu_ex1_act),
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.dout(ex2_act_q)
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);
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tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_isel_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(dec_alu_ex1_act),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex2_sel_isel_offset]),
|
||
|
|
.scout(sov[ex2_sel_isel_offset]),
|
||
|
|
.din(dec_alu_ex1_sel_isel),
|
||
|
|
.dout(ex2_sel_isel_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msb_64b_sel_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(dec_alu_ex1_act),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex2_msb_64b_sel_offset]),
|
||
|
|
.scout(sov[ex2_msb_64b_sel_offset]),
|
||
|
|
.din(dec_alu_ex1_msb_64b_sel),
|
||
|
|
.dout(ex2_msb_64b_sel_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_trap_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(dec_alu_ex1_act),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex2_sel_trap_offset]),
|
||
|
|
.scout(sov[ex2_sel_trap_offset]),
|
||
|
|
.din(dec_alu_ex1_sel_trap),
|
||
|
|
.dout(ex2_sel_trap_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_cmpl_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(dec_alu_ex1_act),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex2_sel_cmpl_offset]),
|
||
|
|
.scout(sov[ex2_sel_cmpl_offset]),
|
||
|
|
.din(dec_alu_ex1_sel_cmpl),
|
||
|
|
.dout(ex2_sel_cmpl_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_cmp_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(dec_alu_ex1_act),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex2_sel_cmp_offset]),
|
||
|
|
.scout(sov[ex2_sel_cmp_offset]),
|
||
|
|
.din(dec_alu_ex1_sel_cmp),
|
||
|
|
.dout(ex2_sel_cmp_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_6to10_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(dec_alu_ex1_act),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex2_instr_6to10_offset:ex2_instr_6to10_offset + 5 - 1]),
|
||
|
|
.scout(sov[ex2_instr_6to10_offset:ex2_instr_6to10_offset + 5 - 1]),
|
||
|
|
.din(dec_alu_ex1_instr[6:10]),
|
||
|
|
.dout(ex2_instr_6to10_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_en_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(dec_alu_ex1_act),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex2_xer_ov_en_offset]),
|
||
|
|
.scout(sov[ex2_xer_ov_en_offset]),
|
||
|
|
.din(dec_alu_ex1_xer_ov_en),
|
||
|
|
.dout(ex2_xer_ov_en_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ca_en_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(dec_alu_ex1_act),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex2_xer_ca_en_offset]),
|
||
|
|
.scout(sov[ex2_xer_ca_en_offset]),
|
||
|
|
.din(dec_alu_ex1_xer_ca_en),
|
||
|
|
.dout(ex2_xer_ca_en_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_ca_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(ex2_act_q),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex3_add_ca_offset]),
|
||
|
|
.scout(sov[ex3_add_ca_offset]),
|
||
|
|
.din(ex2_add_ca),
|
||
|
|
.dout(ex3_add_ca_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_ovf_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(ex2_act_q),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex3_add_ovf_offset]),
|
||
|
|
.scout(sov[ex3_add_ovf_offset]),
|
||
|
|
.din(ex2_add_ovf),
|
||
|
|
.dout(ex3_add_ovf_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_rot_log_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(ex2_act_q),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex3_sel_rot_log_offset]),
|
||
|
|
.scout(sov[ex3_sel_rot_log_offset]),
|
||
|
|
.din(ex2_sel_rot_log),
|
||
|
|
.dout(ex3_sel_rot_log_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex3_xer_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(ex2_act_q),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex3_xer_offset:ex3_xer_offset + 10 - 1]),
|
||
|
|
.scout(sov[ex3_xer_offset:ex3_xer_offset + 10 - 1]),
|
||
|
|
.din(byp_alu_ex2_xer[0:9]),
|
||
|
|
.dout(ex3_xer_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_en_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(ex2_act_q),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex3_xer_ov_en_offset]),
|
||
|
|
.scout(sov[ex3_xer_ov_en_offset]),
|
||
|
|
.din(ex2_xer_ov_en_q),
|
||
|
|
.dout(ex3_xer_ov_en_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ca_en_latch(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.act(ex2_act_q),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[ex3_xer_ca_en_offset]),
|
||
|
|
.scout(sov[ex3_xer_ca_en_offset]),
|
||
|
|
.din(ex2_xer_ca_en_q),
|
||
|
|
.dout(ex3_xer_ca_en_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
|
||
|
|
assign scan_out = sov[0];
|
||
|
|
|
||
|
|
endmodule
|