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302 lines
9.9 KiB
Verilog
302 lines
9.9 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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// Description: XU BCD Assist Instructions
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module xu0_bcd(
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// Clocks
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input [0:`NCLK_WIDTH-1] nclk,
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// Power
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inout vdd,
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inout gnd,
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// Pervasive
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input d_mode_dc,
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input delay_lclkr_dc,
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input mpw1_dc_b,
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input mpw2_dc_b,
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input func_sl_force,
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input func_sl_thold_0_b,
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input sg_0,
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input scan_in,
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output scan_out,
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// Decode Inputs
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input dec_bcd_ex1_val,
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input dec_bcd_ex1_is_addg6s,
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input dec_bcd_ex1_is_cdtbcd,
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// Source Data
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input [64-`GPR_WIDTH:63] byp_bcd_ex2_rs1,
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input [64-`GPR_WIDTH:63] byp_bcd_ex2_rs2,
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// Target Data
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output [64-`GPR_WIDTH:63] bcd_byp_ex3_rt,
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output bcd_byp_ex3_done
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);
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// Latches
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wire ex2_val_q; // input=>dec_bcd_ex1_val ,act=>1'b1
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wire ex2_is_addg6s_q; // input=>dec_bcd_ex1_is_addg6s ,act=>dec_bcd_ex1_val
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wire ex2_is_cdtbcd_q; // input=>dec_bcd_ex1_is_cdtbcd ,act=>dec_bcd_ex1_val
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wire [64-`GPR_WIDTH:63] ex3_bcd_rt_q; // input=>ex2_bcd_rt ,act=>ex2_val_q
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wire [64-`GPR_WIDTH:63] ex2_bcd_rt;
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wire ex3_val_q; // input=>ex2_val_q ,act=>1'b1
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// Scanchains
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localparam ex2_val_offset = 0;
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localparam ex2_is_addg6s_offset = ex2_val_offset + 1;
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localparam ex2_is_cdtbcd_offset = ex2_is_addg6s_offset + 1;
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localparam ex3_bcd_rt_offset = ex2_is_cdtbcd_offset + 1;
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localparam ex3_val_offset = ex3_bcd_rt_offset + `GPR_WIDTH;
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localparam scan_right = ex3_val_offset + 1;
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wire [0:scan_right-1] siv;
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wire [0:scan_right-1] sov;
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wire [0:63] g0;
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wire [0:63] g1;
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wire [0:63] g2;
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wire [0:63] g3;
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wire [0:63] g4;
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wire [0:63] g5;
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wire [0:63] g6;
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wire [0:62] p0;
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wire [0:61] p1;
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wire [0:59] p2;
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wire [0:55] p3;
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wire [0:47] p4;
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wire [0:31] p5;
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wire [0:63] ex2_bcdtd_rt;
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wire [0:63] ex2_dtbcd_rt;
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wire [0:63] ex2_sixes_rt;
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(* analysis_not_referenced="true" *)
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wire unused;
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// BCD to DPD
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xu0_bcd_bcdtd bcdtd00(
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.a(byp_bcd_ex2_rs1[8:19]),
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.y(ex2_bcdtd_rt[12:21])
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);
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xu0_bcd_bcdtd bcdtd01(
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.a(byp_bcd_ex2_rs1[20:31]),
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.y(ex2_bcdtd_rt[22:31])
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);
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xu0_bcd_bcdtd bcdtd10(
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.a(byp_bcd_ex2_rs1[40:51]),
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.y(ex2_bcdtd_rt[44:53])
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);
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xu0_bcd_bcdtd bcdtd11(
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.a(byp_bcd_ex2_rs1[52:63]),
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.y(ex2_bcdtd_rt[54:63])
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);
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assign ex2_bcdtd_rt[0:11] = {12{1'b0}};
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assign ex2_bcdtd_rt[32:43] = {12{1'b0}};
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// DPD to BCD
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xu0_bcd_dtbcd dtbcd00(
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.a(byp_bcd_ex2_rs1[12:21]),
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.y(ex2_dtbcd_rt[8:19])
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);
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xu0_bcd_dtbcd dtbcd01(
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.a(byp_bcd_ex2_rs1[22:31]),
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.y(ex2_dtbcd_rt[20:31])
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);
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xu0_bcd_dtbcd dtbcd10(
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.a(byp_bcd_ex2_rs1[44:53]),
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.y(ex2_dtbcd_rt[40:51])
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);
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xu0_bcd_dtbcd dtbcd11(
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.a(byp_bcd_ex2_rs1[54:63]),
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.y(ex2_dtbcd_rt[52:63])
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);
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assign ex2_dtbcd_rt[0:7] = {8{1'b0}};
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assign ex2_dtbcd_rt[32:39] = {8{1'b0}};
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// ADDG6S
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assign p0[00:62] = byp_bcd_ex2_rs1[00:62] ^ byp_bcd_ex2_rs2[00:62];
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assign g0[00:63] = byp_bcd_ex2_rs1[00:63] & byp_bcd_ex2_rs2[00:63];
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// L1 (1)
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assign g1[00:62] = (p0[00:62] & g0[01:63]) | g0[00:62];
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assign g1[63:63] = g0[63:63];
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assign p1[00:61] = p0[00:61] & p0[01:62];
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// L2 (2)
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assign g2[00:61] = (p1[00:61] & g1[02:63]) | g1[00:61];
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assign g2[62:63] = g1[62:63];
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assign p2[00:59] = p1[00:59] & p1[02:61];
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// L3 (4)
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assign g3[00:59] = (p2[00:59] & g2[04:63]) | g2[00:59];
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assign g3[60:63] = g2[60:63];
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assign p3[00:55] = p2[00:55] & p2[04:59];
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// L4 (8)
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assign g4[00:55] = (p3[00:55] & g3[08:63]) | g3[00:55];
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assign g4[56:63] = g3[56:63];
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assign p4[00:47] = p3[00:47] & p3[08:55];
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// L5 (16)
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assign g5[00:47] = (p4[00:47] & g4[16:63]) | g4[00:47];
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assign g5[48:63] = g4[48:63];
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assign p5[00:31] = p4[00:31] & p4[16:47];
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// L6 (32)
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assign g6[00:31] = (p5[00:31] & g5[32:63]) | g5[00:31];
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assign g6[32:63] = g5[32:63];
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generate
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genvar b;
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for (b = 0; b <= 15; b = b + 1)
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begin : nibble
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assign ex2_sixes_rt[4 * b:4 * b + 3] = (g6[b * 4] == 1'b0) ? 4'b0110 :
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4'b0000;
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end
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endgenerate
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//!! bugspray include: tri_a2o.bil
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//!! %for(i=0;i<16;++i)
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//!! [count; scenarios.addg6s_n%(i)_0 ; bugclk] : (pri2) <= ex2_val_q and ex2_is_addg6s_q and not g6(%(i*4));
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//!! [count; scenarios.addg6s_n%(i)_1 ; bugclk] : (pri2) <= ex2_val_q and ex2_is_addg6s_q and g6(%(i*4));
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//!! %end
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assign ex2_bcd_rt = ({ex2_is_addg6s_q, ex2_is_cdtbcd_q} == 2'b10) ? ex2_sixes_rt :
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({ex2_is_addg6s_q, ex2_is_cdtbcd_q} == 2'b01) ? ex2_dtbcd_rt :
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ex2_bcdtd_rt;
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assign bcd_byp_ex3_rt = ex3_bcd_rt_q;
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assign bcd_byp_ex3_done = ex3_val_q;
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// Latches
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tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(1'b1),
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.force_t(func_sl_force),
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.d_mode(d_mode_dc),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.scin(siv[ex2_val_offset]),
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.scout(sov[ex2_val_offset]),
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.din(dec_bcd_ex1_val),
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.dout(ex2_val_q)
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);
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tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_addg6s_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(dec_bcd_ex1_val),
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.force_t(func_sl_force),
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.d_mode(d_mode_dc),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.scin(siv[ex2_is_addg6s_offset]),
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.scout(sov[ex2_is_addg6s_offset]),
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.din(dec_bcd_ex1_is_addg6s),
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.dout(ex2_is_addg6s_q)
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);
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tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_cdtbcd_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(dec_bcd_ex1_val),
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.force_t(func_sl_force),
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.d_mode(d_mode_dc),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.scin(siv[ex2_is_cdtbcd_offset]),
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.scout(sov[ex2_is_cdtbcd_offset]),
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.din(dec_bcd_ex1_is_cdtbcd),
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.dout(ex2_is_cdtbcd_q)
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);
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tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_bcd_rt_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(ex2_val_q),
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.force_t(func_sl_force),
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.d_mode(d_mode_dc),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.scin(siv[ex3_bcd_rt_offset:ex3_bcd_rt_offset + `GPR_WIDTH - 1]),
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.scout(sov[ex3_bcd_rt_offset:ex3_bcd_rt_offset + `GPR_WIDTH - 1]),
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.din(ex2_bcd_rt),
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.dout(ex3_bcd_rt_q)
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);
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tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(1'b1),
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.force_t(func_sl_force),
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.d_mode(d_mode_dc),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.scin(siv[ex3_val_offset]),
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.scout(sov[ex3_val_offset]),
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.din(ex2_val_q),
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.dout(ex3_val_q)
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);
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assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
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assign scan_out = sov[0];
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assign unused = (|g6[1:3]) | (|g6[5:7]) | (|g6[9:11]) | (|g6[13:15]) | (|g6[17:19]) | (|g6[21:23]) | (|g6[25:27]) |
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(|g6[29:31]) | (|g6[33:35]) | (|g6[37:39]) | (|g6[41:43]) | (|g6[45:47]) | (|g6[49:51]) | (|g6[53:55]) |
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(|g6[57:59]) | (|g6[61:63]);
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endmodule
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