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333 lines
8.6 KiB
Verilog
333 lines
8.6 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *********************************************************************
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//
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// This is the ENTITY for fu_perv
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//
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// *********************************************************************
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`include "tri_a2o.vh"
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module fu_perv(
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vdd,
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gnd,
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nclk,
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pc_fu_sg_3,
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pc_fu_abst_sl_thold_3,
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pc_fu_func_sl_thold_3,
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pc_fu_func_slp_sl_thold_3,
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pc_fu_gptr_sl_thold_3,
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pc_fu_time_sl_thold_3,
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pc_fu_ary_nsl_thold_3,
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pc_fu_cfg_sl_thold_3,
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pc_fu_repr_sl_thold_3,
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pc_fu_fce_3,
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tc_ac_ccflush_dc,
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tc_ac_scan_diag_dc,
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abst_sl_thold_1,
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func_sl_thold_1,
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time_sl_thold_1,
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ary_nsl_thold_1,
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cfg_sl_thold_1,
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gptr_sl_thold_0,
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func_slp_sl_thold_1,
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fce_1,
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sg_1,
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clkoff_dc_b,
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act_dis,
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delay_lclkr_dc,
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mpw1_dc_b,
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mpw2_dc_b,
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repr_scan_in,
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repr_scan_out,
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gptr_scan_in,
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gptr_scan_out
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);
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inout vdd;
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inout gnd;
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input [0:`NCLK_WIDTH-1] nclk;
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input [0:1] pc_fu_sg_3;
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input pc_fu_abst_sl_thold_3;
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input [0:1] pc_fu_func_sl_thold_3;
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input [0:1] pc_fu_func_slp_sl_thold_3;
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input pc_fu_gptr_sl_thold_3;
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input pc_fu_time_sl_thold_3;
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input pc_fu_ary_nsl_thold_3;
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input pc_fu_cfg_sl_thold_3;
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input pc_fu_repr_sl_thold_3;
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input pc_fu_fce_3;
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input tc_ac_ccflush_dc;
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input tc_ac_scan_diag_dc;
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output abst_sl_thold_1;
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output [0:1] func_sl_thold_1;
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output time_sl_thold_1;
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output ary_nsl_thold_1;
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output cfg_sl_thold_1;
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output gptr_sl_thold_0;
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output func_slp_sl_thold_1;
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output fce_1;
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output [0:1] sg_1;
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output clkoff_dc_b;
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output act_dis;
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output [0:9] delay_lclkr_dc;
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output [0:9] mpw1_dc_b;
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output [0:1] mpw2_dc_b;
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input repr_scan_in; //tc_ac_repr_scan_in(2)
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output repr_scan_out; //tc_ac_repr_scan_in(2)
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input gptr_scan_in;
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output gptr_scan_out;
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//--
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wire abst_sl_thold_2;
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wire time_sl_thold_2;
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wire [0:1] func_sl_thold_2;
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wire func_slp_sl_thold_2;
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wire gptr_sl_thold_0_int;
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wire gptr_sl_thold_2;
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wire ary_nsl_thold_2;
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wire cfg_sl_thold_2;
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wire repr_sl_thold_2;
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wire [0:1] sg_2;
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wire fce_2;
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wire gptr_sl_thold_1;
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wire repr_sl_thold_1;
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wire [0:1] sg_1_int;
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wire repr_sl_thold_0;
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wire repr_sl_force;
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wire repr_sl_thold_0_b;
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wire repr_in;
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wire repr_UNUSED;
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(* analysis_not_assigned="true" *)
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(* analysis_not_referenced="true" *)
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wire spare_unused;
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wire sg_0;
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wire gptr_sio;
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wire [0:9] prv_delay_lclkr_dc;
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wire [0:9] prv_mpw1_dc_b;
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wire [0:1] prv_mpw2_dc_b;
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wire prv_act_dis;
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wire prv_clkoff_dc_b;
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wire tihi;
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wire tiup;
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assign tihi = 1'b1;
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assign tiup = 1'b1;
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tri_plat #(.WIDTH(12)) perv_3to2_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({
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pc_fu_func_sl_thold_3[0:1],
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pc_fu_gptr_sl_thold_3,
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pc_fu_abst_sl_thold_3,
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pc_fu_sg_3[0:1],
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pc_fu_time_sl_thold_3,
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pc_fu_fce_3,
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pc_fu_ary_nsl_thold_3,
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pc_fu_cfg_sl_thold_3,
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pc_fu_repr_sl_thold_3,
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pc_fu_func_slp_sl_thold_3[0]}),
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.q({
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func_sl_thold_2[0:1],
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gptr_sl_thold_2,
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abst_sl_thold_2,
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sg_2[0:1],
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time_sl_thold_2,
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fce_2,
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ary_nsl_thold_2,
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cfg_sl_thold_2,
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repr_sl_thold_2,
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func_slp_sl_thold_2})
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);
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tri_plat #(.WIDTH(12)) perv_2to1_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({
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func_sl_thold_2[0:1],
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gptr_sl_thold_2,
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abst_sl_thold_2,
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sg_2[0:1],
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time_sl_thold_2,
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fce_2,
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ary_nsl_thold_2,
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cfg_sl_thold_2,
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repr_sl_thold_2,
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func_slp_sl_thold_2}),
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.q({
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func_sl_thold_1[0:1],
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gptr_sl_thold_1,
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abst_sl_thold_1,
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sg_1_int[0:1],
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time_sl_thold_1,
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fce_1,
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ary_nsl_thold_1,
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cfg_sl_thold_1,
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repr_sl_thold_1,
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func_slp_sl_thold_1})
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);
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assign sg_1[0:1] = sg_1_int[0:1];
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tri_plat #(.WIDTH(3)) perv_1to0_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(tc_ac_ccflush_dc),
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.din({ gptr_sl_thold_1,
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sg_1_int[0],
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repr_sl_thold_1}),
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.q({ gptr_sl_thold_0_int,
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sg_0,
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repr_sl_thold_0})
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);
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assign gptr_sl_thold_0 = gptr_sl_thold_0_int;
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// Pipeline mapping of mpw1_b and delay_lclkr, mpw2_b
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// RF0 8 1
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// RF1 0 0
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// EX1 1 0
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// EX2 2 0
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// EX3 3 0
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// EX4 4 0
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// EX5 5 1
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// EX6 6 1
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// EX7 7 1
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// Ctrl 9 1
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tri_lcbcntl_mac perv_lcbctrl0(
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.vdd(vdd),
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.gnd(gnd),
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.sg(sg_0),
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.nclk(nclk),
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.scan_in(gptr_scan_in),
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.scan_diag_dc(tc_ac_scan_diag_dc),
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.thold(gptr_sl_thold_0_int),
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.clkoff_dc_b(prv_clkoff_dc_b),
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.delay_lclkr_dc(prv_delay_lclkr_dc[0:4]),
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.act_dis_dc(),
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.mpw1_dc_b(prv_mpw1_dc_b[0:4]),
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.mpw2_dc_b(prv_mpw2_dc_b[0]),
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.scan_out(gptr_sio)
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);
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tri_lcbcntl_mac perv_lcbctrl1(
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.vdd(vdd),
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.gnd(gnd),
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.sg(sg_0),
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.nclk(nclk),
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.scan_in(gptr_sio),
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.scan_diag_dc(tc_ac_scan_diag_dc),
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.thold(gptr_sl_thold_0_int),
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.clkoff_dc_b(),
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.delay_lclkr_dc(prv_delay_lclkr_dc[5:9]),
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.act_dis_dc(),
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.mpw1_dc_b(prv_mpw1_dc_b[5:9]),
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.mpw2_dc_b(prv_mpw2_dc_b[1]),
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.scan_out(gptr_scan_out)
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);
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//Outputs
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assign delay_lclkr_dc[0:9] = prv_delay_lclkr_dc[0:9];
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assign mpw1_dc_b[0:9] = prv_mpw1_dc_b[0:9];
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assign mpw2_dc_b[0:1] = prv_mpw2_dc_b[0:1];
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//never disable act pins, they are used functionally
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assign prv_act_dis = 1'b0;
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assign act_dis = prv_act_dis;
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assign clkoff_dc_b = prv_clkoff_dc_b;
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// Repower latch for repr scan ins/outs
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tri_lcbor repr_sl_lcbor_0(
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.clkoff_b(prv_clkoff_dc_b),
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.thold(repr_sl_thold_0),
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.sg(sg_0),
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.act_dis(prv_act_dis),
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.force_t(repr_sl_force),
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.thold_b(repr_sl_thold_0_b)
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);
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assign repr_in = 1'b0;
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tri_rlmreg_p #(.INIT(0), .WIDTH(1)) repr_rpwr_lat(
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.nclk(nclk),
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.act(tihi),
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.force_t(repr_sl_force),
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.d_mode(tiup),
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.delay_lclkr(prv_delay_lclkr_dc[9]),
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.mpw1_b(prv_mpw1_dc_b[9]),
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.mpw2_b(prv_mpw2_dc_b[1]),
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.thold_b(repr_sl_thold_0_b),
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.sg(sg_0),
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.vd(vdd),
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.gd(gnd),
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.scin(repr_scan_in),
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.scout(repr_scan_out),
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//-------------------------------------------
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.din(repr_in),
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//-------------------------------------------
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.dout(repr_UNUSED)
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);
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// Unused logic
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assign spare_unused = pc_fu_func_slp_sl_thold_3[1];
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endmodule
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