478 lines
15 KiB
Verilog
478 lines
15 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module fu_lza(
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vdd,
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gnd,
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clkoff_b,
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act_dis,
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flush,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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sg_1,
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thold_1,
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fpu_enable,
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nclk,
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f_lza_si,
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f_lza_so,
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ex2_act_b,
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f_sa3_ex4_s,
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f_sa3_ex4_c,
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f_alg_ex3_effsub_eac_b,
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f_lze_ex3_lzo_din,
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f_lze_ex4_sh_rgt_amt,
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f_lze_ex4_sh_rgt_en,
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f_lza_ex5_no_lza_edge,
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f_lza_ex5_lza_amt,
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f_lza_ex5_lza_dcd64_cp1,
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f_lza_ex5_lza_dcd64_cp2,
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f_lza_ex5_lza_dcd64_cp3,
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f_lza_ex5_sh_rgt_en,
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f_lza_ex5_sh_rgt_en_eov,
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f_lza_ex5_lza_amt_eov
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);
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inout vdd;
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inout gnd;
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input clkoff_b; // tiup
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input act_dis; // ??tidn??
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input flush; // ??tidn??
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input [3:4] delay_lclkr; // tidn,
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input [3:4] mpw1_b; // tidn,
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input [0:0] mpw2_b; // tidn,
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input sg_1;
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input thold_1;
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input fpu_enable; //dc_act
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input [0:`NCLK_WIDTH-1] nclk;
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input f_lza_si; //perv
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output f_lza_so; //perv
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input ex2_act_b; //act
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input [0:162] f_sa3_ex4_s; // data
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input [53:161] f_sa3_ex4_c; // data
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input f_alg_ex3_effsub_eac_b;
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input [0:162] f_lze_ex3_lzo_din;
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input [0:7] f_lze_ex4_sh_rgt_amt;
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input f_lze_ex4_sh_rgt_en;
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output f_lza_ex5_no_lza_edge; //fpic
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output [0:7] f_lza_ex5_lza_amt; //fnrm
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output [0:2] f_lza_ex5_lza_dcd64_cp1; //fnrm
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output [0:1] f_lza_ex5_lza_dcd64_cp2; //fnrm
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output [0:0] f_lza_ex5_lza_dcd64_cp3; //fnrm
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output f_lza_ex5_sh_rgt_en;
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output f_lza_ex5_sh_rgt_en_eov;
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output [0:7] f_lza_ex5_lza_amt_eov; //feov
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// ENTITY
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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wire thold_0_b;
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wire thold_0;
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wire force_t;
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wire sg_0;
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wire ex3_act;
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wire ex4_act;
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wire ex2_act;
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(* analysis_not_referenced="TRUE" *)
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wire [0:3] act_spare_unused;
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//--------------------------------------
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wire [0:5] act_so; //SCAN
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wire [0:5] act_si; //SCAN
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wire [0:162] ex4_lzo_so; //SCAN
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wire [0:162] ex4_lzo_si; //SCAN
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wire [0:0] ex4_sub_so; //SCAN
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wire [0:0] ex4_sub_si; //SCAN
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wire [0:15] ex5_amt_so; //SCAN
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wire [0:15] ex5_amt_si; //SCAN
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wire [0:8] ex5_dcd_so; //SCAN
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wire [0:8] ex5_dcd_si; //SCAN
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//--------------------------------------
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wire ex4_lza_any_b;
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wire ex4_effsub;
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wire ex5_no_edge;
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wire ex4_no_edge_b;
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wire [0:162] ex4_lzo;
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wire [0:7] ex4_lza_amt_b;
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wire [0:7] ex5_amt_eov;
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wire [0:7] ex5_amt;
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wire [0:162] ex4_sum;
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wire [53:162] ex4_car;
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wire [0:162] ex4_lv0_or;
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wire ex4_sh_rgt_en_b;
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wire ex4_lv6_or_0_b;
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wire ex4_lv6_or_1_b;
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wire ex4_lv6_or_0_t;
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wire ex4_lv6_or_1_t;
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wire ex4_lza_dcd64_0_b;
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wire ex4_lza_dcd64_1_b;
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wire ex4_lza_dcd64_2_b;
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wire [0:2] ex5_lza_dcd64_cp1;
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wire [0:1] ex5_lza_dcd64_cp2;
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wire [0:0] ex5_lza_dcd64_cp3;
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wire ex5_sh_rgt_en;
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wire ex5_sh_rgt_en_eov;
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wire ex3_effsub_eac;
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wire ex3_effsub_eac_b;
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wire [0:162] ex4_lzo_b;
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wire [0:162] ex4_lzo_l2_b;
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wire ex4_lv6_or_0;
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wire ex4_lv6_or_1;
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wire [0:7] ex4_rgt_amt_b;
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wire lza_ex5_d1clk;
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wire lza_ex5_d2clk;
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wire lza_ex4_d1clk;
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wire lza_ex4_d2clk;
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wire [0:`NCLK_WIDTH-1] lza_ex5_lclk;
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wire [0:`NCLK_WIDTH-1] lza_ex4_lclk;
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//=###############################################################
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//= map block attributes
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//=###############################################################
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//=###############################################################
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//= pervasive
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//=###############################################################
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tri_plat thold_reg_0(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(flush),
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.din(thold_1),
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.q(thold_0)
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);
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tri_plat sg_reg_0(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(flush),
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.din(sg_1),
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.q(sg_0)
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);
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tri_lcbor lcbor_0(
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.clkoff_b(clkoff_b),
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.thold(thold_0),
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.sg(sg_0),
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.act_dis(act_dis),
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.force_t(force_t),
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.thold_b(thold_0_b)
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);
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//=###############################################################
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//= act
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//=###############################################################
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assign ex2_act = (~ex2_act_b);
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tri_rlmreg_p #(.WIDTH(6), .NEEDS_SRESET(0)) act_lat(
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.force_t(force_t), //i-- tidn,
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.d_mode(tiup),
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.delay_lclkr(delay_lclkr[3]), //i-- tidn,
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.mpw1_b(mpw1_b[3]), //i-- tidn,
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.mpw2_b(mpw2_b[0]), //i-- tidn,
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(fpu_enable),
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.thold_b(thold_0_b),
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.sg(sg_0),
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.scout(act_so),
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.scin(act_si),
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//-----------------
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.din({ act_spare_unused[0],
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act_spare_unused[1],
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ex2_act,
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ex3_act,
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act_spare_unused[2],
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act_spare_unused[3]}),
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//-----------------
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.dout({ act_spare_unused[0],
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act_spare_unused[1],
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ex3_act,
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ex4_act,
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act_spare_unused[2],
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act_spare_unused[3]})
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);
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tri_lcbnd lza_ex4_lcb(
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.delay_lclkr(delay_lclkr[3]), // tidn ,--in
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.mpw1_b(mpw1_b[3]), // tidn ,--in
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.mpw2_b(mpw2_b[0]), // tidn ,--in
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.force_t(force_t), // tidn ,--in
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.nclk(nclk), //in
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.vd(vdd), //inout
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.gd(gnd), //inout
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.act(ex3_act), //in
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.sg(sg_0), //in
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.thold_b(thold_0_b), //in
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.d1clk(lza_ex4_d1clk), //out
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.d2clk(lza_ex4_d2clk), //out
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.lclk(lza_ex4_lclk) //out
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);
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tri_lcbnd lza_ex5_lcb(
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.delay_lclkr(delay_lclkr[4]), // tidn ,--in
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.mpw1_b(mpw1_b[4]), // tidn ,--in
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.mpw2_b(mpw2_b[0]), // tidn ,--in
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.force_t(force_t), // tidn ,--in
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.nclk(nclk), //in
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.vd(vdd), //inout
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.gd(gnd), //inout
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.act(ex4_act), //in
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.sg(sg_0), //in
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.thold_b(thold_0_b), //in
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.d1clk(lza_ex5_d1clk), //out
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.d2clk(lza_ex5_d2clk), //out
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.lclk(lza_ex5_lclk) //out
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);
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//=###############################################################
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//= ex4 latches
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//=###############################################################
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tri_inv_nlats #(.WIDTH(163), .NEEDS_SRESET(0)) ex4_lzo_lat(
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.vd(vdd),
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.gd(gnd),
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.lclk(lza_ex4_lclk), // lclk.clk
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.d1clk(lza_ex4_d1clk),
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.d2clk(lza_ex4_d2clk),
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.scanin(ex4_lzo_si),
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.scanout(ex4_lzo_so),
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.d(f_lze_ex3_lzo_din[0:162]),
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.qb(ex4_lzo_l2_b[0:162])
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);
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assign ex4_lzo[0:162] = (~ex4_lzo_l2_b[0:162]);
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assign ex4_lzo_b[0:162] = (~ex4_lzo[0:162]);
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assign ex3_effsub_eac = (~f_alg_ex3_effsub_eac_b);
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assign ex3_effsub_eac_b = (~ex3_effsub_eac);
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tri_inv_nlats #(.WIDTH(1), .NEEDS_SRESET(0)) ex4_sub_lat(
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.vd(vdd),
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.gd(gnd),
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.lclk(lza_ex4_lclk), // lclk.clk
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.d1clk(lza_ex4_d1clk),
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.d2clk(lza_ex4_d2clk),
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.scanin(ex4_sub_si[0]),
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.scanout(ex4_sub_so[0]),
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.d(ex3_effsub_eac_b),
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.qb(ex4_effsub)
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);
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assign ex4_sum[0:52] = f_sa3_ex4_s[0:52];
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//=###############################################################
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//= ex4 logic
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//=###############################################################
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assign ex4_sum[53:162] = f_sa3_ex4_s[53:162];
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assign ex4_car[53:162] = {f_sa3_ex4_c[53:161], tidn};
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//=#------------------------------------------------
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//=#-- EDGE DETECTION
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//=#------------------------------------------------
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fu_lza_ej lzaej(
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.effsub(ex4_effsub), //i--
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.sum(ex4_sum[0:162]), //i--
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.car(ex4_car[53:162]), //i--
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.lzo_b(ex4_lzo_b[0:162]), //i--
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.edge_t(ex4_lv0_or[0:162]) //o--
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);
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//=#------------------------------------------------
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//=#-- ENCODING TREE (CLZ) count leading zeroes
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//=#------------------------------------------------
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fu_lza_clz lzaclz(
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.lv0_or(ex4_lv0_or[0:162]), //i--
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.lv6_or_0(ex4_lv6_or_0), //o--
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.lv6_or_1(ex4_lv6_or_1), //o--
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.lza_any_b(ex4_lza_any_b), //i--
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.lza_amt_b(ex4_lza_amt_b[0:7]) //o--
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);
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assign ex4_no_edge_b = (~ex4_lza_any_b);
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//=###############################################################
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//= ex5 latches
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//=###############################################################
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assign ex4_rgt_amt_b[0:7] = (~f_lze_ex4_sh_rgt_amt[0:7]);
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assign ex4_sh_rgt_en_b = (~f_lze_ex4_sh_rgt_en);
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assign ex4_lv6_or_0_b = (~ex4_lv6_or_0);
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assign ex4_lv6_or_1_b = (~ex4_lv6_or_1);
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assign ex4_lv6_or_0_t = (~ex4_lv6_or_0_b);
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assign ex4_lv6_or_1_t = (~ex4_lv6_or_1_b);
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assign ex4_lza_dcd64_0_b = (~(ex4_lv6_or_0_t & ex4_sh_rgt_en_b));
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assign ex4_lza_dcd64_1_b = (~(ex4_lv6_or_0_b & ex4_lv6_or_1_t & ex4_sh_rgt_en_b));
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assign ex4_lza_dcd64_2_b = (~(ex4_lv6_or_0_b & ex4_lv6_or_1_b & ex4_sh_rgt_en_b));
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tri_inv_nlats #(.WIDTH(9), .NEEDS_SRESET(0)) ex5_dcd_lat(
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.vd(vdd),
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.gd(gnd),
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.lclk(lza_ex5_lclk), // lclk.clk
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.d1clk(lza_ex5_d1clk),
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.d2clk(lza_ex5_d2clk),
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.scanin(ex5_dcd_si[0:8]),
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.scanout(ex5_dcd_so[0:8]),
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.d({ex4_lza_dcd64_0_b, //( 0)
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ex4_lza_dcd64_0_b, //( 1)
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ex4_lza_dcd64_0_b, //( 2)
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ex4_lza_dcd64_1_b, //( 3)
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ex4_lza_dcd64_1_b, //( 4)
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ex4_lza_dcd64_2_b, //( 5)
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ex4_sh_rgt_en_b, //( 6)
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ex4_sh_rgt_en_b, //( 7)
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ex4_no_edge_b}), //(24)
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//-----------------
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.qb({ex5_lza_dcd64_cp1[0], //( 6)
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ex5_lza_dcd64_cp2[0], //( 9)
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ex5_lza_dcd64_cp3[0], //( 1)
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ex5_lza_dcd64_cp1[1], //( 7)
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ex5_lza_dcd64_cp2[1], //( 0)
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ex5_lza_dcd64_cp1[2], //( 8)
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ex5_sh_rgt_en, //( 2)
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ex5_sh_rgt_en_eov, //( 3)
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ex5_no_edge}) //(24)
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);
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||
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||
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tri_nand2_nlats #(.WIDTH(16), .NEEDS_SRESET(0)) ex5_amt_lat(
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.vd(vdd),
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|
.gd(gnd),
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||
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.lclk(lza_ex5_lclk), //in --lclk.clk
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.d1clk(lza_ex5_d1clk), //in
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.d2clk(lza_ex5_d2clk), //in
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.scanin(ex5_amt_si[0:15]),
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||
|
.scanout(ex5_amt_so[0:15]),
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||
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.a1({ ex4_lza_amt_b[0], //( 8)
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ex4_lza_amt_b[0], //( 9)
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|
ex4_lza_amt_b[1], //(10)
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||
|
ex4_lza_amt_b[1], //(11)
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||
|
ex4_lza_amt_b[2], //(12)
|
||
|
ex4_lza_amt_b[2], //(13)
|
||
|
ex4_lza_amt_b[3], //(14)
|
||
|
ex4_lza_amt_b[3], //(15)
|
||
|
ex4_lza_amt_b[4], //(16)
|
||
|
ex4_lza_amt_b[4], //(17)
|
||
|
ex4_lza_amt_b[5], //(18)
|
||
|
ex4_lza_amt_b[5], //(19)
|
||
|
ex4_lza_amt_b[6], //(20)
|
||
|
ex4_lza_amt_b[6], //(21)
|
||
|
ex4_lza_amt_b[7], //(22)
|
||
|
ex4_lza_amt_b[7]}), //(23)
|
||
|
|
||
|
.a2({ ex4_rgt_amt_b[0], //( 8)
|
||
|
ex4_rgt_amt_b[0], //( 9)
|
||
|
ex4_rgt_amt_b[1], //(10)
|
||
|
ex4_rgt_amt_b[1], //(11)
|
||
|
ex4_rgt_amt_b[2], //(12)
|
||
|
ex4_rgt_amt_b[2], //(13)
|
||
|
ex4_rgt_amt_b[3], //(14)
|
||
|
ex4_rgt_amt_b[3], //(15)
|
||
|
ex4_rgt_amt_b[4], //(16)
|
||
|
ex4_rgt_amt_b[4], //(17)
|
||
|
ex4_rgt_amt_b[5], //(18)
|
||
|
ex4_rgt_amt_b[5], //(19)
|
||
|
ex4_rgt_amt_b[6], //(20)
|
||
|
ex4_rgt_amt_b[6], //(21)
|
||
|
ex4_rgt_amt_b[7], //(22)
|
||
|
ex4_rgt_amt_b[7] }), //(23)
|
||
|
|
||
|
//-----------------
|
||
|
.qb({ ex5_amt[0], //( 0)
|
||
|
ex5_amt_eov[0], //( 8)
|
||
|
ex5_amt[1], //(11)
|
||
|
ex5_amt_eov[1], //(19)
|
||
|
ex5_amt[2], //(12)
|
||
|
ex5_amt_eov[2], //(10)
|
||
|
ex5_amt[3], //(13)
|
||
|
ex5_amt_eov[3], //(11)
|
||
|
ex5_amt[4], //(14)
|
||
|
ex5_amt_eov[4], //(12)
|
||
|
ex5_amt[5], //(15)
|
||
|
ex5_amt_eov[5], //(13)
|
||
|
ex5_amt[6], //(26)
|
||
|
ex5_amt_eov[6], //(24)
|
||
|
ex5_amt[7], //(27)
|
||
|
ex5_amt_eov[7]}) //(24)
|
||
|
);
|
||
|
|
||
|
assign f_lza_ex5_sh_rgt_en = ex5_sh_rgt_en;
|
||
|
assign f_lza_ex5_sh_rgt_en_eov = ex5_sh_rgt_en_eov;
|
||
|
|
||
|
assign f_lza_ex5_lza_amt = ex5_amt[0:7]; //output-- --fnrm--
|
||
|
|
||
|
assign f_lza_ex5_lza_dcd64_cp1[0:2] = ex5_lza_dcd64_cp1[0:2]; //ouptut-- --fnrm
|
||
|
assign f_lza_ex5_lza_dcd64_cp2[0:1] = ex5_lza_dcd64_cp2[0:1]; //ouptut-- --fnrm
|
||
|
assign f_lza_ex5_lza_dcd64_cp3[0] = ex5_lza_dcd64_cp3[0]; //ouptut-- --fnrm
|
||
|
|
||
|
assign f_lza_ex5_lza_amt_eov = ex5_amt_eov[0:7]; //output-- --feov--
|
||
|
assign f_lza_ex5_no_lza_edge = ex5_no_edge; //output-- --fpic--
|
||
|
|
||
|
//=###############################################################
|
||
|
//= scan string
|
||
|
//=###############################################################
|
||
|
|
||
|
assign ex4_lzo_si[0:162] = {ex4_lzo_so[1:162], f_lza_si};
|
||
|
assign ex4_sub_si[0] = ex4_lzo_so[0];
|
||
|
assign ex5_amt_si[0:15] = {ex5_amt_so[1:15], ex4_sub_so[0]};
|
||
|
assign ex5_dcd_si[0:8] = {ex5_dcd_so[1:8], ex5_amt_so[0]};
|
||
|
assign act_si[0:5] = {act_so[1:5], ex5_dcd_so[0]};
|
||
|
assign f_lza_so = act_so[0];
|
||
|
|
||
|
endmodule
|