534 lines
18 KiB
Verilog
534 lines
18 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`define THREADS1
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`include "tri_a2o.vh"
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module c_wrapper(
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// vcs,
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// vdd,
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// gnd,
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clk,
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clk2x,
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clk4x,
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reset,
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an_ac_coreid,
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an_ac_pm_thread_stop,
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an_ac_ext_interrupt,
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an_ac_crit_interrupt,
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an_ac_perf_interrupt,
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an_ac_external_mchk,
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an_ac_flh2l2_gate,
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an_ac_reservation_vld,
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ac_an_debug_trigger,
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an_ac_debug_stop,
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an_ac_tb_update_enable,
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an_ac_tb_update_pulse,
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an_ac_hang_pulse,
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ac_an_pm_thread_running,
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ac_an_machine_check,
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ac_an_recov_err,
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ac_an_checkstop,
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ac_an_local_checkstop,
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an_ac_stcx_complete,
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an_ac_stcx_pass,
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an_ac_reld_data_vld,
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an_ac_reld_core_tag,
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an_ac_reld_data,
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an_ac_reld_qw,
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an_ac_reld_ecc_err,
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an_ac_reld_ecc_err_ue,
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an_ac_reld_data_coming,
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an_ac_reld_crit_qw,
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an_ac_reld_l1_dump,
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an_ac_req_ld_pop,
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an_ac_req_st_pop,
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an_ac_req_st_gather,
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an_ac_sync_ack,
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ac_an_req_pwr_token,
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ac_an_req,
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ac_an_req_ra,
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ac_an_req_ttype,
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ac_an_req_thread,
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ac_an_req_wimg_w,
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ac_an_req_wimg_i,
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ac_an_req_wimg_m,
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ac_an_req_wimg_g,
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ac_an_req_user_defined,
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ac_an_req_ld_core_tag,
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ac_an_req_ld_xfr_len,
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ac_an_st_byte_enbl,
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ac_an_st_data,
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ac_an_req_endian,
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ac_an_st_data_pwr_token
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);
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input clk;
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input clk2x;
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input clk4x;
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input reset;
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input [0:7] an_ac_coreid;
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input [0:3] an_ac_pm_thread_stop;
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input [0:3] an_ac_ext_interrupt;
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input [0:3] an_ac_crit_interrupt;
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input [0:3] an_ac_perf_interrupt;
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input [0:3] an_ac_external_mchk;
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input an_ac_flh2l2_gate; // Gate L1 Hit forwarding SPR config bit
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input [0:3] an_ac_reservation_vld;
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output [0:3] ac_an_debug_trigger;
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input an_ac_debug_stop;
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input an_ac_tb_update_enable;
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input an_ac_tb_update_pulse;
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input [0:3] an_ac_hang_pulse;
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output [0:3] ac_an_pm_thread_running;
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output [0:3] ac_an_machine_check;
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output [0:2] ac_an_recov_err;
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output [0:2] ac_an_checkstop;
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output [0:2] ac_an_local_checkstop;
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wire scan_in;
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wire scan_out;
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// Pervasive clock control
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wire an_ac_rtim_sl_thold_8;
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wire an_ac_func_sl_thold_8;
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wire an_ac_func_nsl_thold_8;
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wire an_ac_ary_nsl_thold_8;
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wire an_ac_sg_8;
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wire an_ac_fce_8;
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wire [0:7] an_ac_abst_scan_in;
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// L2 STCX complete
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input [0:3] an_ac_stcx_complete;
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input [0:3] an_ac_stcx_pass;
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// ICBI ACK Interface
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wire an_ac_icbi_ack;
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wire [0:1] an_ac_icbi_ack_thread;
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// Back invalidate interface
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wire an_ac_back_inv;
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wire [22:63] an_ac_back_inv_addr;
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wire [0:4] an_ac_back_inv_target; // connect to bit(0)
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wire an_ac_back_inv_local;
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wire an_ac_back_inv_lbit;
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wire an_ac_back_inv_gs;
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wire an_ac_back_inv_ind;
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wire [0:7] an_ac_back_inv_lpar_id;
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wire ac_an_back_inv_reject;
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wire [0:7] ac_an_lpar_id;
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// L2 Reload Inputs
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input an_ac_reld_data_vld; // reload data is coming next cycle
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input [0:4] an_ac_reld_core_tag; // reload data destinatoin tag (which load queue)
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input [0:127] an_ac_reld_data; // Reload Data
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input [57:59] an_ac_reld_qw; // quadword address of reload data beat
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input an_ac_reld_ecc_err; // Reload Data contains a Correctable ECC error
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input an_ac_reld_ecc_err_ue; // Reload Data contains an Uncorrectable ECC error
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input an_ac_reld_data_coming;
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wire an_ac_reld_ditc;
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input an_ac_reld_crit_qw;
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input an_ac_reld_l1_dump;
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wire [0:3] an_ac_req_spare_ctrl_a1; // spare control bits from L2
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// load/store credit control
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input an_ac_req_ld_pop; // credit for a load (L2 can take a load command)
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input an_ac_req_st_pop; // credit for a store (L2 can take a store command)
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input an_ac_req_st_gather; // credit for a store due to L2 gathering of store commands
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input [0:3] an_ac_sync_ack;
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//SCOM Satellite
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wire [0:3] an_ac_scom_sat_id;
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wire an_ac_scom_dch;
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wire an_ac_scom_cch;
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wire ac_an_scom_dch;
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wire ac_an_scom_cch;
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// FIR and Error Signals
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wire [0:0] ac_an_special_attn;
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wire ac_an_trace_error;
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wire ac_an_livelock_active;
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wire an_ac_checkstop;
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// Perfmon Event Bus
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wire [0:3] ac_an_event_bus0;
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wire [0:3] ac_an_event_bus1;
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// Reset related
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wire an_ac_reset_1_complete;
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wire an_ac_reset_2_complete;
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wire an_ac_reset_3_complete;
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wire an_ac_reset_wd_complete;
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// Power Management
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wire [0:0] an_ac_pm_fetch_halt;
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wire ac_an_power_managed;
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wire ac_an_rvwinkle_mode;
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// Clock, Test, and LCB Controls
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wire an_ac_gsd_test_enable_dc;
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wire an_ac_gsd_test_acmode_dc;
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wire an_ac_ccflush_dc;
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wire an_ac_ccenable_dc;
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wire an_ac_lbist_en_dc;
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wire an_ac_lbist_ip_dc;
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wire an_ac_lbist_ac_mode_dc;
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wire an_ac_scan_diag_dc;
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wire an_ac_scan_dis_dc_b;
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//Thold input to clock control macro
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wire [0:8] an_ac_scan_type_dc;
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// Pervasive
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wire ac_an_reset_1_request;
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wire ac_an_reset_2_request;
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wire ac_an_reset_3_request;
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wire ac_an_reset_wd_request;
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wire an_ac_lbist_ary_wrt_thru_dc;
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wire [0:0] an_ac_sleep_en;
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wire [0:3] an_ac_chipid_dc;
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wire [0:0] an_ac_uncond_dbg_event;
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wire [0:31] ac_an_debug_bus;
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wire ac_an_coretrace_first_valid; // coretrace_ctrls[0]
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wire ac_an_coretrace_valid; // coretrace_ctrls[1]
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wire [0:1] ac_an_coretrace_type; // coretrace_ctrls[2:3]
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// L2 Outputs
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output ac_an_req_pwr_token; // power token for command coming next cycle
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output ac_an_req; // command request valid
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output [22:63] ac_an_req_ra; // real address for request
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output [0:5] ac_an_req_ttype; // command (transaction) type
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output [0:2] ac_an_req_thread; // encoded thread ID
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output ac_an_req_wimg_w; // write-through
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output ac_an_req_wimg_i; // cache-inhibited
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output ac_an_req_wimg_m; // memory coherence required
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output ac_an_req_wimg_g; // guarded memory
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output [0:3] ac_an_req_user_defined; // User Defined Bits
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wire [0:3] ac_an_req_spare_ctrl_a0; // Spare bits
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output [0:4] ac_an_req_ld_core_tag; // load command tag (which load Q)
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output [0:2] ac_an_req_ld_xfr_len; // transfer length for non-cacheable load
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output [0:31] ac_an_st_byte_enbl; // byte enables for store data
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output [0:255] ac_an_st_data; // store data
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output ac_an_req_endian; // endian mode (0=big endian, 1=little endian)
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output ac_an_st_data_pwr_token; // store data power token
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// constant EXPAND_TYPE : integer $ 1;
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wire clk_reset;
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wire [0:15] rate;
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wire [0:3] div2;
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wire [0:3] div3;
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wire [0:`NCLK_WIDTH-1] nclk;
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wire [1:3] osc;
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// component variable_osc
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// Pervasive clock control
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// L2 STCX complete
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// ICBI ACK Interface
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// Back invalidate interface
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// connect to bit(0)
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// L2 Reload Inputs
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// reload data is coming next cycle
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// reload data destinatoin tag (which load queue)
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// Reload Data
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// quadword address of reload data beat
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// Reload Data contains a Correctable ECC error
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// Reload Data contains an Uncorrectable ECC error
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// spare control bits from L2
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// load/store credit control
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// Gate L1 Hit forwarding SPR config bit
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// credit for a load (L2 can take a load command)
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// credit for a store (L2 can take a store command)
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// credit for a store due to L2 gathering of store commands
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//SCOM Satellite
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// FIR and Error Signals
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// Perfmon Event Bus
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// Reset related
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// Power Management
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// Clock, Test, and LCB Controls
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//Thold input to clock control macro
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// PSRO Sensors
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// ABIST Engine
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// Bolt-On ABIST system interface
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// Pervasive
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// L2 Outputs
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// power token for command coming next cycle
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// command request valid
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// real address for request
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// command (transaction) type
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// encoded thread ID
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// write-through
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// cache-inhibited
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// memory coherence required
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// guarded memory
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// User Defined Bits
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// Spare bits
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// load command tag (which load Q)
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// transfer length for non-cacheable load
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// byte enables for store data
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// store data
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// endian mode (0=big endian, 1=little endian)
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// store data power token
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assign rate = 16'b0000000100000000;
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assign div2 = 4'b0010;
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assign div3 = 4'b0100;
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assign clk_reset = 1'b1;
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assign an_ac_ccflush_dc = 1'b0;
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assign an_ac_rtim_sl_thold_8= 1'b0;
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assign an_ac_func_sl_thold_8= 1'b0;
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assign an_ac_func_nsl_thold_8= 1'b0;
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assign an_ac_ary_nsl_thold_8= 1'b0;
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assign an_ac_sg_8= 1'b0;
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assign an_ac_fce_8= 1'b0;
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assign scan_in = 'b0;
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assign an_ac_abst_scan_in = 'b0;
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assign an_ac_icbi_ack = 'b0;
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assign an_ac_icbi_ack_thread = 'b0;
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assign an_ac_back_inv = 'b0;
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assign an_ac_back_inv_addr = 'b0;
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assign an_ac_back_inv_target = 'b0;
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assign an_ac_back_inv_local = 'b0;
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assign an_ac_back_inv_lbit = 'b0;
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assign an_ac_back_inv_gs = 'b0;
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assign an_ac_back_inv_ind = 'b0;
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assign an_ac_back_inv_lpar_id = 'b0;
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assign an_ac_reld_ditc = 'b0;
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assign an_ac_req_spare_ctrl_a1 = 'b0;
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assign an_ac_scom_sat_id = 'b0;
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assign an_ac_scom_dch = 'b0;
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assign an_ac_scom_cch = 'b0;
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assign an_ac_checkstop = 'b0;
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assign an_ac_reset_1_complete = 'b0;
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assign an_ac_reset_2_complete = 'b0;
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assign an_ac_reset_3_complete = 'b0;
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assign an_ac_reset_wd_complete = 'b0;
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assign an_ac_pm_fetch_halt = 'b0;
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assign an_ac_gsd_test_enable_dc = 'b0;
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assign an_ac_gsd_test_acmode_dc = 'b0;
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assign an_ac_ccflush_dc = 'b0;
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assign an_ac_ccenable_dc = 'b0;
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assign an_ac_lbist_en_dc = 'b0;
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assign an_ac_lbist_ip_dc = 'b0;
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assign an_ac_lbist_ac_mode_dc = 'b0;
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assign an_ac_scan_diag_dc = 'b0;
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assign an_ac_scan_dis_dc_b = 'b0;
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assign an_ac_scan_type_dc = 'b0;
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assign an_ac_lbist_ary_wrt_thru_dc = 'b0;
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assign an_ac_sleep_en = 'b0;
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assign an_ac_chipid_dc = 'b0;
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assign an_ac_uncond_dbg_event = 'b0;
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assign nclk[0] = clk;
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assign nclk[1] = reset;
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assign nclk[2] = clk2x;
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assign nclk[3] = clk4x;
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assign nclk[4] = 'b0;
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assign nclk[5] = 'b0;
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(*dont_touch = "true" *) c c0(
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// .vcs(vcs),
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// .vdd(vdd),
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// .gnd(gnd),
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.nclk(nclk),
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.scan_in(scan_in),
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.scan_out(scan_out),
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// Pervasive clock control
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.an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
|
||
|
.an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
|
||
|
.an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
|
||
|
.an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
|
||
|
.an_ac_sg_8(an_ac_sg_8),
|
||
|
.an_ac_fce_8(an_ac_fce_8),
|
||
|
.an_ac_abst_scan_in(an_ac_abst_scan_in),
|
||
|
|
||
|
// L2 STCX complete
|
||
|
.an_ac_stcx_complete(an_ac_stcx_complete[0:`THREADS-1]),
|
||
|
.an_ac_stcx_pass(an_ac_stcx_pass[0:`THREADS-1]),
|
||
|
|
||
|
// ICBI ACK Interface
|
||
|
.an_ac_icbi_ack(an_ac_icbi_ack),
|
||
|
.an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),
|
||
|
|
||
|
// Back invalidate interface
|
||
|
.an_ac_back_inv(an_ac_back_inv),
|
||
|
.an_ac_back_inv_addr(an_ac_back_inv_addr),
|
||
|
.an_ac_back_inv_target(an_ac_back_inv_target),
|
||
|
.an_ac_back_inv_local(an_ac_back_inv_local),
|
||
|
.an_ac_back_inv_lbit(an_ac_back_inv_lbit),
|
||
|
.an_ac_back_inv_gs(an_ac_back_inv_gs),
|
||
|
.an_ac_back_inv_ind(an_ac_back_inv_ind),
|
||
|
.an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
|
||
|
.ac_an_back_inv_reject(ac_an_back_inv_reject),
|
||
|
.ac_an_lpar_id(ac_an_lpar_id),
|
||
|
|
||
|
// L2 Reload Inputs
|
||
|
.an_ac_reld_data_vld(an_ac_reld_data_vld),
|
||
|
.an_ac_reld_core_tag(an_ac_reld_core_tag),
|
||
|
.an_ac_reld_data(an_ac_reld_data),
|
||
|
.an_ac_reld_qw(an_ac_reld_qw[58:59]),
|
||
|
.an_ac_reld_ecc_err(an_ac_reld_ecc_err),
|
||
|
.an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
|
||
|
.an_ac_reld_data_coming(an_ac_reld_data_coming),
|
||
|
.an_ac_reld_ditc(an_ac_reld_ditc),
|
||
|
.an_ac_reld_crit_qw(an_ac_reld_crit_qw),
|
||
|
.an_ac_reld_l1_dump(an_ac_reld_l1_dump),
|
||
|
.an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),
|
||
|
|
||
|
// load/store credit control
|
||
|
.an_ac_flh2l2_gate(an_ac_flh2l2_gate),
|
||
|
.an_ac_req_ld_pop(an_ac_req_ld_pop),
|
||
|
.an_ac_req_st_pop(an_ac_req_st_pop),
|
||
|
.an_ac_req_st_gather(an_ac_req_st_gather),
|
||
|
.an_ac_sync_ack(an_ac_sync_ack[0:`THREADS-1]),
|
||
|
|
||
|
//SCOM Satellite
|
||
|
.an_ac_scom_sat_id(an_ac_scom_sat_id),
|
||
|
.an_ac_scom_dch(an_ac_scom_dch),
|
||
|
.an_ac_scom_cch(an_ac_scom_cch),
|
||
|
.ac_an_scom_dch(ac_an_scom_dch),
|
||
|
.ac_an_scom_cch(ac_an_scom_cch),
|
||
|
|
||
|
// FIR and Error Signals
|
||
|
.ac_an_special_attn(ac_an_special_attn),
|
||
|
.ac_an_checkstop(ac_an_checkstop),
|
||
|
.ac_an_local_checkstop(ac_an_local_checkstop),
|
||
|
.ac_an_recov_err(ac_an_recov_err),
|
||
|
.ac_an_trace_error(ac_an_trace_error),
|
||
|
.ac_an_livelock_active(ac_an_livelock_active),
|
||
|
.an_ac_checkstop(an_ac_checkstop),
|
||
|
.an_ac_external_mchk(an_ac_external_mchk[0:`THREADS-1]),
|
||
|
|
||
|
// Perfmon Event Bus
|
||
|
.ac_an_event_bus0(ac_an_event_bus0),
|
||
|
.ac_an_event_bus1(ac_an_event_bus1),
|
||
|
|
||
|
// Reset related
|
||
|
.an_ac_reset_1_complete(an_ac_reset_1_complete),
|
||
|
.an_ac_reset_2_complete(an_ac_reset_2_complete),
|
||
|
.an_ac_reset_3_complete(an_ac_reset_3_complete),
|
||
|
.an_ac_reset_wd_complete(an_ac_reset_wd_complete),
|
||
|
|
||
|
// Power Management
|
||
|
.ac_an_pm_thread_running(ac_an_pm_thread_running[0:`THREADS-1]),
|
||
|
.an_ac_pm_thread_stop(an_ac_pm_thread_stop[0:`THREADS-1]),
|
||
|
.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
|
||
|
.ac_an_power_managed(ac_an_power_managed),
|
||
|
.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
|
||
|
|
||
|
// Clock, Test, and LCB Controls
|
||
|
.an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
|
||
|
.an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
|
||
|
.an_ac_ccflush_dc(an_ac_ccflush_dc),
|
||
|
.an_ac_ccenable_dc(an_ac_ccenable_dc),
|
||
|
.an_ac_lbist_en_dc(an_ac_lbist_en_dc),
|
||
|
.an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
|
||
|
.an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
|
||
|
.an_ac_scan_diag_dc(an_ac_scan_diag_dc),
|
||
|
.an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
|
||
|
|
||
|
//Thold input to clock control macro
|
||
|
.an_ac_scan_type_dc(an_ac_scan_type_dc),
|
||
|
|
||
|
// Pervasive
|
||
|
.ac_an_reset_1_request(ac_an_reset_1_request),
|
||
|
.ac_an_reset_2_request(ac_an_reset_2_request),
|
||
|
.ac_an_reset_3_request(ac_an_reset_3_request),
|
||
|
.ac_an_reset_wd_request(ac_an_reset_wd_request),
|
||
|
.an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
|
||
|
.an_ac_reservation_vld(an_ac_reservation_vld[0:`THREADS-1]),
|
||
|
.an_ac_sleep_en(an_ac_sleep_en),
|
||
|
.an_ac_ext_interrupt(an_ac_ext_interrupt[0:`THREADS-1]),
|
||
|
.an_ac_crit_interrupt(an_ac_crit_interrupt[0:`THREADS-1]),
|
||
|
.an_ac_perf_interrupt(an_ac_perf_interrupt[0:`THREADS-1]),
|
||
|
.an_ac_hang_pulse(an_ac_hang_pulse[0:`THREADS-1]),
|
||
|
.an_ac_tb_update_enable(an_ac_tb_update_enable),
|
||
|
.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
|
||
|
.an_ac_chipid_dc(an_ac_chipid_dc),
|
||
|
.an_ac_coreid(an_ac_coreid),
|
||
|
.ac_an_machine_check(ac_an_machine_check[0:`THREADS-1]),
|
||
|
.an_ac_debug_stop(an_ac_debug_stop),
|
||
|
.ac_an_debug_trigger(ac_an_debug_trigger[0:`THREADS-1]),
|
||
|
.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
|
||
|
.ac_an_debug_bus(ac_an_debug_bus),
|
||
|
.ac_an_coretrace_first_valid(ac_an_coretrace_first_valid),
|
||
|
.ac_an_coretrace_valid(ac_an_coretrace_valid),
|
||
|
.ac_an_coretrace_type(ac_an_coretrace_type),
|
||
|
|
||
|
// L2 Outputs
|
||
|
.ac_an_req_pwr_token(ac_an_req_pwr_token),
|
||
|
.ac_an_req(ac_an_req),
|
||
|
.ac_an_req_ra(ac_an_req_ra),
|
||
|
.ac_an_req_ttype(ac_an_req_ttype),
|
||
|
.ac_an_req_thread(ac_an_req_thread),
|
||
|
.ac_an_req_wimg_w(ac_an_req_wimg_w),
|
||
|
.ac_an_req_wimg_i(ac_an_req_wimg_i),
|
||
|
.ac_an_req_wimg_m(ac_an_req_wimg_m),
|
||
|
.ac_an_req_wimg_g(ac_an_req_wimg_g),
|
||
|
.ac_an_req_user_defined(ac_an_req_user_defined),
|
||
|
.ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
|
||
|
.ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
|
||
|
.ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
|
||
|
.ac_an_st_byte_enbl(ac_an_st_byte_enbl),
|
||
|
.ac_an_st_data(ac_an_st_data),
|
||
|
.ac_an_req_endian(ac_an_req_endian),
|
||
|
.ac_an_st_data_pwr_token(ac_an_st_data_pwr_token)
|
||
|
);
|
||
|
|
||
|
endmodule
|