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427 lines
15 KiB
Verilog
427 lines
15 KiB
Verilog
2 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_64x144_1r1w.v
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// *! DESCRIPTION : 64 Entry x 144 bit array, 9 bit writeable
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// *!
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_64x144_1r1w(
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gnd,
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vdd,
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vcs,
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nclk,
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rd_act,
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wr_act,
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sg_0,
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abst_sl_thold_0,
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ary_nsl_thold_0,
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time_sl_thold_0,
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repr_sl_thold_0,
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func_sl_force,
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func_sl_thold_0_b,
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g8t_clkoff_dc_b,
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ccflush_dc,
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scan_dis_dc_b,
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scan_diag_dc,
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g8t_d_mode_dc,
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g8t_mpw1_dc_b,
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g8t_mpw2_dc_b,
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g8t_delay_lclkr_dc,
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d_mode_dc,
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mpw1_dc_b,
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mpw2_dc_b,
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delay_lclkr_dc,
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wr_abst_act,
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rd0_abst_act,
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abist_di,
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abist_bw_odd,
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abist_bw_even,
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abist_wr_adr,
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abist_rd0_adr,
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tc_lbist_ary_wrt_thru_dc,
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abist_ena_1,
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abist_g8t_rd0_comp_ena,
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abist_raw_dc_b,
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obs0_abist_cmp,
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abst_scan_in,
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time_scan_in,
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repr_scan_in,
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func_scan_in,
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abst_scan_out,
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time_scan_out,
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repr_scan_out,
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func_scan_out,
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lcb_bolt_sl_thold_0,
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pc_bo_enable_2,
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pc_bo_reset,
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pc_bo_unload,
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pc_bo_repair,
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pc_bo_shdata,
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pc_bo_select,
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bo_pc_failout,
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bo_pc_diagloop,
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tri_lcb_mpw1_dc_b,
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tri_lcb_mpw2_dc_b,
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tri_lcb_delay_lclkr_dc,
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tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc,
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write_enable,
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addr_wr,
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data_in,
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addr_rd,
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data_out
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);
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parameter addressable_ports = 64; // number of addressable register in this array
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parameter addressbus_width = 6; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
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parameter port_bitwidth = 144; // bitwidth of ports (per way)
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parameter bit_write_type = 9; // gives the number of bits that shares one write-enable; must divide evenly into array
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parameter ways = 1; // number of ways
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// POWER PINS
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inout gnd;
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inout vdd;
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inout vcs;
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// CLOCK and CLOCKCONTROL ports
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input [0:`NCLK_WIDTH-1] nclk;
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input rd_act;
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input wr_act;
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input sg_0;
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input abst_sl_thold_0;
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input ary_nsl_thold_0;
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input time_sl_thold_0;
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input repr_sl_thold_0;
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input func_sl_force;
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input func_sl_thold_0_b;
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input g8t_clkoff_dc_b;
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input ccflush_dc;
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input scan_dis_dc_b;
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input scan_diag_dc;
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input g8t_d_mode_dc;
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input [0:4] g8t_mpw1_dc_b;
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input g8t_mpw2_dc_b;
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input [0:4] g8t_delay_lclkr_dc;
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input d_mode_dc;
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input mpw1_dc_b;
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input mpw2_dc_b;
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input delay_lclkr_dc;
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// ABIST
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input wr_abst_act;
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input rd0_abst_act;
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input [0:3] abist_di;
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input abist_bw_odd;
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input abist_bw_even;
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input [0:addressbus_width-1] abist_wr_adr;
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input [0:addressbus_width-1] abist_rd0_adr;
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input tc_lbist_ary_wrt_thru_dc;
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input abist_ena_1;
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input abist_g8t_rd0_comp_ena;
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input abist_raw_dc_b;
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input [0:3] obs0_abist_cmp;
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// Scan
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input abst_scan_in;
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input time_scan_in;
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input repr_scan_in;
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input func_scan_in;
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output abst_scan_out;
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output time_scan_out;
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output repr_scan_out;
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output func_scan_out;
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// BOLT-ON
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input lcb_bolt_sl_thold_0;
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input pc_bo_enable_2; // general bolt-on enable
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input pc_bo_reset; // reset
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input pc_bo_unload; // unload sticky bits
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input pc_bo_repair; // execute sticky bit decode
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input pc_bo_shdata; // shift data for timing write and diag loop
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input [0:1] pc_bo_select; // select for mask and hier writes
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output [0:1] bo_pc_failout; // fail/no-fix reg
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output [0:1] bo_pc_diagloop;
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input tri_lcb_mpw1_dc_b;
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input tri_lcb_mpw2_dc_b;
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input tri_lcb_delay_lclkr_dc;
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input tri_lcb_clkoff_dc_b;
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input tri_lcb_act_dis_dc;
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// Write Ports
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input write_enable;
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input [0:addressbus_width-1] addr_wr;
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input [0:port_bitwidth-1] data_in;
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// Read Ports
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input [0:addressbus_width-1] addr_rd;
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output [0:port_bitwidth-1] data_out;
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// tri_64x144_1r1w
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// Configuration Statement for NCsim
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//for all:RAMB36 use entity unisim.RAMB36;
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parameter data_width = ((((port_bitwidth - 1)/36) + 1) * 36) - 1;
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parameter rd_act_offset = 0;
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parameter data_out_offset = rd_act_offset + 1;
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parameter scan_right = data_out_offset + port_bitwidth - 1;
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wire [0:data_width-(data_width/9)-1] ramb_data_in;
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wire [0:data_width/9] ramb_par_in;
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wire [0:data_width-(data_width/9)-1] ramb_data_out;
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wire [0:data_width/9] ramb_par_out;
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wire [0:data_width-(data_width/9)-1] ramb_data_dummy;
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wire [0:data_width/9] ramb_par_dummy;
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wire [0:15] ramb_wr_addr;
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wire [0:15] ramb_rd_addr;
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wire [0:data_width] data_in_pad;
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wire [0:data_width] data_out_pad;
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wire [0:((port_bitwidth-1)/36)] cascadeoutlata;
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wire [0:((port_bitwidth-1)/36)] cascadeoutlatb;
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wire [0:((port_bitwidth-1)/36)] cascadeoutrega;
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wire [0:((port_bitwidth-1)/36)] cascadeoutregb;
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wire rd_act_d;
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wire rd_act_q;
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wire [0:port_bitwidth-1] data_out_d;
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wire [0:port_bitwidth-1] data_out_q;
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wire tiup;
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wire tidn;
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wire [0:(((((port_bitwidth-1)/36)+1)*36)/9)-1] wrt_en;
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wire act;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov;
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(* analysis_not_referenced="true" *)
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wire unused;
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generate begin
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assign tiup = 1'b1;
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assign tidn = 1'b0;
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assign wrt_en = {(((((port_bitwidth-1)/36)+1)*36)/9){write_enable}};
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assign act = rd_act | wr_act;
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assign rd_act_d = rd_act;
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assign ramb_wr_addr[0] = 1'b0;
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assign ramb_wr_addr[11:15] = 5'b0;
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assign ramb_rd_addr[0] = 1'b0;
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assign ramb_rd_addr[11:15] = 5'b0;
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genvar addr;
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for (addr = 0; addr < 10; addr = addr + 1) begin : padA0
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if (addr < 10 - addressbus_width)
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begin
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assign ramb_wr_addr[addr + 1] = 1'b0;
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assign ramb_rd_addr[addr + 1] = 1'b0;
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end
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if (addr >= 10 - addressbus_width)
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begin
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assign ramb_wr_addr[addr + 1] = addr_wr[addr - (10 - addressbus_width)];
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assign ramb_rd_addr[addr + 1] = addr_rd[addr - (10 - addressbus_width)];
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end
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end
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// PORTA => Used for Writing
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// PORTB => Used for Reading
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genvar arr;
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for (arr = 0; arr <= (port_bitwidth - 1)/36; arr = arr + 1)
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begin : padD0
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genvar b;
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for (b = 0; b < 36; b = b + 1)
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begin : numBit
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if ((arr * 36) + b < port_bitwidth)
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begin
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assign data_in_pad[(arr * 36) + b] = data_in[(arr * 36) + b];
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end
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if ((arr * 36) + b >= port_bitwidth)
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begin
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assign data_in_pad[(arr * 36) + b] = 1'b0;
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end
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end
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end
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genvar bb;
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for (bb = 0; bb <= (data_width)/9; bb = bb + 1)
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begin : dInFixUp
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assign ramb_data_in[bb * 8:(bb * 8) + 7] = data_in_pad[(bb * 8) + bb:(bb * 8) + 7 + bb];
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assign ramb_par_in[bb] = data_in_pad[(bb * 8) + bb + 8];
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end
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for (bb = 0; bb <= (data_width)/9; bb = bb + 1)
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begin : dOutFixUp
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assign data_out_pad[(bb * 8) + bb:(bb * 8) + 7 + bb] = ramb_data_out[bb * 8:(bb * 8) + 7];
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assign data_out_pad[(bb * 8) + bb + 8] = ramb_par_out[bb];
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end
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genvar anum;
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for (anum = 0; anum <= (port_bitwidth - 1)/36; anum = anum + 1)
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begin : arrNum
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RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) ARR(
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.CASCADEOUTLATA(cascadeoutlata[anum]),
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.CASCADEOUTLATB(cascadeoutlatb[anum]),
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.CASCADEOUTREGA(cascadeoutrega[anum]),
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.CASCADEOUTREGB(cascadeoutregb[anum]),
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.DOA(ramb_data_dummy[(32 * anum):31 + (32 * anum)]),
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.DOB(ramb_data_out[(32 * anum):31 + (32 * anum)]),
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.DOPA(ramb_par_dummy[(4 * anum):3 + (4 * anum)]),
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.DOPB(ramb_par_out[(4 * anum):3 + (4 * anum)]),
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.ADDRA(ramb_wr_addr),
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.ADDRB(ramb_rd_addr),
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.CASCADEINLATA(1'b0),
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.CASCADEINLATB(1'b0),
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.CASCADEINREGA(1'b0),
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.CASCADEINREGB(1'b0),
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.CLKA(nclk[0]),
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.CLKB(nclk[0]),
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.DIA(ramb_data_in[(32 * anum):31 + (32 * anum)]),
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.DIB(32'b0),
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.DIPA(ramb_par_in[(4 * anum):3 + (4 * anum)]),
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.DIPB(4'b0),
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.ENA(act),
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.ENB(act),
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.REGCEA(1'b0),
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.REGCEB(1'b0),
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.SSRA(nclk[1]), //sreset
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.SSRB(nclk[1]),
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.WEA(wrt_en[anum * 4:anum * 4 + 3]),
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.WEB(4'b0) //'
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);
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end
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assign data_out_d = data_out_pad[0:port_bitwidth - 1];
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assign data_out = data_out_q;
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assign abst_scan_out = tidn;
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assign time_scan_out = tidn;
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assign repr_scan_out = tidn;
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assign bo_pc_failout = 2'b00;
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assign bo_pc_diagloop = 2'b00;
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end
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endgenerate
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assign unused = | {
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cascadeoutlata ,
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cascadeoutlatb ,
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cascadeoutrega ,
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cascadeoutregb ,
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||
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ramb_data_dummy ,
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||
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ramb_par_dummy ,
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||
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nclk[2:`NCLK_WIDTH-1] ,
|
||
|
|
gnd ,
|
||
|
|
vdd ,
|
||
|
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vcs ,
|
||
|
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sg_0 ,
|
||
|
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abst_sl_thold_0 ,
|
||
|
|
ary_nsl_thold_0 ,
|
||
|
|
time_sl_thold_0 ,
|
||
|
|
repr_sl_thold_0 ,
|
||
|
|
g8t_clkoff_dc_b ,
|
||
|
|
ccflush_dc ,
|
||
|
|
scan_dis_dc_b ,
|
||
|
|
scan_diag_dc ,
|
||
|
|
g8t_d_mode_dc ,
|
||
|
|
g8t_mpw1_dc_b ,
|
||
|
|
g8t_mpw2_dc_b ,
|
||
|
|
g8t_delay_lclkr_dc ,
|
||
|
|
wr_abst_act ,
|
||
|
|
rd0_abst_act ,
|
||
|
|
abist_di ,
|
||
|
|
abist_bw_odd ,
|
||
|
|
abist_bw_even ,
|
||
|
|
abist_wr_adr ,
|
||
|
|
abist_rd0_adr ,
|
||
|
|
tc_lbist_ary_wrt_thru_dc ,
|
||
|
|
abist_ena_1 ,
|
||
|
|
abist_g8t_rd0_comp_ena ,
|
||
|
|
abist_raw_dc_b ,
|
||
|
|
obs0_abist_cmp ,
|
||
|
|
abst_scan_in ,
|
||
|
|
time_scan_in ,
|
||
|
|
repr_scan_in ,
|
||
|
|
lcb_bolt_sl_thold_0 ,
|
||
|
|
pc_bo_enable_2 ,
|
||
|
|
pc_bo_reset ,
|
||
|
|
pc_bo_unload ,
|
||
|
|
pc_bo_repair ,
|
||
|
|
pc_bo_shdata ,
|
||
|
|
pc_bo_select ,
|
||
|
|
tri_lcb_mpw1_dc_b ,
|
||
|
|
tri_lcb_mpw2_dc_b ,
|
||
|
|
tri_lcb_delay_lclkr_dc ,
|
||
|
|
tri_lcb_clkoff_dc_b ,
|
||
|
|
tri_lcb_act_dis_dc };
|
||
|
|
|
||
|
|
// ####################################################
|
||
|
|
// Registers
|
||
|
|
// ####################################################
|
||
|
|
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.nclk(nclk),
|
||
|
|
.act(tiup),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[rd_act_offset]),
|
||
|
|
.scout(sov[rd_act_offset]),
|
||
|
|
.din(rd_act_d),
|
||
|
|
.dout(rd_act_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out_reg(
|
||
|
|
.vd(vdd),
|
||
|
|
.gd(gnd),
|
||
|
|
.nclk(nclk),
|
||
|
|
.act(rd_act_q),
|
||
|
|
.force_t(func_sl_force),
|
||
|
|
.d_mode(d_mode_dc),
|
||
|
|
.delay_lclkr(delay_lclkr_dc),
|
||
|
|
.mpw1_b(mpw1_dc_b),
|
||
|
|
.mpw2_b(mpw2_dc_b),
|
||
|
|
.thold_b(func_sl_thold_0_b),
|
||
|
|
.sg(sg_0),
|
||
|
|
.scin(siv[data_out_offset:data_out_offset + port_bitwidth - 1]),
|
||
|
|
.scout(sov[data_out_offset:data_out_offset + port_bitwidth - 1]),
|
||
|
|
.din(data_out_d),
|
||
|
|
.dout(data_out_q)
|
||
|
|
);
|
||
|
|
|
||
|
|
assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in};
|
||
|
|
assign func_scan_out = sov[0];
|
||
|
|
|
||
|
|
endmodule
|