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Verilog

2 years ago
// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
2 years ago
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
2 years ago
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
2 years ago
`timescale 1 ns / 1 ns
//----------------------------------------------------------------------------------------------------
// Title: rv_station.vhdl
// Desc: Parameterizable reservation station
//-----------------------------------------------------------------------------------------------------
module rv_station(
cp_flush,
cp_next_itag,
rv0_instr_i0_vld,
rv0_instr_i0_rte,
rv0_instr_i1_vld,
rv0_instr_i1_rte,
rv0_instr_i0_dat,
rv0_instr_i0_dat_ex0,
rv0_instr_i0_itag,
rv0_instr_i0_ord,
rv0_instr_i0_cord,
rv0_instr_i0_spec,
rv0_instr_i0_s1_v,
rv0_instr_i0_s1_dep_hit,
rv0_instr_i0_s1_itag,
rv0_instr_i0_s2_v,
rv0_instr_i0_s2_dep_hit,
rv0_instr_i0_s2_itag,
rv0_instr_i0_s3_v,
rv0_instr_i0_s3_dep_hit,
rv0_instr_i0_s3_itag,
rv0_instr_i0_is_brick,
rv0_instr_i0_brick,
rv0_instr_i0_ilat,
rv0_instr_i1_dat,
rv0_instr_i1_dat_ex0,
rv0_instr_i1_itag,
rv0_instr_i1_ord,
rv0_instr_i1_cord,
rv0_instr_i1_spec,
rv0_instr_i1_s1_v,
rv0_instr_i1_s1_dep_hit,
rv0_instr_i1_s1_itag,
rv0_instr_i1_s2_v,
rv0_instr_i1_s2_dep_hit,
rv0_instr_i1_s2_itag,
rv0_instr_i1_s3_v,
rv0_instr_i1_s3_dep_hit,
rv0_instr_i1_s3_itag,
rv0_instr_i1_is_brick,
rv0_instr_i1_brick,
rv0_instr_i1_ilat,
fx0_rv_itag_vld,
fx0_rv_itag,
fx1_rv_itag_vld,
fx1_rv_itag,
axu0_rv_itag_vld,
axu0_rv_itag,
axu1_rv_itag_vld,
axu1_rv_itag,
lq_rv_itag0_vld,
lq_rv_itag0,
lq_rv_itag1_vld,
lq_rv_itag1,
lq_rv_itag2_vld,
lq_rv_itag2,
fx0_rv_itag_abort,
fx1_rv_itag_abort,
axu0_rv_itag_abort,
axu1_rv_itag_abort,
lq_rv_itag0_abort,
lq_rv_itag1_abort,
lq_rv_itag1_restart,
lq_rv_itag1_hold,
lq_rv_itag1_cord,
lq_rv_itag1_rst_vld,
lq_rv_itag1_rst,
lq_rv_clr_hold,
xx_rv_ex2_s1_abort,
xx_rv_ex2_s2_abort,
xx_rv_ex2_s3_abort,
q_hold_all,
q_ord_complete,
q_ord_tid,
rv1_other_ilat0_vld,
rv1_other_ilat0_itag,
rv1_other_ilat0_vld_out,
rv1_other_ilat0_itag_out,
rv1_instr_vld,
rv1_instr_dat,
rv1_instr_spec,
rv1_instr_ord,
rv1_instr_is_brick,
rv1_instr_itag,
rv1_instr_ilat,
rv1_instr_ilat0_vld,
rv1_instr_ilat1_vld,
rv1_instr_s1_itag,
rv1_instr_s2_itag,
rv1_instr_s3_itag,
ex0_instr_dat,
ex1_credit_free,
rvs_empty,
rvs_perf_bus,
rvs_dbg_bus,
vdd,
gnd,
nclk,
sg_1,
func_sl_thold_1,
ccflush_dc,
act_dis,
clkoff_b,
d_mode,
delay_lclkr,
mpw1_b,
mpw2_b,
scan_in,
scan_out
);
`include "tri_a2o.vh"
parameter q_dat_width_g = 80;
parameter q_dat_ex0_width_g = 60;
parameter q_num_entries_g = 12;
parameter q_barf_enc_g = 4;
parameter q_itag_busses_g = 7; // 2 fx, 3 lq, 2 axu
parameter q_ord_g = 1; // ordered Logic
parameter q_cord_g = 1; // Completion Ordered ordered Logic
parameter q_brick_g = 1'b1; // Brick Logic
parameter q_lq_g=0;
parameter q_noilat0_g=0;
input [0:`THREADS-1] cp_flush;
input [0:(`THREADS*`ITAG_SIZE_ENC)-1] cp_next_itag;
input [0:`THREADS-1] rv0_instr_i0_vld;
input rv0_instr_i0_rte;
input [0:`THREADS-1] rv0_instr_i1_vld;
input rv0_instr_i1_rte;
input [0:q_dat_width_g-1] rv0_instr_i0_dat;
input [0:q_dat_ex0_width_g-1] rv0_instr_i0_dat_ex0;
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag;
input rv0_instr_i0_ord;
input rv0_instr_i0_cord;
input rv0_instr_i0_spec;
input rv0_instr_i0_s1_v;
input rv0_instr_i0_s1_dep_hit;
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag;
input rv0_instr_i0_s2_v;
input rv0_instr_i0_s2_dep_hit;
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag;
input rv0_instr_i0_s3_v;
input rv0_instr_i0_s3_dep_hit;
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag;
input rv0_instr_i0_is_brick;
input [0:2] rv0_instr_i0_brick;
input [0:3] rv0_instr_i0_ilat;
input [0:q_dat_width_g-1] rv0_instr_i1_dat;
input [0:q_dat_ex0_width_g-1] rv0_instr_i1_dat_ex0;
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag;
input rv0_instr_i1_ord;
input rv0_instr_i1_cord;
input rv0_instr_i1_spec;
input rv0_instr_i1_s1_v;
input rv0_instr_i1_s1_dep_hit;
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag;
input rv0_instr_i1_s2_v;
input rv0_instr_i1_s2_dep_hit;
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag;
input rv0_instr_i1_s3_v;
input rv0_instr_i1_s3_dep_hit;
input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag;
input rv0_instr_i1_is_brick;
input [0:2] rv0_instr_i1_brick;
input [0:3] rv0_instr_i1_ilat;
input [0:`THREADS-1] fx0_rv_itag_vld;
input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag;
input [0:`THREADS-1] fx1_rv_itag_vld;
input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag;
input [0:`THREADS-1] axu0_rv_itag_vld;
input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag;
input [0:`THREADS-1] axu1_rv_itag_vld;
input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag;
input [0:`THREADS-1] lq_rv_itag0_vld;
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0;
input [0:`THREADS-1] lq_rv_itag1_vld;
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1;
input [0:`THREADS-1] lq_rv_itag2_vld;
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2;
input fx0_rv_itag_abort;
input fx1_rv_itag_abort;
input axu0_rv_itag_abort;
input axu1_rv_itag_abort;
input lq_rv_itag0_abort;
input lq_rv_itag1_abort;
input lq_rv_itag1_restart;
input lq_rv_itag1_hold;
input lq_rv_itag1_cord;
input [0:`THREADS-1] lq_rv_itag1_rst_vld;
input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst;
input [0:`THREADS-1] lq_rv_clr_hold;
input xx_rv_ex2_s1_abort;
input xx_rv_ex2_s2_abort;
input xx_rv_ex2_s3_abort;
input q_hold_all;
input [0:`THREADS-1] q_ord_complete;
output [0:`THREADS-1] q_ord_tid;
input [0:`THREADS-1] rv1_other_ilat0_vld;
input [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag;
output [0:`THREADS-1] rv1_other_ilat0_vld_out;
output [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag_out;
output [0:`THREADS-1] rv1_instr_vld;
output [0:q_dat_width_g-1] rv1_instr_dat;
output rv1_instr_spec;
output rv1_instr_ord;
output [0:`ITAG_SIZE_ENC-1] rv1_instr_itag;
output [0:3] rv1_instr_ilat;
output [0:`THREADS-1] rv1_instr_ilat0_vld;
output [0:`THREADS-1] rv1_instr_ilat1_vld;
output [0:`ITAG_SIZE_ENC-1] rv1_instr_s1_itag;
output [0:`ITAG_SIZE_ENC-1] rv1_instr_s2_itag;
output [0:`ITAG_SIZE_ENC-1] rv1_instr_s3_itag;
output rv1_instr_is_brick;
output [0:q_dat_ex0_width_g-1] ex0_instr_dat;
output [0:`THREADS-1] ex1_credit_free;
output [0:`THREADS-1] rvs_empty;
output [0:8*`THREADS-1] rvs_perf_bus;
output [0:31] rvs_dbg_bus;
// pervasive
inout vdd;
inout gnd;
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk;
input sg_1;
input func_sl_thold_1;
input ccflush_dc;
input act_dis;
input clkoff_b;
input d_mode;
input delay_lclkr;
input mpw1_b;
input mpw2_b;
input scan_in;
output scan_out;
//-------------------------------------------------------------------------------------------------------
// Type definitions
//-------------------------------------------------------------------------------------------------------
parameter q_ilat_width_g = 4;
wire [0:`THREADS-1] flush;
wire [0:`THREADS-1] flush2;
wire sg_0;
wire func_sl_thold_0;
wire func_sl_thold_0_b;
wire force_t;
wire rv0_load1;
wire rv0_load2;
wire rv0_load1_instr_select;
wire rv0_instr_i0_flushed;
wire rv0_instr_i1_flushed;
wire rv0_instr_i0_s1_rdy;
wire rv0_instr_i0_s2_rdy;
wire rv0_instr_i0_s3_rdy;
wire rv0_instr_i1_s1_rdy;
wire rv0_instr_i1_s2_rdy;
wire rv0_instr_i1_s3_rdy;
wire rv0_i0_s1_itag_clear;
wire rv0_i0_s2_itag_clear;
wire rv0_i0_s3_itag_clear;
wire rv0_i1_s1_itag_clear;
wire rv0_i1_s2_itag_clear;
wire rv0_i1_s3_itag_clear;
wire rv0_i0_s1_itag_abort;
wire rv0_i0_s2_itag_abort;
wire rv0_i0_s3_itag_abort;
wire rv0_i1_s1_itag_abort;
wire rv0_i1_s2_itag_abort;
wire rv0_i1_s3_itag_abort;
wire [0:`THREADS-1] rv0_instr_i0_tid;
wire [0:`THREADS-1] rv0_instr_i1_tid;
wire lq_rv_itag1_restart_q;
wire lq_rv_itag1_hold_q;
wire lq_rv_itag1_cord_q;
wire [0:`THREADS-1] lq_rv_clr_hold_q;
wire [0:`THREADS-1] lq_rv_itag1_rst_vld_q;
wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst_q;
// reservation station entry elements
wire [0:q_num_entries_g-1] q_ev_b;
wire [0:q_num_entries_g-1] q_ev_d;
wire [0:q_num_entries_g-1] q_ev_q;
wire [0:q_num_entries_g-1] q_ord_d;
wire [0:q_num_entries_g-1] q_ord_q;
wire [0:q_num_entries_g-1] q_cord_d;
wire [0:q_num_entries_g-1] q_cord_q;
wire [0:`ITAG_SIZE_ENC-1] q_itag_d[0:q_num_entries_g-1];
wire [0:`ITAG_SIZE_ENC-1] q_itag_q[0:q_num_entries_g-1];
wire [0:q_num_entries_g-1] q_is_brick_d;
wire [0:q_num_entries_g-1] q_is_brick_q;
wire [0:`THREADS-1] q_tid_d[0:q_num_entries_g-1];
wire [0:`THREADS-1] q_tid_q[0:q_num_entries_g-1];
wire [0:2] q_brick_d[0:q_num_entries_g-1];
wire [0:2] q_brick_q[0:q_num_entries_g-1];
wire [0:3] q_ilat_d[0:q_num_entries_g-1];
wire [0:3] q_ilat_q[0:q_num_entries_g-1];
wire [0:q_num_entries_g-1] q_spec_d;
wire [0:q_num_entries_g-1] q_spec_q;
wire [0:q_num_entries_g-1] q_s1_v_d;
wire [0:q_num_entries_g-1] q_s1_v_q;
wire [0:`ITAG_SIZE_ENC-1] q_s1_itag_d[0:q_num_entries_g-1];
wire [0:`ITAG_SIZE_ENC-1] q_s1_itag_q[0:q_num_entries_g-1];
wire [0:q_num_entries_g-1] q_s2_v_d;
wire [0:q_num_entries_g-1] q_s2_v_q;
wire [0:`ITAG_SIZE_ENC-1] q_s2_itag_d[0:q_num_entries_g-1];
wire [0:`ITAG_SIZE_ENC-1] q_s2_itag_q[0:q_num_entries_g-1];
wire [0:q_num_entries_g-1] q_s3_v_d;
wire [0:q_num_entries_g-1] q_s3_v_q;
wire [0:`ITAG_SIZE_ENC-1] q_s3_itag_d[0:q_num_entries_g-1];
wire [0:`ITAG_SIZE_ENC-1] q_s3_itag_q[0:q_num_entries_g-1];
wire [0:q_num_entries_g-1] q_s1_rdy_d;
wire [0:q_num_entries_g-1] q_s1_rdy_q;
wire [0:q_num_entries_g-1] q_s2_rdy_d;
wire [0:q_num_entries_g-1] q_s2_rdy_q;
wire [0:q_num_entries_g-1] q_s3_rdy_d;
wire [0:q_num_entries_g-1] q_s3_rdy_q;
wire [0:q_num_entries_g-1] q_rdy_d;
wire [0:q_num_entries_g-1] q_rdy_q;
wire [0:q_num_entries_g-1] q_rdy_qb;
wire [0:q_num_entries_g-1] q_issued_d;
wire [0:q_num_entries_g-1] q_issued_q;
wire [0:q_num_entries_g-1] q_e_miss_d;
wire [0:q_num_entries_g-1] q_e_miss_q;
wire [0:q_dat_width_g-1] q_dat_d[0:q_num_entries_g-1];
wire [0:q_dat_width_g-1] q_dat_q[0:q_num_entries_g-1];
wire [0:q_num_entries_g-1] q_flushed_d;
wire [0:q_num_entries_g-1] q_flushed_q;
wire [0:q_num_entries_g-1] q_flushed_nxt;
// reservation station set/clr/nxt signals
wire [0:q_num_entries_g-1] q_ev_clr;
wire [0:q_num_entries_g-1] q_ev_nxt;
wire [0:q_num_entries_g-1] q_ord_nxt;
wire [0:q_num_entries_g-1] q_cord_set;
wire [0:q_num_entries_g-1] q_cord_nxt;
wire [0:q_num_entries_g-1] q_spec_clr;
wire [0:q_num_entries_g-1] q_spec_nxt;
wire [0:q_num_entries_g-1] q_sx_rdy_nxt;
wire [0:q_num_entries_g-1] q_s1_rdy_sets;
wire [0:q_num_entries_g-1] q_s2_rdy_sets;
wire [0:q_num_entries_g-1] q_s3_rdy_sets;
wire [0:q_num_entries_g-1] q_s1_rdy_setf;
wire [0:q_num_entries_g-1] q_s2_rdy_setf;
wire [0:q_num_entries_g-1] q_s3_rdy_setf;
wire [0:q_num_entries_g-1] q_s1_rdy_clr;
wire [0:q_num_entries_g-1] q_s1_rdy_nxt;
wire [0:q_num_entries_g-1] q_s2_rdy_clr;
wire [0:q_num_entries_g-1] q_s2_rdy_nxt;
wire [0:q_num_entries_g-1] q_s3_rdy_clr;
wire [0:q_num_entries_g-1] q_s3_rdy_nxt;
wire q_i0_s_rdy;
wire q_i1_s_rdy;
wire [0:q_num_entries_g-1] q_rdy_set;
wire [0:q_num_entries_g-1] q_rdy_nxt;
wire [4:q_num_entries_g-1] q_issued_set;
wire [4:q_num_entries_g-1] q_issued_clr;
wire [0:q_num_entries_g-1] q_issued_nxt;
wire [0:q_num_entries_g-1] q_e_miss_set;
wire [0:q_num_entries_g-1] q_e_miss_clr;
wire [0:q_num_entries_g-1] q_e_miss_nxt;
// itag match signals
wire [0:q_num_entries_g-1] q_lq_itag_match;
wire [0:q_num_entries_g-1] q_ilat0_match_s1;
wire [0:q_num_entries_g-1] q_ilat0_match_s2;
wire [0:q_num_entries_g-1] q_ilat0_match_s3;
wire [0:q_num_entries_g-1] q_other_ilat0_match_s1;
wire [0:q_num_entries_g-1] q_other_ilat0_match_s2;
wire [0:q_num_entries_g-1] q_other_ilat0_match_s3;
wire [0:q_num_entries_g-1] q_xx_itag_clear_s1;
wire [0:q_num_entries_g-1] q_xx_itag_clear_s2;
wire [0:q_num_entries_g-1] q_xx_itag_clear_s3;
wire [0:q_num_entries_g-1] q_xx_itag_abort_s1;
wire [0:q_num_entries_g-1] q_xx_itag_abort_s2;
wire [0:q_num_entries_g-1] q_xx_itag_abort_s3;
// entry rdy/select/etc signals
wire [4:q_num_entries_g-1] q_entry_rdy;
wire [4:q_num_entries_g-1] q_entry_rdy_l1_b;
wire [4:q_num_entries_g-1] q_entry_rdy_l2a;
wire [4:q_num_entries_g-1] q_entry_rdy_l2b;
wire [4:q_num_entries_g-1] q_entry_rdy_l2c;
wire [4:q_num_entries_g-1] q_entry_rdy_pri;
wire [4:q_num_entries_g-1] q_entry_select;
wire [0:q_num_entries_g-1] q_entry_or_tree;
wire [0:q_num_entries_g-1] q_entry_and_tree;
wire [0:`THREADS-1] q_entry_ilat0[4:q_num_entries_g-1];
wire [0:`THREADS-1] q_entry_ilat1[4:q_num_entries_g-1];
wire [0:q_dat_width_g-1] q_instr_dat;
wire [0:`THREADS-1] q_instr_vld;
wire [0:`THREADS-1] q_instr_ilat0_vld;
wire [0:`THREADS-1] q_instr_ilat0_vld_l1a_b;
wire [0:`THREADS-1] q_instr_ilat0_vld_l1b_b;
wire [0:`THREADS-1] q_instr_ilat0_vld_rp;
wire [0:`THREADS-1] q_instr_ilat1_vld;
wire q_instr_is_brick;
wire [0:2] q_instr_brick;
wire [0:`ITAG_SIZE_ENC-1] q_instr_itag;
wire [0:`ITAG_SIZE_ENC-1] q_instr_itag_rp;
wire [0:`ITAG_SIZE_ENC-1] q_instr_itag_l1a_b;
wire [0:`ITAG_SIZE_ENC-1] q_instr_itag_l1b_b;
wire [0:`ITAG_SIZE_ENC-1] q_instr_s1_itag;
wire [0:`ITAG_SIZE_ENC-1] q_instr_s2_itag;
wire [0:`ITAG_SIZE_ENC-1] q_instr_s3_itag;
wire [0:`THREADS-1] q_instr_ilat0;
wire [0:`THREADS-1] q_instr_ilat1;
wire [0:`THREADS-1] q_tid_vld;
// hold signals
wire q_hold_all_d;
wire q_hold_all_q;
wire [0:`THREADS-1] q_ord_completed;
wire [0:`THREADS-1] q_hold_ord_d;
wire [0:`THREADS-1] q_hold_ord_q;
wire q_hold_brick_d;
wire q_hold_brick_q;
wire q_hold_brick;
wire [0:2] q_hold_brick_cnt_d;
wire [0:2] q_hold_brick_cnt_q;
wire [0:`THREADS-1] q_hold_ord_set;
wire q_cord_match;
wire [0:`ITAG_SIZE_ENC-1] q_cp_next_itag;
//credit release
wire [0:q_num_entries_g-1] q_credit_d;
wire [0:q_num_entries_g-1] q_credit_q;
wire [0:q_num_entries_g-1] q_credit_nxt;
wire [0:q_num_entries_g-1] q_credit_rdy;
wire [0:q_num_entries_g-1] q_credit_set;
wire [0:q_num_entries_g-1] q_credit_clr;
wire [0:q_num_entries_g-1] q_credit_take;
wire [0:q_num_entries_g-1] q_credit_ex3;
wire [0:q_num_entries_g-1] q_credit_ex6;
wire [0:q_num_entries_g-1] q_credit_flush;
wire [0:`THREADS-1] ex1_credit_free_d;
wire [0:`THREADS-1] ex1_credit_free_q;
wire [0:`THREADS-1] q_entry_tvld[0:q_num_entries_g-1];
wire [0:q_num_entries_g-1] q_entry_tvld_rev[0:`THREADS-1];
wire [0:`THREADS-1] rvs_empty_d;
wire [0:`THREADS-1] rvs_empty_q;
//load/shift signals
wire [0:q_num_entries_g-1] q_entry_load;
wire [0:q_num_entries_g-1] q_entry_load2;
wire [0:q_num_entries_g-1] q_entry_load_i0;
wire [0:q_num_entries_g-1] q_entry_load_i1;
wire [0:q_num_entries_g-1] q_entry_shift;
wire [0:q_num_entries_g-1] q_entry_hold;
wire [0:q_num_entries_g-1] q_cord_act;
wire [0:q_num_entries_g-1] q_dat_act;
wire [0:q_num_entries_g-1] q_e_miss_act;
wire [0:3] issued_addr;
wire [0:q_num_entries_g-1] issued_shift[0:3];
wire [0:3] issued_addr_d[0:4];
wire [0:3] issued_addr_q[0:4];
wire [0:`THREADS-1] issued_vld_d[0:4];
wire [0:`THREADS-1] issued_vld_q[0:4];
wire xx_rv_ex2_abort;
wire xx_rv_ex3_abort;
wire xx_rv_ex4_abort;
wire [0:q_num_entries_g-1] ex3_instr_issued;
wire [0:q_num_entries_g-1] ex4_instr_issued;
(* analysis_not_referenced="<0:3>true" *)
wire [0:q_num_entries_g-1] ex4_instr_aborted;
wire w0_en;
wire w1_en;
wire [0:q_num_entries_g] w_act;
wire [0:`THREADS-1] rv0_w0_en;
wire [0:`THREADS-1] rv0_w1_en;
wire [0:`THREADS-1] barf_ev_d[0:q_num_entries_g];
wire [0:`THREADS-1] barf_ev_q[0:q_num_entries_g];
wire [0:q_num_entries_g] barf_w0_ev_b;
wire [0:q_num_entries_g] barf_w1_ev_b;
wire [0:q_num_entries_g] barf_w0_or_tree;
wire [0:q_num_entries_g] barf_w1_or_tree;
wire [0:q_num_entries_g] rv0_w0_addr;
wire [0:q_num_entries_g] rv0_w1_addr;
wire [0:q_barf_enc_g-1] rv0_w0_addr_enc;
wire [0:q_barf_enc_g-1] rv0_w1_addr_enc;
wire [0:q_barf_enc_g-1] ex0_barf_addr_d;
wire [0:q_barf_enc_g-1] ex0_barf_addr_q;
wire [0:q_barf_enc_g-1] barf_clr_addr;
wire [0:q_num_entries_g] q_barf_clr;
wire [0:q_barf_enc_g-1] q_barf_addr_d[0:q_num_entries_g-1];
wire [0:q_barf_enc_g-1] q_barf_addr_q[0:q_num_entries_g-1];
wire [0:`THREADS-1] xx_rv_rel_vld_d[0:q_itag_busses_g-1];
wire [0:`THREADS-1] xx_rv_rel_vld_q[0:q_itag_busses_g-1];
wire [0:q_itag_busses_g-1] xx_rv_abort_d;
wire [0:q_itag_busses_g-1] xx_rv_abort_q;
wire [0:`ITAG_SIZE_ENC-1] xx_rv_rel_itag_d[0:q_itag_busses_g-1];
wire [0:`ITAG_SIZE_ENC-1] xx_rv_rel_itag_q[0:q_itag_busses_g-1];
wire [4*q_dat_width_g:q_dat_width_g*q_num_entries_g-1] q_dat_ary;
wire [4*`THREADS:`THREADS*q_num_entries_g-1] q_tid_ary;
wire [4*3:3*q_num_entries_g-1] q_brick_ary;
wire [4*`THREADS:`THREADS*q_num_entries_g-1] q_ilat0_ary;
wire [4*`THREADS:`THREADS*q_num_entries_g-1] q_ilat1_ary;
wire [4*`ITAG_SIZE_ENC:`ITAG_SIZE_ENC*q_num_entries_g-1] q_itag_ary;
wire [4*`ITAG_SIZE_ENC:`ITAG_SIZE_ENC*q_num_entries_g-1] q_s1_itag_ary;
wire [4*`ITAG_SIZE_ENC:`ITAG_SIZE_ENC*q_num_entries_g-1] q_s2_itag_ary;
wire [4*`ITAG_SIZE_ENC:`ITAG_SIZE_ENC*q_num_entries_g-1] q_s3_itag_ary;
wire [4*q_ilat_width_g:q_ilat_width_g*q_num_entries_g-1] q_ilat_ary;
wire [4*q_barf_enc_g:q_barf_enc_g*q_num_entries_g-1] q_barf_addr_ary;
wire [0 :q_barf_enc_g*q_num_entries_g-1] q_barf_clr_addr_ary;
wire [0:`THREADS*q_num_entries_g-1] q_tid_full_ary;
wire [0:q_itag_busses_g*`THREADS-1] xx_rv_itag_vld_ary;
wire [0:q_itag_busses_g*(`ITAG_SIZE_ENC)-1] xx_rv_itag_ary;
wire [0:8*`THREADS-1] perf_bus_d;
wire [0:8*`THREADS-1] perf_bus_q;
wire [0:31] dbg_bus_d;
wire [0:31] dbg_bus_q;
(* analysis_not_referenced="true" *)
wire no_lq_unused;
(* analysis_not_referenced="true" *)
wire brick_unused;
(* analysis_not_referenced="true" *)
wire [0:q_num_entries_g-1] brickn_unused;
wire tiup;
//-------------------------------------------------------------------
// Scanchain
//-------------------------------------------------------------------
parameter barf_offset = 0;
parameter barf_ev_offset = barf_offset + 1;
parameter ex0_barf_addr_offset = barf_ev_offset + (q_num_entries_g+1)* `THREADS;
parameter issued_vld_offset =ex0_barf_addr_offset + q_barf_enc_g;
parameter issued_addr_offset =issued_vld_offset + 5*`THREADS;
parameter xx_rv_ex3_abort_offset = issued_addr_offset + 5*4;
parameter xx_rv_ex4_abort_offset = xx_rv_ex3_abort_offset + 1;
parameter flush_reg_offset = xx_rv_ex4_abort_offset + 1;
parameter flush2_reg_offset = flush_reg_offset + `THREADS;
parameter q_dat_offset = flush2_reg_offset + `THREADS;
parameter q_itag_offset = q_dat_offset + q_num_entries_g * q_dat_width_g;
parameter q_brick_offset = q_itag_offset + q_num_entries_g * `ITAG_SIZE_ENC;
parameter q_ilat_offset = q_brick_offset + q_num_entries_g * 3;
parameter q_barf_addr_offset = q_ilat_offset + q_num_entries_g * 4;
parameter q_tid_offset = q_barf_addr_offset + q_num_entries_g * q_barf_enc_g;
parameter q_s1_itag_offset = q_tid_offset + q_num_entries_g * `THREADS;
parameter q_s2_itag_offset = q_s1_itag_offset + q_num_entries_g * `ITAG_SIZE_ENC;
parameter q_s3_itag_offset = q_s2_itag_offset + q_num_entries_g * `ITAG_SIZE_ENC;
parameter lq_rv_itag1_restart_offset = q_s3_itag_offset + q_num_entries_g * `ITAG_SIZE_ENC;
parameter lq_rv_itag1_hold_offset = lq_rv_itag1_restart_offset + 1;
parameter lq_rv_itag1_cord_offset = lq_rv_itag1_hold_offset + 1;
parameter lq_rv_clr_hold_offset = lq_rv_itag1_cord_offset + 1;
parameter lq_rv_itag1_rst_vld_offset = lq_rv_clr_hold_offset + `THREADS;
parameter lq_rv_itag1_rst_offset = lq_rv_itag1_rst_vld_offset + `THREADS;
parameter xx_rv_rel_vld_offset = lq_rv_itag1_rst_offset + `ITAG_SIZE_ENC;
parameter xx_rv_rel_itag_offset = xx_rv_rel_vld_offset + q_itag_busses_g * `THREADS;
parameter xx_rv_abort_offset = xx_rv_rel_itag_offset + q_itag_busses_g * `ITAG_SIZE_ENC;
parameter q_ev_offset = xx_rv_abort_offset + q_itag_busses_g;
parameter q_flushed_offset = q_ev_offset + q_num_entries_g;
parameter q_credit_offset = q_flushed_offset + q_num_entries_g;
parameter ex1_credit_free_offset = q_credit_offset + q_num_entries_g;
parameter rvs_empty_offset = ex1_credit_free_offset + `THREADS;
parameter q_ord_offset = rvs_empty_offset + `THREADS;
parameter q_cord_offset = q_ord_offset + q_num_entries_g;
parameter q_is_brick_offset = q_cord_offset + q_num_entries_g;
parameter q_spec_offset = q_is_brick_offset + q_num_entries_g;
parameter q_s1_v_offset = q_spec_offset + q_num_entries_g;
parameter q_s2_v_offset = q_s1_v_offset + q_num_entries_g;
parameter q_s3_v_offset = q_s2_v_offset + q_num_entries_g;
parameter q_s1_rdy_offset = q_s3_v_offset + q_num_entries_g;
parameter q_s2_rdy_offset = q_s1_rdy_offset + q_num_entries_g;
parameter q_s3_rdy_offset = q_s2_rdy_offset + q_num_entries_g;
parameter q_rdy_offset = q_s3_rdy_offset + q_num_entries_g;
parameter q_issued_offset = q_rdy_offset + q_num_entries_g;
parameter q_e_miss_offset = q_issued_offset + q_num_entries_g;
parameter q_hold_all_offset = q_e_miss_offset + q_num_entries_g;
parameter q_hold_ord_offset = q_hold_all_offset + 1;
parameter q_hold_brick_offset = q_hold_ord_offset + `THREADS;
parameter q_hold_brick_cnt_offset = q_hold_brick_offset + 1;
parameter perf_bus_offset = q_hold_brick_cnt_offset + 3;
parameter dbg_bus_offset = perf_bus_offset + 8*`THREADS;
parameter scan_right = dbg_bus_offset + 32;
wire [0:scan_right-1] siv /*verilator split_var*/;
2 years ago
wire [0:scan_right-1] sov;
genvar n;
genvar t;
genvar i;
//-------------------------------------------------------------------------------------------------------
// Bugspray
//-------------------------------------------------------------------------------------------------------
//!! Bugspray Include: rv_station;
//-------------------------------------------------------------------------------------------------------
// misc
//-------------------------------------------------------------------------------------------------------
assign tiup = 1'b1;
//-------------------------------------------------------------------------------------------------------
// Barf array. Data not needed until EX0
//-------------------------------------------------------------------------------------------------------
rv_barf #(.q_dat_width_g(q_dat_ex0_width_g), .q_num_entries_g(q_num_entries_g+1), .q_barf_enc_g(q_barf_enc_g) )
barf(
.w0_dat(rv0_instr_i0_dat_ex0),
.w0_addr(rv0_w0_addr_enc),
.w0_en(w0_en),
.w1_dat(rv0_instr_i1_dat_ex0),
.w1_addr(rv0_w1_addr_enc),
.w1_en(w1_en),
.w_act(w_act),
.r0_addr(ex0_barf_addr_q),
.r0_dat(ex0_instr_dat),
.nclk(nclk),
.vdd(vdd),
.gnd(gnd),
.sg_1(sg_1),
.func_sl_thold_1(func_sl_thold_1),
.ccflush_dc(ccflush_dc),
.act_dis(act_dis),
.clkoff_b(clkoff_b),
.d_mode(d_mode),
.delay_lclkr(delay_lclkr),
.mpw1_b(mpw1_b),
.mpw2_b(mpw2_b),
.scan_in(siv[barf_offset]),
.scan_out(sov[barf_offset])
);
assign rv0_w0_en = {`THREADS{rv0_instr_i0_rte}} & rv0_instr_i0_vld & ~({`THREADS{&flush2}}) ;
assign rv0_w1_en = {`THREADS{rv0_instr_i1_rte}} & rv0_instr_i1_vld & ~({`THREADS{&flush2}}) ;
assign w0_en = |rv0_w0_en;
assign w1_en = |rv0_w1_en;
assign w_act = (rv0_w0_addr | rv0_w1_addr) & {q_num_entries_g+1{(rv0_instr_i0_rte | rv0_instr_i1_rte)}};
generate
begin : xhdlbbar
for (n = 0; n <= (q_num_entries_g ); n = n + 1)
begin : genaddr
wire [0:q_barf_enc_g-1] id=n;
assign barf_w0_ev_b[n] = ~(|(barf_ev_q[n]));
assign barf_w1_ev_b[n] = ~(|(barf_ev_q[n]));
assign barf_w0_or_tree[n] = |(barf_w0_ev_b[n:q_num_entries_g]);
assign barf_w1_or_tree[n] = |(barf_w1_ev_b[0:n]);
//Mark the entry valid if it was written
assign barf_ev_d[n] = ((rv0_w0_en & {`THREADS{rv0_w0_addr[n]}}) |
(rv0_w1_en & {`THREADS{rv0_w1_addr[n]}}) |
(barf_ev_q[n] & ~{`THREADS{q_barf_clr[n]}}) ) & ~({`THREADS{&flush}}) ;
//Clear logic
assign q_barf_clr[n] = |q_credit_rdy & (barf_clr_addr==id);
end // block: genaddr
if(q_num_entries_g==12)
begin : baenc12
assign rv0_w0_addr_enc[0]= rv0_w0_addr[ 8]|rv0_w0_addr[ 9]|rv0_w0_addr[10]|rv0_w0_addr[11]|rv0_w0_addr[12];
assign rv0_w0_addr_enc[1]= rv0_w0_addr[ 4]|rv0_w0_addr[ 5]|rv0_w0_addr[ 6]|rv0_w0_addr[ 7]|rv0_w0_addr[12];
assign rv0_w0_addr_enc[2]= rv0_w0_addr[ 2]|rv0_w0_addr[ 3]|rv0_w0_addr[ 6]|rv0_w0_addr[ 7]|
rv0_w0_addr[10]|rv0_w0_addr[11];
assign rv0_w0_addr_enc[3]= rv0_w0_addr[ 1]|rv0_w0_addr[ 3]|rv0_w0_addr[ 5]|rv0_w0_addr[ 7]|
rv0_w0_addr[ 9]|rv0_w0_addr[11];
assign rv0_w1_addr_enc[0]= rv0_w1_addr[ 8]|rv0_w1_addr[ 9]|rv0_w1_addr[10]|rv0_w1_addr[11]|rv0_w1_addr[12];
assign rv0_w1_addr_enc[1]= rv0_w1_addr[ 4]|rv0_w1_addr[ 5]|rv0_w1_addr[ 6]|rv0_w1_addr[ 7]|rv0_w1_addr[12];
assign rv0_w1_addr_enc[2]= rv0_w1_addr[ 2]|rv0_w1_addr[ 3]|rv0_w1_addr[ 6]|rv0_w1_addr[ 7]|
rv0_w1_addr[10]|rv0_w1_addr[11];
assign rv0_w1_addr_enc[3]= rv0_w1_addr[ 1]|rv0_w1_addr[ 3]|rv0_w1_addr[ 5]|rv0_w1_addr[ 7]|
rv0_w1_addr[ 9]|rv0_w1_addr[11];
end
else
begin : baenc16
assign rv0_w0_addr_enc[0]= rv0_w0_addr[16];
assign rv0_w0_addr_enc[1]= rv0_w0_addr[ 8]|rv0_w0_addr[ 9]|rv0_w0_addr[10]|rv0_w0_addr[11]|
rv0_w0_addr[12]|rv0_w0_addr[13]|rv0_w0_addr[14]|rv0_w0_addr[15];
assign rv0_w0_addr_enc[2]= rv0_w0_addr[ 4]|rv0_w0_addr[ 5]|rv0_w0_addr[ 6]|rv0_w0_addr[ 7]|
rv0_w0_addr[12]|rv0_w0_addr[13]|rv0_w0_addr[14]|rv0_w0_addr[15];
assign rv0_w0_addr_enc[3]= rv0_w0_addr[ 2]|rv0_w0_addr[ 3]|rv0_w0_addr[ 6]|rv0_w0_addr[ 7]|
rv0_w0_addr[10]|rv0_w0_addr[11]|rv0_w0_addr[14]|rv0_w0_addr[15];
assign rv0_w0_addr_enc[4]= rv0_w0_addr[ 1]|rv0_w0_addr[ 3]|rv0_w0_addr[ 5]|rv0_w0_addr[ 7]|
rv0_w0_addr[ 9]|rv0_w0_addr[11]|rv0_w0_addr[13]|rv0_w0_addr[15];
assign rv0_w1_addr_enc[0]= rv0_w1_addr[16];
assign rv0_w1_addr_enc[1]= rv0_w1_addr[ 8]|rv0_w1_addr[ 9]|rv0_w1_addr[10]|rv0_w1_addr[11]|
rv0_w1_addr[12]|rv0_w1_addr[13]|rv0_w1_addr[14]|rv0_w1_addr[15];
assign rv0_w1_addr_enc[2]= rv0_w1_addr[ 4]|rv0_w1_addr[ 5]|rv0_w1_addr[ 6]|rv0_w1_addr[ 7]|
rv0_w1_addr[12]|rv0_w1_addr[13]|rv0_w1_addr[14]|rv0_w1_addr[15];
assign rv0_w1_addr_enc[3]= rv0_w1_addr[ 2]|rv0_w1_addr[ 3]|rv0_w1_addr[ 6]|rv0_w1_addr[ 7]|
rv0_w1_addr[10]|rv0_w1_addr[11]|rv0_w1_addr[14]|rv0_w1_addr[15];
assign rv0_w1_addr_enc[4]= rv0_w1_addr[ 1]|rv0_w1_addr[ 3]|rv0_w1_addr[ 5]|rv0_w1_addr[ 7]|
rv0_w1_addr[ 9]|rv0_w1_addr[11]|rv0_w1_addr[13]|rv0_w1_addr[15];
end
end
endgenerate
assign rv0_w0_addr[0] = barf_w0_or_tree[0] & ~barf_w0_or_tree[1];
assign rv0_w1_addr[0] = barf_w1_or_tree[0];
generate
begin : xhdlbbar2
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : genaddr2
assign rv0_w0_addr[n] = barf_w0_or_tree[n] & ~barf_w0_or_tree[n+1];
assign rv0_w1_addr[n] = barf_w1_or_tree[n] & ~barf_w1_or_tree[n-1];
end
end
endgenerate
assign rv0_w0_addr[q_num_entries_g] = barf_w0_or_tree[q_num_entries_g];
assign rv0_w1_addr[q_num_entries_g] = barf_w1_or_tree[q_num_entries_g] & ~barf_w1_or_tree[q_num_entries_g-1];
//-------------------------------------------------------------------------------------------------------
// Compute instruction bus controls in RV0
//-------------------------------------------------------------------------------------------------------
assign rv0_load1 = (rv0_instr_i0_rte | rv0_instr_i1_rte ) & (~(&(flush)) & ~(&(flush2)));
assign rv0_load2 = (rv0_instr_i0_rte & rv0_instr_i1_rte ) & (~(&(flush)) & ~(&(flush2)));
assign rv0_load1_instr_select = (rv0_instr_i1_rte ) & (~rv0_load2);
assign rv0_instr_i0_tid = rv0_instr_i0_vld;
assign rv0_instr_i1_tid = rv0_instr_i1_vld;
assign rv0_instr_i0_flushed = |(rv0_instr_i0_vld & (flush | flush2));
assign rv0_instr_i1_flushed = |(rv0_instr_i1_vld & (flush | flush2));
//-------------------------------------------------------------------------------------------------------
// generation of logic to manage the q ev (entry valid) bits.
//-------------------------------------------------------------------------------------------------------
assign q_ev_d[0] = (q_entry_load_i1[0]) | (q_entry_load_i0[0]) | (1'b0 & q_entry_shift[0]) | (q_ev_nxt[0] & q_entry_hold[0]);
generate
begin : xhdl1
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ev_gen
assign q_ev_d[n] = (q_entry_load_i1[n]) | (q_entry_load_i0[n]) | (q_ev_nxt[n - 1] & q_entry_shift[n]) | (q_ev_nxt[n] & q_entry_hold[n]);
end
end
endgenerate
generate
begin : xhdl2
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ev_nxt_gen
assign q_ev_clr[n] = q_credit_take[n] | &(flush);
assign q_ev_nxt[n] = q_ev_q[n] & (~q_ev_clr[n]);
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// generation of the itag for this entry's cmd
//-------------------------------------------------------------------------------------------------------
assign q_itag_d[0] = (rv0_instr_i1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[0]}}) |
(rv0_instr_i0_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) |
(q_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}});
generate
begin : xhdl7
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_itag_gen
assign q_itag_d[n] = (rv0_instr_i1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) |
(rv0_instr_i0_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[n]}}) |
(q_itag_q[n - 1] & {`ITAG_SIZE_ENC{q_entry_shift[n]}}) |
(q_itag_q[n] & {`ITAG_SIZE_ENC{q_entry_hold[n]}});
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// generation of the tid for this entry's cmd
//-------------------------------------------------------------------------------------------------------
assign q_tid_d[0] = ({`THREADS{q_entry_load_i1[0]}} & rv0_instr_i1_tid ) |
({`THREADS{q_entry_load_i0[0]}} & rv0_instr_i0_tid ) |
({`THREADS{q_entry_hold[0]}} & q_tid_q[0]);
generate
begin : xhdl10
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_tid_gen
assign q_tid_d[n] = ({`THREADS{q_entry_load_i1[n]}} & rv0_instr_i1_tid ) |
({`THREADS{q_entry_load_i0[n]}} & rv0_instr_i0_tid ) |
({`THREADS{q_entry_shift[n]}} & q_tid_q[n - 1] ) |
({`THREADS{q_entry_hold[n]}} & q_tid_q[n]);
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// generation of the flush for this entry's cmd
//-------------------------------------------------------------------------------------------------------
assign q_flushed_d[0] = (rv0_instr_i1_flushed & q_entry_load_i1[0]) | (rv0_instr_i0_flushed & q_entry_load_i0[0]) | (q_flushed_nxt[0] & q_entry_hold[0]);
generate
begin : xhdl11
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_flushed_gen
assign q_flushed_d[n] = (rv0_instr_i1_flushed & q_entry_load_i1[n]) |
(rv0_instr_i0_flushed & q_entry_load_i0[n]) |
(q_flushed_nxt[n - 1] & q_entry_shift[n]) |
(q_flushed_nxt[n] & q_entry_hold[n]);
end
end
endgenerate
generate
begin : xhdl12
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_flushed_nxt_gen
assign q_flushed_nxt[n] = q_ev_q[n] & |(q_tid_q[n] & ({`THREADS{q_flushed_q[n]}} | flush));
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// Save the ex0 indirect address
//-------------------------------------------------------------------------------------------------------
assign q_barf_addr_d[0] = (rv0_w0_addr_enc & {q_barf_enc_g{q_entry_load_i0[0]}}) |
(rv0_w1_addr_enc & {q_barf_enc_g{q_entry_load_i1[0]}}) |
(q_barf_addr_q[0] & {q_barf_enc_g{q_entry_hold[0]}});
generate
begin : xhdl11b
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_barf_addr_gen
assign q_barf_addr_d[n] = (rv0_w0_addr_enc & {q_barf_enc_g{q_entry_load_i0[n]}}) |
(rv0_w1_addr_enc & {q_barf_enc_g{q_entry_load_i1[n]}}) |
(q_barf_addr_q[n - 1] & {q_barf_enc_g{q_entry_shift[n]}}) |
(q_barf_addr_q[n] & {q_barf_enc_g{q_entry_hold[n]}});
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// ILAT
//-------------------------------------------------------------------------------------------------------
assign q_ilat_d[0] = ({q_ilat_width_g{q_entry_load_i1[0]}} & rv0_instr_i1_ilat ) |
({q_ilat_width_g{q_entry_load_i0[0]}} & rv0_instr_i0_ilat ) |
({q_ilat_width_g{q_entry_hold[0]}} & q_ilat_q[0]);
generate
begin : xhdl13
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_ilat_gen
assign q_ilat_d[n] = ({q_ilat_width_g{q_entry_load_i1[n]}} & rv0_instr_i1_ilat ) |
({q_ilat_width_g{q_entry_load_i0[n]}} & rv0_instr_i0_ilat ) |
({q_ilat_width_g{q_entry_shift[n]}} & q_ilat_q[n - 1] ) |
({q_ilat_width_g{q_entry_hold[n]}} & q_ilat_q[n]);
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// generation of logic for the source valid fields that are present in each reservation station entry
//-------------------------------------------------------------------------------------------------------
assign q_s1_v_d[0] = (rv0_instr_i1_s1_v & q_entry_load_i1[0]) |
(rv0_instr_i0_s1_v & q_entry_load_i0[0]) |
(q_s1_v_q[0] & q_entry_hold[0]);
assign q_s2_v_d[0] = (rv0_instr_i1_s2_v & q_entry_load_i1[0]) |
(rv0_instr_i0_s2_v & q_entry_load_i0[0]) |
(q_s2_v_q[0] & q_entry_hold[0]);
assign q_s3_v_d[0] = (rv0_instr_i1_s3_v & q_entry_load_i1[0]) |
(rv0_instr_i0_s3_v & q_entry_load_i0[0]) |
(q_s3_v_q[0] & q_entry_hold[0]);
generate
begin : xhdl16
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_sv_gen
assign q_s1_v_d[n] = (rv0_instr_i1_s1_v & q_entry_load_i1[n]) |
(rv0_instr_i0_s1_v & q_entry_load_i0[n]) |
(q_s1_v_q[n - 1] & q_entry_shift[n]) |
(q_s1_v_q[n] & q_entry_hold[n]);
assign q_s2_v_d[n] = (rv0_instr_i1_s2_v & q_entry_load_i1[n]) |
(rv0_instr_i0_s2_v & q_entry_load_i0[n]) |
(q_s2_v_q[n - 1] & q_entry_shift[n]) |
(q_s2_v_q[n] & q_entry_hold[n]);
assign q_s3_v_d[n] = (rv0_instr_i1_s3_v & q_entry_load_i1[n]) |
(rv0_instr_i0_s3_v & q_entry_load_i0[n]) |
(q_s3_v_q[n - 1] & q_entry_shift[n]) |
(q_s3_v_q[n] & q_entry_hold[n]);
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// generation of logic for the dependent itags
//-------------------------------------------------------------------------------------------------------
assign q_s1_itag_d[0] = (rv0_instr_i1_s1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[0]}}) |
(rv0_instr_i0_s1_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) |
(q_s1_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}});
assign q_s2_itag_d[0] = (rv0_instr_i1_s2_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[0]}}) |
(rv0_instr_i0_s2_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) |
(q_s2_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}});
assign q_s3_itag_d[0] = (rv0_instr_i1_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[0]}}) |
(rv0_instr_i0_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) |
(q_s3_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}});
generate
begin : xhdl17
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_sitag_gen
assign q_s1_itag_d[n] = (rv0_instr_i1_s1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) |
(rv0_instr_i0_s1_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[n]}}) |
(q_s1_itag_q[n-1] & {`ITAG_SIZE_ENC{q_entry_shift[n]}}) |
(q_s1_itag_q[n] & {`ITAG_SIZE_ENC{q_entry_hold[n]}});
assign q_s2_itag_d[n] = (rv0_instr_i1_s2_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) |
(rv0_instr_i0_s2_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[n]}}) |
(q_s2_itag_q[n-1] & {`ITAG_SIZE_ENC{q_entry_shift[n]}}) |
(q_s2_itag_q[n] & {`ITAG_SIZE_ENC{q_entry_hold[n]}});
assign q_s3_itag_d[n] = (rv0_instr_i1_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) |
(rv0_instr_i0_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[n]}}) |
(q_s3_itag_q[n-1] & {`ITAG_SIZE_ENC{q_entry_shift[n]}}) |
(q_s3_itag_q[n] & {`ITAG_SIZE_ENC{q_entry_hold[n]}});
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// generation of source rdy logic
//-------------------------------------------------------------------------------------------------------lol
assign q_s1_rdy_d[0] = (rv0_instr_i1_s1_rdy & q_entry_load_i1[0]) |
(rv0_instr_i0_s1_rdy & q_entry_load_i0[0]) |
(q_s1_rdy_nxt[0] & q_entry_hold[0] );
assign q_s2_rdy_d[0] = (rv0_instr_i1_s2_rdy & q_entry_load_i1[0]) |
(rv0_instr_i0_s2_rdy & q_entry_load_i0[0]) |
(q_s2_rdy_nxt[0] & q_entry_hold[0] );
assign q_s3_rdy_d[0] = (rv0_instr_i1_s3_rdy & q_entry_load_i1[0]) |
(rv0_instr_i0_s3_rdy & q_entry_load_i0[0]) |
(q_s3_rdy_nxt[0] & q_entry_hold[0] );
generate
begin : xhdl20
for (n = 1; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_srdy_gen
assign q_s1_rdy_d[n] = (rv0_instr_i1_s1_rdy & q_entry_load_i1[n]) |
(rv0_instr_i0_s1_rdy & q_entry_load_i0[n]) |
(q_s1_rdy_nxt[n - 1] & q_entry_shift[n]) |
(q_s1_rdy_nxt[n] & q_entry_hold[n]);
assign q_s2_rdy_d[n] = (rv0_instr_i1_s2_rdy & q_entry_load_i1[n]) |
(rv0_instr_i0_s2_rdy & q_entry_load_i0[n]) |
(q_s2_rdy_nxt[n - 1] & q_entry_shift[n]) |
(q_s2_rdy_nxt[n] & q_entry_hold[n]);
assign q_s3_rdy_d[n] = (rv0_instr_i1_s3_rdy & q_entry_load_i1[n]) |
(rv0_instr_i0_s3_rdy & q_entry_load_i0[n]) |
(q_s3_rdy_nxt[n - 1] & q_entry_shift[n]) |
(q_s3_rdy_nxt[n] & q_entry_hold[n]);
end
end
endgenerate
generate
begin : xhdl21
for (n = 0; n <= (q_num_entries_g - 1); n = n + 1)
begin : q_srdy_nxt_gen
assign q_s1_rdy_setf[n] = (q_other_ilat0_match_s1[n] | q_ilat0_match_s1[n]);
assign q_s2_rdy_setf[n] = (q_other_ilat0_match_s2[n] | q_ilat0_match_s2[n]);
assign q_s3_rdy_setf[n] = (q_other_ilat0_match_s3[n] | q_ilat0_match_s3[n]);
assign q_s1_rdy_sets[n] = q_xx_itag_clear_s1[n] | q_s1_rdy_q[n] | ~q_s1_v_q[n];
assign q_s2_rdy_sets[n] = q_xx_itag_clear_s2[n] | q_s2_rdy_q[n] | ~q_s2_v_q[n];
assign q_s3_rdy_sets[n] = q_xx_itag_clear_s3[n] | q_s3_rdy_q[n] | ~q_s3_v_q[n];
assign q_s1_rdy_clr[n] = q_xx_itag_abort_s1[n] & q_s1_v_q[n];
assign q_s2_rdy_clr[n] = q_xx_itag_abort_s2[n] & q_s2_v_q[n] ;
assign q_s3_rdy_clr[n] = q_xx_itag_abort_s3[n] & q_s3_v_q[n];
assign q_s1_rdy_nxt[n] = ((q_s1_rdy_setf[n] | q_s1_rdy_sets[n]) & (~q_s1_rdy_clr[n]) ) ;
assign q_s2_rdy_nxt[n] = ((q_s2_rdy_setf[n] | q_s2_rdy_sets[n]) & (~q_s2_rdy_clr[n]) ) ;
assign q_s3_rdy_nxt[n] = ((q_s3_rdy_setf[n] | q_s3_rdy_sets[n]) & (~q_s3_rdy_clr[n]) ) ;
assign q_sx_rdy_nxt[n] = q_s1_rdy_nxt[n] & q_s2_rdy_nxt[n] & q_s3_rdy_nxt[n] ;
end
end
endgenerate
//-------------------------------------------------------------------------------------------------------
// generation of rdy logic
//-------------------------------------------------------------------------------------------------------
assign q_i0_s_rdy = (rv0_instr_i0_s1_rdy) & (rv0_instr_i0_s2_rdy) & (rv0_instr_i0_s3_rdy) & ~(rv0_instr_i0_ord | rv0_instr_i0_cord | rv0_instr_i0_flushed);
assign q_i1_s_rdy = (rv0_instr_i1_s1_rdy) & (rv0_instr_i1_s2_rdy) & (rv0_instr_i1_s3_rdy) & ~(rv0_instr_i1_ord | rv0_instr_i1_cord | rv0_instr_i1_flushed);
assign q_rdy_d[0] = (q_i1_s_rdy & q_entry_load_i1[0]) |
(q_i0_s_rdy & q_entry_load_i0[0]) |
(q_entry_hold[