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160 lines
6.8 KiB
Verilog
160 lines
6.8 KiB
Verilog
2 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//********************************************************************
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//*
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//* TITLE: Debug Mux Component (16:1 Debug Groups; 4:1 Trigger Groups)
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//*
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//* NAME: tri_debug_mux16.vhdl
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//*
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//********************************************************************
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module tri_debug_mux16(
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// vd,
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// gd,
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select_bits,
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dbg_group0,
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dbg_group1,
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dbg_group2,
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dbg_group3,
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dbg_group4,
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dbg_group5,
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dbg_group6,
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dbg_group7,
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dbg_group8,
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dbg_group9,
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dbg_group10,
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dbg_group11,
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dbg_group12,
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dbg_group13,
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dbg_group14,
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dbg_group15,
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trace_data_in,
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trace_data_out,
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// Instruction Trace (HTM) Controls
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coretrace_ctrls_in,
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coretrace_ctrls_out
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);
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// Include model build parameters
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parameter DBG_WIDTH = 32; // A2o=32; A2i=88
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//=====================================================================
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// Port Definitions
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//=====================================================================
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input [0:10] select_bits;
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input [0:DBG_WIDTH-1] dbg_group0;
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input [0:DBG_WIDTH-1] dbg_group1;
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input [0:DBG_WIDTH-1] dbg_group2;
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input [0:DBG_WIDTH-1] dbg_group3;
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input [0:DBG_WIDTH-1] dbg_group4;
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input [0:DBG_WIDTH-1] dbg_group5;
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input [0:DBG_WIDTH-1] dbg_group6;
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input [0:DBG_WIDTH-1] dbg_group7;
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input [0:DBG_WIDTH-1] dbg_group8;
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input [0:DBG_WIDTH-1] dbg_group9;
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input [0:DBG_WIDTH-1] dbg_group10;
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input [0:DBG_WIDTH-1] dbg_group11;
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input [0:DBG_WIDTH-1] dbg_group12;
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input [0:DBG_WIDTH-1] dbg_group13;
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input [0:DBG_WIDTH-1] dbg_group14;
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input [0:DBG_WIDTH-1] dbg_group15;
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input [0:DBG_WIDTH-1] trace_data_in;
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output [0:DBG_WIDTH-1] trace_data_out;
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// Instruction Trace (HTM) Control Signals:
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// 0 - ac_an_coretrace_first_valid
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// 1 - ac_an_coretrace_valid
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// 2:3 - ac_an_coretrace_type[0:1]
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input [0:3] coretrace_ctrls_in;
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output [0:3] coretrace_ctrls_out;
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//=====================================================================
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// Signal Declarations / Misc
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//=====================================================================
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parameter DBG_1FOURTH = DBG_WIDTH/4;
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parameter DBG_2FOURTH = DBG_WIDTH/2;
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parameter DBG_3FOURTH = 3 * DBG_WIDTH/4;
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wire [0:DBG_WIDTH-1] debug_grp_selected;
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wire [0:DBG_WIDTH-1] debug_grp_rotated;
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// Don't reference unused inputs:
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(* analysis_not_referenced="true" *)
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wire unused;
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assign unused = select_bits[4];
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// Instruction Trace controls are passed-through:
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assign coretrace_ctrls_out = coretrace_ctrls_in ;
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//=====================================================================
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// Mux Function
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//=====================================================================
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// Debug Mux
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assign debug_grp_selected = (select_bits[0:3] == 4'b0000) ? dbg_group0 :
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(select_bits[0:3] == 4'b0001) ? dbg_group1 :
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(select_bits[0:3] == 4'b0010) ? dbg_group2 :
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(select_bits[0:3] == 4'b0011) ? dbg_group3 :
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(select_bits[0:3] == 4'b0100) ? dbg_group4 :
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(select_bits[0:3] == 4'b0101) ? dbg_group5 :
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(select_bits[0:3] == 4'b0110) ? dbg_group6 :
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(select_bits[0:3] == 4'b0111) ? dbg_group7 :
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(select_bits[0:3] == 4'b1000) ? dbg_group8 :
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(select_bits[0:3] == 4'b1001) ? dbg_group9 :
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(select_bits[0:3] == 4'b1010) ? dbg_group10 :
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(select_bits[0:3] == 4'b1011) ? dbg_group11 :
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(select_bits[0:3] == 4'b1100) ? dbg_group12 :
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(select_bits[0:3] == 4'b1101) ? dbg_group13 :
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(select_bits[0:3] == 4'b1110) ? dbg_group14 :
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dbg_group15;
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assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} :
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(select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} :
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(select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} :
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debug_grp_selected[0:DBG_WIDTH - 1];
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assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] :
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debug_grp_rotated[0:DBG_1FOURTH - 1];
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assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] :
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debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1];
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assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] :
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debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1];
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assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] :
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debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1];
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endmodule
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