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272 lines
10 KiB
Verilog
272 lines
10 KiB
Verilog
2 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: XU_FX ALU Top
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module xu_gpr(
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//-------------------------------------------------------------------
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// Clocks & Power
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//-------------------------------------------------------------------
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input [0:`NCLK_WIDTH-1] nclk,
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inout vdd,
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inout gnd,
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//-------------------------------------------------------------------
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// Pervasive
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//-------------------------------------------------------------------
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input pc_xu_ccflush_dc,
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input d_mode_dc,
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input delay_lclkr_dc,
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input mpw1_dc_b,
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input mpw2_dc_b,
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input func_sl_force,
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input func_sl_thold_0_b,
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input sg_0,
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input scan_in,
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output scan_out,
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//-------------------------------------------------------------------
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// Read Ports
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//-------------------------------------------------------------------
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input r0e,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r0a,
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output [64-`GPR_WIDTH:63] r0d,
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input r1e,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a,
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output [64-`GPR_WIDTH:63] r1d,
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input r2e,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a,
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output [64-`GPR_WIDTH:63] r2d,
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input r3e,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r3a,
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output [64-`GPR_WIDTH:63] r3d,
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// Special Port for 3src instructions- erativax
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input r4e,
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input [0:2] r4t_q,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r4a,
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output r0_pe,
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output r1_pe,
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output r2_pe,
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output r3_pe,
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//-------------------------------------------------------------------
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// Write ports
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//-------------------------------------------------------------------
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input w0e,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w0a,
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input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w0d,
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input w1e,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a,
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input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w1d,
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input w2e,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a,
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input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w2d,
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input w3e,
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input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a,
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input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w3d
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);
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// Latches
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wire r4e_q; // input=>r4e ,act=>1'b1
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r4a_q; // input=>r4a ,act=>1'b1
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// Scanchain
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localparam r4e_offset = 2;
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localparam r4a_offset = r4e_offset + 1;
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localparam scan_right = r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
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wire [0:scan_right-1] siv;
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wire [0:scan_right-1] sov;
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// Signals
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wire [64-`GPR_WIDTH:77] w0d_int;
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wire [64-`GPR_WIDTH:77] w1d_int;
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wire [64-`GPR_WIDTH:77] w2d_int;
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wire [64-`GPR_WIDTH:77] w3d_int;
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wire [64-`GPR_WIDTH:77] r0d_int;
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wire [64-`GPR_WIDTH:77] r1d_int;
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wire [64-`GPR_WIDTH:77] r2d_int;
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wire [64-`GPR_WIDTH:77] r3d_int;
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wire [0:`GPR_WIDTH/8-1] r0d_par;
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wire [0:`GPR_WIDTH/8-1] r1d_par;
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wire [0:`GPR_WIDTH/8-1] r2d_par;
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wire [0:`GPR_WIDTH/8-1] r3d_par;
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wire r0e_int;
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wire r4e_sel;
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wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r0a_int;
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assign r4e_sel = r4e_q & ~|r4t_q;
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assign r0e_int = r4e_sel | r0e;
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assign r0a_int = (r4e_sel == 1'b1) ? r4a_q : r0a;
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assign r0d = r0d_int[64 - `GPR_WIDTH:63];
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assign r1d = r1d_int[64 - `GPR_WIDTH:63];
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assign r2d = r2d_int[64 - `GPR_WIDTH:63];
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assign r3d = r3d_int[64 - `GPR_WIDTH:63];
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assign w0d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w0d;
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assign w0d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}};
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assign w1d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w1d;
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assign w1d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}};
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assign w2d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w2d;
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assign w2d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}};
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assign w3d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w3d;
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assign w3d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}};
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generate
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genvar i;
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for (i = 0; i <= `GPR_WIDTH/8 - 1; i = i + 1)
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begin : parity
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assign r0d_par[i] = ^(r0d_int[8 * i:8 * i + 7]);
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assign r1d_par[i] = ^(r1d_int[8 * i:8 * i + 7]);
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assign r2d_par[i] = ^(r2d_int[8 * i:8 * i + 7]);
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assign r3d_par[i] = ^(r3d_int[8 * i:8 * i + 7]);
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end
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endgenerate
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assign r0_pe = r0e & (r0d_par != r0d_int[64:63 + `GPR_WIDTH/8]);
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assign r1_pe = r1e & (r1d_par != r1d_int[64:63 + `GPR_WIDTH/8]);
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assign r2_pe = r2e & (r2d_par != r2d_int[64:63 + `GPR_WIDTH/8]);
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assign r3_pe = r3e & (r3d_par != r3d_int[64:63 + `GPR_WIDTH/8]);
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tri_144x78_2r4w gpr0(
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.vdd(vdd),
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.gnd(gnd),
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.nclk(nclk),
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.delay_lclkr_dc(delay_lclkr_dc),
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.mpw1_dc_b(mpw1_dc_b),
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.mpw2_dc_b(mpw2_dc_b),
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.func_sl_force(func_sl_force),
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.func_sl_thold_0_b(func_sl_thold_0_b),
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.func_slp_sl_force(func_sl_force),
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.func_slp_sl_thold_0_b(func_sl_thold_0_b),
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.sg_0(sg_0),
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.scan_in(siv[0]),
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.scan_out(sov[0]),
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.r_late_en_1(r0e_int),
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.r_addr_in_1(r0a_int),
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.r_data_out_1(r0d_int),
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.r_late_en_2(r1e),
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.r_addr_in_2(r1a),
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.r_data_out_2(r1d_int),
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.w_late_en_1(w0e),
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.w_addr_in_1(w0a),
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.w_data_in_1(w0d_int),
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.w_late_en_2(w1e),
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.w_addr_in_2(w1a),
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.w_data_in_2(w1d_int),
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.w_late_en_3(w2e),
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.w_addr_in_3(w2a),
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.w_data_in_3(w2d_int),
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.w_late_en_4(w3e),
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.w_addr_in_4(w3a),
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.w_data_in_4(w3d_int)
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);
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tri_144x78_2r4w gpr1(
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.vdd(vdd),
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.gnd(gnd),
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.nclk(nclk),
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.delay_lclkr_dc(delay_lclkr_dc),
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.mpw1_dc_b(mpw1_dc_b),
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.mpw2_dc_b(mpw2_dc_b),
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.func_sl_force(func_sl_force),
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.func_sl_thold_0_b(func_sl_thold_0_b),
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.func_slp_sl_force(func_sl_force),
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.func_slp_sl_thold_0_b(func_sl_thold_0_b),
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.sg_0(sg_0),
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.scan_in(siv[1]),
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.scan_out(sov[1]),
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.r_late_en_1(r2e),
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.r_addr_in_1(r2a),
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.r_data_out_1(r2d_int),
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.r_late_en_2(r3e),
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.r_addr_in_2(r3a),
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.r_data_out_2(r3d_int),
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.w_late_en_1(w0e),
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.w_addr_in_1(w0a),
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.w_data_in_1(w0d_int),
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.w_late_en_2(w1e),
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.w_addr_in_2(w1a),
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.w_data_in_2(w1d_int),
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.w_late_en_3(w2e),
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.w_addr_in_3(w2a),
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.w_data_in_3(w2d_int),
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.w_late_en_4(w3e),
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.w_addr_in_4(w3a),
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.w_data_in_4(w3d_int)
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);
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tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r4e_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(1'b1),
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.force_t(func_sl_force),
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.d_mode(d_mode_dc),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.scin(siv[r4e_offset]),
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.scout(sov[r4e_offset]),
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.din(r4e),
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.dout(r4e_q)
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);
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tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r4a_latch(
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.nclk(nclk),
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.vd(vdd),
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.gd(gnd),
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.act(1'b1),
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.force_t(func_sl_force),
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.d_mode(d_mode_dc),
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.delay_lclkr(delay_lclkr_dc),
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.mpw1_b(mpw1_dc_b),
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.mpw2_b(mpw2_dc_b),
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.thold_b(func_sl_thold_0_b),
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.sg(sg_0),
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.scin(siv[r4a_offset:r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
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.scout(sov[r4a_offset:r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
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.din(r4a),
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.dout(r4a_q)
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);
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assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
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assign scan_out = sov[0];
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endmodule
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