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466 lines
21 KiB
Verilog
466 lines
21 KiB
Verilog
2 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: Simple Execution Unit
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//
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//*****************************************************************************
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`include "tri_a2o.vh"
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module xu1(
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//-------------------------------------------------------------------
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// Clocks & Power
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//-------------------------------------------------------------------
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input [0:`NCLK_WIDTH-1] nclk,
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inout vdd,
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inout gnd,
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//-------------------------------------------------------------------
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// Pervasive
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//-------------------------------------------------------------------
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input d_mode_dc,
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input delay_lclkr_dc,
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input mpw1_dc_b,
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input mpw2_dc_b,
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input func_sl_force,
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input func_sl_thold_0_b,
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input sg_0,
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input scan_in,
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output scan_out,
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output xu1_pc_ram_done,
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output [64-`GPR_WIDTH:63] xu1_pc_ram_data,
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input xu0_xu1_ex3_act,
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input lq_xu_ex5_act,
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//-------------------------------------------------------------------
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// Interface with SPR
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//-------------------------------------------------------------------
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input [0:`THREADS-1] spr_msr_cm, // 0: 32 bit mode, 1: 64 bit mode
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//-------------------------------------------------------------------
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// Interface with CP
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//-------------------------------------------------------------------
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input [0:`THREADS-1] cp_flush,
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//-------------------------------------------------------------------
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// Interface with RV
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//-------------------------------------------------------------------
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input [0:`THREADS-1] rv_xu1_vld,
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input rv_xu1_s1_v,
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input rv_xu1_s2_v,
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input rv_xu1_s3_v,
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input [0:31] rv_xu1_ex0_instr,
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input [0:`ITAG_SIZE_ENC-1] rv_xu1_ex0_itag,
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input rv_xu1_ex0_isstore,
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input [1:1] rv_xu1_ex0_ucode,
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input rv_xu1_ex0_t1_v,
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input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t1_p,
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input rv_xu1_ex0_t2_v,
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input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t2_p,
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input rv_xu1_ex0_t3_v,
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input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t3_p,
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input rv_xu1_ex0_s1_v,
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input [0:2] rv_xu1_ex0_s3_t,
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input [0:`THREADS-1] rv_xu1_ex0_spec_flush,
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input [0:`THREADS-1] rv_xu1_ex1_spec_flush,
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input [0:`THREADS-1] rv_xu1_ex2_spec_flush,
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//-------------------------------------------------------------------
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// Interface with Bypass Controller
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//-------------------------------------------------------------------
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input [1:11] rv_xu1_s1_fxu0_sel,
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input [1:11] rv_xu1_s2_fxu0_sel,
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input [2:11] rv_xu1_s3_fxu0_sel,
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input [1:6] rv_xu1_s1_fxu1_sel,
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input [1:6] rv_xu1_s2_fxu1_sel,
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input [2:6] rv_xu1_s3_fxu1_sel,
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input [4:8] rv_xu1_s1_lq_sel,
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input [4:8] rv_xu1_s2_lq_sel,
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input [4:8] rv_xu1_s3_lq_sel,
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input [2:3] rv_xu1_s1_rel_sel,
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input [2:3] rv_xu1_s2_rel_sel,
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//-------------------------------------------------------------------
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// Interface with LQ
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//-------------------------------------------------------------------
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output [0:`THREADS-1] xu1_lq_ex2_stq_val,
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output [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag,
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output [1:4] xu1_lq_ex2_stq_size,
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output xu1_lq_ex3_illeg_lswx,
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output xu1_lq_ex3_strg_noop,
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output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc1_cmp,
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output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc2_cmp,
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//-------------------------------------------------------------------
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// Interface with IU
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//-------------------------------------------------------------------
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output [0:`THREADS-1] xu1_iu_execute_vld,
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output [0:`ITAG_SIZE_ENC-1] xu1_iu_itag,
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output [0:`THREADS-1] xu_iu_ucode_xer_val,
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output [3:9] xu_iu_ucode_xer,
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output xu1_rv_ex2_s1_abort,
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output xu1_rv_ex2_s2_abort,
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output xu1_rv_ex2_s3_abort,
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//-------------------------------------------------------------------
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// Bypass Inputs
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//-------------------------------------------------------------------
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// Regfile Data
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input [64-`GPR_WIDTH:63] gpr_xu1_ex1_r1d,
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input [64-`GPR_WIDTH:63] gpr_xu1_ex1_r2d,
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input [0:9] xer_xu1_ex1_r3d,
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input [0:3] cr_xu1_ex1_r3d,
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// External Bypass
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input xu0_xu1_ex2_abort,
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input xu0_xu1_ex6_abort,
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input lq_xu_ex5_abort,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex2_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex3_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex4_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex5_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex6_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex7_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex8_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex6_lq_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex7_lq_rt,
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input [64-`GPR_WIDTH:63] xu0_xu1_ex8_lq_rt,
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input [64-`GPR_WIDTH:63] lq_xu_ex5_rt,
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input [64-`GPR_WIDTH:63] lq_xu_rel_rt,
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input lq_xu_rel_act,
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// CR
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input [0:3] lq_xu_ex5_cr,
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input [0:3] xu0_xu1_ex3_cr,
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input [0:3] xu0_xu1_ex4_cr,
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input [0:3] xu0_xu1_ex6_cr,
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// XER
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input [0:9] xu0_xu1_ex3_xer,
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input [0:9] xu0_xu1_ex4_xer,
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input [0:9] xu0_xu1_ex6_xer,
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//-------------------------------------------------------------------
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// Bypass Outputs
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//-------------------------------------------------------------------
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output xu1_xu0_ex3_act,
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output xu1_xu0_ex2_abort,
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output xu1_lq_ex3_abort,
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output [64-`GPR_WIDTH:63] xu1_xu0_ex2_rt,
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output [64-`GPR_WIDTH:63] xu1_xu0_ex3_rt,
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output [64-`GPR_WIDTH:63] xu1_xu0_ex4_rt,
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output [64-`GPR_WIDTH:63] xu1_xu0_ex5_rt,
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output [64-`GPR_WIDTH:63] xu1_lq_ex3_rt,
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// CR
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output [0:3] xu1_xu0_ex3_cr,
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// XER
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output [0:9] xu1_xu0_ex3_xer,
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//-------------------------------------------------------------------
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// Interface with Regfiles
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//-------------------------------------------------------------------
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output xu1_gpr_ex3_we,
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output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa,
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output [64-`GPR_WIDTH:65+`GPR_WIDTH/8] xu1_gpr_ex3_wd,
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output xu1_xer_ex3_we,
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output [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] xu1_xer_ex3_wa,
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output [0:9] xu1_xer_ex3_w0d,
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output xu1_cr_ex3_we,
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output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_cr_ex3_wa,
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output [0:3] xu1_cr_ex3_w0d,
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input [0:`THREADS-1] pc_xu_ram_active,
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`ifndef THREADS1
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input [64-`GPR_WIDTH:63] spr_dvc1_t1,
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input [64-`GPR_WIDTH:63] spr_dvc2_t1,
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`endif
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input [64-`GPR_WIDTH:63] spr_dvc1_t0,
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input [64-`GPR_WIDTH:63] spr_dvc2_t0,
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// Debug
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input [0:10] pc_xu_debug_mux_ctrls,
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input [0:31] xu1_debug_bus_in,
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output [0:31] xu1_debug_bus_out,
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input [0:3] xu1_coretrace_ctrls_in,
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output [0:3] xu1_coretrace_ctrls_out
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);
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//!! Bugspray Include: xu1_byp;
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localparam scan_right = 3;
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wire [0:scan_right-1] siv;
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wire [0:scan_right-1] sov;
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// Signals
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wire byp_dec_ex2_abort;
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wire dec_byp_ex0_act;
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wire [64-`GPR_WIDTH:63] dec_byp_ex1_imm;
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wire [24:25] dec_byp_ex1_instr;
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wire dec_byp_ex0_rs2_sel_imm;
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wire dec_byp_ex0_rs1_sel_zero;
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wire [0:`THREADS-1] dec_byp_ex2_tid;
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wire [(64-`GPR_WIDTH)/8:7] dec_byp_ex2_dvc_mask;
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wire dec_alu_ex1_act;
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wire [0:31] dec_alu_ex1_instr;
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wire dec_alu_ex1_sel_isel;
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wire [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv;
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wire [0:1] dec_alu_ex2_add_ci_sel;
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wire dec_alu_ex1_sel_trap;
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wire dec_alu_ex1_sel_cmpl;
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wire dec_alu_ex1_sel_cmp;
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wire dec_alu_ex1_msb_64b_sel;
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wire dec_alu_ex1_xer_ov_en;
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wire dec_alu_ex1_xer_ca_en;
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wire [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt;
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wire [64-`GPR_WIDTH:63] alu_byp_ex3_rt;
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wire [0:3] alu_byp_ex3_cr;
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wire [0:9] alu_byp_ex3_xer;
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wire [64-`GPR_WIDTH:63] byp_alu_ex2_rs1;
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wire [64-`GPR_WIDTH:63] byp_alu_ex2_rs2;
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wire byp_alu_ex2_cr_bit;
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wire [0:9] byp_alu_ex2_xer;
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wire [3:9] byp_dec_ex2_xer;
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assign xu1_debug_bus_out = xu1_debug_bus_in;
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assign xu1_coretrace_ctrls_out = xu1_coretrace_ctrls_in;
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xu_alu alu(
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.nclk(nclk),
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.vdd(vdd),
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.gnd(gnd),
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.d_mode_dc(d_mode_dc),
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.delay_lclkr_dc(delay_lclkr_dc),
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.mpw1_dc_b(mpw1_dc_b),
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.mpw2_dc_b(mpw2_dc_b),
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.func_sl_force(func_sl_force),
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.func_sl_thold_0_b(func_sl_thold_0_b),
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.sg_0(sg_0),
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.scan_in(siv[0]),
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.scan_out(sov[0]),
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.dec_alu_ex1_act(dec_alu_ex1_act),
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.dec_alu_ex1_instr(dec_alu_ex1_instr),
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.dec_alu_ex1_sel_isel(dec_alu_ex1_sel_isel),
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.dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv),
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.dec_alu_ex2_add_ci_sel(dec_alu_ex2_add_ci_sel),
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.dec_alu_ex1_sel_trap(dec_alu_ex1_sel_trap),
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.dec_alu_ex1_sel_cmpl(dec_alu_ex1_sel_cmpl),
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.dec_alu_ex1_sel_cmp(dec_alu_ex1_sel_cmp),
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.dec_alu_ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel),
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.dec_alu_ex1_xer_ov_en(dec_alu_ex1_xer_ov_en),
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.dec_alu_ex1_xer_ca_en(dec_alu_ex1_xer_ca_en),
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.byp_alu_ex2_rs1(byp_alu_ex2_rs1),
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.byp_alu_ex2_rs2(byp_alu_ex2_rs2),
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.byp_alu_ex2_cr_bit(byp_alu_ex2_cr_bit),
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.byp_alu_ex2_xer(byp_alu_ex2_xer),
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.alu_byp_ex2_add_rt(alu_byp_ex2_add_rt),
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.alu_byp_ex3_rt(alu_byp_ex3_rt),
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.alu_byp_ex3_cr(alu_byp_ex3_cr),
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.alu_byp_ex3_xer(alu_byp_ex3_xer),
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.alu_dec_ex3_trap_val()
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);
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xu1_byp byp(
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.nclk(nclk),
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.vdd(vdd),
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.gnd(gnd),
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.d_mode_dc(d_mode_dc),
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.delay_lclkr_dc(delay_lclkr_dc),
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.mpw1_dc_b(mpw1_dc_b),
|
||
|
|
.mpw2_dc_b(mpw2_dc_b),
|
||
|
|
.func_sl_force(func_sl_force),
|
||
|
|
.func_sl_thold_0_b(func_sl_thold_0_b),
|
||
|
|
.sg_0(sg_0),
|
||
|
|
.scan_in(siv[1]),
|
||
|
|
.scan_out(sov[1]),
|
||
|
|
.dec_byp_ex0_act(dec_byp_ex0_act),
|
||
|
|
.byp_dec_ex2_abort(byp_dec_ex2_abort),
|
||
|
|
.xu0_xu1_ex3_act(xu0_xu1_ex3_act),
|
||
|
|
.lq_xu_ex5_act(lq_xu_ex5_act),
|
||
|
|
.dec_byp_ex1_imm(dec_byp_ex1_imm),
|
||
|
|
.dec_byp_ex1_instr(dec_byp_ex1_instr),
|
||
|
|
.dec_byp_ex0_rs2_sel_imm(dec_byp_ex0_rs2_sel_imm),
|
||
|
|
.dec_byp_ex0_rs1_sel_zero(dec_byp_ex0_rs1_sel_zero),
|
||
|
|
.dec_byp_ex2_tid(dec_byp_ex2_tid),
|
||
|
|
.dec_byp_ex2_dvc_mask(dec_byp_ex2_dvc_mask),
|
||
|
|
.rv_xu1_s1_v(rv_xu1_s1_v),
|
||
|
|
.rv_xu1_s2_v(rv_xu1_s2_v),
|
||
|
|
.rv_xu1_s3_v(rv_xu1_s3_v),
|
||
|
|
.rv_xu1_s1_fxu0_sel(rv_xu1_s1_fxu0_sel),
|
||
|
|
.rv_xu1_s2_fxu0_sel(rv_xu1_s2_fxu0_sel),
|
||
|
|
.rv_xu1_s3_fxu0_sel(rv_xu1_s3_fxu0_sel),
|
||
|
|
.rv_xu1_s1_fxu1_sel(rv_xu1_s1_fxu1_sel),
|
||
|
|
.rv_xu1_s2_fxu1_sel(rv_xu1_s2_fxu1_sel),
|
||
|
|
.rv_xu1_s3_fxu1_sel(rv_xu1_s3_fxu1_sel),
|
||
|
|
.rv_xu1_s1_lq_sel(rv_xu1_s1_lq_sel),
|
||
|
|
.rv_xu1_s2_lq_sel(rv_xu1_s2_lq_sel),
|
||
|
|
.rv_xu1_s3_lq_sel(rv_xu1_s3_lq_sel),
|
||
|
|
.rv_xu1_s1_rel_sel(rv_xu1_s1_rel_sel),
|
||
|
|
.rv_xu1_s2_rel_sel(rv_xu1_s2_rel_sel),
|
||
|
|
.gpr_xu1_ex1_r1d(gpr_xu1_ex1_r1d),
|
||
|
|
.gpr_xu1_ex1_r2d(gpr_xu1_ex1_r2d),
|
||
|
|
.xer_xu1_ex1_r3d(xer_xu1_ex1_r3d),
|
||
|
|
.cr_xu1_ex1_r3d(cr_xu1_ex1_r3d),
|
||
|
|
.xu0_xu1_ex2_abort(xu0_xu1_ex2_abort),
|
||
|
|
.xu0_xu1_ex6_abort(xu0_xu1_ex6_abort),
|
||
|
|
.xu0_xu1_ex2_rt(xu0_xu1_ex2_rt),
|
||
|
|
.xu0_xu1_ex3_rt(xu0_xu1_ex3_rt),
|
||
|
|
.xu0_xu1_ex4_rt(xu0_xu1_ex4_rt),
|
||
|
|
.xu0_xu1_ex5_rt(xu0_xu1_ex5_rt),
|
||
|
|
.xu0_xu1_ex6_rt(xu0_xu1_ex6_rt),
|
||
|
|
.xu0_xu1_ex7_rt(xu0_xu1_ex7_rt),
|
||
|
|
.xu0_xu1_ex8_rt(xu0_xu1_ex8_rt),
|
||
|
|
.xu0_xu1_ex6_lq_rt(xu0_xu1_ex6_lq_rt),
|
||
|
|
.xu0_xu1_ex7_lq_rt(xu0_xu1_ex7_lq_rt),
|
||
|
|
.xu0_xu1_ex8_lq_rt(xu0_xu1_ex8_lq_rt),
|
||
|
|
.lq_xu_ex5_abort(lq_xu_ex5_abort),
|
||
|
|
.lq_xu_ex5_rt(lq_xu_ex5_rt),
|
||
|
|
.lq_xu_rel_act(lq_xu_rel_act),
|
||
|
|
.lq_xu_rel_rt(lq_xu_rel_rt),
|
||
|
|
.lq_xu_ex5_cr(lq_xu_ex5_cr),
|
||
|
|
.xu0_xu1_ex3_cr(xu0_xu1_ex3_cr),
|
||
|
|
.xu0_xu1_ex4_cr(xu0_xu1_ex4_cr),
|
||
|
|
.xu0_xu1_ex6_cr(xu0_xu1_ex6_cr),
|
||
|
|
.xu0_xu1_ex3_xer(xu0_xu1_ex3_xer),
|
||
|
|
.xu0_xu1_ex4_xer(xu0_xu1_ex4_xer),
|
||
|
|
.xu0_xu1_ex6_xer(xu0_xu1_ex6_xer),
|
||
|
|
.alu_byp_ex2_add_rt(alu_byp_ex2_add_rt),
|
||
|
|
.alu_byp_ex3_rt(alu_byp_ex3_rt),
|
||
|
|
.alu_byp_ex3_cr(alu_byp_ex3_cr),
|
||
|
|
.alu_byp_ex3_xer(alu_byp_ex3_xer),
|
||
|
|
.xu1_xu0_ex2_abort(xu1_xu0_ex2_abort),
|
||
|
|
.xu1_lq_ex3_abort(xu1_lq_ex3_abort),
|
||
|
|
.xu1_xu0_ex2_rt(xu1_xu0_ex2_rt),
|
||
|
|
.xu1_xu0_ex3_rt(xu1_xu0_ex3_rt),
|
||
|
|
.xu1_xu0_ex4_rt(xu1_xu0_ex4_rt),
|
||
|
|
.xu1_xu0_ex5_rt(xu1_xu0_ex5_rt),
|
||
|
|
.xu1_lq_ex3_rt(xu1_lq_ex3_rt),
|
||
|
|
.xu1_pc_ram_data(xu1_pc_ram_data),
|
||
|
|
.xu1_xu0_ex3_cr(xu1_xu0_ex3_cr),
|
||
|
|
.xu1_xu0_ex3_xer(xu1_xu0_ex3_xer),
|
||
|
|
.byp_alu_ex2_rs1(byp_alu_ex2_rs1),
|
||
|
|
.byp_alu_ex2_rs2(byp_alu_ex2_rs2),
|
||
|
|
.byp_alu_ex2_cr_bit(byp_alu_ex2_cr_bit),
|
||
|
|
.byp_alu_ex2_xer(byp_alu_ex2_xer),
|
||
|
|
.byp_dec_ex2_xer(byp_dec_ex2_xer),
|
||
|
|
.xu_iu_ucode_xer(xu_iu_ucode_xer),
|
||
|
|
.xu1_rv_ex2_s1_abort(xu1_rv_ex2_s1_abort),
|
||
|
|
.xu1_rv_ex2_s2_abort(xu1_rv_ex2_s2_abort),
|
||
|
|
.xu1_rv_ex2_s3_abort(xu1_rv_ex2_s3_abort),
|
||
|
|
.xu1_gpr_ex3_wd(xu1_gpr_ex3_wd),
|
||
|
|
.xu1_xer_ex3_w0d(xu1_xer_ex3_w0d),
|
||
|
|
.xu1_cr_ex3_w0d(xu1_cr_ex3_w0d),
|
||
|
|
.xu1_lq_ex2_stq_dvc1_cmp(xu1_lq_ex2_stq_dvc1_cmp),
|
||
|
|
.xu1_lq_ex2_stq_dvc2_cmp(xu1_lq_ex2_stq_dvc2_cmp),
|
||
|
|
`ifndef THREADS1
|
||
|
|
.spr_dvc1_t1(spr_dvc1_t1),
|
||
|
|
.spr_dvc2_t1(spr_dvc2_t1),
|
||
|
|
`endif
|
||
|
|
.spr_dvc1_t0(spr_dvc1_t0),
|
||
|
|
.spr_dvc2_t0(spr_dvc2_t0)
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
xu1_dec dec(
|
||
|
|
.nclk(nclk),
|
||
|
|
.vdd(vdd),
|
||
|
|
.gnd(gnd),
|
||
|
|
.d_mode_dc(d_mode_dc),
|
||
|
|
.delay_lclkr_dc(delay_lclkr_dc),
|
||
|
|
.mpw1_dc_b(mpw1_dc_b),
|
||
|
|
.mpw2_dc_b(mpw2_dc_b),
|
||
|
|
.func_sl_force(func_sl_force),
|
||
|
|
.func_sl_thold_0_b(func_sl_thold_0_b),
|
||
|
|
.sg_0(sg_0),
|
||
|
|
.scan_in(siv[2]),
|
||
|
|
.scan_out(sov[2]),
|
||
|
|
.spr_msr_cm(spr_msr_cm), // 0=> 0,
|
||
|
|
.cp_flush(cp_flush),
|
||
|
|
.rv_xu1_vld(rv_xu1_vld),
|
||
|
|
.rv_xu1_ex0_instr(rv_xu1_ex0_instr),
|
||
|
|
.rv_xu1_ex0_itag(rv_xu1_ex0_itag),
|
||
|
|
.rv_xu1_ex0_isstore(rv_xu1_ex0_isstore),
|
||
|
|
.rv_xu1_ex0_ucode(rv_xu1_ex0_ucode),
|
||
|
|
.rv_xu1_ex0_t1_v(rv_xu1_ex0_t1_v),
|
||
|
|
.rv_xu1_ex0_t1_p(rv_xu1_ex0_t1_p),
|
||
|
|
.rv_xu1_ex0_t2_v(rv_xu1_ex0_t2_v),
|
||
|
|
.rv_xu1_ex0_t2_p(rv_xu1_ex0_t2_p),
|
||
|
|
.rv_xu1_ex0_t3_v(rv_xu1_ex0_t3_v),
|
||
|
|
.rv_xu1_ex0_t3_p(rv_xu1_ex0_t3_p),
|
||
|
|
.rv_xu1_ex0_s1_v(rv_xu1_ex0_s1_v),
|
||
|
|
.rv_xu1_ex0_s3_t(rv_xu1_ex0_s3_t),
|
||
|
|
.rv_xu1_ex0_spec_flush(rv_xu1_ex0_spec_flush),
|
||
|
|
.rv_xu1_ex1_spec_flush(rv_xu1_ex1_spec_flush),
|
||
|
|
.rv_xu1_ex2_spec_flush(rv_xu1_ex2_spec_flush),
|
||
|
|
.xu1_lq_ex2_stq_val(xu1_lq_ex2_stq_val),
|
||
|
|
.xu1_lq_ex2_stq_itag(xu1_lq_ex2_stq_itag),
|
||
|
|
.xu1_lq_ex2_stq_size(xu1_lq_ex2_stq_size),
|
||
|
|
.xu1_lq_ex3_illeg_lswx(xu1_lq_ex3_illeg_lswx),
|
||
|
|
.xu1_lq_ex3_strg_noop(xu1_lq_ex3_strg_noop),
|
||
|
|
.xu1_iu_execute_vld(xu1_iu_execute_vld),
|
||
|
|
.xu1_iu_itag(xu1_iu_itag),
|
||
|
|
.xu_iu_ucode_xer_val(xu_iu_ucode_xer_val),
|
||
|
|
.xu1_pc_ram_done(xu1_pc_ram_done),
|
||
|
|
.dec_alu_ex1_act(dec_alu_ex1_act),
|
||
|
|
.dec_alu_ex1_instr(dec_alu_ex1_instr),
|
||
|
|
.dec_alu_ex1_sel_isel(dec_alu_ex1_sel_isel),
|
||
|
|
.dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv),
|
||
|
|
.dec_alu_ex2_add_ci_sel(dec_alu_ex2_add_ci_sel),
|
||
|
|
.dec_alu_ex1_sel_trap(dec_alu_ex1_sel_trap),
|
||
|
|
.dec_alu_ex1_sel_cmpl(dec_alu_ex1_sel_cmpl),
|
||
|
|
.dec_alu_ex1_sel_cmp(dec_alu_ex1_sel_cmp),
|
||
|
|
.dec_alu_ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel),
|
||
|
|
.dec_alu_ex1_xer_ov_en(dec_alu_ex1_xer_ov_en),
|
||
|
|
.dec_alu_ex1_xer_ca_en(dec_alu_ex1_xer_ca_en),
|
||
|
|
.xu1_xu0_ex3_act(xu1_xu0_ex3_act),
|
||
|
|
.dec_byp_ex0_act(dec_byp_ex0_act),
|
||
|
|
.byp_dec_ex2_abort(byp_dec_ex2_abort),
|
||
|
|
.dec_byp_ex1_imm(dec_byp_ex1_imm),
|
||
|
|
.dec_byp_ex1_instr(dec_byp_ex1_instr),
|
||
|
|
.dec_byp_ex0_rs2_sel_imm(dec_byp_ex0_rs2_sel_imm),
|
||
|
|
.dec_byp_ex0_rs1_sel_zero(dec_byp_ex0_rs1_sel_zero),
|
||
|
|
.dec_byp_ex2_tid(dec_byp_ex2_tid),
|
||
|
|
.dec_byp_ex2_dvc_mask(dec_byp_ex2_dvc_mask),
|
||
|
|
.byp_dec_ex2_xer(byp_dec_ex2_xer),
|
||
|
|
.xu1_gpr_ex3_we(xu1_gpr_ex3_we),
|
||
|
|
.xu1_gpr_ex3_wa(xu1_gpr_ex3_wa),
|
||
|
|
.xu1_xer_ex3_we(xu1_xer_ex3_we),
|
||
|
|
.xu1_xer_ex3_wa(xu1_xer_ex3_wa),
|
||
|
|
.xu1_cr_ex3_we(xu1_cr_ex3_we),
|
||
|
|
.xu1_cr_ex3_wa(xu1_cr_ex3_wa),
|
||
|
|
.pc_xu_ram_active(pc_xu_ram_active)
|
||
|
|
);
|
||
|
|
|
||
|
|
assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in};
|
||
|
|
assign scan_out = sov[0];
|
||
|
|
|
||
|
|
endmodule
|