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272 lines
10 KiB
Verilog
272 lines
10 KiB
Verilog
2 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//
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// Description: Pervasive Core LCB Controls
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module pcq_clks(
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// Include model build parameters
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`include "tri_a2o.vh"
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inout vdd,
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inout gnd,
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input [0:`NCLK_WIDTH-1] nclk,
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input rtim_sl_thold_7,
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input func_sl_thold_7,
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input func_nsl_thold_7,
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input ary_nsl_thold_7,
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input sg_7,
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input fce_7,
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input gsd_test_enable_dc,
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input gsd_test_acmode_dc,
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input ccflush_dc,
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input ccenable_dc,
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input lbist_en_dc,
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input lbist_ip_dc,
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input rg_ck_fast_xstop,
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input ct_ck_pm_ccflush_disable,
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input ct_ck_pm_raise_tholds,
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input [0:8] scan_type_dc,
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// --Thold + control outputs to the units
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output pc_pc_ccflush_out_dc,
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output pc_pc_gptr_sl_thold_4,
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output pc_pc_time_sl_thold_4,
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output pc_pc_repr_sl_thold_4,
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output pc_pc_abst_sl_thold_4,
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output pc_pc_abst_slp_sl_thold_4,
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output pc_pc_regf_sl_thold_4,
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output pc_pc_regf_slp_sl_thold_4,
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output pc_pc_func_sl_thold_4,
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output pc_pc_func_slp_sl_thold_4,
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output pc_pc_cfg_sl_thold_4,
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output pc_pc_cfg_slp_sl_thold_4,
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output pc_pc_func_nsl_thold_4,
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output pc_pc_func_slp_nsl_thold_4,
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output pc_pc_ary_nsl_thold_4,
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output pc_pc_ary_slp_nsl_thold_4,
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output pc_pc_rtim_sl_thold_4,
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output pc_pc_sg_4,
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output pc_pc_fce_4,
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// Thold + control signals used by fu
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output pc_fu_ccflush_dc,
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output pc_fu_gptr_sl_thold_3,
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output pc_fu_time_sl_thold_3,
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output pc_fu_repr_sl_thold_3,
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output pc_fu_abst_sl_thold_3,
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output pc_fu_abst_slp_sl_thold_3,
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output [0:1] pc_fu_func_sl_thold_3,
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output [0:1] pc_fu_func_slp_sl_thold_3,
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output pc_fu_cfg_sl_thold_3,
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output pc_fu_cfg_slp_sl_thold_3,
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output pc_fu_func_nsl_thold_3,
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output pc_fu_func_slp_nsl_thold_3,
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output pc_fu_ary_nsl_thold_3,
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output pc_fu_ary_slp_nsl_thold_3,
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output [0:1] pc_fu_sg_3,
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output pc_fu_fce_3,
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// Thold + control signals used in pcq
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output pc_pc_ccflush_dc,
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output pc_pc_gptr_sl_thold_0,
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output pc_pc_func_sl_thold_0,
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output pc_pc_func_slp_sl_thold_0,
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output pc_pc_cfg_sl_thold_0,
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output pc_pc_cfg_slp_sl_thold_0,
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output pc_pc_sg_0
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);
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//=====================================================================
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// Signal Declarations
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//=====================================================================
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wire rtim_sl_thold_6;
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wire func_sl_thold_6;
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wire func_nsl_thold_6;
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wire ary_nsl_thold_6;
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wire sg_6;
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wire fce_6;
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wire ccflush_out_dc;
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wire gptr_sl_thold_5;
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wire time_sl_thold_5;
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wire repr_sl_thold_5;
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wire abst_sl_thold_5;
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wire abst_slp_sl_thold_5;
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wire regf_sl_thold_5;
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wire regf_slp_sl_thold_5;
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wire func_sl_thold_5;
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wire func_slp_sl_thold_5;
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wire cfg_sl_thold_5;
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wire cfg_slp_sl_thold_5;
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wire func_nsl_thold_5;
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wire func_slp_nsl_thold_5;
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wire ary_nsl_thold_5;
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wire ary_slp_nsl_thold_5;
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wire rtim_sl_thold_5;
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wire sg_5;
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wire fce_5;
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//=====================================================================
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// Clock Control and Staging Logic
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//=====================================================================
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pcq_clks_ctrl clkctrl(
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.vdd(vdd),
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.gnd(gnd),
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.nclk(nclk),
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.rtim_sl_thold_6(rtim_sl_thold_6),
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.func_sl_thold_6(func_sl_thold_6),
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.func_nsl_thold_6(func_nsl_thold_6),
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.ary_nsl_thold_6(ary_nsl_thold_6),
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.sg_6(sg_6),
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.fce_6(fce_6),
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.gsd_test_enable_dc(gsd_test_enable_dc),
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.gsd_test_acmode_dc(gsd_test_acmode_dc),
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.ccflush_dc(ccflush_dc),
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.ccenable_dc(ccenable_dc),
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.scan_type_dc(scan_type_dc),
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.lbist_en_dc(lbist_en_dc),
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.lbist_ip_dc(lbist_ip_dc),
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.rg_ck_fast_xstop(rg_ck_fast_xstop),
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.ct_ck_pm_ccflush_disable(ct_ck_pm_ccflush_disable),
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.ct_ck_pm_raise_tholds(ct_ck_pm_raise_tholds),
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// --Thold + control outputs to the units
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.ccflush_out_dc(ccflush_out_dc),
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.gptr_sl_thold_5(gptr_sl_thold_5),
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.time_sl_thold_5(time_sl_thold_5),
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.repr_sl_thold_5(repr_sl_thold_5),
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.cfg_sl_thold_5(cfg_sl_thold_5),
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.cfg_slp_sl_thold_5(cfg_slp_sl_thold_5),
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.abst_sl_thold_5(abst_sl_thold_5),
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.abst_slp_sl_thold_5(abst_slp_sl_thold_5),
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.regf_sl_thold_5(regf_sl_thold_5),
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.regf_slp_sl_thold_5(regf_slp_sl_thold_5),
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.func_sl_thold_5(func_sl_thold_5),
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.func_slp_sl_thold_5(func_slp_sl_thold_5),
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.func_nsl_thold_5(func_nsl_thold_5),
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.func_slp_nsl_thold_5(func_slp_nsl_thold_5),
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.ary_nsl_thold_5(ary_nsl_thold_5),
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.ary_slp_nsl_thold_5(ary_slp_nsl_thold_5),
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.rtim_sl_thold_5(rtim_sl_thold_5),
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.sg_5(sg_5),
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.fce_5(fce_5)
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);
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pcq_clks_stg clkstg(
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.vdd(vdd),
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.gnd(gnd),
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.nclk(nclk),
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.ccflush_out_dc(ccflush_out_dc),
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.gptr_sl_thold_5(gptr_sl_thold_5),
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.time_sl_thold_5(time_sl_thold_5),
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.repr_sl_thold_5(repr_sl_thold_5),
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.cfg_sl_thold_5(cfg_sl_thold_5),
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.cfg_slp_sl_thold_5(cfg_slp_sl_thold_5),
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.abst_sl_thold_5(abst_sl_thold_5),
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.abst_slp_sl_thold_5(abst_slp_sl_thold_5),
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.regf_sl_thold_5(regf_sl_thold_5),
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.regf_slp_sl_thold_5(regf_slp_sl_thold_5),
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.func_sl_thold_5(func_sl_thold_5),
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.func_slp_sl_thold_5(func_slp_sl_thold_5),
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.func_nsl_thold_5(func_nsl_thold_5),
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.func_slp_nsl_thold_5(func_slp_nsl_thold_5),
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.ary_nsl_thold_5(ary_nsl_thold_5),
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.ary_slp_nsl_thold_5(ary_slp_nsl_thold_5),
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.rtim_sl_thold_5(rtim_sl_thold_5),
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.sg_5(sg_5),
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.fce_5(fce_5),
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// Thold + control outputs to the units
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.pc_pc_ccflush_out_dc(pc_pc_ccflush_out_dc),
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.pc_pc_gptr_sl_thold_4(pc_pc_gptr_sl_thold_4),
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.pc_pc_time_sl_thold_4(pc_pc_time_sl_thold_4),
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.pc_pc_repr_sl_thold_4(pc_pc_repr_sl_thold_4),
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.pc_pc_abst_sl_thold_4(pc_pc_abst_sl_thold_4),
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.pc_pc_abst_slp_sl_thold_4(pc_pc_abst_slp_sl_thold_4),
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.pc_pc_regf_sl_thold_4(pc_pc_regf_sl_thold_4),
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.pc_pc_regf_slp_sl_thold_4(pc_pc_regf_slp_sl_thold_4),
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.pc_pc_func_sl_thold_4(pc_pc_func_sl_thold_4),
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.pc_pc_func_slp_sl_thold_4(pc_pc_func_slp_sl_thold_4),
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.pc_pc_cfg_sl_thold_4(pc_pc_cfg_sl_thold_4),
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.pc_pc_cfg_slp_sl_thold_4(pc_pc_cfg_slp_sl_thold_4),
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.pc_pc_func_nsl_thold_4(pc_pc_func_nsl_thold_4),
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.pc_pc_func_slp_nsl_thold_4(pc_pc_func_slp_nsl_thold_4),
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.pc_pc_ary_nsl_thold_4(pc_pc_ary_nsl_thold_4),
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.pc_pc_ary_slp_nsl_thold_4(pc_pc_ary_slp_nsl_thold_4),
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.pc_pc_rtim_sl_thold_4(pc_pc_rtim_sl_thold_4),
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.pc_pc_sg_4(pc_pc_sg_4),
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.pc_pc_fce_4(pc_pc_fce_4),
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// Thold + control signals used by fu
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.pc_fu_ccflush_dc(pc_fu_ccflush_dc),
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.pc_fu_gptr_sl_thold_3(pc_fu_gptr_sl_thold_3),
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.pc_fu_time_sl_thold_3(pc_fu_time_sl_thold_3),
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.pc_fu_repr_sl_thold_3(pc_fu_repr_sl_thold_3),
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.pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3),
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.pc_fu_abst_slp_sl_thold_3(pc_fu_abst_slp_sl_thold_3),
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.pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3),
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.pc_fu_func_slp_sl_thold_3(pc_fu_func_slp_sl_thold_3),
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.pc_fu_cfg_sl_thold_3(pc_fu_cfg_sl_thold_3),
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.pc_fu_cfg_slp_sl_thold_3(pc_fu_cfg_slp_sl_thold_3),
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.pc_fu_func_nsl_thold_3(pc_fu_func_nsl_thold_3),
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.pc_fu_func_slp_nsl_thold_3(pc_fu_func_slp_nsl_thold_3),
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.pc_fu_ary_nsl_thold_3(pc_fu_ary_nsl_thold_3),
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.pc_fu_ary_slp_nsl_thold_3(pc_fu_ary_slp_nsl_thold_3),
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.pc_fu_sg_3(pc_fu_sg_3),
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.pc_fu_fce_3(pc_fu_fce_3),
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// PC Unit thold + control signals
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.pc_pc_ccflush_dc(pc_pc_ccflush_dc),
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.pc_pc_gptr_sl_thold_0(pc_pc_gptr_sl_thold_0),
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.pc_pc_func_sl_thold_0(pc_pc_func_sl_thold_0),
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.pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0),
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.pc_pc_cfg_sl_thold_0(pc_pc_cfg_sl_thold_0),
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.pc_pc_cfg_slp_sl_thold_0(pc_pc_cfg_slp_sl_thold_0),
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.pc_pc_sg_0(pc_pc_sg_0)
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);
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tri_plat #(.WIDTH(6)) lvl7to6_plat(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(ccflush_dc),
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.din({rtim_sl_thold_7, func_sl_thold_7, func_nsl_thold_7,
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ary_nsl_thold_7, sg_7, fce_7}),
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.q( {rtim_sl_thold_6, func_sl_thold_6, func_nsl_thold_6,
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ary_nsl_thold_6, sg_6, fce_6})
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);
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endmodule
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