a2o/dev/verilog/trilib/tri_oai21.v

// © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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//    necessary for implementation of the Work that are available from OpenPOWER
//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
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`timescale 1 ns / 1 ns

// *!****************************************************************
// *! FILENAME    : tri_oai21.v
// *! DESCRIPTION : OAI21 gate
// *!****************************************************************

`include "tri_a2o.vh"

module tri_oai21(
   y,
   a0,
   a1,
   b0
);
   parameter                      WIDTH = 1;
   parameter                      BTR = "OAI21_X2M_NONE";  //Specify full BTR name, else let tool select
   output [0:WIDTH-1]  y;
   input [0:WIDTH-1]   a0;
   input [0:WIDTH-1]   a1;
   input [0:WIDTH-1]   b0;

   // tri_oai21
   genvar 	       i;
   wire [0:WIDTH-1]    outA;

   generate
	   for (i = 0; i < WIDTH; i = i + 1) begin : w

	      or   I0(outA[i], a0[i], a1[i]);
	      nand I2(y[i], outA[i], b0[i]);

	   end

   endgenerate
endmodule