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102 lines
4.0 KiB
Verilog
102 lines
4.0 KiB
Verilog
3 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: Address Decoder
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//
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//*****************************************************************************
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module tri_addrcmp(
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enable_lsb,
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d0,
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d1,
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eq
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);
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input enable_lsb; // when "0" the LSB is disabled
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input [0:35] d0;
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input [0:35] d1;
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output eq;
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// tri_addrcmp
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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wire [0:35] eq01_b;
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wire [0:18] eq02;
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wire [0:9] eq04_b;
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wire [0:4] eq08;
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wire [0:1] eq24_b;
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assign eq01_b[0:35] = (d0[0:35] ^ d1[0:35]);
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assign eq02[0] = (~(eq01_b[0] | eq01_b[1]));
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assign eq02[1] = (~(eq01_b[2] | eq01_b[3]));
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assign eq02[2] = (~(eq01_b[4] | eq01_b[5]));
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assign eq02[3] = (~(eq01_b[6] | eq01_b[7]));
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assign eq02[4] = (~(eq01_b[8] | eq01_b[9]));
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assign eq02[5] = (~(eq01_b[10] | eq01_b[11]));
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assign eq02[6] = (~(eq01_b[12] | eq01_b[13]));
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assign eq02[7] = (~(eq01_b[14] | eq01_b[15]));
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assign eq02[8] = (~(eq01_b[16] | eq01_b[17]));
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assign eq02[9] = (~(eq01_b[18] | eq01_b[19]));
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assign eq02[10] = (~(eq01_b[20] | eq01_b[21]));
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assign eq02[11] = (~(eq01_b[22] | eq01_b[23]));
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assign eq02[12] = (~(eq01_b[24] | eq01_b[25]));
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assign eq02[13] = (~(eq01_b[26] | eq01_b[27]));
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assign eq02[14] = (~(eq01_b[28] | eq01_b[29]));
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assign eq02[15] = (~(eq01_b[30] | eq01_b[31]));
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assign eq02[16] = (~(eq01_b[32] | eq01_b[33]));
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assign eq02[17] = (~(eq01_b[34]));
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assign eq02[18] = (~(eq01_b[35] & enable_lsb));
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assign eq04_b[0] = (~(eq02[0] & eq02[1]));
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assign eq04_b[1] = (~(eq02[2] & eq02[3]));
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assign eq04_b[2] = (~(eq02[4] & eq02[5]));
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assign eq04_b[3] = (~(eq02[6] & eq02[7]));
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assign eq04_b[4] = (~(eq02[8] & eq02[9]));
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assign eq04_b[5] = (~(eq02[10] & eq02[11]));
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assign eq04_b[6] = (~(eq02[12] & eq02[13]));
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assign eq04_b[7] = (~(eq02[14] & eq02[15]));
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assign eq04_b[8] = (~(eq02[16] & eq02[17]));
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assign eq04_b[9] = (~(eq02[18]));
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assign eq08[0] = (~(eq04_b[0] | eq04_b[1]));
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assign eq08[1] = (~(eq04_b[2] | eq04_b[3]));
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assign eq08[2] = (~(eq04_b[4] | eq04_b[5]));
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assign eq08[3] = (~(eq04_b[6] | eq04_b[7]));
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assign eq08[4] = (~(eq04_b[8] | eq04_b[9]));
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assign eq24_b[0] = (~(eq08[0] & eq08[1] & eq08[2]));
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assign eq24_b[1] = (~(eq08[3] & eq08[4]));
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assign eq = (~(eq24_b[0] | eq24_b[1])); // output
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endmodule
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