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// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`include "tri_a2o.vh"
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`timescale 1ns/1ps
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module a2owb (
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input [0:`NCLK_WIDTH-1] nclk,
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input scan_in,
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output scan_out,
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// Pervasive clock control
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input an_ac_rtim_sl_thold_8,
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input an_ac_func_sl_thold_8,
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input an_ac_func_nsl_thold_8,
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input an_ac_ary_nsl_thold_8,
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input an_ac_sg_8,
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input an_ac_fce_8,
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input [0:7] an_ac_abst_scan_in,
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//SCOM Satellite
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input [0:3] an_ac_scom_sat_id,
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input an_ac_scom_dch,
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input an_ac_scom_cch,
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output ac_an_scom_dch,
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output ac_an_scom_cch,
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// FIR and Error Signals
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output [0:`THREADS-1] ac_an_special_attn,
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output [0:2] ac_an_checkstop,
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output [0:2] ac_an_local_checkstop,
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output [0:2] ac_an_recov_err,
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output ac_an_trace_error,
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output ac_an_livelock_active,
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// Perfmon Event Bus
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output [0:4*`THREADS-1] ac_an_event_bus0,
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output [0:4*`THREADS-1] ac_an_event_bus1,
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// Power Management
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output [0:`THREADS-1] ac_an_pm_thread_running,
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input [0:`THREADS-1] an_ac_pm_thread_stop,
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input [0:`THREADS-1] an_ac_pm_fetch_halt,
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// Clock, Test, and LCB Controls
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input an_ac_gsd_test_enable_dc,
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input an_ac_gsd_test_acmode_dc,
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input an_ac_ccflush_dc,
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input an_ac_ccenable_dc,
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input an_ac_lbist_en_dc,
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input an_ac_lbist_ip_dc,
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input an_ac_lbist_ac_mode_dc,
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input an_ac_scan_diag_dc,
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input an_ac_scan_dis_dc_b,
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//Thold input to clock control macro
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input [0:8] an_ac_scan_type_dc,
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// Pervasive
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output ac_an_reset_1_request,
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output ac_an_reset_2_request,
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output ac_an_reset_3_request,
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output ac_an_reset_wd_request,
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input an_ac_lbist_ary_wrt_thru_dc,
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input [0:`THREADS-1] an_ac_sleep_en,
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input [0:`THREADS-1] an_ac_ext_interrupt,
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input [0:`THREADS-1] an_ac_crit_interrupt,
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input [0:`THREADS-1] an_ac_perf_interrupt,
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input [0:`THREADS-1] an_ac_hang_pulse,
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input an_ac_tb_update_enable,
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input an_ac_tb_update_pulse,
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input [0:3] an_ac_chipid_dc,
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input [0:7] an_ac_coreid,
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output [0:`THREADS-1] ac_an_machine_check,
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input an_ac_debug_stop,
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output [0:`THREADS-1] ac_an_debug_trigger,
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input [0:`THREADS-1] an_ac_uncond_dbg_event,
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output [0:31] ac_an_debug_bus,
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output ac_an_coretrace_first_valid,
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output ac_an_coretrace_valid,
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output [0:1] ac_an_coretrace_type,
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input an_ac_flh2l2_gate,
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input an_ac_reset_1_complete,
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input an_ac_reset_2_complete,
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input an_ac_reset_3_complete,
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input an_ac_reset_wd_complete,
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output an_ac_checkstop,
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input [0:`THREADS-1] an_ac_external_mchk,
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output ac_an_power_managed,
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output ac_an_rvwinkle_mode,
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// direct-attach mem
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output [0:31] mem_adr,
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input [0:127] mem_dat,
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output mem_wr_val,
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output [0:15] mem_wr_be,
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output [0:127] mem_wr_dat,
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// wishbone
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output wb_stb,
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output wb_cyc,
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output [31:0] wb_adr,
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output wb_we,
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output [3:0] wb_sel,
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output [31:0] wb_datw,
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input wb_ack,
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input [31:0] wb_datr
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);
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wire [0:`THREADS-1] an_ac_stcx_complete;
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wire [0:`THREADS-1] an_ac_stcx_pass;
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wire [0:1] an_ac_icbi_ack_thread;
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wire [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra;
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wire [0:4] an_ac_back_inv_target;
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wire [0:7] an_ac_back_inv_lpar_id;
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wire [0:7] ac_an_lpar_id;
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wire [0:4] an_ac_reld_core_tag;
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wire [0:127] an_ac_reld_data;
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wire [0:1] an_ac_reld_qw;
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wire [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr;
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wire [0:5] ac_an_req_ttype;
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wire [0:2] ac_an_req_thread;
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wire [0:3] ac_an_req_user_defined;
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wire [0:3] ac_an_req_spare_ctrl_a0;
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wire [0:4] ac_an_req_ld_core_tag;
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wire [0:2] ac_an_req_ld_xfr_len;
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wire [0:31] ac_an_st_byte_enbl;
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wire [0:255] ac_an_st_data;
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wire [0:3] an_ac_req_spare_ctrl_a1;
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wire [0:`THREADS-1] an_ac_sync_ack;
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wire [0:`THREADS-1] an_ac_reservation_vld;
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c c0(
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.nclk(nclk),
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.scan_in(scan_in),
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.scan_out(scan_out),
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.an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
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.an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
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.an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
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.an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
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.an_ac_sg_8(an_ac_sg_8),
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.an_ac_fce_8(an_ac_fce_8),
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.an_ac_abst_scan_in(an_ac_abst_scan_in),
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.an_ac_stcx_complete(an_ac_stcx_complete[0]),
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.an_ac_stcx_pass(an_ac_stcx_pass[0]),
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.an_ac_reservation_vld(an_ac_reservation_vld[0]),
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.an_ac_icbi_ack(an_ac_icbi_ack),
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.an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),
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.an_ac_sync_ack(an_ac_sync_ack[0]),
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.an_ac_back_inv(an_ac_back_inv),
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.an_ac_back_inv_addr(an_ac_back_inv_addr),
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.an_ac_back_inv_target(an_ac_back_inv_target),
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.an_ac_back_inv_local(an_ac_back_inv_local),
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.an_ac_back_inv_lbit(an_ac_back_inv_lbit),
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.an_ac_back_inv_gs(an_ac_back_inv_gs),
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.an_ac_back_inv_ind(an_ac_back_inv_ind),
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.an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
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.ac_an_back_inv_reject(ac_an_back_inv_reject),
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.ac_an_lpar_id(ac_an_lpar_id),
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.an_ac_reld_data_vld(an_ac_reld_data_vld),
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.an_ac_reld_core_tag(an_ac_reld_core_tag),
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.an_ac_reld_data(an_ac_reld_data),
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.an_ac_reld_qw(an_ac_reld_qw),
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.an_ac_reld_ecc_err(an_ac_reld_ecc_err),
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.an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
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.an_ac_reld_data_coming(an_ac_reld_data_coming),
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.an_ac_reld_ditc(an_ac_reld_ditc),
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.an_ac_reld_crit_qw(an_ac_reld_crit_qw),
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.an_ac_reld_l1_dump(an_ac_reld_l1_dump),
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.an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),
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.an_ac_flh2l2_gate(an_ac_flh2l2_gate),
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.an_ac_req_ld_pop(an_ac_req_ld_pop),
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.an_ac_req_st_pop(an_ac_req_st_pop),
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.an_ac_req_st_gather(an_ac_req_st_gather),
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.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
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.an_ac_scom_sat_id(an_ac_scom_sat_id),
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.an_ac_scom_dch(an_ac_scom_dch),
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.an_ac_scom_cch(an_ac_scom_cch),
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.ac_an_scom_dch(ac_an_scom_dch),
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.ac_an_scom_cch(ac_an_scom_cch),
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.ac_an_special_attn(ac_an_special_attn),
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.ac_an_checkstop(ac_an_checkstop),
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.ac_an_local_checkstop(ac_an_local_checkstop),
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.ac_an_recov_err(ac_an_recov_err),
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.ac_an_trace_error(ac_an_trace_error),
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.ac_an_livelock_active(ac_an_livelock_active),
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.an_ac_checkstop(an_ac_checkstop),
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.an_ac_external_mchk(an_ac_external_mchk),
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.ac_an_event_bus0(ac_an_event_bus0),
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.an_ac_reset_1_complete(an_ac_reset_1_complete),
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.an_ac_reset_2_complete(an_ac_reset_2_complete),
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.an_ac_reset_3_complete(an_ac_reset_3_complete),
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.an_ac_reset_wd_complete(an_ac_reset_wd_complete),
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.ac_an_pm_thread_running(ac_an_pm_thread_running),
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.an_ac_pm_thread_stop(an_ac_pm_thread_stop),
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.ac_an_power_managed(ac_an_power_managed),
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.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
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.an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
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.an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
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.an_ac_ccflush_dc(an_ac_ccflush_dc),
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.an_ac_ccenable_dc(an_ac_ccenable_dc),
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.an_ac_lbist_en_dc(an_ac_lbist_en_dc),
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.an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
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.an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
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.an_ac_scan_diag_dc(an_ac_scan_diag_dc),
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.an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
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.an_ac_scan_type_dc(an_ac_scan_type_dc),
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.ac_an_reset_1_request(ac_an_reset_1_request),
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.ac_an_reset_2_request(ac_an_reset_2_request),
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.ac_an_reset_3_request(ac_an_reset_3_request),
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.ac_an_reset_wd_request(ac_an_reset_wd_request),
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.an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
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.an_ac_sleep_en(an_ac_sleep_en),
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.an_ac_ext_interrupt(an_ac_ext_interrupt),
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.an_ac_crit_interrupt(an_ac_crit_interrupt),
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.an_ac_perf_interrupt(an_ac_perf_interrupt),
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.an_ac_hang_pulse(an_ac_hang_pulse),
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.an_ac_tb_update_enable(an_ac_tb_update_enable),
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.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
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.an_ac_chipid_dc(an_ac_chipid_dc),
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.an_ac_coreid(an_ac_coreid),
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.ac_an_machine_check(ac_an_machine_check),
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.an_ac_debug_stop(an_ac_debug_stop),
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.ac_an_debug_trigger(ac_an_debug_trigger),
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.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
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.ac_an_req_pwr_token(ac_an_req_pwr_token),
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.ac_an_req(ac_an_req),
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.ac_an_req_ra(ac_an_req_ra),
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.ac_an_req_ttype(ac_an_req_ttype),
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.ac_an_req_thread(ac_an_req_thread),
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.ac_an_req_wimg_w(ac_an_req_wimg_w),
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.ac_an_req_wimg_i(ac_an_req_wimg_i),
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.ac_an_req_wimg_m(ac_an_req_wimg_m),
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.ac_an_req_wimg_g(ac_an_req_wimg_g),
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.ac_an_req_user_defined(ac_an_req_user_defined),
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.ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
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.ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
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.ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
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.ac_an_st_byte_enbl(ac_an_st_byte_enbl),
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.ac_an_st_data(ac_an_st_data),
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.ac_an_req_endian(ac_an_req_endian),
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.ac_an_st_data_pwr_token(ac_an_st_data_pwr_token)
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);
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a2l2wb n0(
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.clk(clk_1x),
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.rst(rst),
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// request
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.ac_an_req_pwr_token(ac_an_req_pwr_token),
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.ac_an_req(ac_an_req),
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.ac_an_req_ra(ac_an_req_ra),
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.ac_an_req_ttype(ac_an_req_ttype),
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.ac_an_req_thread(ac_an_req_thread),
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.ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
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.ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
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.ac_an_st_data_pwr_token(ac_an_st_data_pwr_token),
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.ac_an_st_byte_enbl(ac_an_st_byte_enbl),
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.ac_an_st_data(ac_an_st_data),
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.ac_an_req_wimg_w(ac_an_req_wimg_w),
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.ac_an_req_wimg_i(ac_an_req_wimg_i),
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.ac_an_req_wimg_m(ac_an_req_wimg_m),
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.ac_an_req_wimg_g(ac_an_req_wimg_g),
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.ac_an_req_endian(ac_an_req_endian),
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|
.ac_an_req_user_defined(ac_an_req_user_defined),
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|
.ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
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// reload
|
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.an_ac_reld_data_vld(an_ac_reld_data_vld),
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.an_ac_reld_core_tag(an_ac_reld_core_tag),
|
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|
|
|
.an_ac_reld_data(an_ac_reld_data),
|
|
|
|
|
.an_ac_reld_qw(an_ac_reld_qw),
|
|
|
|
|
.an_ac_reld_ecc_err(an_ac_reld_ecc_err),
|
|
|
|
|
.an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
|
|
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|
|
.an_ac_reld_data_coming(an_ac_reld_data_coming),
|
|
|
|
|
.an_ac_reld_ditc(an_ac_reld_ditc),
|
|
|
|
|
.an_ac_reld_crit_qw(an_ac_reld_crit_qw),
|
|
|
|
|
.an_ac_reld_l1_dump(an_ac_reld_l1_dump),
|
|
|
|
|
.an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),
|
|
|
|
|
|
|
|
|
|
// larx/stcx
|
|
|
|
|
.an_ac_stcx_complete(an_ac_stcx_complete),
|
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|
|
|
.an_ac_stcx_pass(an_ac_stcx_pass),
|
|
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|
|
.an_ac_reservation_vld(an_ac_reservation_vld),
|
|
|
|
|
|
|
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|
|
// icbi
|
|
|
|
|
.an_ac_icbi_ack(an_ac_icbi_ack),
|
|
|
|
|
.an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),
|
|
|
|
|
|
|
|
|
|
// back invalidate
|
|
|
|
|
.an_ac_back_inv(an_ac_back_inv),
|
|
|
|
|
.an_ac_back_inv_addr(an_ac_back_inv_addr),
|
|
|
|
|
.an_ac_back_inv_target(an_ac_back_inv_target),
|
|
|
|
|
.an_ac_back_inv_local(an_ac_back_inv_local),
|
|
|
|
|
.an_ac_back_inv_lbit(an_ac_back_inv_lbit),
|
|
|
|
|
.an_ac_back_inv_gs(an_ac_back_inv_gs),
|
|
|
|
|
.an_ac_back_inv_ind(an_ac_back_inv_ind),
|
|
|
|
|
.an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
|
|
|
|
|
.ac_an_back_inv_reject(ac_an_back_inv_reject),
|
|
|
|
|
.ac_an_lpar_id(ac_an_lpar_id),
|
|
|
|
|
|
|
|
|
|
// credits
|
|
|
|
|
.an_ac_req_ld_pop(an_ac_req_ld_pop),
|
|
|
|
|
.an_ac_req_st_pop(an_ac_req_st_pop),
|
|
|
|
|
.an_ac_req_st_gather(an_ac_req_st_gather),
|
|
|
|
|
.an_ac_sync_ack(an_ac_sync_ack),
|
|
|
|
|
//.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
|
|
|
|
|
|
|
|
|
|
// misc
|
|
|
|
|
//.an_ac_flh2l2_gate(an_ac_flh2l2_gate),
|
|
|
|
|
//.an_ac_reset_1_complete(an_ac_reset_1_complete),
|
|
|
|
|
//.an_ac_reset_2_complete(an_ac_reset_2_complete),
|
|
|
|
|
//.an_ac_reset_3_complete(an_ac_reset_3_complete),
|
|
|
|
|
//.an_ac_reset_wd_complete(an_ac_reset_wd_complete),
|
|
|
|
|
//.an_ac_sleep_en(an_ac_sleep_en),
|
|
|
|
|
//.an_ac_ext_interrupt(an_ac_ext_interrupt),
|
|
|
|
|
//.an_ac_crit_interrupt(an_ac_crit_interrupt),
|
|
|
|
|
//.an_ac_perf_interrupt(an_ac_perf_interrupt),
|
|
|
|
|
//.an_ac_hang_pulse(an_ac_hang_pulse),
|
|
|
|
|
//.an_ac_tb_update_enable(an_ac_tb_update_enable),
|
|
|
|
|
//.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
|
|
|
|
|
//.an_ac_chipid_dc(an_ac_chipid_dc),
|
|
|
|
|
//.an_ac_coreid(an_ac_coreid),
|
|
|
|
|
//.an_ac_debug_stop(an_ac_debug_stop),
|
|
|
|
|
//.ac_an_debug_trigger(ac_an_debug_trigger),
|
|
|
|
|
//.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
|
|
|
|
|
|
|
|
|
|
// scom
|
|
|
|
|
//.an_ac_scom_sat_id(an_ac_scom_sat_id),
|
|
|
|
|
//.an_ac_scom_dch(an_ac_scom_dch),
|
|
|
|
|
//.an_ac_scom_cch(an_ac_scom_cch),
|
|
|
|
|
//.ac_an_scom_dch(ac_an_scom_dch),
|
|
|
|
|
//.ac_an_scom_cch(ac_an_scom_cch),
|
|
|
|
|
|
|
|
|
|
// errors
|
|
|
|
|
//.ac_an_special_attn(ac_an_special_attn),
|
|
|
|
|
//.ac_an_checkstop(ac_an_checkstop),
|
|
|
|
|
//.ac_an_local_checkstop(ac_an_local_checkstop),
|
|
|
|
|
//.ac_an_recov_err(ac_an_recov_err),
|
|
|
|
|
//.ac_an_trace_error(ac_an_trace_error),
|
|
|
|
|
//.ac_an_livelock_active(ac_an_livelock_active),
|
|
|
|
|
.an_ac_checkstop(an_ac_checkstop),
|
|
|
|
|
//.an_ac_external_mchk(an_ac_external_mchk),
|
|
|
|
|
//.ac_an_machine_check(ac_an_machine_check),
|
|
|
|
|
|
|
|
|
|
// perfmon
|
|
|
|
|
//.ac_an_event_bus0(ac_an_event_bus0),
|
|
|
|
|
//.ac_an_event_bus1(ac_an_event_bus1),
|
|
|
|
|
|
|
|
|
|
// power
|
|
|
|
|
//.ac_an_pm_thread_running(ac_an_pm_thread_running),
|
|
|
|
|
//.an_ac_pm_thread_stop(an_ac_pm_thread_stop),
|
|
|
|
|
//.ac_an_power_managed(ac_an_power_managed),
|
|
|
|
|
//.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode)
|
|
|
|
|
// direct-attach mem
|
|
|
|
|
.mem_adr(mem_adr),
|
|
|
|
|
.mem_dat(mem_dat),
|
|
|
|
|
.mem_wr_be(mem_wr_be),
|
|
|
|
|
.mem_wr_val(mem_wr_val),
|
|
|
|
|
|
|
|
|
|
.mem_wr_dat(mem_wr_dat),
|
|
|
|
|
|
|
|
|
|
// wishbone
|
|
|
|
|
.wb_stb(wb_stb),
|
|
|
|
|
.wb_cyc(wb_cyc),
|
|
|
|
|
.wb_adr(wb_adr),
|
|
|
|
|
.wb_we(wb_we),
|
|
|
|
|
.wb_ack(wb_ack),
|
|
|
|
|
.wb_sel(wb_sel),
|
|
|
|
|
.wb_datr(wb_datr),
|
|
|
|
|
.wb_datw(wb_datw)
|
|
|
|
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
wire clk_1x, clk_2x, clk_4x, rst;
|
|
|
|
|
|
|
|
|
|
assign clk_1x = nclk[0];
|
|
|
|
|
assign clk_2x = nclk[2];
|
|
|
|
|
assign clk_4x = nclk[3];
|
|
|
|
|
assign rst = nclk[1];
|
|
|
|
|
|
|
|
|
|
endmodule
|
