start a2l2wb
parent
bc0e3204b7
commit
0dcb681aad
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# a2o tb-node
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SIM_BUILD ?= build_node
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SIM ?= icarus
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# icarus
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VERILOG_ROOT = ../../verilog
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COMPILE_ARGS = -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/a2node
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# other options
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# rtl
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TOPLEVEL_LANG = verilog
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# top-level to enable trace, etc.
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VERILOG_SOURCES = ./cocotb_icarus_node.v
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TOPLEVEL = cocotb_icarus_node
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# python test
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MODULE = tb_node
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# cocotb make rules
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include $(shell cocotb-config --makefiles)/Makefile.sim
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build: clean sim fst
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run: sim fst
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vcd: sim
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fst:
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vcd2fst a2onode.vcd a2onode.fst
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rm a2onode.vcd
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`include "tri_a2o.vh"
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`timescale 1ns/1ps
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// might add some sim-only lines to enable clks, etc.
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module cocotb_icarus_node (
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input[0:`NCLK_WIDTH-1] nclk,
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input scan_in,
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output scan_out,
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// Pervasive clock control
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input an_ac_rtim_sl_thold_8,
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input an_ac_func_sl_thold_8,
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input an_ac_func_nsl_thold_8,
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input an_ac_ary_nsl_thold_8,
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input an_ac_sg_8,
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input an_ac_fce_8,
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input [0:7] an_ac_abst_scan_in,
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//SCOM Satellite
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input [0:3] an_ac_scom_sat_id,
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input an_ac_scom_dch,
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input an_ac_scom_cch,
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output ac_an_scom_dch,
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output ac_an_scom_cch,
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// FIR and Error Signals
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output [0:`THREADS-1] ac_an_special_attn,
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output [0:2] ac_an_checkstop,
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output [0:2] ac_an_local_checkstop,
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output [0:2] ac_an_recov_err,
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output ac_an_trace_error,
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output ac_an_livelock_active,
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input [0:`THREADS-1] an_ac_external_mchk,
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output an_ac_checkstop,
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// Perfmon Event Bus
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output [0:4*`THREADS-1] ac_an_event_bus0,
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output [0:4*`THREADS-1] ac_an_event_bus1,
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// Reset related
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input an_ac_reset_1_complete,
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input an_ac_reset_2_complete,
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input an_ac_reset_3_complete,
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input an_ac_reset_wd_complete,
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// Power Management
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output [0:`THREADS-1] ac_an_pm_thread_running,
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input [0:`THREADS-1] an_ac_pm_thread_stop,
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input [0:`THREADS-1] an_ac_pm_fetch_halt,
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output ac_an_power_managed,
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output ac_an_rvwinkle_mode,
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input an_ac_flh2l2_gate,
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// Clock, Test, and LCB Controls
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input an_ac_gsd_test_enable_dc,
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input an_ac_gsd_test_acmode_dc,
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input an_ac_ccflush_dc,
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input an_ac_ccenable_dc,
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input an_ac_lbist_en_dc,
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input an_ac_lbist_ip_dc,
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input an_ac_lbist_ac_mode_dc,
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input an_ac_scan_diag_dc,
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input an_ac_scan_dis_dc_b,
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//Thold input to clock control macro
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input [0:8] an_ac_scan_type_dc,
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// Pervasive
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output ac_an_reset_1_request,
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output ac_an_reset_2_request,
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output ac_an_reset_3_request,
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output ac_an_reset_wd_request,
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input an_ac_lbist_ary_wrt_thru_dc,
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input [0:`THREADS-1] an_ac_sleep_en,
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input [0:`THREADS-1] an_ac_ext_interrupt,
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input [0:`THREADS-1] an_ac_crit_interrupt,
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input [0:`THREADS-1] an_ac_perf_interrupt,
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input [0:`THREADS-1] an_ac_hang_pulse,
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input an_ac_tb_update_enable,
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input an_ac_tb_update_pulse,
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input [0:3] an_ac_chipid_dc,
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input [0:7] an_ac_coreid,
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output [0:`THREADS-1] ac_an_machine_check,
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input an_ac_debug_stop,
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output [0:`THREADS-1] ac_an_debug_trigger,
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input [0:`THREADS-1] an_ac_uncond_dbg_event,
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output [0:31] ac_an_debug_bus,
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output ac_an_coretrace_first_valid,
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output ac_an_coretrace_valid,
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output [0:1] ac_an_coretrace_type,
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output [0:31] mem_adr,
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input [0:127] mem_dat,
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output mem_wr_val,
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output [0:15] mem_wr_be,
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output [0:127] mem_wr_dat,
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output wb_stb,
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output wb_cyc,
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output [31:0] wb_adr,
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output wb_we,
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output [3:0] wb_sel,
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output [31:0] wb_datw,
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input wb_ack,
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input [31:0] wb_datr
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);
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a2owb c0 (
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.nclk(nclk),
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.scan_in(scan_in),
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.scan_out(scan_out),
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// Pervasive clock control
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.an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
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.an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
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.an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
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.an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
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.an_ac_sg_8(an_ac_sg_8),
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.an_ac_fce_8(an_ac_fce_8),
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.an_ac_abst_scan_in(an_ac_abst_scan_in),
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//SCOM Satellite
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.an_ac_scom_sat_id(an_ac_scom_sat_id),
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.an_ac_scom_dch(an_ac_scom_dch),
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.an_ac_scom_cch(an_ac_scom_cch),
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.ac_an_scom_dch(ac_an_scom_dch),
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.ac_an_scom_cch(ac_an_scom_cch),
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// FIR and Error Signals
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.ac_an_special_attn(ac_an_special_attn),
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.ac_an_checkstop(ac_an_checkstop),
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.ac_an_local_checkstop(ac_an_local_checkstop),
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.ac_an_recov_err(ac_an_recov_err),
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.ac_an_trace_error(ac_an_trace_error),
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.ac_an_livelock_active(ac_an_livelock_active),
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.an_ac_checkstop(an_ac_checkstop),
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.an_ac_external_mchk(an_ac_external_mchk),
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// Perfmon Event Bus
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.ac_an_event_bus0(ac_an_event_bus0),
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.ac_an_event_bus1(ac_an_event_bus1),
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// Reset related
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.an_ac_reset_1_complete(an_ac_reset_1_complete),
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.an_ac_reset_2_complete(an_ac_reset_2_complete),
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.an_ac_reset_3_complete(an_ac_reset_3_complete),
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.an_ac_reset_wd_complete(an_ac_reset_wd_complete),
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// Power Management
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.ac_an_pm_thread_running(ac_an_pm_thread_running),
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.an_ac_pm_thread_stop(an_ac_pm_thread_stop),
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.ac_an_power_managed(ac_an_power_managed),
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.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
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.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
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// Clock, Test, and LCB Controls
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.an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
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.an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
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.an_ac_ccflush_dc(an_ac_ccflush_dc),
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.an_ac_ccenable_dc(an_ac_ccenable_dc),
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.an_ac_lbist_en_dc(an_ac_lbist_en_dc),
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.an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
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.an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
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.an_ac_scan_diag_dc(an_ac_scan_diag_dc),
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.an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
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//Thold input to clock control macro
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.an_ac_scan_type_dc(an_ac_scan_type_dc),
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// Pervasive
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.ac_an_reset_1_request(ac_an_reset_1_request),
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.ac_an_reset_2_request(ac_an_reset_2_request),
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.ac_an_reset_3_request(ac_an_reset_3_request),
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.ac_an_reset_wd_request(ac_an_reset_wd_request),
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.an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
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.an_ac_sleep_en(an_ac_sleep_en),
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.an_ac_ext_interrupt(an_ac_ext_interrupt),
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.an_ac_crit_interrupt(an_ac_crit_interrupt),
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.an_ac_perf_interrupt(an_ac_perf_interrupt),
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.an_ac_hang_pulse(an_ac_hang_pulse),
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.an_ac_tb_update_enable(an_ac_tb_update_enable),
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.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
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.an_ac_chipid_dc(an_ac_chipid_dc),
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.an_ac_coreid(an_ac_coreid),
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.ac_an_machine_check(ac_an_machine_check),
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.an_ac_debug_stop(an_ac_debug_stop),
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.ac_an_debug_trigger(ac_an_debug_trigger),
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.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
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// direct-attach mem
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.mem_adr(mem_adr),
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.mem_dat(mem_dat),
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.mem_wr_val(mem_wr_val),
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.mem_wr_be(mem_wr_be),
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.mem_wr_dat(mem_wr_dat),
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// wishbone
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.wb_stb(wb_stb),
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.wb_cyc(wb_cyc),
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.wb_adr(wb_adr),
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.wb_we(wb_we),
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.wb_ack(wb_ack),
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.wb_sel(wb_sel),
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.wb_datr(wb_datr),
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.wb_datw(wb_datw)
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);
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initial begin
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$dumpfile ("a2onode.vcd");
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// you can do it by levels and also by module so could prune down
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$dumpvars;
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// need to explicitly specify arrays for icarus
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// guess not: $dumpvars cannot dump a vpiMemory
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//$dumpvars(0, c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q);
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#1;
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end
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// see if coco lets me risingedge() these
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wire clk_1x, clk_2x, clk_4x, rst;
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assign clk_1x = nclk[0];
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assign clk_2x = nclk[2];
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assign clk_4x = nclk[3];
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assign rst = nclk[1];
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endmodule
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# Cocotb Sim
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```
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make -f Makefile.node build |& grep -v Anac
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```
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# a2o test tb
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# a2owb with external sim mem interface
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import cocotb
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from cocotb.clock import Clock
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from cocotb.triggers import Timer
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from cocotb.triggers import FallingEdge
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from cocotb.handle import Force
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from cocotb.handle import Release
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import itertools
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from dotmap import DotMap
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from OPEnv import *
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from A2O import *
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from A2L2 import *
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# ------------------------------------------------------------------------------------------------
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# Tasks
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# get rid of z on anything that will be sampled here
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# is there a func to get all inputs?
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async def init(dut, sim):
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"""Initialize inputs. """
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dut.nclk.value = 0
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dut.scan_in.value = 0
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dut.an_ac_scan_type_dc.value = 0x0
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dut.an_ac_chipid_dc.value = 0x0
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dut.an_ac_coreid.value = 0x0
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dut.an_ac_scom_sat_id.value = 0x0
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dut.an_ac_lbist_ary_wrt_thru_dc.value = 0
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dut.an_ac_gsd_test_enable_dc.value = 0
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dut.an_ac_gsd_test_acmode_dc.value = 0
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dut.an_ac_ccflush_dc.value = 0
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dut.an_ac_ccenable_dc.value = 0
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dut.an_ac_lbist_en_dc.value = 0
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dut.an_ac_lbist_ip_dc.value = 0
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dut.an_ac_lbist_ac_mode_dc.value = 0
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dut.an_ac_scan_diag_dc.value = 0
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dut.an_ac_scan_dis_dc_b.value = 0
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dut.an_ac_rtim_sl_thold_8.value = 0
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dut.an_ac_func_sl_thold_8.value = 0
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dut.an_ac_func_nsl_thold_8.value = 0
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dut.an_ac_ary_nsl_thold_8.value = 0
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dut.an_ac_sg_8.value = 0
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dut.an_ac_fce_8.value = 0
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dut.an_ac_abst_scan_in.value = 0
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dut.an_ac_reset_1_complete.value = 0
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dut.an_ac_reset_2_complete.value = 0
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dut.an_ac_reset_3_complete.value = 0
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dut.an_ac_reset_wd_complete.value = 0
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dut.an_ac_pm_fetch_halt.value = 0
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dut.an_ac_debug_stop.value = 0
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dut.an_ac_tb_update_enable.value = 1
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dut.an_ac_tb_update_pulse.value = 0 # tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock)
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# why is coco turning [0] into non-vector??? or is that gpi/vpi/icarus/???
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if sim.threads == 1:
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dut.an_ac_pm_thread_stop.value = 0x1
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dut.an_ac_external_mchk.value = 0
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dut.an_ac_sleep_en.value = 0
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dut.an_ac_ext_interrupt.value = 0
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dut.an_ac_crit_interrupt.value = 0
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dut.an_ac_perf_interrupt.value = 0
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dut.an_ac_hang_pulse.value = 0
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dut.an_ac_uncond_dbg_event.value = 0
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else:
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for i in range(sim.threads):
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dut.an_ac_pm_thread_stop[i].value = 0x1
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dut.an_ac_external_mchk[i].value = 0
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dut.an_ac_sleep_en[i].value = 0
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dut.an_ac_ext_interrupt[i].value = 0
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dut.an_ac_crit_interrupt[i].value = 0
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dut.an_ac_perf_interrupt[i].value = 0
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dut.an_ac_hang_pulse[i].value = 0
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dut.an_ac_uncond_dbg_event[i].value = 0
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await Timer(9, units='ns')
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async def config(dut, sim):
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"""Configure node, etc. """
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await RisingEdge(dut.clk_1x)
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# trilib/tri.vh:`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5xClk
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async def genReset(dut, sim):
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"""Generate reset. """
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first = True
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done = False
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while not done:
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await RisingEdge(dut.clk_1x)
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if sim.cycle < sim.resetCycle:
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if first:
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dut._log.info(f'[{sim.cycle:08d}] Resetting...')
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first = False
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dut.nclk[1].value = 1
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elif not done:
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dut._log.info(f'[{sim.cycle:08d}] Releasing reset.')
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dut.nclk[1].value = 0
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done = True
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sim.resetDone = True
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async def genClocks(dut, sim):
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"""Generate 1x, 2x, 4x clock pulses, depending on parms. """
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if sim.clk2x and sim.clk4x:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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sim.clk4x = Clock(dut.nclk[3], 2, 'ns')
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await cocotb.start(sim.clk4x.start())
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elif sim.clk2x:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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sim.clk2x = Clock(dut.nclk[2], 4, 'ns')
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await cocotb.start(sim.clk2x.start())
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else:
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sim.clk1x = Clock(dut.nclk[0], 8, 'ns')
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await cocotb.start(sim.clk1x.start())
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for cycle in range(sim.maxCycles):
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sim.cycle = cycle
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if cycle % sim.hbCycles == 0:
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dut._log.info(f'[{cycle:08d}] ...tick...')
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await RisingEdge(dut.clk_1x)
|
||||
|
||||
dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.')
|
||||
sim.ok = False
|
||||
sim.fail = 'Max cycle reached.'
|
||||
|
||||
# 16B interface
|
||||
async def memory(dut, sim):
|
||||
"""Handle external memory interface (BE)"""
|
||||
|
||||
me = 'Memory'
|
||||
ok = True
|
||||
sim.msg(f'{me}: started.')
|
||||
|
||||
while ok:
|
||||
await RisingEdge(dut.clk_1x)
|
||||
|
||||
try:
|
||||
addr = dut.mem_adr.value.integer
|
||||
w0 = sim.mem.read(addr)
|
||||
w1 = sim.mem.read(addr+4)
|
||||
w2 = sim.mem.read(addr+8)
|
||||
w3 = sim.mem.read(addr+12)
|
||||
v = cocotb.binary.BinaryValue()
|
||||
v.assign(f'{w0:0>32b}{w1:0>32b}{w2:0>32b}{w3:0>32b}')
|
||||
dut.mem_dat.value = v.value
|
||||
except Exception as e:
|
||||
#print(e)
|
||||
dut.mem_dat.value = 0
|
||||
|
||||
if dut.mem_wr_val.value:
|
||||
addr = dut.mem_adr.value.integer
|
||||
dat = hex(dut.mem_wr_dat, 32)
|
||||
be = f'{dut.mem_wr_be.value.integer:016b}'
|
||||
for i in range(4):
|
||||
sim.mem.write(addr, dat[i*8:i*8+8], be[i*4:i*4+4])
|
||||
addr += 4
|
||||
|
||||
sim.msg(f'{me}: ended.')
|
||||
|
||||
async def checker(dut, sim):
|
||||
"""Watch for error indicators"""
|
||||
|
||||
me = 'Node Checker'
|
||||
ok = True
|
||||
sim.msg(f'{me}: started.')
|
||||
|
||||
# errors
|
||||
nodeCheckstop = dut.an_ac_checkstop
|
||||
errors = [
|
||||
{'name': 'A2Node Checkstop', 'sig': nodeCheckstop}
|
||||
]
|
||||
|
||||
while ok:
|
||||
|
||||
await RisingEdge(dut.clk_1x)
|
||||
|
||||
if not sim.resetDone:
|
||||
continue
|
||||
|
||||
for i in range(len(errors)):
|
||||
assert errors[i]['sig'].value == 0, f'{me} Error: {errors[i]["name"]}'
|
||||
|
||||
|
||||
# ------------------------------------------------------------------------------------------------
|
||||
# Interfaces
|
||||
|
||||
# SCOM
|
||||
async def scom(dut, sim):
|
||||
"""scom interface"""
|
||||
|
||||
dut.an_ac_scom_dch.value = 0
|
||||
dut.an_ac_scom_cch.value = 0
|
||||
|
||||
|
||||
# ------------------------------------------------------------------------------------------------
|
||||
# Do something
|
||||
|
||||
@cocotb.test()
|
||||
async def tb_node(dut):
|
||||
"""A Vulgar Display of OpenPower"""
|
||||
|
||||
sim = Sim(dut)
|
||||
sim.mem = Memory(sim)
|
||||
sim.maxCycles = 20000
|
||||
|
||||
'''
|
||||
# rom
|
||||
sim.memFiles = ['../mem/boot.bin.hex'] #wtf cmdline parm
|
||||
|
||||
for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
|
||||
sim.mem.loadFile(sim.memFiles[i])
|
||||
'''
|
||||
|
||||
'''
|
||||
# rom+test; should end at 700
|
||||
sim.memFiles = [
|
||||
{
|
||||
'addr': 0x00000000,
|
||||
'file' : '../mem/test1/rom.init'
|
||||
},
|
||||
{
|
||||
'addr': 0x10000000,
|
||||
'file' : '../mem/test1/test.init'
|
||||
}
|
||||
]
|
||||
'''
|
||||
'''
|
||||
# rom+bios; should end at 7FC
|
||||
sim.memFiles = [
|
||||
{
|
||||
'addr': 0x00000000,
|
||||
'file' : '../mem/test2/rom.init'
|
||||
}
|
||||
]
|
||||
'''
|
||||
|
||||
# rom+bios+arcitst
|
||||
sim.memFiles = [
|
||||
{
|
||||
'addr': 0x00000000,
|
||||
'file' : '../mem/test3/rom.init'
|
||||
}
|
||||
]
|
||||
|
||||
for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc.
|
||||
sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
|
||||
|
||||
if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
|
||||
sim.mem.write(sim.resetAddr, sim.resetOp)
|
||||
sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')
|
||||
|
||||
# init stuff
|
||||
await init(dut, sim)
|
||||
|
||||
# start clocks,reset
|
||||
await cocotb.start(genClocks(dut, sim))
|
||||
await cocotb.start(genReset(dut, sim))
|
||||
|
||||
# start interfaces
|
||||
await cocotb.start(scom(dut, sim))
|
||||
|
||||
sim.a2o = A2OCore(sim, dut.c0.c0)
|
||||
sim.a2o.traceFacUpdates = True
|
||||
sim.a2o.stopOnLoop = 50
|
||||
sim.a2o.iarPass = 0x7F0
|
||||
sim.a2o.iarFail = 0x7F4
|
||||
|
||||
await cocotb.start(A2O.driver(dut, sim))
|
||||
|
||||
await cocotb.start(memory(dut, sim))
|
||||
#await cocotb.start(A2L2.driver(dut, sim))
|
||||
await cocotb.start(A2L2.checker(dut, sim))
|
||||
await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))
|
||||
|
||||
await Timer((sim.resetCycle + 5)*8, units='ns')
|
||||
if dut.nclk[1].value != 0:
|
||||
sim.ok = False
|
||||
sim.fail = 'Reset active too long!'
|
||||
|
||||
# config stuff
|
||||
# original fpga design needed 4 cred, no fwd (set in logic currently)
|
||||
sim.a2o.config.creditsLd = 1
|
||||
sim.a2o.config.creditsSt = 1
|
||||
sim.a2o.config.creditsLdStSingle = True # need for node right now
|
||||
#sim.a2o.lsDataForward = 0 # disable=1
|
||||
#sim.a2o.cpcr4_sq_cnt = 0 # default=6
|
||||
|
||||
await A2O.config(dut, sim)
|
||||
|
||||
await cocotb.start(A2O.checker(dut, sim))
|
||||
await cocotb.start(A2O.monitor(dut, sim))
|
||||
|
||||
await cocotb.start(checker(dut, sim))
|
||||
|
||||
# release thread(s)
|
||||
dut.an_ac_pm_thread_stop.value = 0
|
||||
await RisingEdge(dut.clk_1x)
|
||||
dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')
|
||||
|
||||
# should await sim.done
|
||||
await Timer((sim.maxCycles+100)*8, units='ns')
|
||||
|
||||
if sim.ok:
|
||||
dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
|
||||
else:
|
||||
dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
|
||||
dut._log.info(f'[{sim.cycle:08d}] {sim.fail}')
|
||||
assert False
|
@ -0,0 +1,683 @@
|
||||
48000400
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
48000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
7CBE6AA6
|
||||
2C250000
|
||||
408200E0
|
||||
3C608C00
|
||||
3800001F
|
||||
38400015
|
||||
38800000
|
||||
3900023F
|
||||
7C7CFBA6
|
||||
7C4011A6
|
||||
7C8009A6
|
||||
7D0001A6
|
||||
4C00012C
|
||||
39400000
|
||||
654A0000
|
||||
614A003F
|
||||
3800001E
|
||||
38800000
|
||||
64840001
|
||||
60840000
|
||||
39000000
|
||||
65080001
|
||||
61080000
|
||||
6108023F
|
||||
7D4011A6
|
||||
7C8009A6
|
||||
7D0001A6
|
||||
4C00012C
|
||||
3C608800
|
||||
3800000F
|
||||
3840003F
|
||||
38800000
|
||||
3900023F
|
||||
7C7CFBA6
|
||||
7C4011A6
|
||||
7C8009A6
|
||||
7D0001A6
|
||||
4C00012C
|
||||
3800000D
|
||||
38800000
|
||||
64840001
|
||||
60840000
|
||||
39000000
|
||||
65080001
|
||||
61080000
|
||||
6108023F
|
||||
7D4011A6
|
||||
7C8009A6
|
||||
7D0001A6
|
||||
4C00012C
|
||||
48000004
|
||||
39400000
|
||||
654A8002
|
||||
614AB000
|
||||
7D400124
|
||||
4C00012C
|
||||
802008F0
|
||||
48000020
|
||||
39400000
|
||||
654A8002
|
||||
614AB000
|
||||
7D400124
|
||||
4C00012C
|
||||
802008F4
|
||||
48000004
|
||||
3C600000
|
||||
60630900
|
||||
7C6903A6
|
||||
7C7E6AA6
|
||||
4E800421
|
||||
480002E4
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
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48000000
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48000000
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00000000
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00000000
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48000000
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0001FFF8
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0000FFF8
|
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60000000
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60000000
|
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9421FFC0
|
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90610038
|
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3D200001
|
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81290000
|
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9121000C
|
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81210038
|
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2C090000
|
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4182000C
|
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3920FFFF
|
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4800017C
|
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3D200000
|
||||
81290AAC
|
||||
91210008
|
||||
48000028
|
||||
8121000C
|
||||
39490004
|
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9141000C
|
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81410008
|
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814A0000
|
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91490000
|
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81210008
|
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39290004
|
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91210008
|
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3D200000
|
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81290AAC
|
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81410008
|
||||
7C0A4840
|
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4180FFCC
|
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3D200001
|
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81290000
|
||||
91210008
|
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48000020
|
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3D200001
|
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81290000
|
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39400000
|
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91490000
|
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81210008
|
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39290004
|
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91210008
|
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3D200001
|
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81290000
|
||||
81410008
|
||||
7C0A4840
|
||||
4180FFD4
|
||||
3D200300
|
||||
91210030
|
||||
81210030
|
||||
3C800000
|
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60840009
|
||||
7C934BA6
|
||||
60000000
|
||||
39200000
|
||||
9121002C
|
||||
8121002C
|
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3C800000
|
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60840009
|
||||
7C9603A6
|
||||
60000000
|
||||
39200000
|
||||
91210028
|
||||
81210028
|
||||
3C800000
|
||||
60840009
|
||||
7C9D43A6
|
||||
60000000
|
||||
39200000
|
||||
91210024
|
||||
81210024
|
||||
3C800000
|
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60840009
|
||||
7C9C43A6
|
||||
60000000
|
||||
3D20FE00
|
||||
91210020
|
||||
81210020
|
||||
3C800000
|
||||
60840009
|
||||
7C9053A6
|
||||
60000000
|
||||
7D36FAA6
|
||||
9121001C
|
||||
8121001C
|
||||
552905AC
|
||||
91210018
|
||||
81210018
|
||||
3C800000
|
||||
60840009
|
||||
7C96FBA6
|
||||
60000000
|
||||
39200000
|
||||
91210014
|
||||
81210014
|
||||
3C800000
|
||||
60840009
|
||||
7C9053A6
|
||||
60000000
|
||||
39200000
|
||||
91210010
|
||||
81210010
|
||||
3C800000
|
||||
60840009
|
||||
7C9453A6
|
||||
60000000
|
||||
39200000
|
||||
7D234B78
|
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38210040
|
||||
4E800020
|
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