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121 lines
4.3 KiB
Verilog
121 lines
4.3 KiB
Verilog
![]()
2 years ago
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// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module fu_alg_bypmux(
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ex3_byp_sel_byp_neg,
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ex3_byp_sel_byp_pos,
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ex3_byp_sel_neg,
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ex3_byp_sel_pos,
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ex3_prd_sel_neg_hi,
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ex3_prd_sel_neg_lo,
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ex3_prd_sel_neg_lohi,
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ex3_prd_sel_pos_hi,
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ex3_prd_sel_pos_lo,
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ex3_prd_sel_pos_lohi,
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ex3_sh_lvl3,
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f_fmt_ex3_pass_frac,
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f_alg_ex3_res
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);
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//--------- BYPASS CONTROLS -----------------
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input ex3_byp_sel_byp_neg;
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input ex3_byp_sel_byp_pos;
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input ex3_byp_sel_neg;
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input ex3_byp_sel_pos;
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input ex3_prd_sel_neg_hi;
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input ex3_prd_sel_neg_lo;
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input ex3_prd_sel_neg_lohi;
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input ex3_prd_sel_pos_hi;
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input ex3_prd_sel_pos_lo;
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input ex3_prd_sel_pos_lohi;
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//--------- BYPASS DATA -----------------
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input [0:162] ex3_sh_lvl3;
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input [0:52] f_fmt_ex3_pass_frac;
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//-------- BYPASS OUTPUT ---------------
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output [0:162] f_alg_ex3_res;
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// ENTITY
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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wire [0:162] m0_b;
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wire [0:162] m1_b;
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wire [0:162] ex3_sh_lvl3_b;
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wire [0:52] f_fmt_ex3_pass_frac_b;
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//#-------------------------------------------------
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//# bypass mux & operand flip
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//#-------------------------------------------------
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//# integer operation positions
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//# 32 32
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//# 99:130 131:162
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assign ex3_sh_lvl3_b[0:162] = (~(ex3_sh_lvl3[0:162]));
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assign f_fmt_ex3_pass_frac_b[0:52] = (~(f_fmt_ex3_pass_frac[0:52]));
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//--------------------------------------------------------------
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assign m0_b[0:52] = (~(({53{ex3_byp_sel_pos}} & ex3_sh_lvl3[0:52]) |
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({53{ex3_byp_sel_neg}} & ex3_sh_lvl3_b[0:52])));
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assign m1_b[0:52] = (~(({53{ex3_byp_sel_byp_pos}} & f_fmt_ex3_pass_frac[0:52]) |
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({53{ex3_byp_sel_byp_neg}} & f_fmt_ex3_pass_frac_b[0:52])));
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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assign m0_b[53:98] = (~({46{ex3_prd_sel_pos_hi}} & ex3_sh_lvl3[53:98]));
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assign m1_b[53:98] = (~({46{ex3_prd_sel_neg_hi}} & ex3_sh_lvl3_b[53:98]));
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//---------------------------------------------------------------
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assign m0_b[99:130] = (~({32{ex3_prd_sel_pos_lohi}} & ex3_sh_lvl3[99:130]));
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assign m1_b[99:130] = (~({32{ex3_prd_sel_neg_lohi}} & ex3_sh_lvl3_b[99:130]));
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//---------------------------------------------------------------
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assign m0_b[131:162] = (~({32{ex3_prd_sel_pos_lo}} & ex3_sh_lvl3[131:162]));
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assign m1_b[131:162] = (~({32{ex3_prd_sel_neg_lo}} & ex3_sh_lvl3_b[131:162]));
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//---------------------------------------------------------------
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assign f_alg_ex3_res[0:162] = (~(m0_b[0:162] & m1_b[0:162]));
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endmodule
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