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223 lines
9.3 KiB
XML
223 lines
9.3 KiB
XML
<!--
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Copyright (c) 2019 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<chapter version="5.0" xml:lang="en" xmlns="http://docbook.org/ns/docbook" xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
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<!-- Chapter Title goes here. -->
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<title>Introduction to Vector Programming on POWER</title>
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<section>
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<title>A Brief History</title>
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<para>
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The history of vector programming on POWER processors begins
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with the AIM (Apple, IBM, Motorola) alliance in the 1990s. The
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AIM partners developed the Power Vector Media Extension (VMX) to
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accelerate multimedia applications, particularly image
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processing. VMX is the name still used by IBM for this
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instruction set. Freescale (formerly Motorola) used the
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trademark "AltiVec," while Apple at one time called it "Velocity
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Engine." While VMX remains the most official name, the term
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AltiVec is still in common use today. Freescale's AltiVec
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Technology Programming Interface Manual (the "AltiVec PIM") is
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still available online for reference (see <xref
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linkend="VIPR.intro.links" />).
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</para>
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<para>
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The original VMX specification provided for thirty-two 128-bit
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vector registers (VRs). Each register can be treated as
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containing sixteen 8-bit character values, eight 16-bit short
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integer values, four 32-bit integer values, or four 32-bit
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single-precision floating-point values (the "VMX data types").
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Furthermore, the integer data types have signed, unsigned, and
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boolean variants. An extensive set of arithmetic, logical,
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comparison, conversion, memory access, and permute class
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operations were specified to operate on these registers.
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</para>
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<para>
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The AltiVec PIM documents intrinsic functions to be used by
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programmers to access the VMX instruction set. Because similar
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operations are provided for all the VMX data types, the PIM
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provides for overloaded intrinsics that can operate on different
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data types. However, such function overloading is not normally
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acceptable in the C programming language, so compilers compliant
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with the AltiVec PIM (such as GCC and Clang) were required to
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add special handling to their parsers to permit this. The PIM
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suggested (but did not mandate) the use of a header file,
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<code><altivec.h></code>, for implementations that provide
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AltiVec intrinsics. This is common practice for all compliant
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compilers today.
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</para>
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<para>
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The first chips incorporating the VMX instruction set were
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introduced by Freescale in 1999, and used primarly in Apple
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desktop computers. IBM's last desktop CPU (the PowerPC 970)
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also included AltiVec support, and was used in the Apple
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PowerMac G5. IBM initially omitted support for VMX from its
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server-class computers, but added support for it in the POWER6
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server family.
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</para>
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<para>
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IBM extended VMX by introducing the Vector-Scalar Extension
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(VSX) for the POWER7 family of processors. VSX adds 64 logical
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Vector Scalar Registers (VSRs); however, to optimize the amount
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of per-process register state, the registers overlap with the
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VRs and the scalar floating-point registers (FPRs) (see <xref
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linkend="VIPR.intro.unified" />). The VSRs can represent all
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the data types representable by the VRs, and can also be treated
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as containing two 64-bit integers or two 64-bit double-precision
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floating-point values.
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</para>
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<para>
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Both the VMX and VSX instruction sets have been expanded for the
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POWER8 and POWER9 processor families. Starting with POWER8,
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a VSR can now contain a single 128-bit integer; and starting
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with POWER9, a VSR can contain a single 128-bit floating-point
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value. The VMX and VSX instruction sets together may be
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referred to as the POWER SIMD (single-instruction,
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multiple-data) instructions.
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</para>
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<section>
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<title>Little-Endian Linux</title>
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<para>
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The POWER architecture has supported operation in either
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big-endian (BE) or little-endian (LE) mode from the
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beginning. However, IBM's POWER servers were only shipped
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with big-endian operating systems (AIX, Linux, i5/OS) prior to
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the introduction of POWER8. With POWER8, IBM began
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supporting little-endian Linux distributions for the first
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time, and introduced a new application binary interface (the
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64-Bit ELFv2 ABI Specification <xref
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linkend="VIPR.intro.links" />) that can be used for either
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big- or little-endian support. In practice, the ELFv2 ABI is
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currently used only for little-endian Linux.
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</para>
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<para>
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Although POWER has always supported big- and little-endian
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memory accesses, the introduction of vector register support
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added a layer of complexity to programming for processors
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operating in different endian modes. Arrays of elements
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loaded into a VR or VSR will be indexed from left to right in
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the register in big-endian mode, but will be indexed from
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right to left in the register in little-endian mode. However,
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the VMX and VSX instructions originally assumed that elements
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will always be indexed from left to right in the register.
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This is an inconvenience that needs to be hidden from the
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application programmer wherever possible. To this end, IBM
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developed a bi-endian vector programming model (see <xref
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linkend="VIPR.biendian" />). The intrinsic functions provided
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for the bi-endian vector programming model are described in
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<xref linkend="VIPR.vec-ref" />.
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</para>
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</section>
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</section>
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<section xml:id="VIPR.intro.unified">
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<title>The Unified Vector Register Set</title>
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<para>
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In OpenPOWER-compliant processors, floating-point and vector
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operations are implemented using a unified vector-scalar model.
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As shown in <xref linkend="FPR-VSR" /> and <xref
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linkend="VR-VSR" />, there are 64 vector-scalar registers; each
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is 128 bits wide.
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</para>
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<para>
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The vector-scalar registers can be addressed with VSX
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instructions, for vector and scalar processing of all 64
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registers, or with the "classic" POWER floating-point
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instructions to refer to a 32-register subset of these, having
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64 bits per register. They can also be addressed with VMX
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instructions to refer to a 32-register subset of 128-bit registers.
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</para>
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<figure pgwide="1" xml:id="FPR-VSR">
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<title>Floating-Point Registers as Part of VSRs</title>
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<mediaobject>
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<imageobject>
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<imagedata fileref="fig-fpr-vsr.png" format="PNG"
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scalefit="1" width="100%" />
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</imageobject>
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</mediaobject>
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</figure>
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<figure pgwide="1" xml:id="VR-VSR">
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<title>Vector Registers as Part of VSRs</title>
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<mediaobject>
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<imageobject>
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<imagedata fileref="fig-vr-vsr.png" format="PNG"
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scalefit="1" width="100%" />
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</imageobject>
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</mediaobject>
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</figure>
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</section>
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<section xml:id="VIPR.intro.links">
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<title>Useful Links</title>
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<para>
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The following documents provide additional reference materials.
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</para>
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<itemizedlist>
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<listitem>
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<para>
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<emphasis>64-Bit ELF V2 ABI Specification - Power
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Architecture.</emphasis>
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<emphasis>
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<link xlink:href="https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture">https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture
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</link>
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</emphasis>
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</para>
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</listitem>
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<listitem>
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<para>
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<emphasis>AltiVec Technology Program Interface
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Manual.</emphasis>
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<emphasis>
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<link xlink:href="https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf">https://www.nxp.com/docs/en/reference-manual/ALTIVECPIM.pdf
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</link>
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</emphasis>
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</para>
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</listitem>
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<listitem>
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<para>
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<emphasis>Intel Architecture Instruction Set Extensions and
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Future Features Programming Reference.</emphasis>
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<emphasis>
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<link xlink:href="https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf">https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
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</link>
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</emphasis>
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</para>
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</listitem>
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<listitem>
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<para>
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<emphasis>Power Vector Library.</emphasis>
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<emphasis>
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<link xlink:href="https://github.com/open-power-sdk/pveclib">https://github.com/open-power-sdk/pveclib
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</link>
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</emphasis>
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</para>
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</listitem>
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<listitem>
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<para>
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<emphasis>Using the GNU Compiler Collection.</emphasis>
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<emphasis>
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<link xlink:href="https://gcc.gnu.org/onlinedocs/gcc.pdf">https://gcc.gnu.org/onlinedocs/gcc.pdf
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</link>
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</emphasis>
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</para>
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</listitem>
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</itemizedlist>
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</section>
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</chapter>
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