Programming-Guides/Intrinsics_Reference/ch_vec_reference.xml

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<chapter version="5.0" xml:lang="en" xmlns="http://docbook.org/ns/docbook" xmlns:xi="http://www.w3.org/2001/XInclude"
xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.vec-ref">
  
  <!-- Chapter Title goes here. -->
  <title>Vector Intrinsic Reference</title>
 
  <section>
    <title>How to Use This Reference</title>
    <para>
      This chapter contains reference material for each supported
      vector intrinsic.  The information for each intrinsic includes:
    </para>
    <itemizedlist>
      <listitem>
	<para>
	  The intrinsic name and extended name;
	</para>
      </listitem>
      <listitem>
	<para>
	  A type-free example of the intrinsic's usage;
	</para>
      </listitem>
      <listitem>
	<para>
	  A description of the intrinsic's purpose;
	</para>
      </listitem>
      <listitem>
	<para>
	  A description of the value(s) returned from the intrinsic,
	  if any;
	</para>
      </listitem>
      <listitem>
	<para>
	  A description of any unusual characteristics of the
	  intrinsic when different target endiannesses are in force.
	  If the semantics of the intrinsic in big-endian and
	  little-endian modes are identical, the description will read
	  "None.";
	</para>
      </listitem>
      <listitem>
	<para>
	  Optionally, additional explanatory notes about the
	  intrinsic; and
	</para>
      </listitem>
      <listitem>
	<para>
	  A table of supported type signatures for the intrinsic.
	</para>
      </listitem>
    </itemizedlist>
    <para>
      Most intrinsics are overloaded, supporting multiple type
      signatures.  The types of the input arguments always determine
      the type of the result argument; that is, it is not possible to
      define two intrinsic overloads with the same input argument
      types and different result argument types.
    </para>
    <para>
      The type-free example of the intrinsic's usage uses the
      convention that <emphasis role="bold">r</emphasis> represents
      the result of the intrinsic, and <emphasis
      role="bold">a</emphasis>, <emphasis role="bold">b</emphasis>,
      etc., represent the input arguments.  The allowed type
      combinations of these variables are shown as rows in the table
      of supported type signatures.
    </para>
    <para>
      Each row contains at least one example implementation.  This
      shows one way that a conforming compiler might achieve the
      intended semantics of the intrinsic, but compilers are not
      required to generate this code specifically.  The letters
      <emphasis role="bold">r</emphasis>, <emphasis
      role="bold">a</emphasis>, <emphasis role="bold">b</emphasis>,
      etc., in the examples represent vector registers containing the
      values of those variables.  The letters <emphasis
      role="bold">t</emphasis>, <emphasis role="bold">u</emphasis>,
      etc., represent vector registers containing temporary
      intermediate results.  The same register is assumed to be used
      for each instance of one of these letters.
    </para>
    <para>
      When implementations differ for big- and little-endian targets,
      separate example implementations are shown for each endianness.
    </para>
    <para>
      The implementations show a sequence of instructions that may be
      used in the implementation of a particular intrinsic, and
      usually include vector instructions.  When trying to
      determine which intrinsic to use, it can be useful to have a
      cross-reference from a specific vector instruction to the
      intrinsics whose implementations make use of it.  This manual
      contains such a cross-reference (<xref
      linkend="section_isa_intrin_xref" />) for the programmer's
      convenience.
    </para>
    <para>
      For some intrinsics, restrictions are shown in the
      implementation table for some of the rows.  Possible
      restrictions include:
    </para>
    <itemizedlist>
      <listitem>
	<para>
	  <emphasis role="bold">ISA 3.0 or later</emphasis>.  This
	  form is only available starting with PowerISA 3.0,
	  corresponding to POWER9 servers.  The Power Vector Library
	  (see <xref linkend="VIPR.intro.links" /> provides equivalent
	  POWER7/POWER8 implementations for many ISA 3.0 vector
	  instructions, which may be preferred for portability.
	</para>
      </listitem>
      <listitem>
	<para>
	  <emphasis role="bold">Deprecated</emphasis>.  This form of
	  the intrinsic is currently available, but may be removed in
	  the future.  Programmers are discouraged from using it.
	</para>
      </listitem>
    </itemizedlist>
    <section>
      <title>Terminology</title>
      <para>
	Some intrinsic descriptions indicate that either
	<emphasis>modular</emphasis> arithmetic or
	<emphasis>saturating</emphasis> arithmetic is used.  This
	refers to what happens when an operation overflows the number
	of available bits.  A modular operation that overflows
	truncates the result on the left, also known as wrapping the
	result.  A saturating operation that overflows produces the
	largest (or smallest) possible result representable in the
	output element type.
      </para>
      <para>
	Operands are sometimes represented as having a <code>const
	int</code> type.  In such cases, the programmer is expected to
	provide an integer literal.  When the literal has specific
	required bounds, this is often represented instead by such
	phrases as "5-bit signed literal" or "2-bit unsigned literal"
	to specify them.  In such cases, compilers are encouraged to
	at least warn upon detecting an out-of-range value.  Providing
	a variable when a literal is required is a compile-time error.
      </para>
    </section>
  </section>

  <?hard-pagebreak?>
  <section xml:id="VIPR.reference.vecfns">
    <title>Built-In Vector Functions</title>

    <simplesect xml:id="vec_abs">
      <title>vec_abs</title>
      <subtitle>Vector Absolute Value</subtitle>
      <programlisting>
      r = vec_abs (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector <emphasis role="bold">r</emphasis> that contains the
      absolute values of the contents of the vector
      <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      absolute value of the corresponding element of
      <emphasis role="bold">a</emphasis>.  For integer vectors, the arithmetic
      is modular.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_abs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsububm</primary>
	<secondary>vec_abs</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsb</primary>
	<secondary>vec_abs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuwm</primary>
	<secondary>vec_abs</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsw</primary>
	<secondary>vec_abs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubudm</primary>
	<secondary>vec_abs</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsd</primary>
	<secondary>vec_abs</secondary>
      </indexterm>
      <indexterm>
	<primary>xvabssp</primary>
	<secondary>vec_abs</secondary>
      </indexterm>
      <indexterm>
	<primary>xvabsdp</primary>
	<secondary>vec_abs</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_abs</title>
	<tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,0
   vsububm  t,t,a
   vmaxsb   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,0
   vsubuhm  t,t,a
   vmaxsh   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,0
   vsubuwm  t,t,a
   vmaxsw   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,0
   vsubudm  t,t,a
   vmaxsd   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvabssp  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvabsdp  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_absd">
      <title>vec_absd</title>
      <subtitle>Vector Absolute Difference</subtitle>
      <programlisting>
      r = vec_absd (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Computes the absolute difference of two vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      absolute difference of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>, using
      modular arithmetic.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vabsdub</primary>
	<secondary>vec_absd</secondary>
      </indexterm>
      <indexterm>
	<primary>vabsduh</primary>
	<secondary>vec_absd</secondary>
      </indexterm>
      <indexterm>
	<primary>vabsduw</primary>
	<secondary>vec_absd</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_absd</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vabsdub r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vabsduh r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vabsduw r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_abss">
      <title>vec_abss</title>
      <subtitle>Vector Absolute Value Saturated</subtitle>
      <programlisting>
      r = vec_abss (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector <emphasis role="bold">r</emphasis> that contains the
      saturated absolute values of the contents of the vector
      <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      saturated absolute value of the corresponding element of
      <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisb</primary>
	<secondary>vec_abss</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubsbs</primary>
	<secondary>vec_abss</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsb</primary>
	<secondary>vec_abss</secondary>
      </indexterm>
      <indexterm>
	<primary>vspltish</primary>
	<secondary>vec_abss</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubshs</primary>
	<secondary>vec_abss</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsh</primary>
	<secondary>vec_abss</secondary>
      </indexterm>
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_abss</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubsws</primary>
	<secondary>vec_abss</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsw</primary>
	<secondary>vec_abss</secondary>
      </indexterm>


      <table frame="all">
	<title>Supported type signatures for vec_abss</title>
	<tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vspltisb t,0
   vsubsbs  t,t,a
   vmaxsb   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vspltish t,0
   vsubshs  t,t,a
   vmaxsh   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,0
   vsubsws  t,t,a
   vmaxsw   r,t,a
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_add">
      <title>vec_add</title>
      <subtitle>Vector Addition</subtitle>
      <programlisting>
      r = vec_add (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Computes the sum of two vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      sum of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.  Modular
      arithmetic is used for both signed and unsigned integers.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vaddubm</primary>
	<secondary>vec_add</secondary>
      </indexterm>
      <indexterm>
	<primary>vadduhm</primary>
	<secondary>vec_add</secondary>
      </indexterm>
      <indexterm>
	<primary>vadduwm</primary>
	<secondary>vec_add</secondary>
      </indexterm>
      <indexterm>
	<primary>vaddudm</primary>
	<secondary>vec_add</secondary>
      </indexterm>
      <indexterm>
	<primary>vadduqm</primary>
	<secondary>vec_add</secondary>
      </indexterm>
      <indexterm>
	<primary>xvaddsp</primary>
	<secondary>vec_add</secondary>
      </indexterm>
      <indexterm>
	<primary>xvadddp</primary>
	<secondary>vec_add</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_add</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vaddubm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vaddubm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vadduhm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vadduhm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vadduwm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vadduwm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vaddudm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   vaddudm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry>
		<programlisting>
   vadduqm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry>
		<programlisting>
   vadduqm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvaddsp r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvadddp r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_addc">
      <title>vec_addc</title>
      <subtitle>Vector Add Carrying</subtitle>
      <programlisting>
      r = vec_addc (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector of carries produced by adding two vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      carry produced by adding the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> (1
      if there is a carry, 0 otherwise).
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vaddcuw</primary>
	<secondary>vec_addc</secondary>
      </indexterm>
      <indexterm>
	<primary>vaddcuq</primary>
	<secondary>vec_addc</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_addc</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vaddcuw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vaddcuw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry>
		<programlisting>
   vaddcuq r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry>
		<programlisting>
   vaddcuq r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_adde">
      <title>vec_adde</title>
      <subtitle>Vector Add Extended</subtitle>
      <programlisting>
      r = vec_adde (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector formed as the sum of two vectors and a carry vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is
      produced by adding the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> with
      a carry specified in the corresponding element of <emphasis
      role="bold">c</emphasis> (1 if there is a carry, 0 otherwise).
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
      Code generated for this intrinsic should ensure only the
      low-order bit of <emphasis role="bold">c</emphasis> participates
      in the sum.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_adde</secondary>
      </indexterm>
      <indexterm>
	<primary>vadduwm</primary>
	<secondary>vec_adde</secondary>
      </indexterm>
      <indexterm>
	<primary>xxland</primary>
	<secondary>vec_adde</secondary>
      </indexterm>
      <indexterm>
	<primary>vaddeuqm</primary>
	<secondary>vec_adde</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_adde</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">c</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,1
   vadduwm  r,a,b
   xxland   c,c,t
   vadduwm  r,r,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,1
   vadduwm  r,a,b
   xxland   c,c,t
   vadduwm  r,r,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry>
		<programlisting>
   vaddeuqm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry>
		<programlisting>
   vaddeuqm r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_addec">
      <title>vec_addec</title>
      <subtitle>Vector Add Extended Carrying</subtitle>
      <programlisting>
      r = vec_addec (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector of carries produced by adding two vectors and
      a carry vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is
      the carry produced by adding the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> and
      a carry specified in the corresponding element of <emphasis
      role="bold">c</emphasis> (1 if there is a carry, 0 otherwise).
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
      Code generated for this intrinsic should ensure only the
      low-order bit of <emphasis role="bold">c</emphasis> participates
      in the sum.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_addec</secondary>
      </indexterm>
      <indexterm>
	<primary>xxland</primary>
	<secondary>vec_addec</secondary>
      </indexterm>
      <indexterm>
	<primary>vadduwm</primary>
	<secondary>vec_addec</secondary>
      </indexterm>
      <indexterm>
	<primary>vaddcuw</primary>
	<secondary>vec_addec</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlor</primary>
	<secondary>vec_addec</secondary>
      </indexterm>
      <indexterm>
	<primary>vaddecuq</primary>
	<secondary>vec_addec</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_addec</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">c</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,1
   xxland   u,c,t
   vadduwm  v,a,b
   vaddcuw  w,a,b
   vaddcuw  x,v,u
   xxlor    r,w,x
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vspltisw t,1
   xxland   u,c,t
   vadduwm  v,a,b
   vaddcuw  w,a,b
   vaddcuw  x,v,u
   xxlor    r,w,x
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed __int128</para>
              </entry>
              <entry>
		<programlisting>
   vaddecuq r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry>
		<programlisting>
   vaddecuq r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_adds">
      <title>vec_adds</title>
      <subtitle>Vector Add Saturating</subtitle>
      <programlisting>
      r = vec_adds (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Computes the saturated sum of two vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      saturated sum of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vaddsbs</primary>
	<secondary>vec_adds</secondary>
      </indexterm>
      <indexterm>
	<primary>vaddubs</primary>
	<secondary>vec_adds</secondary>
      </indexterm>
      <indexterm>
	<primary>vaddshs</primary>
	<secondary>vec_adds</secondary>
      </indexterm>
      <indexterm>
	<primary>vadduhs</primary>
	<secondary>vec_adds</secondary>
      </indexterm>
      <indexterm>
	<primary>vaddsws</primary>
	<secondary>vec_adds</secondary>
      </indexterm>
      <indexterm>
	<primary>vadduws</primary>
	<secondary>vec_adds</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_adds</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vaddsbs r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vaddubs r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vaddshs r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vadduhs r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vaddsws r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vadduws r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_eq">
      <title>vec_all_eq</title>
      <subtitle>Vector All Equal</subtitle>
      <programlisting>
      r = vec_all_eq (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis>
      are equal to the corresponding elements of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if each
      element of <emphasis role="bold">a</emphasis> is equal to the
      corresponding element of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpequb.</primary>
	<secondary>vec_all_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequw.</primary>
	<secondary>vec_all_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequd.</primary>
	<secondary>vec_all_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequh.</primary>
	<secondary>vec_all_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_all_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_all_eq</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_eq</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequb.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequb.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequb.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequh.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequh.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequh.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector pixel</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequh.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequw.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequw.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequw.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqsp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqdp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_ge">
      <title>vec_all_ge</title>
      <subtitle>Vector All Greater or Equal</subtitle>
      <programlisting>
      r = vec_all_ge (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis> are
      greater than or equal to the corresponding elements of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are greater
      than or equal to the corresponding elements of <emphasis
      role="bold">b</emphasis>.  Otherwise, <emphasis
      role="bold">r</emphasis> is 0.</para> 
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgedp.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp.</primary>
	<secondary>vec_all_ge</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_ge</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsb.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtub.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsh.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuh.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsw.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuw.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsd.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtud.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgesp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgedp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_gt">
      <title>vec_all_gt</title>
      <subtitle>Vector All Greater Than</subtitle>
      <programlisting>
      r = vec_all_gt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis> are
      greater than the corresponding elements of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value: r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are greater
      than the corresponding elements of <emphasis
      role="bold">b</emphasis>.  Otherwise, <emphasis
      role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtdp.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp.</primary>
	<secondary>vec_all_gt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_gt</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsb.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtub.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsh.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuh.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsw.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuw.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsd.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtud.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtsp. t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp. t,a,b
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_in">
      <title>vec_all_in</title>
      <subtitle>Vector All In Range</subtitle>
      <programlisting>
      r = vec_all_in (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of a vector are within a given range.
      </para>
      <para><emphasis role="bold">Result value:  r </emphasis> is 1 if each
      element of <emphasis role="bold">a</emphasis> has a value less than or
      equal to the value of the corresponding element of <emphasis
      role="bold">b</emphasis>, and greater than or equal to the negative of
      the value of the corresponding element of <emphasis
      role="bold">b</emphasis>. Otherwise, <emphasis role="bold">r</emphasis>
      is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpbfp.</primary>
	<secondary>vec_all_in</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_in</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_in</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_in</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  vcmpbfp.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,27,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_le">
      <title>vec_all_le</title>
      <subtitle>Vector All Less or Equal</subtitle>
      <programlisting>
      r = vec_all_le (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis> are
      less than or equal to the corresponding elements of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if all
      elements of <emphasis role="bold">a</emphasis> are less than or equal to
      the corresponding elements of <emphasis role="bold">b</emphasis>.
      Otherwise, <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgedp.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp.</primary>
	<secondary>vec_all_le</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_le</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsb.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtub.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsh.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuh.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsw.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuw.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsd.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtud.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgesp.  t,b,a
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
	    </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgedp.  t,b,a
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_lt">
      <title>vec_all_lt</title>
      <subtitle>Vector All Less Than</subtitle>
      <programlisting>
      r = vec_all_lt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis> are
      less than the corresponding elements of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if all
      elements of <emphasis role="bold">a</emphasis> are less than the
      corresponding elements of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtdp.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp.</primary>
	<secondary>vec_all_lt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_lt</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsb.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtub.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsh.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuh.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsw.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuw.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsd.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtud.  t,b,a
  mfocrf     u,2
  rlwinm     r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtsp.  t,b,a
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp.  t,b,a
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_nan">
      <title>vec_all_nan</title>
      <subtitle>Vector All Not-a-Number</subtitle>
      <programlisting>
      r = vec_all_nan (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis>
      are not-a-number (NaN).
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are
      NaN.  Otherwise, <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_all_nan</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_nan</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_nan</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_all_nan</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_nan</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqsp.  t,a,a
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqdp.  t,a,a
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_ne">
      <title>vec_all_ne</title>
      <subtitle>Vector All Not Equal</subtitle>
      <programlisting>
      r = vec_all_ne (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis>
      are not equal to the corresponding elements of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are not equal
      to the corresponding elements of <emphasis
      role="bold">b</emphasis>.  Otherwise, <emphasis
      role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpneb.</primary>
	<secondary>vec_all_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnew.</primary>
	<secondary>vec_all_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequd.</primary>
	<secondary>vec_all_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpneh.</primary>
	<secondary>vec_all_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_all_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_all_ne</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_ne</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneb.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneb.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneb.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
	    </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneh.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneh.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneh.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector pixel</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneh.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnew.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnew.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnew.  t,a,b
  mfocrf    u,2
  rlwinm    r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqsp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqdp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_nge">
      <title>vec_all_nge</title>
      <subtitle>Vector All Not Greater or Equal</subtitle>
      <programlisting>
      r = vec_all_nge (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis>
      are not greater than or equal to the corresponding elements of
      <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are not
      greater than or equal to the corresponding elements of <emphasis
      role="bold">b</emphasis>. Otherwise, <emphasis
      role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_all_nge</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_nge</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_nge</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_all_nge</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_nge</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgesp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgedp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_ngt">
      <title>vec_all_ngt</title>
      <subtitle>Vector All Not Greater Than</subtitle>
      <programlisting>
      r = vec_all_ngt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis>
      are not greater than the corresponding elements of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are not
      greater than the corresponding elements of <emphasis
      role="bold">b</emphasis>.  Otherwise, <emphasis
      role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpgtdp.</primary>
	<secondary>vec_all_ngt</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_ngt</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_ngt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp.</primary>
	<secondary>vec_all_ngt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_ngt</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtsp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_nle">
      <title>vec_all_nle</title>
      <subtitle>Vector All Not Less or Equal</subtitle>
      <programlisting>
      r = vec_all_nle (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis>
      are not less than or equal to the corresponding elements of
      <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are not less
      than or equal to the corresponding elements of <emphasis
      role="bold">b</emphasis>.  Otherwise, <emphasis
      role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpgedp.</primary>
	<secondary>vec_all_nle</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_nle</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_nle</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp.</primary>
	<secondary>vec_all_nle</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_nle</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgesp.  t,b,a
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgedp.  t,b,a
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_nlt">
      <title>vec_all_nlt</title>
      <subtitle>Vector All Not Less Than</subtitle>
      <programlisting>
      r = vec_all_nlt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of <emphasis role="bold">a</emphasis>
      are not less than the corresponding elements of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are not less
      than the corresponding elements of <emphasis
      role="bold">b</emphasis>.  Otherwise, <emphasis
      role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpgtdp.</primary>
	<secondary>vec_all_nlt</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_nlt</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_nlt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp.</primary>
	<secondary>vec_all_nlt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_nlt</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtsp.  t,b,a
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp.  t,b,a
  mfocrf      u,2
  rlwinm      r,u,27,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_all_numeric">
      <title>vec_all_numeric</title>
      <subtitle>Vector All Numeric</subtitle>
      <programlisting>
      r = vec_all_numeric (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether all elements of the vector are numeric (not NaN).
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if
      all elements of <emphasis role="bold">a</emphasis> are numeric
      (not NaN).  Otherwise, <emphasis role="bold">r</emphasis> is
      0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_all_numeric</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_all_numeric</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_all_numeric</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_all_numeric</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_all_numeric</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqsp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqdp.  t,a,b
  mfocrf      u,2
  rlwinm      r,u,25,1
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_and">
      <title>vec_and</title>
      <subtitle>Vector AND</subtitle>
      <programlisting>
      r = vec_and (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bitwise AND of two vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of <emphasis role="bold">r</emphasis> is the bitwise AND
      of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxland</primary>
	<secondary>vec_and</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_and</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xxland r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_andc">
      <title>vec_andc</title>
      <subtitle>Vector AND with Complement</subtitle>
      <programlisting>
      r = vec_andc (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bitwise AND of one vector with the bitwise complement of
      another vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of <emphasis role="bold">r</emphasis> is the bitwise AND
      of <emphasis role="bold">a</emphasis> with the bitwise complement
      of <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxlandc</primary>
	<secondary>vec_andc</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_andc</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xxlandc r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_eq">
      <title>vec_any_eq</title>
      <subtitle>Vector Any Equal</subtitle>
      <programlisting>
      r = vec_any_eq (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis>
      is equal to the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is equal to the
      corresponding element of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpneb.</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnew.</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequd.</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpneh.</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_any_eq</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_eq</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneb.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneb.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneb.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneh.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneh.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneh.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector pixel</para>
              </entry>
              <entry>
                <programlisting>
  vcmpneh.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnew.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnew.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnew.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,25,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqsp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqdp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_ge">
      <title>vec_any_ge</title>
      <subtitle>Vector Any Greater or Equal</subtitle>
      <programlisting>
      r = vec_any_ge (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis> is
      greater than or equal to the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is greater than or equal
      to the corresponding element of <emphasis role="bold">b</emphasis>.
      Otherwise, <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgedp.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp.</primary>
	<secondary>vec_any_ge</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_ge</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsb.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtub.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsw.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuw.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsd.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtud.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsh.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuh.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgedp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgesp.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_gt">
      <title>vec_any_gt</title>
      <subtitle>Vector Any Greater Than</subtitle>
      <programlisting>
      r = vec_any_gt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis> is
      greater than the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is greater than the
      corresponding element of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtdp.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp.</primary>
	<secondary>vec_any_gt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_gt</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsb.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtub.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsh.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuh.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsw.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuw.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsd.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtud.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtsp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_le">
      <title>vec_any_le</title>
      <subtitle>Vector Any Less or Equal</subtitle>
      <programlisting>
      r = vec_any_le (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis> is less
      than or equal to the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is less than or equal to
      the corresponding element of <emphasis role="bold">b</emphasis>.
      Otherwise, <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgedp.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp.</primary>
	<secondary>vec_any_le</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_le</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsb.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtub.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsh.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuh.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsw.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuw.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsd.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtud.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgesp.  t,b,a
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgedp.  t,b,a
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_lt">
      <title>vec_any_lt</title>
      <subtitle>Vector Any Less Than</subtitle>
      <programlisting>
      r = vec_any_lt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis> is less
      than the corresponding element of <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is less than the
      corresponding element of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtdp.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp.</primary>
	<secondary>vec_any_lt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_lt</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsb.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtub.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsh.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuh.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsw.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtuw.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtsd.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpgtud.  t,b,a
  mfocrf     u,2
  rlwinm     v,u,27,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtsp.  t,b,a
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp.  t,b,a
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_nan">
      <title>vec_any_nan</title>
      <subtitle>Vector Any Not-a-Number</subtitle>
      <programlisting>
      r = vec_any_nan (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of the source vector is a NaN.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is a NaN. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_any_nan</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_nan</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_nan</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_nan</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_nan</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_any_nan</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_nan</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqsp.  t,a,a
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqdp.  t,a,a
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_ne">
      <title>vec_any_ne</title>
      <subtitle>Vector Any Not Equal</subtitle>
      <programlisting>
      r = vec_any_ne (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis>
      is not equal to the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is not equal to the
      corresponding element of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpequb.</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequw.</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequd.</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequh.</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_any_ne</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_ne</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequb.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequb.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequb.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequh.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequh.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequh.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector pixel</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequh.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequw.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequw.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequw.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vcmpequd.  t,a,b
  mfocrf     u,2
  rlwinm     v,u,25,1
  cntlzw     w,v
  srwi       r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqsp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqdp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_nge">
      <title>vec_any_nge</title>
      <subtitle>Vector Any Not Greater or Equal</subtitle>
      <programlisting>
      r = vec_any_nge (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis> is not
      greater than or equal to the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is not greater than or
      equal to the corresponding element of <emphasis
      role="bold">b</emphasis>. Otherwise, <emphasis role="bold">r</emphasis>
      is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpgedp.</primary>
	<secondary>vec_any_nge</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_nge</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_nge</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_nge</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_nge</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp.</primary>
	<secondary>vec_any_nge</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_nge</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgesp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgedp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_ngt">
      <title>vec_any_ngt</title>
      <subtitle>Vector Any Not Greater Than</subtitle>
      <programlisting>
      r = vec_any_ngt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis> is not
      greater than the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is not greater than the
      corresponding element of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpgtdp.</primary>
	<secondary>vec_any_ngt</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_ngt</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_ngt</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_ngt</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_ngt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp.</primary>
	<secondary>vec_any_ngt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_ngt</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtsp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp.  t,a,b
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_nle">
      <title>vec_any_nle</title>
      <subtitle>Vector Any Not Less or Equal</subtitle>
      <programlisting>
      r = vec_any_nle (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis> is not
      less than or equal to the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is not less than or equal
      to the corresponding element of <emphasis role="bold">b</emphasis>.
      Otherwise, <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpgedp.</primary>
	<secondary>vec_any_nle</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_nle</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_nle</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_nle</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_nle</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp.</primary>
	<secondary>vec_any_nle</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_nle</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgesp.  t,b,a
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgedp.  t,b,a
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_nlt">
      <title>vec_any_nlt</title>
      <subtitle>Vector Any Not Less Than</subtitle>
      <programlisting>
      r = vec_any_nlt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of <emphasis role="bold">a</emphasis> is not
      less than the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is not less than the
      corresponding element of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpgtdp.</primary>
	<secondary>vec_any_nlt</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_nlt</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_nlt</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_nlt</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_nlt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp.</primary>
	<secondary>vec_any_nlt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_nlt</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp.  t,b,a
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpgtdp.  t,b,a
  mfocrf      u,2
  rlwinm      v,u,25,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_numeric">
      <title>vec_any_numeric</title>
      <subtitle>Vector Any Numeric</subtitle>
      <programlisting>
      r = vec_any_numeric (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether any element of the source vector is numeric (not a NaN).
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if any
      element of <emphasis role="bold">a</emphasis> is numeric (not a NaN).
      Otherwise, <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcmpeqdp.</primary>
	<secondary>vec_any_numeric</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_numeric</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_numeric</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_numeric</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_numeric</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp.</primary>
	<secondary>vec_any_numeric</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_numeric</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqsp.  t,a,a
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcmpeqdp.  t,a,a
  mfocrf      u,2
  rlwinm      v,u,27,1
  cntlzw      w,v
  srwi        r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_any_out">
      <title>vec_any_out</title>
      <subtitle>Vector Any Out of Range</subtitle>
      <programlisting>
      r = vec_any_out (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Tests whether the value of any element of a vector is outside of a
      given range.
      </para>
      <para><emphasis role="bold">Result value:  r</emphasis> is 1 if the
      value of any element of <emphasis role="bold">a</emphasis> is greater
      than the value of the corresponding element of <emphasis
      role="bold">b</emphasis> or less than the negative of the value of the
      corresponding element of <emphasis role="bold">b</emphasis>. Otherwise,
      <emphasis role="bold">r</emphasis> is 0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpbfp.</primary>
	<secondary>vec_any_out</secondary>
      </indexterm>
      <indexterm>
	<primary>mfocrf</primary>
	<secondary>vec_any_out</secondary>
      </indexterm>
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_any_out</secondary>
      </indexterm>
      <indexterm>
	<primary>cntlzw</primary>
	<secondary>vec_any_out</secondary>
      </indexterm>
      <indexterm>
	<primary>srwi</primary>
	<secondary>vec_any_out</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_any_out</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  vcmpbfp.  t,a,b
  mfocrf    u,2
  rlwinm    v,u,27,1
  cntlzw    w,v
  srwi      r,w,5
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_avg">
      <title>vec_avg</title>
      <subtitle>Vector Average</subtitle>
      <programlisting>
      r = vec_avg (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the elementwise average of two vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      average of the value of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vavgsb</primary>
	<secondary>vec_avg</secondary>
      </indexterm>
      <indexterm>
	<primary>vavgub</primary>
	<secondary>vec_avg</secondary>
      </indexterm>
      <indexterm>
	<primary>vavgsh</primary>
	<secondary>vec_avg</secondary>
      </indexterm>
      <indexterm>
	<primary>vavguh</primary>
	<secondary>vec_avg</secondary>
      </indexterm>
      <indexterm>
	<primary>vavgsw</primary>
	<secondary>vec_avg</secondary>
      </indexterm>
      <indexterm>
	<primary>vavguw</primary>
	<secondary>vec_avg</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_avg</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vavgsb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vavgub r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vavgsh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vavguh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vavgsw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vavguw r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_bperm">
      <title>vec_bperm</title>
      <subtitle>Vector Bit Permute</subtitle>
      <programlisting>
      r = vec_bperm (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Gathers up to 16 one-bit values from a quadword or from each
      doubleword element in the specified order, zeroing other bits.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      When the type of <emphasis role="bold">a</emphasis> is vector
      unsigned char or vector unsigned __int128:
      <itemizedlist spacing="compact">
	<listitem>
	  <para>
	    For each <emphasis>i</emphasis>
	    <inlineequation>
	      <mathphrase>
		(0 &#x2264; <emphasis>i</emphasis> &lt; 16),
	      </mathphrase>
            </inlineequation>
	    let bit index <emphasis>j</emphasis> denote the byte value of the
	    <emphasis>i</emphasis><superscript>th</superscript>
	    element of <emphasis role="bold">b</emphasis>.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    If bit index <emphasis>j</emphasis> is greater than or equal to
	    128, bit <emphasis>i</emphasis> of
	    <emphasis role="bold">r</emphasis> is set to 0.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    If bit index <emphasis>j</emphasis> is smaller than 128, bit
	    <emphasis>i</emphasis> of <emphasis role="bold">r</emphasis>
	    is set to the value of the
	    <emphasis>j</emphasis><superscript>th</superscript> bit of
	    <emphasis role="bold">a</emphasis>.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    All other bits of <emphasis role="bold">r</emphasis> are zeroed.
	  </para>
	</listitem>
      </itemizedlist>
      </para>
      <para>
	When the type of <emphasis role="bold">a</emphasis> is vector
	unsigned long long:
	<itemizedlist spacing="compact">
	  <listitem>
	    <para>
	      For each doubleword element <emphasis>i</emphasis>
	      <inlineequation>
		<mathphrase>
		  (0 &#x2264; <emphasis>i</emphasis> &lt; 2)
		</mathphrase>
	      </inlineequation>
	      of <emphasis role="bold">a</emphasis>:
	      <itemizedlist spacing="compact">
		<listitem>
		  <para>
		    For each <emphasis>j</emphasis>
		    <inlineequation>
		      <mathphrase>
			(0 &#x2264; <emphasis>j</emphasis> &lt; 8),
		      </mathphrase>
		    </inlineequation>
		    let bit index <emphasis>k</emphasis> denote the byte
		    value of the
		    <emphasis>j</emphasis><superscript>th</superscript>
		    element of <emphasis role="bold">b</emphasis>.
		  </para>
		</listitem>
		<listitem>
		  <para>
		    If bit index <emphasis>k</emphasis> is greater than or
		    equal to 64, bit <emphasis>j</emphasis> of element
		    <emphasis>i</emphasis> of <emphasis
		    role="bold">r</emphasis> is set to 0.
		  </para>
		</listitem>
		<listitem>
		  <para>
		    If bit index <emphasis>k</emphasis> is less than 64,
		    bit <emphasis>j</emphasis> of element
		    <emphasis>i</emphasis> of <emphasis
		    role="bold">r</emphasis> is set to the value of the
		    <emphasis>k</emphasis><superscript>th</superscript>
		    bit of element <emphasis>i</emphasis> of input
		    <emphasis role="bold">a</emphasis>.
		  </para>
		</listitem>
		<listitem>
		  <para>
		    All other bits are zeroed.
		  </para>
		</listitem>
	      </itemizedlist>
	    </para>
	  </listitem>
	</itemizedlist>
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      All bit and byte numberings within each element in the above
      description denote big-endian (i.e., left-to-right) order,
      reflecting the underlying hardware instruction.  Unlike most
      of the vector intrinsics in this chapter, <code>vec_bperm</code>
      does not follow the bi-endian programming model.
      </para>
      
      <indexterm>
	<primary>vbpermq</primary>
	<secondary>vec_bperm</secondary>
      </indexterm>
      <indexterm>
	<primary>vbpermd</primary>
	<secondary>vec_bperm</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_bperm</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vbpermq r,a,b
		</programlisting>
              </entry>
	      <entry>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vbpermq r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vbpermd r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
		<para></para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_ceil">
      <title>vec_ceil</title>
      <subtitle>Vector Ceiling</subtitle>
      <programlisting>
      r = vec_ceil (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector <emphasis role="bold">r</emphasis> that contains the
      result of applying the floating-point ceiling function to each
      element of <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      smallest representable floating-point integral value greater than or
      equal to the value of the corresponding element of
      <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvrspip</primary>
	<secondary>vec_ceil</secondary>
      </indexterm>
      <indexterm>
	<primary>xvrdpip</primary>
	<secondary>vec_ceil</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_ceil</title>
	<tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvrspip  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvrdpip  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cipher_be">
      <title>vec_cipher_be</title>
      <subtitle>Vector AES Cipher Big-Endian</subtitle>
      <programlisting>
      r = vec_cipher_be (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs one round of the AES cipher operation on an intermediate state
      array <emphasis role="bold">a</emphasis> by using a given round key
      <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Result value: r</emphasis> contains the
      resulting intermediate state, after one round of the AES cipher
      operation on intermediate state array <emphasis role="bold">a</emphasis>,
      using the round key specified by <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Endian considerations:</emphasis>
      All element and bit numberings of the AES cipher operation use
      big-endian (i.e., left-to-right) order, reflecting the underlying
      hardware insruction.  Unlike most of the vector intrinsics in this
      chapter, <code>vec_cipher_be</code> does not follow the bi-endian
      programming model.
      </para>

      <indexterm>
	<primary>vcipher</primary>
	<secondary>vec_cipher_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_cipher_be</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcipher  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_cipherlast_be">
      <title>vec_cipherlast_be</title>
      <subtitle>Vector AES Cipher Last Big-Endian</subtitle>
      <programlisting>
      r = vec_cipherlast_be (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs the final round of the AES cipher operation on an intermediate
      state array <emphasis role="bold">a</emphasis> using the specified
      round key <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Result value: r</emphasis> contains the
      resulting final state, after the final round of the AES cipher
      operation on intermediate state array <emphasis role="bold">a</emphasis>,
      using the round key specified by <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Endian considerations:</emphasis>
      All element and bit numberings of the AES cipher-last operation use
      big-endian (i.e., left-to-right) order, reflecting the underlying
      hardware insruction.  Unlike most of the vector intrinsics in this
      chapter, <code>vec_cipherlast_be</code> does not follow the bi-endian
      programming model.
      </para>

      <indexterm>
	<primary>vcipherlast</primary>
	<secondary>vec_cipherlast_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_cipherlast_be</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcipherlast  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_cmpb">
      <title>vec_cmpb</title>
      <subtitle>Vector Compare Bytes</subtitle>
      <programlisting>
      r = vec_cmpb (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bounds comparison of each set of corresponding elements
      of two vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      Each element of <emphasis role="bold">r</emphasis> has the value 0
      if the value of the corresponding element of <emphasis
      role="bold">a</emphasis> is less than or equal to the value of
      the corresponding element of <emphasis role="bold">b</emphasis>
      and greater than or equal to the negated value of the corresponding
      element of <emphasis role="bold">b</emphasis>.  Otherwise:
      <itemizedlist spacing="compact">
	<listitem>
	  <para>
	    If an element of <emphasis role="bold">b</emphasis> is greater
	    than or equal to 0, then the value of the corresponding
	    element of <emphasis role="bold">r</emphasis> is 0 if the
	    absolute value of the corresponding element of <emphasis
	    role="bold">a</emphasis> is equal to the value of the
	    corresponding element of <emphasis role="bold">b</emphasis>.
	    The value is negative if it is greater than the value of the
	    corresponding element of <emphasis role="bold">b</emphasis>.
	    It is positive if it is less than the value of the corresponding
	    element of <emphasis role="bold">b</emphasis>.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    If an element of <emphasis role="bold">b</emphasis> is less
	    than 0, then the value of the element of <emphasis
	    role="bold">r</emphasis> is positive if the value of the
	    corresponding element of <emphasis role="bold">a</emphasis> is
	    less than or equal to the value of the element of <emphasis
	    role="bold">b</emphasis>.  Otherwise, it is negative.
	  </para>
	</listitem>
      </itemizedlist>
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpbfp</primary>
	<secondary>vec_cmpb</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cmpb</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   vcmpbfp  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cmpeq">
      <title>vec_cmpeq</title>
      <subtitle>Vector Compare Equal</subtitle>
      <programlisting>
      r = vec_cmpeq (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of comparing each set of
      corresponding elements of two vectors for equality.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      For each element of <emphasis role="bold">r</emphasis>, the value
      of each bit is 1 if the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>
      are equal.  Otherwise, the value of each bit is 0.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpequb</primary>
	<secondary>vec_cmpeq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequh</primary>
	<secondary>vec_cmpeq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequw</primary>
	<secondary>vec_cmpeq</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequd</primary>
	<secondary>vec_cmpeq</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp</primary>
	<secondary>vec_cmpeq</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqdp</primary>
	<secondary>vec_cmpeq</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cmpeq</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequd  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequd  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequd  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpeqsp  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpeqdp  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cmpge">
      <title>vec_cmpge</title>
      <subtitle>Vector Compare Greater or Equal</subtitle>
      <programlisting>
      r = vec_cmpge (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of a greater-than-or-equal-to
      comparison between each set of corresponding elements of two
      vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      For each element of <emphasis role="bold">r</emphasis>, the value
      of each bit is 1 if the corresponding element of <emphasis
      role="bold">a</emphasis> is greater than or equal to the corresponding
      element of <emphasis role="bold">b</emphasis>.  Otherwise, the value
      of each bit is 0.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlnor</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgedp</primary>
	<secondary>vec_cmpge</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cmpge</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsb  t,b,a
   xxlnor    r,t,t		  
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtub  t,b,a
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsh  t,b,a
   xxlnor    r,t,t		  
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtuh  t,b,a
   xxlnor    r,t,t		  
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsw  t,b,a
   xxlnor    r,t,t		  
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtuw  t,b,a
   xxlnor    r,t,t		  
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsd  t,b,a
   xxlnor    r,t,t		  
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtud  t,b,a
   xxlnor    r,t,t		  
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpgesp  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpgedp  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cmpgt">
      <title>vec_cmpgt</title>
      <subtitle>Vector Compare Greater Than</subtitle>
      <programlisting>
      r = vec_cmpgt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of a greater-than
      comparison between each set of corresponding elements of two
      vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      For each element of <emphasis role="bold">r</emphasis>, the value
      of each bit is 1 if the corresponding element of <emphasis
      role="bold">a</emphasis> is greater than the corresponding
      element of <emphasis role="bold">b</emphasis>.  Otherwise, the value
      of each bit is 0.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtdp</primary>
	<secondary>vec_cmpgt</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cmpgt</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtub  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtuh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtuw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsd  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtud  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpgtsp  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpgtdp  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cmple">
      <title>vec_cmple</title>
      <subtitle>Vector Compare Less Than or Equal</subtitle>
      <programlisting>
      r = vec_cmple (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of a less-than-or-equal
      comparison between each set of corresponding elements of two
      vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      For each element of <emphasis role="bold">r</emphasis>, the value
      of each bit is 1 if the corresponding element of <emphasis
      role="bold">a</emphasis> is less than or equal to the corresponding
      element of <emphasis role="bold">b</emphasis>.  Otherwise, the value
      of each bit is 0.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlnor</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgesp</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgedp</primary>
	<secondary>vec_cmple</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cmple</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsb  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtub  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsh  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtuh  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsw  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtuw  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsd  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtud  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpgesp  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpgedp  r,b,a
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cmplt">
      <title>vec_cmplt</title>
      <subtitle>Vector Compare Less Than</subtitle>
      <programlisting>
      r = vec_cmplt (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of a less-than
      comparison between each set of corresponding elements of two
      vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      For each element of <emphasis role="bold">r</emphasis>, the value
      of each bit is 1 if the corresponding element of <emphasis
      role="bold">a</emphasis> is less than the corresponding
      element of <emphasis role="bold">b</emphasis>.  Otherwise, the value
      of each bit is 0.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpgtsb</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtub</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsh</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuh</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsw</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtuw</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtsd</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpgtud</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtsp</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpgtdp</primary>
	<secondary>vec_cmplt</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cmplt</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsb  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtub  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsh  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtuh  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsw  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtuw  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtsd  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpgtud  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpgtsp  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpgtdp  r,b,a
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cmpne">
      <title>vec_cmpne</title>
      <subtitle>Vector Compare Not Equal</subtitle>
      <programlisting>
      r = vec_cmpne (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of comparing each set of
      corresponding elements of two vectors for inequality.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      For each element of <emphasis role="bold">r</emphasis>, the value
      of each bit is 1 if the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>
      are not equal.  Otherwise, the value of each bit is 0.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpneb</primary>
	<secondary>vec_cmpne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpneh</primary>
	<secondary>vec_cmpne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnew</primary>
	<secondary>vec_cmpne</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpequd</primary>
	<secondary>vec_cmpne</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlnor</primary>
	<secondary>vec_cmpne</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqsp</primary>
	<secondary>vec_cmpne</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcmpeqdp</primary>
	<secondary>vec_cmpne</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cmpne</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpneb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpneb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpneb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpneh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpneh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpneh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnew  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnew  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnew  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequd  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequd  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   vcmpequd  t,a,b
   xxlnor    r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpeqsp  t,a,b
   xxlnor     r,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvcmpeqdp  t,a,b
   xxlnor     r,t,t
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cmpnez">
      <title>vec_cmpnez</title>
      <subtitle>Vector Compare Not Equal or Zero</subtitle>
      <programlisting>
      r = vec_cmpnez (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of comparing each set of
      corresponding elements of two vectors for inequality, or for
      an element with a zero value.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      For each element of <emphasis role="bold">r</emphasis>, the value
      of each bit is 1 if the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>
      are not equal, or if the <emphasis role="bold">a</emphasis> element or
      the <emphasis role="bold">b</emphasis> element is zero.  Otherwise,
      the value of each bit is 0.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpnezb</primary>
	<secondary>vec_cmpnez</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezh</primary>
	<secondary>vec_cmpnez</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezw</primary>
	<secondary>vec_cmpnez</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cmpnez</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnezb  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnezb  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnezh  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnezh  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnezw  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vcmpnezw  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cntlz">
      <title>vec_cntlz</title>
      <subtitle>Vector Count Leading Zeros</subtitle>
      <programlisting>
      r = vec_cntlz (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the number of most-significant bits
      equal to zero of each corresponding element of the source vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is
      set to the number of leading zeros of the corresponding element
      of <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vclzb</primary>
	<secondary>vec_cntlz</secondary>
      </indexterm>
      <indexterm>
	<primary>vclzh</primary>
	<secondary>vec_cntlz</secondary>
      </indexterm>
      <indexterm>
	<primary>vclzw</primary>
	<secondary>vec_cntlz</secondary>
      </indexterm>
      <indexterm>
	<primary>vclzd</primary>
	<secondary>vec_cntlz</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cntlz</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
		  <emphasis role="bold">Restrictions</emphasis>
		</para>
	      </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vclzb  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vclzb  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vclzh  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vclzh  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vclzw  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vclzw  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vclzd  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int long long</para>
              </entry>
              <entry>
		<programlisting>
   vclzd  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cntlz_lsbb">
      <title>vec_cntlz_lsbb</title>
      <subtitle>Vector Count Leading Zero Least-Significant Bits by
      Byte</subtitle>
      <programlisting>
      r = vec_cntlz_lsbb (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns the number of leading byte elements (starting at the
      lowest-numbered element) of a vector that have a least-significant
      bit of zero.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of <emphasis role="bold">r</emphasis> is set to the
      number of leading byte elements (starting at the lowest-numbered
      element) of <emphasis role="bold">a</emphasis> that have a
      least-significant bit of zero.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vclzlsbb</primary>
	<secondary>vec_cntlz_lsbb</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cntlz_lsbb</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
		  <emphasis role="bold">Restrictions</emphasis>
		</para>
	      </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vclzlsbb  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vclzlsbb  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cnttz">
      <title>vec_cnttz</title>
      <subtitle>Vector Count Trailing Zeros</subtitle>
      <programlisting>
      r = vec_cnttz (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the number of least-significant bits
      equal to zero of each corresponding element of the source vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is
      set to the number of trailing zeros of the corresponding element
      of <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vctzb</primary>
	<secondary>vec_cnttz</secondary>
      </indexterm>
      <indexterm>
	<primary>vctzh</primary>
	<secondary>vec_cnttz</secondary>
      </indexterm>
      <indexterm>
	<primary>vctzw</primary>
	<secondary>vec_cnttz</secondary>
      </indexterm>
      <indexterm>
	<primary>vctzd</primary>
	<secondary>vec_cnttz</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cnttz</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
		  <emphasis role="bold">Restrictions</emphasis>
		</para>
	      </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vctzb  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vctzb  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   vctzh  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   vctzh  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   vctzw  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   vctzw  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   vctzd  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int long long</para>
              </entry>
              <entry>
		<programlisting>
   vctzd  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cnttz_lsbb">
      <title>vec_cnttz_lsbb</title>
      <subtitle>Vector Count Trailing Zero Least-Significant Bits by
      Byte</subtitle>
      <programlisting>
      r = vec_cnttz_lsbb (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns the number of trailing byte elements (starting at the
      highest-numbered element) of a vector that have a least-significant
      bit of zero.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of <emphasis role="bold">r</emphasis> is set to the
      number of trailing byte elements (starting at the highest-numbered
      element) of <emphasis role="bold">a</emphasis> that have a
      least-significant bit of zero.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vctzlsbb</primary>
	<secondary>vec_cnttz_lsbb</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cnttz_lsbb</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
		  <emphasis role="bold">Restrictions</emphasis>
		</para>
	      </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   vctzlsbb  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   vctzlsbb  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para>ISA 3.0 or later</para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cpsgn">
      <title>vec_cpsgn</title>
      <subtitle>Vector Copy Sign</subtitle>
      <programlisting>
      r = vec_cpsgn (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector by copying the sign of the elements in one
      vector to the sign of the corresponding elements of another
      vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is set
      to the corresponding element of <emphasis role="bold">b</emphasis>
      with its sign replaced by the sign from the corresponding element of
      <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcpsgnsp</primary>
	<secondary>vec_cpsgn</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcpsgndp</primary>
	<secondary>vec_cpsgn</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cpsgn</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
		  <emphasis role="bold">Restrictions</emphasis>
		</para>
	      </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvcpsgnsp  r,b,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvcpsgndp  r,b,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_ctf">
      <title>vec_ctf</title>
      <subtitle>Vector Convert to Floating-Point</subtitle>
      <programlisting>
      r = vec_ctf (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts an integer vector into a floating-point vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      closest floating-point approximation of the value of the
      corresponding element of <emphasis role="bold">a</emphasis> divided
      by 2 to the power of <emphasis role="bold">b</emphasis>, which must
      be in the range 0&#x2013;31.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
        The example implementations below assume <emphasis
	role="bold">b</emphasis> is zero, so that the scaling code
	is omitted.  Scaling is accomplished by multiplying each
	element of <emphasis role="bold">r</emphasis> by 2 to the
	power of &#x2013;<emphasis role="bold">b</emphasis>.
      </para>
      
      <indexterm>
	<primary>vcfsx</primary>
	<secondary>vec_ctf</secondary>
      </indexterm>
      <indexterm>
	<primary>vcfux</primary>
	<secondary>vec_ctf</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_ctf</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>5-bit unsigned literal</para>
              </entry>
              <entry>
		<programlisting>
   vcfsx  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>5-bit unsigned literal</para>
              </entry>
              <entry>
		<programlisting>
   vcfux  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>5-bit unsigned literal</para>
              </entry>
              <entry>
		<programlisting>
   xvcvsxddp  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>5-bit unsigned literal</para>
              </entry>
              <entry>
		<programlisting>
   xvcvuxddp  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_cts">
      <title>vec_cts</title>
      <subtitle>Vector Convert to Signed Integer</subtitle>
      <programlisting>
      r = vec_cts (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts a floating-point vector into a signed integer vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      saturated signed-integer value, truncated towards zero, obtained by
      multiplying the corresponding element of <emphasis
      role="bold">a</emphasis> multiplied by 2 to the power of <emphasis
      role="bold">b</emphasis>, which must be in the range 0&#x2013;31.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vctsxs</primary>
	<secondary>vec_cts</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_cts</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>5-bit unsigned literal</para>
              </entry>
              <entry>
		<programlisting>
   vctsxs  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_ctu">
      <title>vec_ctu</title>
      <subtitle>Vector Convert to Unsigned Integer</subtitle>
      <programlisting>
      r = vec_ctu (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts a floating-point vector into an unsigned integer vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      saturated unsigned-integer value, truncated towards zero, obtained by
      multiplying the corresponding element of <emphasis
      role="bold">a</emphasis> multiplied by 2 to the power of <emphasis
      role="bold">b</emphasis>, which must be in the range 0&#x2013;31.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vctuxs</primary>
	<secondary>vec_ctu</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_ctu</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>5-bit unsigned literal</para>
              </entry>
              <entry>
		<programlisting>
   vctuxs  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_div">
      <title>vec_div</title>
      <subtitle>Vector Divide</subtitle>
      <programlisting>
      r = vec_div (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Divides the elements in one vector by the corresponding elements
      in another vector and places the quotients in the result vector.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is
      obtained by dividing the corresponding element of <emphasis
      role="bold">a</emphasis> by the corresponding element of <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxspltd</primary>
	<secondary>vec_div</secondary>
      </indexterm>
      <indexterm>
	<primary>mfvsrd</primary>
	<secondary>vec_div</secondary>
      </indexterm>
      <indexterm>
	<primary>divd</primary>
	<secondary>vec_div</secondary>
      </indexterm>
      <indexterm>
	<primary>mtvsrd</primary>
	<secondary>vec_div</secondary>
      </indexterm>
      <indexterm>
	<primary>xxmrghd</primary>
	<secondary>vec_div</secondary>
      </indexterm>
      <indexterm>
	<primary>xvdivsp</primary>
	<secondary>vec_div</secondary>
      </indexterm>
      <indexterm>
	<primary>xvdivdp</primary>
	<secondary>vec_div</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_div</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   xxspltd t,a,1
   mfvsrd  u,t
   xxspltd v,b,1
   mfvsrd  w,v
   divd    x,u,w
   mfvsrd  u,a
   mtvsrd  y,x
   mfvsrd  w,b
   divd    x,u,w
   mtvsrd  z,x
   xxmrghd r,z,y
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   xxspltd t,a,1
   mfvsrd  u,t
   xxspltd v,b,1
   mfvsrd  w,v
   divd    x,u,w
   mfvsrd  u,a
   mtvsrd  y,x
   mfvsrd  w,b
   divd    x,u,w
   mtvsrd  z,x
   xxmrghd r,z,y
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvdivsp r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xvdivdp r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_double">
      <title>vec_double</title>
      <subtitle>Vector Convert to Double Precision</subtitle>
      <programlisting>
      r = vec_double (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts a vector of long integers into a vector of double-precision
      numbers.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is
      obtained by converting the corresponding element of <emphasis
      role="bold">a</emphasis> to double precision floating-point.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcvsxddp</primary>
	<secondary>vec_double</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvuxddp</primary>
	<secondary>vec_double</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_double</title>
	<tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   xvcvsxddp r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   xvcvuxddp r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_doublee">
      <title>vec_doublee</title>
      <subtitle>Vector Convert Even Elements to Double Precision</subtitle>
      <programlisting>
      r = vec_doublee (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts the even elements of a vector into a vector of double-precision
      numbers.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      Elements 0 and 1 of <emphasis role="bold">r</emphasis> are set to
      the converted values of elements 0 and 2 of <emphasis
      role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      Differences in element numbering require different implementations
      for big- and little-endian code generation.
      </para>
      
      <indexterm>
	<primary>xxsldwi</primary>
	<secondary>vec_doublee</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvsxwdp</primary>
	<secondary>vec_doublee</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvuxwdp</primary>
	<secondary>vec_doublee</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvspdp</primary>
	<secondary>vec_doublee</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_doublee</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example LE Implementation</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example BE Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xvcvsxwdp  r,t
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xvcvsxwdp  r,a

		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xvcvuxwdp  r,t
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xvcvuxwdp  r,a

		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xvcvspdp   r,t
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xvcvspdp   r,a

		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_doubleh">
      <title>vec_doubleh</title>
      <subtitle>Vector Convert High Elements to Double Precision</subtitle>
      <programlisting>
      r = vec_doubleh (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts the high-order elements of a vector into a vector
      of double-precision numbers.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      Elements 0 and 1 of <emphasis role="bold">r</emphasis> are set to
      the converted values of elements 0 and 1 of <emphasis
      role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      Differences in element numbering require different implementations
      for big- and little-endian code generation.
      </para>
      
      <indexterm>
	<primary>xxsldwi</primary>
	<secondary>vec_doubleh</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvsxwdp</primary>
	<secondary>vec_doubleh</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvuxwdp</primary>
	<secondary>vec_doubleh</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvspdp</primary>
	<secondary>vec_doubleh</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_doubleh</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example LE Implementation</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example BE Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,3
   xxsldwi    u,a,t,2
   xvcvsxwdp  r,u
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xxsldwi    u,t,a,3
   xvcvsxwdp  r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,3
   xxsldwi    u,a,t,2
   xvcvuxwdp  r,u
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xxsldwi    u,t,a,3
   xvcvuxwdp  r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,3
   xxsldwi    u,a,t,2
   xvcvspdp   r,u
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xxsldwi    u,t,a,3
   xvcvspdp   r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_doublel">
      <title>vec_doublel</title>
      <subtitle>Vector Convert Low Elements to Double Precision</subtitle>
      <programlisting>
      r = vec_doublel (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts the low-order elements of a vector into a vector
      of double-precision numbers.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      Elements 0 and 1 of <emphasis role="bold">r</emphasis> are set to
      the converted values of elements 2 and 3 of <emphasis
      role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      Differences in element numbering require different implementations
      for big- and little-endian code generation.
      </para>
      
      <indexterm>
	<primary>xxsldwi</primary>
	<secondary>vec_doublel</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvsxwdp</primary>
	<secondary>vec_doublel</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvuxwdp</primary>
	<secondary>vec_doublel</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvspdp</primary>
	<secondary>vec_doublel</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_doublel</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example LE Implementation</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example BE Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xxsldwi    u,t,a,3
   xvcvsxwdp  r,u
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,3
   xxsldwi    u,a,t,2
   xvcvsxwdp  r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xxsldwi    u,t,a,3
   xvcvuxwdp  r,u
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,3
   xxsldwi    u,a,t,2
   xvcvuxwdp  r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xxsldwi    u,t,a,3
   xvcvspdp   r,u
		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,3
   xxsldwi    u,a,t,2
   xvcvspdp   r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_doubleo">
      <title>vec_doubleo</title>
      <subtitle>Vector Convert Odd Elements to Double Precision</subtitle>
      <programlisting>
      r = vec_doubleo (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts the odd elements of a vector into a vector
      of double-precision numbers.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      Elements 0 and 1 of <emphasis role="bold">r</emphasis> are set to
      the converted values of elements 1 and 3 of <emphasis
      role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      Differences in element numbering require different implementations
      for big- and little-endian code generation.
      </para>
      
      <indexterm>
	<primary>xvcvsxwdp</primary>
	<secondary>vec_doubleo</secondary>
      </indexterm>
      <indexterm>
	<primary>xxsldwi</primary>
	<secondary>vec_doubleo</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvuxwdp</primary>
	<secondary>vec_doubleo</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvspdp</primary>
	<secondary>vec_doubleo</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_doubleo</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example LE Implementation</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example BE Implementation</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Restrictions</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   xvcvsxwdp  r,a

		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xvcvsxwdp  r,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   xvcvuxwdp  r,a

		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xvcvuxwdp  r,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xvcvspdp   r,a

		</programlisting>
              </entry>
              <entry>
		<programlisting>
   xxsldwi    t,a,a,1
   xvcvspdp   r,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
		<para></para>
	      </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_eqv">
      <title>vec_eqv</title>
      <subtitle>Vector Equivalence</subtitle>
      <programlisting>
      r = vec_eqv (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bitwise equivalence (exclusive NOR) of two vectors.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of <emphasis role="bold">r</emphasis> is the bitwise XNOR
      of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxleqv</primary>
	<secondary>vec_eqv</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_eqv</title>
	<tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool char</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned char</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool short</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed short</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned short</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed int</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool int</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned int</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector bool long long</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed long long</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector unsigned long long</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector double</para>
              </entry>
              <entry>
		<programlisting>
   xxleqv r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_expte">
      <title>vec_expte</title>
      <subtitle>Vector Exponential Estimate</subtitle>
      <programlisting>
      r = vec_expte (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector <emphasis role="bold">r</emphasis> containing
      estimates of 2 raised to the power of the corresponding elements
      of <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      estimated value of 2 raised to the power of the corresponding element of
      <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vexptefp</primary>
	<secondary>vec_expte</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_expte</title>
	<tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector float</para>
              </entry>
              <entry>
		<programlisting>
   vexptefp  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_extract">
      <title>vec_extract</title>
      <subtitle>Vector Extract</subtitle>
      <programlisting>
      r = vec_extract (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns the value of the <emphasis role="bold">b</emphasis>th
      element of vector <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Result value:</emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      element of <emphasis role="bold">a</emphasis> at position
      <emphasis role="bold">b</emphasis> modulo the number of elements of
      <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
      Prior to ISA 3.0, less efficient code sequences must be used to
      implement vec_extract.
      </para>
      
      <indexterm>
	<primary>vextubrx</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>extsb</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>vextublx</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>slwi</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>vextuwrx</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>extsw</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>vextuwlx</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>xori</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>rldic</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>mtvsrdd</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>vslo</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>mfvsrd</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>vextuhrx</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>extsh</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>vextuhlx</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>rldicl</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>subfic</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>sldi</primary>
	<secondary>vec_extract</secondary>
      </indexterm>
      <indexterm>
	<primary>xscvspdp</primary>
	<secondary>vec_extract</secondary>
      </indexterm>

      <table frame="all">
	<title>Supported type signatures for vec_extract</title>
	<tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="18*" />
          <colspec colname="c4" colwidth="21*" />
          <colspec colname="c5" colwidth="21*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">r</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">a</emphasis>
		</para>
              </entry>
              <entry align="center" valign="middle">
		<para>
                  <emphasis role="bold">b</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example ISA 3.0 LE
		  Implementation</emphasis>
		</para>
              </entry>
              <entry align="center">
		<para>
                  <emphasis role="bold">Example ISA 3.0 BE
		  Implementation</emphasis>
		</para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
		<para>signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
		<para>signed int</para>
              </entry>
              <entry>
		<programlisting>
 vextubrx t,b,a
 extsb    r,t
		</programlisting>
              </entry>
              <entry>
		<programlisting>
 vextublx t,b,a
 extsb    r,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 vextubrx t,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vextublx t,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 vextubrx t,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vextublx t,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,1
 vextuhrx u,t,a
 extsh    r,u
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,1
 vextuhlx u,t,a
 extsh    r,u
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,1
 vextuhrx r,t,a
                </programlisting>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,1
 vextuhlx r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,1
 vextuhrx r,t,a
                </programlisting>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,1
 vextuhlx r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,2
 vextuwrx u,t,a
 extsw    r,u
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,2
 vextuwlx u,t,a
 extsw    r,u
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,2
 vextuwrx r,t,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,2
 vextuwlx r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,2
 vextuwrx r,t,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 slwi     t,b,2
 vextuwlx r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 xori    t,b,0x1
 rldic   u,t,6,57
 mtvsrdd v,u,u
 vslo    w,a,v
 mfvsrd  r,w
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 rldic   t,b,6,57
 mtvsrdd u,t,t
 vslo    v,a,u
 mfvsrd  r,v

		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
	      <entry>
                <programlisting>
 xori    t,b,0x1
 rldic   u,t,6,57
 mtvsrdd v,u,u
 vslo    w,a,v
 mfvsrd  r,w
		</programlisting>
	      </entry>
              <entry>
                <programlisting>
 rldic   t,b,6,57
 mtvsrdd u,t,t
 vslo    v,a,u
 mfvsrd  r,v

		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 xori    t,b,0x1
 rldic   u,t,6,57
 mtvsrdd v,u,u
 vslo    w,a,v
 mfvsrd  r,w
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 rldic   t,b,6,57
 mtvsrdd u,t,t
 vslo    v,a,u
 mfvsrd  r,v

		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 rldicl   t,b,0,62
 subfic   u,t,3
 sldi     v,u,5
 mtvsrdd  w,v,v
 vslo     x,a,w
 xscvspdp r,x
		</programlisting>
              </entry>
              <entry>
                <programlisting>

 sldi     t,b,5
 mtvsrdd  u,t,t
 vslo     v,a,u
 xscvspdp r,v

		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 xori    t,b,0x1
 rldic   u,t,6,57
 mtvsrdd v,u,u
 vslo    r,a,v
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 rldic   t,b,6,57
 mtvsrdd u,t,t
 vslo    r,a,u

		</programlisting>
              </entry>
            </row>
          </tbody>
	</tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_extract_exp">
      <title>vec_extract_exp</title>
      <subtitle>Vector Extract Exponent</subtitle>
      <programlisting>
      r = vec_extract_exp (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Extracts exponents from a vector of floating-point numbers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      Each element of <emphasis role="bold">r</emphasis> is extracted
      from the exponent field of the corresponding floating-point
      vector element of <emphasis role="bold">a</emphasis>.
      </para>
      <para>The extracted exponents of <emphasis role="bold">a</emphasis>
      are returned as right-justified unsigned integers containing biased
      exponents, in accordance with the exponent representation specified
      by IEEE 754, without further processing.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvxexpdp</primary>
	<secondary>vec_extract_exp</secondary>
      </indexterm>
      <indexterm>
	<primary>xvxexpsp</primary>
	<secondary>vec_extract_exp</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_extract_exp</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvxexpsp r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvxexpdp r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_extract_fp32_from_shorth">
      <title>vec_extract_fp32_from_shorth</title>
      <subtitle>Vector Extract Floats from High Elements of Vector Short Int</subtitle>
      <programlisting>
      r = vec_extract_fp32_from_shorth (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Extracts four single-precision floating-point numbers from the high
      elements of a vector of eight 16-bit elements, interpreting each
      element as a 16-bit floating-point number in IEEE format.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      The first four elements of <emphasis role="bold">a</emphasis> are
      interpreted as 16-bit floating-point numbers in IEEE format, and
      extended to single-precision format, returning a vector with four
      single-precision IEEE numbers.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      <para><emphasis role="bold">Notes:</emphasis> The example
      implementation assumes that the vperm instruction is used for
      big-endian, and the vpermr instruction is used for
      little-endian.  The permute control vector for the vperm or
      vpermr instruction is in a memory location identified by pcv. 
      The value located at pcv is identical in natural element order
      for big- and little-endian:  { 15, 14, 0, 0, 13, 12, 0, 0, 11,
      10, 0, 0, 9, 8, 0, 0 }.
      </para>
      
      <indexterm>
	<primary>lxv</primary>
	<secondary>vec_extract_fp32_from_shorth</secondary>
      </indexterm>
      <indexterm>
	<primary>vperm</primary>
	<secondary>vec_extract_fp32_from_shorth</secondary>
      </indexterm>
      <indexterm>
	<primary>vpermr</primary>
	<secondary>vec_extract_fp32_from_shorth</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvhpsp</primary>
	<secondary>vec_extract_fp32_from_shorth</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_extract_fp32_from_shorth</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  lxv      t,0(pcv)
  vperm[r] u,a,a,t
  xvcvhpsp r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_extract_fp32_from_shortl">
      <title>vec_extract_fp32_from_shortl</title>
      <subtitle>Vector Extract Floats from Low Elements of Vector Short Int</subtitle>
      <programlisting>
      r = vec_extract_fp32_from_shortl (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Extracts four single-precision floating-point numbers from the low
      elements of a vector of eight 16-bit elements, interpreting each
      element as a 16-bit floating-point number in IEEE format.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      The last four elements of <emphasis role="bold">a</emphasis> are
      interpreted as 16-bit floating-point numbers in IEEE format, and
      extended to single-precision format, returning a vector with four
      single-precision IEEE numbers.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      <para><emphasis role="bold">Notes:</emphasis> The example
      implementation assumes that the vperm instruction is used for
      big-endian, and the vpermr instruction is used for
      little-endian.  The permute control vector for the vperm or
      vpermr instruction is in a memory location identified by pcv. 
      The value located at pcv is identical in natural element order
      for big- and little-endian:  { 7, 6, 0, 0, 5, 4, 0, 0, 3, 2, 0,
      0, 1, 0, 0, 0 }.
      </para>
      
      <indexterm>
	<primary>lxv</primary>
	<secondary>vec_extract_fp32_from_shortl</secondary>
      </indexterm>
      <indexterm>
	<primary>vperm</primary>
	<secondary>vec_extract_fp32_from_shortl</secondary>
      </indexterm>
      <indexterm>
	<primary>vpermr</primary>
	<secondary>vec_extract_fp32_from_shortl</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvhpsp</primary>
	<secondary>vec_extract_fp32_from_shortl</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_extract_fp32_from_shortl</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  lxv      t,0(pcv)
  vperm[r] u,a,a,t
  xvcvhpsp r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_extract_sig">
      <title>vec_extract_sig</title>
      <subtitle>Vector Extract Significand</subtitle>
      <programlisting>
      r = vec_extract_sig (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Extracts a vector of significands (mantissas) from a vector of
      floating-point numbers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is extracted from the significand
      (mantissa) field of the corresponding floating-point element of
      <emphasis role="bold">a</emphasis>.</para>
      <para>The significand is from the corresponding floating-point
      number in accordance with the IEEE format. The returned result
      includes the implicit leading digit. The value of that digit is
      not encoded in the IEEE format, but is implied by the exponent.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvxsigdp</primary>
	<secondary>vec_extract_sig</secondary>
      </indexterm>
      <indexterm>
	<primary>xvxsigsp</primary>
	<secondary>vec_extract_sig</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_extract_sig</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
   xvxsigsp r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
   xvxsigdp r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_extract4b">
      <title>vec_extract4b</title>
      <subtitle>Vector Extract Four Bytes</subtitle>
      <programlisting>
      r = vec_extract4b (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Extracts a word from vector <emphasis role="bold">a</emphasis> at
      constant byte position <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The first
      doubleword element of <emphasis role="bold">r</emphasis> contains
      the zero-extended extracted word from <emphasis role="bold">a</emphasis>.
      The second doubleword is set to 0. <emphasis role="bold">b</emphasis>
      specifies the least-significant byte number (0–12) of the word
      to be extracted.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xxextractuw</primary>
	<secondary>vec_extract4b</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_extract4b</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="16*" />
          <colspec colname="c4" colwidth="24*" />
          <colspec colname="c5" colwidth="22*" />
          <colspec colname="c6" colwidth="18*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>const int (range [0,12])</para>
              </entry>
              <entry>
                <programlisting>
 xxextractuw r,a,12-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxextractuw r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_first_match_index">
      <title>vec_first_match_index</title>
      <subtitle>Vector Index of First Match</subtitle>
      <programlisting>
      r = vec_first_match_index (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a comparison of equality on each of the corresponding
      elements of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>, and returns the first position of
      equality.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Returns the
      element index of the position of the first character match in
      natural element order.  If no match, returns the number of
      characters as an element count in the vector argument.</para> 
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpnezb</primary>
	<secondary>vec_first_match_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezh</primary>
	<secondary>vec_first_match_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezw</primary>
	<secondary>vec_first_match_index</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlnor</primary>
	<secondary>vec_first_match_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vctzlsbb</primary>
	<secondary>vec_first_match_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vclzlsbb</primary>
	<secondary>vec_first_match_index</secondary>
      </indexterm>
      <indexterm>
	<primary>rldicl</primary>
	<secondary>vec_first_match_index</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_first_match_index</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="18*" />
          <colspec colname="c2" colwidth="18*" />
          <colspec colname="c3" colwidth="18*" />
          <colspec colname="c4" colwidth="24*" />
          <colspec colname="c5" colwidth="24*" />
          <colspec colname="c6" colwidth="18*" />
          <thead>
            <row valign="middle">
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para> 
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para> 
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnezb  t,a,b
  xxlnor    u,t,t
  vctzlsbb  r,u
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vcmpnezb  t,a,b
  xxlnor    u,t,t
  vclzlsbb  r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnezb  t,a,b
  xxlnor    u,t,t
  vctzlsbb  r,u
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vcmpnezb  t,a,b
  xxlnor    u,t,t
  vclzlsbb  r,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnezh  t,a,b
  xxlnor    u,t,t
  vctzlsbb  v,u
  rldicl    r,v,63,33
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vcmpnezh  t,a,b
  xxlnor    u,t,t
  vclzlsbb  v,u
  rldicl    r,v,63,33
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnezh  t,a,b
  xxlnor    u,t,t
  vctzlsbb  v,u
  rldicl    r,v,63,33
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vcmpnezh  t,a,b
  xxlnor    u,t,t
  vclzlsbb  v,u
  rldicl    r,v,63,33
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnezw  t,a,b
  xxlnor    u,t,t
  vctzlsbb  v,u
  rldicl    r,v,62,34
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vcmpnezw  t,a,b
  xxlnor    u,t,t
  vclzlsbb  v,u
  rldicl    r,v,62,34
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vcmpnezw  t,a,b
  xxlnor    u,t,t
  vctzlsbb  v,u
  rldicl    r,v,62,34
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vcmpnezw  t,a,b
  xxlnor    u,t,t
  vclzlsbb  v,u
  rldicl    r,v,62,34
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_first_match_or_eos_index">
      <title>vec_first_match_or_eos_index</title>
      <subtitle>Vector Index of First Match or End of String</subtitle>
      <programlisting>
      r = vec_first_match_or_eos_index (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a comparison of equality on each of the corresponding
      elements of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>. Returns the first position of
      equality, or the zero string terminator.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Returns the
      element index of the position, in natural element order, of
      either the first character match or an end-of-string (EOS)
      terminator. If no match or terminator, returns the number of
      characters as an element count in the vector argument.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxspltib</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpneb</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezb</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpneh</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezh</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnew</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezw</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>xxland</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlnand</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vctzlsbb</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vclzlsbb</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>rldicl</primary>
	<secondary>vec_first_match_or_eos_index</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_first_match_or_eos_index</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="18*" />
          <colspec colname="c2" colwidth="18*" />
          <colspec colname="c3" colwidth="18*" />
          <colspec colname="c4" colwidth="24*" />
          <colspec colname="c5" colwidth="24*" />
          <colspec colname="c6" colwidth="18*" />
          <thead>
            <row valign="middle">
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneb   u,a,t
 vcmpneb   v,b,t
 vcmpnezb  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vctzlsbb  r,y
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneb   u,a,t
 vcmpneb   v,b,t
 vcmpnezb  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vclzlsbb  r,y
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneb   u,a,t
 vcmpneb   v,b,t
 vcmpnezb  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vctzlsbb  r,y
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneb   u,a,t
 vcmpneb   v,b,t
 vcmpnezb  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vclzlsbb  r,y
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneh   u,a,t
 vcmpneh   v,b,t
 vcmpnezh  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vctzlsbb  z,y
 rldicl    r,z,63,33
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneh   u,a,t
 vcmpneh   v,b,t
 vcmpnezh  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vclzlsbb  z,y
 rldicl    r,z,63,33
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneh   u,a,t
 vcmpneh   v,b,t
 vcmpnezh  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vctzlsbb  z,y
 rldicl    r,z,63,33
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneh   u,a,t
 vcmpneh   v,b,t
 vcmpnezh  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vclzlsbb  z,y
 rldicl    r,z,63,33
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpnew   u,a,t
 vcmpnew   v,b,t
 vcmpnezw  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vctzlsbb  z,y
 rldicl    r,z,62,34
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpnew   u,a,t
 vcmpnew   v,b,t
 vcmpnezw  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vclzlsbb  z,y
 rldicl    r,z,62,34
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpnew   u,a,t
 vcmpnew   v,b,t
 vcmpnezw  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vctzlsbb  z,y
 rldicl    r,z,62,34
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpnew   u,a,t
 vcmpnew   v,b,t
 vcmpnezw  w,a,b
 xxland    x,u,v
 xxlnand   y,x,w
 vclzlsbb  z,y
 rldicl    r,z,62,34
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_first_mismatch_index">
      <title>vec_first_mismatch_index</title>
      <subtitle>Vector Index of First Mismatch</subtitle>
      <programlisting>
      r = vec_first_mismatch_index (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a comparison of inequality on each of the corresponding
      elements of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>, and returns the first position of
      inequality.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Returns the
      element index of the position of the first character mismatch in
      natural element order. If no mismatch, returns the number of
      characters as an element count in the vector argument.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vcmpneb</primary>
	<secondary>vec_first_mismatch_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpneh</primary>
	<secondary>vec_first_mismatch_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnew</primary>
	<secondary>vec_first_mismatch_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vctzlsbb</primary>
	<secondary>vec_first_mismatch_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vclzlsbb</primary>
	<secondary>vec_first_mismatch_index</secondary>
      </indexterm>
      <indexterm>
	<primary>rldicl</primary>
	<secondary>vec_first_mismatch_index</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_first_mismatch_index</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="18*" />
          <colspec colname="c2" colwidth="18*" />
          <colspec colname="c3" colwidth="18*" />
          <colspec colname="c4" colwidth="24*" />
          <colspec colname="c5" colwidth="24*" />
          <colspec colname="c6" colwidth="18*" />
          <thead>
            <row valign="middle">
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
 vcmpneb   t,a,b
 vctzlsbb  r,t
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vcmpneb   t,a,b
 vclzlsbb  r,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vcmpneb   t,a,b
 vctzlsbb  r,t
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vcmpneb   t,a,b
 vclzlsbb  r,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 vcmpneh   t,a,b
 vctzlsbb  u,t
 rldicl    r,u,63,33
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vcmpneh   t,a,b
 vclzlsbb  u,t
 rldicl    r,u,63,33
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
 vcmpneh   t,a,b
 vctzlsbb  u,t
 rldicl    r,u,63,33
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vcmpneh   t,a,b
 vclzlsbb  u,t
 rldicl    r,u,63,33
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vcmpnew   t,a,b
 vctzlsbb  u,t
 rldicl    r,u,62,34
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vcmpnew   t,a,b
 vclzlsbb  u,t
 rldicl    r,u,62,34
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vcmpnew   t,a,b
 vctzlsbb  u,t
 rldicl    r,u,62,34
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vcmpnew   t,a,b
 vclzlsbb  u,t
 rldicl    r,u,62,34
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_first_mismatch_or_eos_index">
      <title>vec_first_mismatch_or_eos_index</title>
      <subtitle>Vector Index of First Mismatch or End of String</subtitle>
      <programlisting>
      r = vec_first_mismatch_or_eos_index (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a comparison of inequality on each of the corresponding
      elements of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>. Returns the first position of
      inequality, or the zero string terminator.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Returns the
      element index of the position, in natural element order, of
      either the first character mismatch or an end-of-string (EOS)
      terminator. If no mismatch or terminator, returns the number of
      characters as an element count in the vector argument.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxspltib</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpneb</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezb</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpneh</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezh</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnew</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vcmpnezw</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>xxland</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlorc</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vctzlsbb</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>vclzlsbb</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>
      <indexterm>
	<primary>rldicl</primary>
	<secondary>vec_first_mismatch_or_eos_index</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for
      vec_first_mismatch_or_eos_index</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="18*" />
          <colspec colname="c2" colwidth="18*" />
          <colspec colname="c3" colwidth="18*" />
          <colspec colname="c4" colwidth="24*" />
          <colspec colname="c5" colwidth="24*" />
          <colspec colname="c6" colwidth="18*" />
          <thead>
            <row valign="middle">
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneb   u,a,t
 vcmpneb   v,b,t
 vcmpnezb  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vctzlsbb  r,y
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneb   u,a,t
 vcmpneb   v,b,t
 vcmpnezb  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vclzlsbb  r,y
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneb   u,a,t
 vcmpneb   v,b,t
 vcmpnezb  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vctzlsbb  r,y
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneb   u,a,t
 vcmpneb   v,b,t
 vcmpnezb  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vclzlsbb  r,y
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneh   u,a,t
 vcmpneh   v,b,t
 vcmpnezh  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vctzlsbb  z,y
 rldicl    r,z,63,33
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneh   u,a,t
 vcmpneh   v,b,t
 vcmpnezh  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vclzlsbb  z,y
 rldicl    r,z,63,33
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneh   u,a,t
 vcmpneh   v,b,t
 vcmpnezh  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vctzlsbb  z,y
 rldicl    r,z,63,33
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpneh   u,a,t
 vcmpneh   v,b,t
 vcmpnezh  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vclzlsbb  z,y
 rldicl    r,z,63,33
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpnew   u,a,t
 vcmpnew   v,b,t
 vcmpnezw  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vctzlsbb  z,y
 rldicr    r,z,62,34
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpnew   u,a,t
 vcmpnew   v,b,t
 vcmpnezw  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vclzlsbb  z,y
 rldicr    r,z,62,34
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpnew   u,a,t
 vcmpnew   v,b,t
 vcmpnezw  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vctzlsbb  z,y
 rldicr    r,z,62,34
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltib  t,0
 vcmpnew   u,a,t
 vcmpnew   v,b,t
 vcmpnezw  w,a,b
 xxland    x,u,v
 xxlorc    y,w,x
 vclzlsbb  z,y
 rldicr    r,z,62,34
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_float">
      <title>vec_float</title>
      <subtitle>Vector Convert Integer to Floating-Point</subtitle>
      <programlisting>
      r = vec_float (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts a vector of integers to a vector of single-precision
      floating-point numbers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Elements of
      <emphasis role="bold">r</emphasis> are obtained by converting the
      respective elements of <emphasis role="bold">a</emphasis> to
      single-precision floating-point numbers.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcvsxwsp</primary>
	<secondary>vec_float</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvuxwsp</primary>
	<secondary>vec_float</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_float</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  xvcvsxwsp r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xvcvuxwsp r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_float2">
      <title>vec_float2</title>
      <subtitle>Vector Convert Two Vectors to Floating-Point</subtitle>
      <programlisting>
      r = vec_float2 (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts two vectors of long long integers or double-precision
      floating-point numbers to a vector of single-precision numbers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Elements of
      <emphasis role="bold">r</emphasis> are obtained by converting the
      elements of <emphasis role="bold">a</emphasis> and
      <emphasis role="bold">b</emphasis> to single-precision numbers.
      Elements 0 and 1 of <emphasis role="bold">r</emphasis> are converted
      from elements 0 and 1 of <emphasis role="bold">a</emphasis>,
      respectively, and elements 2 and 3 of <emphasis role="bold">r</emphasis>
      are converted from elements 0 and 1 of <emphasis
      role="bold">b</emphasis>, respectively. </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_float2</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvsxdsp</primary>
	<secondary>vec_float2</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgow</primary>
	<secondary>vec_float2</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgew</primary>
	<secondary>vec_float2</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_float2</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi  t,b,a,0
 xxpermdi  u,b,a,3
 xvcvsxdsp v,t
 xvcvsxdsp w,u
 vmrgow    r,v,w
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi  t,b,a,0
 xxpermdi  u,b,a,3
 xvcvsxdsp v,t
 xvcvsxdsp w,u
 vmrgew    r,v,w
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi  t,b,a,0
 xxpermdi  u,b,a,3
 xvcvsxdsp v,t
 xvcvsxdsp w,u
 vmrgow    r,v,w
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi  t,b,a,0
 xxpermdi  u,b,a,3
 xvcvsxdsp v,t
 xvcvsxdsp w,u
 vmrgew    r,v,w
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi  t,b,a,0
 xxpermdi  u,b,a,3
 xvcvsxdsp v,t
 xvcvsxdsp w,u
 vmrgow    r,v,w
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi  t,b,a,0
 xxpermdi  u,b,a,3
 xvcvsxdsp v,t
 xvcvsxdsp w,u
 vmrgew    r,v,w
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_floate">
      <title>vec_floate</title>
      <subtitle>Vector Convert to Floating-Point in Even Elements</subtitle>
      <programlisting>
      r = vec_floate (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts the elements of a source vector to single-precision
      floating-point and stores the results in the even elements of
      the target vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The even-numbered
      elements of <emphasis role="bold">r</emphasis> are obtained by
      converting the elements of <emphasis role="bold">a</emphasis> to
      single-precision numbers, using the current floating-point rounding
      mode.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xvcvsxdsp</primary>
	<secondary>vec_floate</secondary>
      </indexterm>
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_floate</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvuxdsp</primary>
	<secondary>vec_floate</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvdpsp</primary>
	<secondary>vec_floate</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_floate</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
 xvcvsxdsp  r,a

		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xvcvsxdsp  t,a
 vsldoi     r,t,t,4
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
 xvcvuxdsp  r,a

		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xvcvuxdsp  t,a
 vsldoi     r,t,t,4
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
 xvcvdpsp  r,a

		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xvcvdpsp  t,a
 vsldoi    r,t,t,4
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_floato">
      <title>vec_floato</title>
      <subtitle>Vector Convert to Floating-Point in Odd Elements</subtitle>
      <programlisting>
      r = vec_floato (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts the elements of a source vector to single-precision
      floating-point and stores the results in the odd elements of the
      target vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The odd-numbered
      elements of <emphasis role="bold">r</emphasis> are obtained by
      converting the elements of <emphasis role="bold">a</emphasis> to
      single-precision numbers, using the current floating-point rounding
      mode.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xvcvsxdsp</primary>
	<secondary>vec_floato</secondary>
      </indexterm>
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_floato</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvuxdsp</primary>
	<secondary>vec_floato</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvdpsp</primary>
	<secondary>vec_floato</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_floato</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  xvcvsxdsp t,a
  vsldoi    r,t,t,4
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xvcvsxdsp r,a

		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xvcvuxdsp t,a
  vsldoi    r,t,t,4
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xvcvuxdsp r,a

		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcvdpsp  t,a
  vsldoi    r,t,t,4
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xvcvdpsp  r,a

		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_floor">
      <title>vec_floor</title>
      <subtitle>Vector Floor</subtitle>
      <programlisting>
      r = vec_floor (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the largest representable floating-point
      integral values less than or equal to the values of the corresponding
      elements of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains the largest representable
      floating-point integral value less than or equal to the value of the
      corresponding element of <emphasis role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvrdpim</primary>
	<secondary>vec_floor</secondary>
      </indexterm>
      <indexterm>
	<primary>xvrspim</primary>
	<secondary>vec_floor</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_floor</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvrspim  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvrdpim  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_gb">
      <title>vec_gb</title>
      <subtitle>Vector Gather Bits by Byte</subtitle>
      <programlisting>
      r = vec_gb (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a gather-bits operation on the input.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Within each
      doubleword, let x(i) (0 ≤ i &lt; 8) denote the byte elements, with
      x(0) the most-significant byte. For each pair of i and j (0 ≤ i
      &lt; 8, 0 ≤ j &lt; 8), the <emphasis>j</emphasis>th bit of the
      <emphasis>i</emphasis>th byte element of
      <emphasis role="bold">r</emphasis> is set to the value of the
      <emphasis>i</emphasis>th bit of the <emphasis>j</emphasis>th byte
      element of <emphasis role="bold">a</emphasis>.</para>
      <para>
	<xref linkend="VIPR.ch-vec.vec_gb" />, taken from the
	Power ISA, shows how bits are combined by the
	<code>vec_gb</code> intrinsic.  Here <code>VR[VRT]</code> is
	equivalent to <emphasis role="bold">r</emphasis>, and
	<code>VR[VRB]</code> is equivalent to <emphasis
	role="bold">a</emphasis>.
      </para>
      <figure pgwide="1" xml:id="VIPR.ch-vec.vec_gb">
	<title>Operation of vec_gb</title>
	<mediaobject>
	  <imageobject>
	    <imagedata fileref="vgbbd.png" format="PNG"
		       scalefit="1" width="100%" />
	  </imageobject>
	</mediaobject>
      </figure>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The <emphasis role="bold">vec_gb</emphasis> intrinsic function assumes
      big-endian (left-to-right) numbering for both bits and bytes, matching
      the ISA 2.07 <emphasis role="bold">vgbbd</emphasis> instruction.
      </para>
      
      <indexterm>
	<primary>vgbbd</primary>
	<secondary>vec_gb</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_gb</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vgbbd  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_insert">
      <title>vec_insert</title>
      <subtitle>Vector Insert</subtitle>
      <programlisting>
      r = vec_insert (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a copy of vector <emphasis role="bold">b</emphasis>  with
      element <emphasis role="bold">c</emphasis> replaced by the value of
      <emphasis role="bold">a</emphasis>.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      <emphasis role="bold">r</emphasis> contains a copy of vector
      <emphasis role="bold">b</emphasis> with element <emphasis
      role="bold">c</emphasis> replaced by the value of <emphasis
      role="bold">a</emphasis>. This function uses modular arithmetic on
      <emphasis role="bold">c</emphasis> to determine the element number.
      For example, if <emphasis role="bold">c</emphasis> is out of range, the
      compiler uses <emphasis role="bold">c</emphasis> modulo the number of
      elements in the vector to determine the element position.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      <para><emphasis role="bold">Notes:</emphasis> The sample
      implementations are given for ISA 3.0 when <emphasis
      role="bold">c</emphasis> is a constant.  For earlier target
      architectures, or when <emphasis role="bold">c</emphasis> is
      variable, less efficient sequences are required.  The sample
      implementations also assume that <emphasis
      role="bold">c</emphasis> is in range; that is, any required
      modulus operations have already been performed on the constant
      index.
      </para>
      
      <indexterm>
	<primary>mtvsrwz</primary>
	<secondary>vec_insert</secondary>
      </indexterm>
      <indexterm>
	<primary>vinsertb</primary>
	<secondary>vec_insert</secondary>
      </indexterm>
      <indexterm>
	<primary>xxinsertw</primary>
	<secondary>vec_insert</secondary>
      </indexterm>
      <indexterm>
	<primary>mtvsrd</primary>
	<secondary>vec_insert</secondary>
      </indexterm>
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_insert</secondary>
      </indexterm>
      <indexterm>
	<primary>vinserth</primary>
	<secondary>vec_insert</secondary>
      </indexterm>
      <indexterm>
	<primary>xscvdpspn</primary>
	<secondary>vec_insert</secondary>
      </indexterm>
      <indexterm>
	<primary>xxextractuw</primary>
	<secondary>vec_insert</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_insert</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="15*" />
          <colspec colname="c2" colwidth="13*" />
          <colspec colname="c3" colwidth="15*" />
          <colspec colname="c4" colwidth="13*" />
          <colspec colname="c5" colwidth="35*" />
          <colspec colname="c6" colwidth="31*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example ISA 3.0 LE Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example ISA 3.0 BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz  t,b
 vinsertb r,t,15-c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz  t,b
 vinsertb r,t,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz  t,b
 vinsertb r,t,15-c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz  t,b
 vinsertb r,t,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz  t,b
 vinserth r,t,a,(7-c)*2
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 mtvsrd   t,b
 vinserth r,t,a,c*2
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz  t,b
 vinserth r,t,a,(7-c)*2
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 mtvsrd   t,b
 vinserth r,t,a,c*2
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz   t,b
 xxinsertw r,t,(3-c)*4
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz  t,b
 vinsertb r,t,c*4
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz   t,b
 xxinsertw r,t,(3-c)*4
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 mtvsrwz  t,b
 vinsertb r,t,c*4
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 mtvsrd   t,b
 xxpermdi r,t,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 mtvsrd   t,b
 xxpermdi r,t,a,1-c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 mtvsrd   t,b
 xxpermdi r,t,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 mtvsrd   t,b
 xxpermdi r,t,a,1-c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 xscvdpspn   t,a
 xxextractuw u,t,0
 xxinsertw   r/b,u,(3-c)*4
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xscvdpspn   t,a
 xxextractuw u,t,0
 xxinsertw   r/b,u,c*4
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,1 [c=0]
        [or]
 xxpermdi r,a,b,1 [c=1]
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,1 [c=0]
        [or]
 xxpermdi r,b,a,1 [c=1]
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_insert_exp">
      <title>vec_insert_exp</title>
      <subtitle>Vector Insert Exponent</subtitle>
      <programlisting>
      r = vec_insert_exp (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Inserts exponents into a vector of floating-point numbers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is generated by combining the exponent
      specified by the corresponding element of <emphasis
      role="bold">b</emphasis> with the sign and significand of the
      corresponding element of <emphasis role="bold">a</emphasis>.</para>
      <para>The inserted exponent of <emphasis role="bold">b</emphasis> is
      treated as a right-justified unsigned integer containing a biased
      exponent, in accordance with the exponent representation specified by
      IEEE 754. It is combined with the sign and significand of
      <emphasis role="bold">a</emphasis> without further processing.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xviexpdp</primary>
	<secondary>vec_insert_exp</secondary>
      </indexterm>
      <indexterm>
	<primary>xviexpsp</primary>
	<secondary>vec_insert_exp</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_insert_exp</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xviexpsp  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xviexpsp  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xviexpdp  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xviexpdp  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_insert4b">
      <title>vec_insert4b</title>
      <subtitle>Vector Insert Four Bytes</subtitle>
      <programlisting>
      r = vec_insert4b (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Inserts a word into a vector at a byte position.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let W be the first
      doubleword element of <emphasis role="bold">a</emphasis>, truncated to
      32 bits. The result vector <emphasis role="bold">r</emphasis> is formed
      by inserting W into <emphasis role="bold">b</emphasis> at the byte
      position (0–12) specified by <emphasis
      role="bold">c</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element and byte numbering within a register is left-to-right for
      big-endian targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_insert4b</secondary>
      </indexterm>
      <indexterm>
	<primary>xxinsertw</primary>
	<secondary>vec_insert4b</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_insert4b</title>
      <tgroup cols="7">
          <colspec colname="c1" colwidth="18*" />
          <colspec colname="c2" colwidth="18*" />
          <colspec colname="c3" colwidth="18*" />
          <colspec colname="c4" colwidth="16*" />
          <colspec colname="c5" colwidth="26*" />
          <colspec colname="c6" colwidth="26*" />
          <colspec colname="c7" colwidth="16*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>const int (range [0,12])</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi  t,a,a,1
 xxinsertw b,t,12-c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxinsertw b,t,c

		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>const int (range [0,12])</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi  t,a,a,1
 xxinsertw b,t,12-c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxinsertw b,t,c

		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_ld">
      <title>vec_ld</title>
      <subtitle>Vector Load Indexed</subtitle>
      <programlisting>
      r = vec_ld (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Loads a 16-byte vector from the memory address specified by the
      displacement and the pointer, ignoring the four low-order bits
      of the calculated address.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of
      <emphasis role="bold">r</emphasis> is obtained by adding <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>,
      masking off the four low-order bits of the result, and
      loading the 16-byte vector from the resultant memory address.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>lvx</primary>
	<secondary>vec_ld</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_ld</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example ISA 3.0
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed __int128 *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed __int128 *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned __int128 *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128 *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double *</para>
              </entry>
              <entry>
                <programlisting>
  lvx  r,b,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_lde">
      <title>vec_lde</title>
      <subtitle>Vector Load Element Indexed</subtitle>
      <programlisting>
      r = vec_lde (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Loads a single element into the position in the vector register
      corresponding to its address, leaving the remaining elements of
      the register undefined.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      The integer value <emphasis role="bold">a</emphasis> is added to the
      pointer value <emphasis role="bold">b</emphasis>.  The resulting
      address is rounded down to the nearest address that is a multiple of
      <emphasis>es</emphasis>, where <emphasis>es</emphasis> is 1 for
      char pointers, 2 for short pointers, and 4 for float or int pointers.
      The element at this address is loaded into an element of <emphasis
      role="bold">r</emphasis>, leaving all other elements of <emphasis
      role="bold">r</emphasis> undefined.  The position of the loaded
      element in <emphasis role="bold">r</emphasis> is determined by taking the
      address modulo 16.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para>
	<emphasis role="bold">Notes:</emphasis>
  	Be careful to note that the address (b+c) is aligned to an
	element boundary.  Do not attempt to load unaligned data
	with this intrinsic.
      </para>
      
      <indexterm>
	<primary>lvebx</primary>
	<secondary>vec_lde</secondary>
      </indexterm>
      <indexterm>
	<primary>lvewx</primary>
	<secondary>vec_lde</secondary>
      </indexterm>
      <indexterm>
	<primary>lvehx</primary>
	<secondary>vec_lde</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_lde</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example ISA 3.0
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  lvebx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  lvebx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed short *</para>
              </entry>
              <entry>
                <programlisting>
  lvehx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  lvehx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed int *</para>
              </entry>
              <entry>
                <programlisting>
  lvewx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  lvewx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>float *</para>
              </entry>
              <entry>
                <programlisting>
  lvewx  r,b,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_ldl">
      <title>vec_ldl</title>
      <subtitle>Vector Load Indexed Least Recently Used</subtitle>
      <programlisting>
      r = vec_ldl (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Loads a 16-byte vector from the memory address specified by the
      displacement and the pointer, ignoring the four low-order bits
      of the calculated address, and marks the cache line loaded from
      as least recently used.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of
      <emphasis role="bold">r</emphasis> is obtained by adding <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>,
      masking off the four low-order bits of the result, and
      loading the 16-byte vector from the resultant memory address.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
        This intrinsic can be used to indicate the last access to a
	portion of memory, as a hint to the data cache controller that
	the associated cache line can be replaced without performance
	loss.
      </para>
      
      <indexterm>
	<primary>lvxl</primary>
	<secondary>vec_ldl</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_ldl</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example ISA 3.0
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double *</para>
              </entry>
              <entry>
                <programlisting>
  lvxl  r,b,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_loge">
      <title>vec_loge</title>
      <subtitle>Vector Base-2 Logarithm Estimate</subtitle>
      <programlisting>
      r = vec_loge (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing estimates of the base-2 logarithms of the
      corresponding elements of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains an estimated value of the
      base-2 logarithm of the corresponding element of <emphasis
      role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vlogefp</primary>
	<secondary>vec_loge</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_loge</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  vlogefp  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_madd">
      <title>vec_madd</title>
      <subtitle>Vector Multiply-Add</subtitle>
      <programlisting>
      r = vec_madd (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a fused
      multiply-add operation for each corresponding set of elements of the
      source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the product of the
      values of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>, added
      to the value of the corresponding element of <emphasis
      role="bold">c</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vmladduhm</primary>
	<secondary>vec_madd</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmaddmdp</primary>
	<secondary>vec_madd</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmaddmsp</primary>
	<secondary>vec_madd</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_madd</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vmladduhm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vmladduhm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vmladduhm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vmladduhm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvmaddmsp r/a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvmaddmdp r/a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_madds">
      <title>vec_madds</title>
      <subtitle>Vector Multiply-Add Saturated</subtitle>
      <programlisting>
      r = vec_madds (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a saturated
      multiply-high-and-add operation for each corresponding set of elements
      of the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is produced as follows:
      The values of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> are
      multiplied. The value of the 17 most-significant bits of this product
      is then added, using 16-bit-saturated addition, to the value of the
      corresponding element of <emphasis role="bold">c</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vmhaddshs</primary>
	<secondary>vec_madds</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_madds</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vmhaddshs r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_max">
      <title>vec_max</title>
      <subtitle>Vector Maximum</subtitle>
      <programlisting>
      r = vec_max (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the maximum value from each set of
      corresponding elements of the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      The value of each element of <emphasis role="bold">r</emphasis> is the
      maximum of the values of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vmaxsb</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxub</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsw</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxuw</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsd</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxud</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxsh</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>vmaxuh</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmaxdp</primary>
	<secondary>vec_max</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmaxsp</primary>
	<secondary>vec_max</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_max</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vmaxsb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vmaxub  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vmaxsh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vmaxuh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vmaxsw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vmaxuw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vmaxsd  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vmaxud  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvmaxsp  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvmaxdp  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mergee">
      <title>vec_mergee</title>
      <subtitle>Vector Merge Even</subtitle>
      <programlisting>
      r = vec_mergee (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Merges the even-numbered values from two vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The even-numbered
      elements of <emphasis role="bold">a</emphasis> are stored into the
      even-numbered elements of <emphasis role="bold">r</emphasis>. The
      even-numbered elements of <emphasis role="bold">b</emphasis> are stored
      into the odd-numbered elements of <emphasis
      role="bold">r</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vmrgow</primary>
	<secondary>vec_mergee</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgew</primary>
	<secondary>vec_mergee</secondary>
      </indexterm>
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_mergee</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mergee</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  vmrgow  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vmrgew  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vmrgow  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vmrgew  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vmrgow  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vmrgew  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,b,a,3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,a,b,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,b,a,3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,a,b,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,b,a,3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,a,b,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  vmrgow  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vmrgew  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,b,a,3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,a,b,0
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mergeh">
      <title>vec_mergeh</title>
      <subtitle>Vector Merge High</subtitle>
      <programlisting>
      r = vec_mergeh (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Merges the first halves (in element order) of two vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The
      <emphasis>n</emphasis>th element of <emphasis role="bold">r</emphasis>,
      if <emphasis>n</emphasis> is an even number, is given the value of the
      (<emphasis>n</emphasis>/2)th element of <emphasis
      role="bold">a</emphasis>.  The (<emphasis>n</emphasis>+1)th element
      of <emphasis role="bold">r</emphasis>, if <emphasis>n</emphasis> is an
      even number, is given the value of the (<emphasis>n</emphasis>/2)th
      element of <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vmrglb</primary>
	<secondary>vec_mergeh</secondary>
      </indexterm>
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_mergeh</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrghb</primary>
	<secondary>vec_mergeh</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrglw</primary>
	<secondary>vec_mergeh</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrghw</primary>
	<secondary>vec_mergeh</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrglh</primary>
	<secondary>vec_mergeh</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrghh</primary>
	<secondary>vec_mergeh</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mergeh</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
 vmrglb r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
 vmrglb r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vmrglb r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
 vmrglh r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 vmrglh r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
 vmrglh r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector pixel</para>
              </entry>
              <entry>
                <programlisting>
 vmrglh r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
 vmrglw r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vmrglw r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vmrglw r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
 vmrglw r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrghw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,0
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mergel">
      <title>vec_mergel</title>
      <subtitle>Vector Merge Low</subtitle>
      <programlisting>
      r = vec_mergel (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Merges the last halves (in element order) of two vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let
      <emphasis>m</emphasis> be the number of elements in <emphasis
      role="bold">r</emphasis>.  The <emphasis>n</emphasis>th element of
      <emphasis role="bold">r</emphasis>, if <emphasis>n</emphasis> is an even
      number, is given the value of the <emphasis>m</emphasis>/2 +
      (<emphasis>n</emphasis>/2)th element of <emphasis
      role="bold">a</emphasis>.  The (<emphasis>n</emphasis>+1)th element
      of <emphasis role="bold">r</emphasis>, if <emphasis>n</emphasis> is an
      even number, is given the value of the <emphasis>m</emphasis>/2 +
      (<emphasis>n</emphasis>/2)th element of <emphasis
      role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vmrghb</primary>
	<secondary>vec_mergel</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrglb</primary>
	<secondary>vec_mergel</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrghw</primary>
	<secondary>vec_mergel</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrglw</primary>
	<secondary>vec_mergel</secondary>
      </indexterm>
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_mergel</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrghh</primary>
	<secondary>vec_mergel</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrglh</primary>
	<secondary>vec_mergel</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mergel</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
 vmrghb r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
 vmrghb r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vmrghb r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
 vmrghh r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 vmrghh r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglh r,a,b
		</programlisting>
              </entry>
	    </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
 vmrghh r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector pixel</para>
              </entry>
              <entry>
                <programlisting>
 vmrghh r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
 vmrghw r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vmrghw r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vmrghw r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,0
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,3
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,0
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,3
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,0
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,3
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
 vmrghw r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrglw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,0
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,3
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mergeo">
      <title>vec_mergeo</title>
      <subtitle>Vector Merge Odd</subtitle>
      <programlisting>
      r = vec_mergeo (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Merges the odd-numbered values from two vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The odd-numbered
      elements of <emphasis role="bold">a</emphasis> are stored into the
      even-numbered elements of <emphasis role="bold">r</emphasis>. The
      odd-numbered elements of <emphasis role="bold">b</emphasis> are stored
      into the odd-numbered elements of <emphasis
      role="bold">r</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vmrgew</primary>
	<secondary>vec_mergeo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgow</primary>
	<secondary>vec_mergeo</secondary>
      </indexterm>
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_mergeo</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mergeo</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
 vmrgew r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrgow r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vmrgew r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrgow r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vmrgew r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrgow r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,0
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,3
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,0
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,3
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,0
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,3
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
 vmrgew r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmrgow r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,b,a,0
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,b,3
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mfvscr">
      <title>vec_mfvscr</title>
      <subtitle>Vector Move From Vector Status and Control Register</subtitle>
      <programlisting>
      r = vec_mfvscr ()
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Copies the contents of the Vector Status and Control Register
      (VSCR) into the result vector.
      </para>
      <para><emphasis role="bold">Result value:  </emphasis>The high-order 16
      bits of the VSCR are copied into the seventh element of <emphasis
      role="bold">r</emphasis>, using big-endian (left-to-right) order. The
      low-order 16 bits of the VSCR are copied into the eighth element of
      <emphasis role="bold">r</emphasis>, using big-endian order.  All other
      elements of <emphasis role="bold">r</emphasis> are set to zero.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The contents of the VSCR are placed in the low-order 32 bits of the
      result vector, regardless of endianness.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
        The use of <code>vector unsigned short</code> as the result
	type eases access to the two bits currently defined in the
	VSCR.  Following execution of <code>vec_mfvscr</code>,
	<emphasis role="bold">r</emphasis>[6] will contain
	VSCR<subscript>NJ</subscript> in the low-order bit, and
	<emphasis role="bold">r</emphasis>[7] will contain
	VSCR<subscript>SAT</subscript> in the low-order bit.
      </para>
      
      <indexterm>
	<primary>mfvscr</primary>
	<secondary>vec_mfvscr</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mfvscr</title>
      <tgroup cols="2">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  mfvscr  a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_min">
      <title>vec_min</title>
      <subtitle>Vector Minimum</subtitle>
      <programlisting>
      r = vec_min (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the minimum value from each set of
      corresponding elements of the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the minimum of the
      values of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vminsb</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>vminub</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>vminsw</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>vminuw</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>vminsd</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>vminud</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>vminsh</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>vminuh</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmindp</primary>
	<secondary>vec_min</secondary>
      </indexterm>
      <indexterm>
	<primary>xvminsp</primary>
	<secondary>vec_min</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_min</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vminsb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vminub  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vminsh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vminuh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vminsw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vminuw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vminsd  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vminud  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvminsp  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvmindp  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mradds">
      <title>vec_mradds</title>
      <subtitle>Vector Multiply-High Round and Add Saturated</subtitle>
      <programlisting>
      r = vec_mradds (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a saturated
      multiply-high-round-and-add operation for each corresponding set of
      elements of the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is produced as follows.
      The values of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> are
      multiplied and rounded such that the 15 least-significant bits are 0.
      The value of the 17 most-significant bits of this rounded product is
      then added, using 16-bit-saturated addition, to the value of the
      corresponding element of <emphasis role="bold">c</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vmhraddshs</primary>
	<secondary>vec_mradds</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mradds</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 vmhraddshs r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_msub">
      <title>vec_msub</title>
      <subtitle>Vector Multiply-Subtract</subtitle>
      <programlisting>
      r = vec_msub (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a multiply-subtract
      operation using the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is produced by multiplying the
      corresponding element of <emphasis role="bold">a</emphasis> by the
      corresponding element of <emphasis role="bold">b</emphasis> and then
      subtracting the corresponding element of <emphasis
      role="bold">c</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvmsubmdp</primary>
	<secondary>vec_msub</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmsubmsp</primary>
	<secondary>vec_msub</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_msub</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
 xvmsubmsp r/a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
 xvmsubmdp r/a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_msum">
      <title>vec_msum</title>
      <subtitle>Vector Multiply-Sum</subtitle>
      <programlisting>
      r = vec_msum (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a multiply-sum
      operation using the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
        There are two cases:
	<itemizedlist>
	  <listitem>
	    <para>
	      When <emphasis role="bold">a</emphasis> is of type
	      vector signed char or vector unsigned char, each word
	      element of <emphasis role="bold">r</emphasis> is
	      computed as follows:
	      <itemizedlist spacing="compact">
		<listitem>
		  <para>
		    Each of the four byte elements contained in the
		    corresponding word element of <emphasis
		    role="bold">a</emphasis> is multiplied by the
		    corresponding byte element of <emphasis
		    role="bold">b</emphasis>.
		  </para>
		</listitem>
		<listitem>
		  <para>
		    The sum of these four halfword products is added
		    to the corresponding word element in <emphasis
		    role="bold">c</emphasis> and placed in the
		    corresponding word element of <emphasis
		    role="bold">r</emphasis>.
		  </para>
		</listitem>
	      </itemizedlist>
	    </para>
	  </listitem>
	  <listitem>
	    <para>
	      When <emphasis role="bold">a</emphasis> is of type
	      vector signed short or vector unsigned short, each word
	      element of <emphasis role="bold">r</emphasis> is
	      computed as follows: 
	      <itemizedlist spacing="compact">
		<listitem>
		  <para>
		    Each of the two halfword elements contained in the
		    corresponding word element of <emphasis
		    role="bold">a</emphasis> is multiplied by the
		    corresponding halfword element of <emphasis
		    role="bold">b</emphasis>.
		  </para>
		</listitem>
		<listitem>
		  <para>
		    The sum of these two word products is added
		    to the corresponding word element in <emphasis
		    role="bold">c</emphasis> and placed in the
		    corresponding word element of <emphasis
		    role="bold">r</emphasis>.
		  </para>
		</listitem>
	      </itemizedlist>
	    </para>
	  </listitem>
	</itemizedlist>
	All operations are performed using 32-bit modular arithmetic.
      </para>

      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vmsummbm</primary>
	<secondary>vec_msum</secondary>
      </indexterm>
      <indexterm>
	<primary>vmsumshm</primary>
	<secondary>vec_msum</secondary>
      </indexterm>
      <indexterm>
	<primary>vmsumubm</primary>
	<secondary>vec_msum</secondary>
      </indexterm>
      <indexterm>
	<primary>vmsumuhm</primary>
	<secondary>vec_msum</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_msum</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vmsummbm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vmsumshm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vmsumubm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vmsumuhm r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_msums">
      <title>vec_msums</title>
      <subtitle>Vector Multiply-Sum Saturated</subtitle>
      <programlisting>
      r = vec_msums (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a saturated
      multiply-sum operation using the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Assume that the
      elements of each vector are numbered beginning with 0. The value of each
      element <emphasis>n</emphasis> of <emphasis role="bold">r</emphasis>
      is obtained as follows. For <emphasis>p</emphasis> =
      2<emphasis>n</emphasis> to 2<emphasis>n</emphasis>+1, multiply element
      <emphasis>p</emphasis> of <emphasis role="bold">a</emphasis> by element
      <emphasis>p</emphasis> of <emphasis role="bold">b</emphasis>. Add the
      sum of these products to element <emphasis>n</emphasis> of
      <emphasis role="bold">c</emphasis>. All additions are performed using
      32-bit saturated arithmetic.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vmsumshs</primary>
	<secondary>vec_msums</secondary>
      </indexterm>
      <indexterm>
	<primary>vmsumuhs</primary>
	<secondary>vec_msums</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_msums</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vmsumshs r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vmsumuhs r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mtvscr">
      <title>vec_mtvscr</title>
      <subtitle>Vector Move to Vector Status and Control Register</subtitle>
      <programlisting>
      vec_mtvscr (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Copies a value into the Vector Status and Control Register
      (VSCR).  The low-order 32 bits of <emphasis
      role="bold">a</emphasis> are copied into the VSCR.
      </para>

      <para><emphasis role="bold">Result value:</emphasis> None.</para>
      
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>mtvscr</primary>
	<secondary>vec_mtvscr</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mtvscr</title>
      <tgroup cols="2">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  mtvscr  a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mul">
      <title>vec_mul</title>
      <subtitle>Vector Multiply</subtitle>
      <programlisting>
      r = vec_mul (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
        Compute the products of corresponding elements of two vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> receives the product of
      the corresponding elements of <emphasis role="bold">a</emphasis> and
      <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis></para>
      <itemizedlist spacing="compact">
	<listitem>
	  <para>
	    The example implementation for vector char assumes that the
	    address of the permute control vector for the vperm instruction
	    is in a register identified by pcv.  Its value is
	    {1,17,3,19,5,21,7,23,9,25,11,27,13,29,15,31}.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    There are currently no vector instructions to support vector long
	    long multiplication, so the compiler must perform two scalar
	    multiplies on the vector elements for this case.
	  </para>
	</listitem>
      </itemizedlist>
      
      <indexterm>
	<primary>vmulesb</primary>
	<secondary>vec_mul</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulosb</primary>
	<secondary>vec_mul</secondary>
      </indexterm>
      <indexterm>
	<primary>lxvw4x</primary>
	<secondary>vec_mul</secondary>
      </indexterm>
      <indexterm>
	<primary>vperm</primary>
	<secondary>vec_mul</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuluwm</primary>
	<secondary>vec_mul</secondary>
      </indexterm>
      <indexterm>
	<primary>xxspltib</primary>
	<secondary>vec_mul</secondary>
      </indexterm>
      <indexterm>
	<primary>vmladduhm</primary>
	<secondary>vec_mul</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmuldp</primary>
	<secondary>vec_mul</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmulsp</primary>
	<secondary>vec_mul</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mul</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vmulesb  t,a,b
  vmulosb  u,a,b
  lxvw4x   v,0,pcv
  vperm    r,t,u,v
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vmulesb  t,a,b
  vmulosb  u,a,b
  lxvw4x   v,0,pcv
  vperm    r,t,u,v
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  xxspltib  t,0
  vmladduhm r,a,b,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxspltib  t,0
  vmladduhm r,a,b,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vmuluwm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vmuluwm r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  [scalarized]
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  [scalarized]
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvmulsp r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvmuldp r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mule">
      <title>vec_mule</title>
      <subtitle>Vector Multiply Even</subtitle>
      <programlisting>
      r = vec_mule (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Multiplies the even-numbered elements of the source vectors to
      produce the target vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element
      <emphasis>n</emphasis> of <emphasis role="bold">r</emphasis> is the
      product of element 2<emphasis>n</emphasis> of <emphasis
      role="bold">a</emphasis> and element 2<emphasis>n</emphasis> of
      <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vmulosh</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulesh</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulouh</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuleuh</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulosw</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulesw</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulouw</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuleuw</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulosb</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulesb</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuloub</primary>
	<secondary>vec_mule</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuleub</primary>
	<secondary>vec_mule</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mule</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
 vmulosb r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmulesb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vmuloub r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmuleub r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 vmulosh r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmulesh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
 vmulouh r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmuleuh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vmulosw r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmulesw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vmulouw r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmuleuw r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_mulo">
      <title>vec_mulo</title>
      <subtitle>Vector Multiply Odd</subtitle>
      <programlisting>
      r = vec_mulo (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Multiplies the odd-numbered elements of the source vectors to
      produce the target vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element
      <emphasis>n</emphasis> of <emphasis role="bold">r</emphasis> is the
      product of element 2<emphasis>n</emphasis>+1 of <emphasis
      role="bold">a</emphasis> and element 2<emphasis>n</emphasis>+1 of
      <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vmulesh</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulosh</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuleuh</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulouh</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulesw</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulosw</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuleuw</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulouw</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulesb</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmulosb</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuleub</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>
      <indexterm>
	<primary>vmuloub</primary>
	<secondary>vec_mulo</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_mulo</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
 vmulesb r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmulosb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vmuleub r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmuloub r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 vmulesh r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmulosh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
 vmuleuh r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmulouh r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vmulesw r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmulosw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vmuleuw r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vmulouw r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_nabs">
      <title>vec_nabs</title>
      <subtitle>Vector Negated Absolute Value</subtitle>
      <programlisting>
      r = vec_nabs (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the negated absolute values of the contents
      of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the negated absolute
      value of the corresponding element of <emphasis
      role="bold">a</emphasis>. For integer vectors, the arithmetic is
      modular.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsububm</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>vminsb</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuwm</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>vminsw</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubudm</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>vminsd</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuhm</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>vminsh</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnabsdp</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnabssp</primary>
	<secondary>vec_nabs</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_nabs</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw t,0
  vsububm  u,t,a
  vminsb   r,u,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw t,0
  vsubuhm  u,t,a
  vminsh   r,u,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw t,0
  vsubuwm  u,t,a
  vminsw   r,u,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw t,0
  vsubudm  u,t,a
  vminsd   r,u,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvnabssp  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvnabsdp  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_nand">
      <title>vec_nand</title>
      <subtitle>Vector NAND</subtitle>
      <programlisting>
      r = vec_nand (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bitwise NAND of two vectors.
      </para>
      <para><emphasis role="bold">Result value: r</emphasis> is the bitwise
      NAND of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxlnand</primary>
	<secondary>vec_nand</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_nand</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xxlnand  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>
    </simplesect>

    <?hard-pagebreak?>
    <simplesect xml:id="vec_ncipher_be">
      <title>vec_ncipher_be</title>
      <subtitle>Vector AES Inverse Cipher Big-Endian</subtitle>
      <programlisting>
      r = vec_ncipher_be (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs one round of the AES inverse cipher operation on an
      intermediate state array <emphasis role="bold">a</emphasis> by using a
      given round key <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Result value: r</emphasis> contains the
      resulting intermediate state, after one round of the AES inverse cipher
      operation on intermediate state array <emphasis role="bold">a</emphasis>,
      using the round key specified by <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Endian considerations:</emphasis>
      All element and bit numberings of the AES inverse cipher operation use
      big-endian (i.e., left-to-right) order, reflecting the underlying
      hardware insruction.  Unlike most of the vector intrinsics in this
      chapter, <code>vec_ncipher_be</code> does not follow the bi-endian
      programming model.
      </para>

      <indexterm>
	<primary>vncipher</primary>
	<secondary>vec_ncipher_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_ncipher_be</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vncipher  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_ncipherlast_be">
      <title>vec_ncipherlast_be</title>
      <subtitle>Vector AES Inverse Cipher Last Big-Endian</subtitle>
      <programlisting>
      r = vec_ncipherlast_be (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs the final round of the AES inverse cipher operation on an
      intermediate state array <emphasis role="bold">a</emphasis> using the
      specified round key <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Result value: r</emphasis> contains the
      resulting final state, after the final round of the AES inverse cipher
      operation on intermediate state array <emphasis role="bold">a</emphasis>,
      using the round key specified by <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Endian considerations:</emphasis>
      All element and bit numberings of the AES inverse cipher-last operation
      use big-endian (i.e., left-to-right) order, reflecting the underlying
      hardware insruction.  Unlike most of the vector intrinsics in this
      chapter, <code>vec_ncipherlast_be</code> does not follow the bi-endian
      programming model.
      </para>

      <indexterm>
	<primary>vncipherlast</primary>
	<secondary>vec_ncipherlast_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_ncipherlast_be</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vncipherlast  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_nearbyint">
      <title>vec_nearbyint</title>
      <subtitle>Vector Nearby Integer</subtitle>
      <programlisting>
      r = vec_nearbyint (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the floating-point integral values nearest to
      the values of the corresponding elements of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each
      element of <emphasis role="bold">r</emphasis> contains the
      nearest representable floating-point integral value to the value
      of the corresponding element of <emphasis
      role="bold">a</emphasis>. When an input element value is exactly
      between two integer values, the input value with the larger
      absolute value is selected.  The current floating-point rounding
      mode is ignored.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvrdpi</primary>
	<secondary>vec_nearbyint</secondary>
      </indexterm>
      <indexterm>
	<primary>xvrspi</primary>
	<secondary>vec_nearbyint</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_nearbyint</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvrspi  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvrdpi  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_neg">
      <title>vec_neg</title>
      <subtitle>Vector Negate</subtitle>
      <programlisting>
      r = vec_neg (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the negated values of the contents of the
      source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the negated value of
      the corresponding element of <emphasis role="bold">a</emphasis>. For
      integer vectors, the arithmetic is modular.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_neg</secondary>
      </indexterm>
      <indexterm>
	<primary>vsububm</primary>
	<secondary>vec_neg</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuwm</primary>
	<secondary>vec_neg</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubudm</primary>
	<secondary>vec_neg</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuhm</primary>
	<secondary>vec_neg</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnegdp</primary>
	<secondary>vec_neg</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnegsp</primary>
	<secondary>vec_neg</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_neg</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  t,0
  vsububm   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  t,0
  vsubuhm   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  t,0
  vsubuwm   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  t,0
  vsubudm   r,t,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvnegsp  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvnegdp  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_nmadd">
      <title>vec_nmadd</title>
      <subtitle>Vector Negated Multiply-Add</subtitle>
      <programlisting>
      r = vec_nmadd (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a negated
      multiply-add operation on the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the product of the
      corresponding elements of <emphasis role="bold">a</emphasis> and
      <emphasis role="bold">b</emphasis>, added to the corresponding elements
      of <emphasis role="bold">c</emphasis>, then multiplied by
      –1.0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvnmaddadp</primary>
	<secondary>vec_nmadd</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnmaddasp</primary>
	<secondary>vec_nmadd</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_nmadd</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvnmaddasp  r/c,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvnmaddadp  r/c,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_nmsub">
      <title>vec_nmsub</title>
      <subtitle>Vector Negated Multiply-Subtract</subtitle>
      <programlisting>
      r = vec_nmsub (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a negated
      multiply-subtract operation on the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the value of the
      corresponding element of <emphasis role="bold">c</emphasis> subtracted
      from the product of the corresponding elements of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>, and
      then multiplied by –1.0.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvnmsubmdp</primary>
	<secondary>vec_nmsub</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnmsubmsp</primary>
	<secondary>vec_nmsub</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_nmsub</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvnmsubmsp  r/a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvnmsubmdp  r/a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_nor">
      <title>vec_nor</title>
      <subtitle>Vector NOR</subtitle>
      <programlisting>
      r = vec_nor (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bitwise NOR of two vectors.
      </para>
      <para><emphasis role="bold">Result value: r</emphasis> is the bitwise NOR
      of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxlnor</primary>
	<secondary>vec_nor</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_nor</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xxlnor  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_or">
      <title>vec_or</title>
      <subtitle>Vector OR</subtitle>
      <programlisting>
      r = vec_or (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bitwise OR of two vectors.
      </para>
      <para><emphasis role="bold">Result value: r</emphasis> is the bitwise OR
      of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxlor</primary>
	<secondary>vec_or</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_or</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xxlor  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_orc">
      <title>vec_orc</title>
      <subtitle>Vector OR with Complement</subtitle>
      <programlisting>
      r = vec_orc (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bitwise OR of the first vector with the bitwise-complemented
      second vector.
      </para>
      <para><emphasis role="bold">Result value: r</emphasis> is the bitwise OR
      of <emphasis role="bold">a</emphasis> and the bitwise complement of
      <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxlorc</primary>
	<secondary>vec_orc</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_orc</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xxlorc  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_pack">
      <title>vec_pack</title>
      <subtitle>Vector Pack</subtitle>
      <programlisting>
      r = vec_pack (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Packs information from each element of two vectors into the result
      vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> represent the concatenation of vectors
      <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>.  For integer types, the value of each element
      of <emphasis role="bold">r</emphasis> is taken from the low-order half
      of the corresponding element of <emphasis role="bold">v</emphasis>. For
      floating-point types, the value of each element of <emphasis
      role="bold">r</emphasis> is the corresponding element of <emphasis
      role="bold">v</emphasis>, rounded to the result type.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vpkuhum</primary>
	<secondary>vec_pack</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkudum</primary>
	<secondary>vec_pack</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkuwum</primary>
	<secondary>vec_pack</secondary>
      </indexterm>
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_pack</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvdpsp</primary>
	<secondary>vec_pack</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgow</primary>
	<secondary>vec_pack</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgew</primary>
	<secondary>vec_pack</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_pack</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
 vpkuhum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkuhum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
 vpkuhum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkuhum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
 vpkuhum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkuhum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
 vpkuwum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkuwum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
 vpkuwum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkuwum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vpkuwum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkuwum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
 vpkudum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkudum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
 vpkudum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkudum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
 vpkudum r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkudum r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <programlisting>
 xxpermdi  t,b,a,0
 xxpermdi  u,b,a,3
 xvcvdpsp  t,t
 xvcvdpsp  u,u
 vmrgow    r,t,u
		</programlisting>
	      </entry>
              <entry align="center" valign="middle">
                <programlisting>
 xxpermdi  t,a,b,0
 xxpermdi  u,a,b,3
 xvcvdpsp  t,t
 xvcvdpsp  u,u
 vmrgew    r,t,u
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_pack_to_short_fp32">
      <title>vec_pack_to_short_fp32</title>
      <subtitle>Vector Pack 32-bit Float to Short</subtitle>
      <programlisting>
      r = vec_pack_to_short_fp32 (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Packs eight single-precision 32-bit floating-point numbers from two
      source vectors into a vector of eight 16-bit floating-point numbers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> represent the 16-element concatenation of
      <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>.  Each value of <emphasis
      role="bold">r</emphasis> contains the result of converting the
      corresponding single-precision element of <emphasis
      role="bold">v</emphasis> to half-precision.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vctuxs</primary>
	<secondary>vec_pack_to_short_fp32</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkswss</primary>
	<secondary>vec_pack_to_short_fp32</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_pack_to_short_fp32</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <colspec colname="c6" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
 vctuxs  t,a,0
 vctuxs  u,b,0
 vpkswss r,u,t
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vctuxs  t,a,0
 vctuxs  u,b,0
 vpkswss r,t,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_packpx">
      <title>vec_packpx</title>
      <subtitle>Vector Pack Pixel</subtitle>
      <programlisting>
      r = vec_packpx (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Packs information from each element of two vectors into the result
      vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> be the concatenation of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.  The
      value of each element of <emphasis role="bold">r</emphasis> is taken
      from the corresponding element of <emphasis role="bold">v</emphasis> as
      follows:</para>
      <itemizedlist spacing="compact">
        <listitem>
          <para>The least-significant bit of the high-order byte is
          stored into the first bit of the result element.</para>
        </listitem>
        <listitem>
          <para>The least-significant 5 bits of each of the remaining
          bytes are stored into the remaining portion of the result
          element.</para>
        </listitem>
      </itemizedlist>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vpkpx</primary>
	<secondary>vec_packpx</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_packpx</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vpkpx r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpkpx r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_packs">
     <title>vec_packs</title>
      <subtitle>Vector Pack Saturated</subtitle>
      <programlisting>
      r = vec_packs (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Packs information from each element of two vectors into the result
      vector, using saturated values.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> be the concatenation of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>. The
      value of each element of <emphasis role="bold">r</emphasis> is the
      saturated value of the corresponding element of <emphasis
      role="bold">v</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vpkshss</primary>
	<secondary>vec_packs</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkuhus</primary>
	<secondary>vec_packs</secondary>
      </indexterm>
      <indexterm>
	<primary>vpksdss</primary>
	<secondary>vec_packs</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkudus</primary>
	<secondary>vec_packs</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkswss</primary>
	<secondary>vec_packs</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkuwus</primary>
	<secondary>vec_packs</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_packs</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vpkshss  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkshss  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vpkuhus  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkuhus  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vpkswss  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkswss  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vpkuwus  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkuwus  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vpksdss  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpksdss  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vpkudus  r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkudus  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
         </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_packsu">
      <title>vec_packsu</title>
      <subtitle>Vector Pack Saturated Unsigned</subtitle>
      <programlisting>
      r = vec_packsu (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Packs information from each element of two vectors into the result
      vector, using unsigned saturated values.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> be the concatenation of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>. The
      value of each element of <emphasis role="bold">r</emphasis> is the
      saturated value of the corresponding element of <emphasis
      role="bold">v</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vpkshus</primary>
	<secondary>vec_packsu</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkuhus</primary>
	<secondary>vec_packsu</secondary>
      </indexterm>
      <indexterm>
	<primary>vpksdus</primary>
	<secondary>vec_packsu</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkudus</primary>
	<secondary>vec_packsu</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkswus</primary>
	<secondary>vec_packsu</secondary>
      </indexterm>
      <indexterm>
	<primary>vpkuwus</primary>
	<secondary>vec_packsu</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_packsu</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vpkshus r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkshus r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vpkuhus r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkuhus r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vpkswus r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkswus r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vpkuwus r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkuwus r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vpksdus r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpksdus r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vpkudus r,b,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vpkudus r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_parity_lsbb">
      <title>vec_parity_lsbb</title>
      <subtitle>Vector Parity over Least-Significant Bits of Bytes</subtitle>
      <programlisting>
      r = vec_parity_lsbb (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Compute parity on the least-significant bit of each byte.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains the parity computed over the
      low-order bit of each of the bytes in the corresponding element of
      <emphasis role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vprtybw</primary>
	<secondary>vec_parity_lsbb</secondary>
      </indexterm>
      <indexterm>
	<primary>vprtybq</primary>
	<secondary>vec_parity_lsbb</secondary>
      </indexterm>
      <indexterm>
	<primary>vprtybd</primary>
	<secondary>vec_parity_lsbb</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_parity_lsbb</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vprtybw  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vprtybw  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vprtybd  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vprtybd  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry>
                <programlisting>
  vprtybq  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry>
                <programlisting>
  vprtybq  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_perm">
      <title>vec_perm</title>
      <subtitle>Vector Permute</subtitle>
      <programlisting>
      r = vec_perm (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector that contains elements selected from two
      vectors, in the order specified by a third vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> be the concatenation of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.  Each
      byte of <emphasis role="bold">r</emphasis> selected by using the
      least-significant 5 bits of the corresponding byte of <emphasis
      role="bold">c</emphasis> as an index into <emphasis
      role="bold">v</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      <para><emphasis role="bold">Notes:</emphasis></para>
      <itemizedlist spacing="compact">
	<listitem>
	  <para>
	    The example little-endian code generation uses the <emphasis
	    role="bold">vpermr</emphasis> instruction from ISA 3.0.  For
	    earlier targets, the compiler must generate an extra instruction
	    to adjust the permute control vector <emphasis
	    role="bold">c</emphasis>.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    The <code>vec_perm</code> built-in should only use
	    permutations that reorder vector elements of the specified
	    type, not to reorder bytes within those elements.  The
	    results are not guaranteed to be consistent across big-
	    and little-endian if you violate this rule.  See <xref
	    linkend="VIPR.biendian.vperm" />.
	  </para>
	</listitem>
      </itemizedlist>
      
      <indexterm>
	<primary>vpermr</primary>
	<secondary>vec_perm</secondary>
      </indexterm>
      <indexterm>
	<primary>vperm</primary>
	<secondary>vec_perm</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_perm</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <colspec colname="c6" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 vpermr r,b,a,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vperm r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_permxor">
      <title>vec_permxor</title>
      <subtitle>Vector Permute and Exclusive-OR</subtitle>
      <programlisting>
      r = vec_permxor (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Applies a permute and exclusive-OR operation on two vectors of byte
      elements, with the selected elements identified by a third vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>For each
      <emphasis>i</emphasis> (0 ≤ <emphasis>i</emphasis> &lt; 16), let
      <emphasis>index1</emphasis> be bits 0–3 and
      <emphasis>index2</emphasis> be bits 4–7 of byte element
      <emphasis>i</emphasis> of <emphasis role="bold">c</emphasis>.  Byte
      element <emphasis>i</emphasis> of <emphasis role="bold">r</emphasis>
      is set to the exclusive-OR of byte elements <emphasis>index1</emphasis>
      of <emphasis role="bold">a</emphasis> and <emphasis>index2</emphasis>
      of <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xxlnor</primary>
	<secondary>vec_permxor</secondary>
      </indexterm>
      <indexterm>
	<primary>vpermxor</primary>
	<secondary>vec_permxor</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_permxor</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <colspec colname="c6" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example LE Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example BE Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
 xxlnor   t,c,c
 vpermxor r,a,b,t
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpermxor r,a,b,c

		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
 xxlnor   t,c,c
 vpermxor r,a,b,t
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpermxor r,a,b,c

		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
 xxlnor   t,c,c
 vpermxor r,a,b,t
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vpermxor r,a,b,c

		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_pmsum_be">
      <title>vec_pmsum_be</title>
      <subtitle>Vector Polynomial Multiply-Sum Big-Endian</subtitle>
      <programlisting>
      r = vec_pmsum_be (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs the exclusive-OR operation (implementing polynomial addition)
      on each even-odd pair of the polynomial-multiplication result of the
      corresponding elements of <emphasis role="bold">a</emphasis> and
      <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element
      <emphasis>i</emphasis> of <emphasis role="bold">r</emphasis> is
      computed by an exclusive-OR operation of the polynomial
      multiplication of input elements 2 &#x00d7; <emphasis>i</emphasis> of
      <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis> and input elements 2 &#x00d7;
      <emphasis>i</emphasis> + 1 of <emphasis role="bold">a</emphasis> and
      <emphasis role="bold">b</emphasis>.
      </para>
      
      <para><emphasis role="bold">Endian considerations:</emphasis>
      All element numberings in the above description denote big-endian
      (i.e., left-to-right) order, reflecting the underlying hardware
      insruction.  Unlike most of the vector intrinsics in this chapter,
      <code>vec_pmsum_be</code> does not follow the bi-endian
      programming model.
      </para>
      
      <indexterm>
	<primary>vpmsumh</primary>
	<secondary>vec_pmsum_be</secondary>
      </indexterm>
      <indexterm>
	<primary>vpmsumd</primary>
	<secondary>vec_pmsum_be</secondary>
      </indexterm>
      <indexterm>
	<primary>vpmsumw</primary>
	<secondary>vec_pmsum_be</secondary>
      </indexterm>
      <indexterm>
	<primary>vpmsumb</primary>
	<secondary>vec_pmsum_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_pmsum_be</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vpmsumb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vpmsumh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vpmsumw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vpmsumd  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_popcnt">
      <title>vec_popcnt</title>
      <subtitle>Vector Population Count</subtitle>
      <programlisting>
      r = vec_popcnt (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the number of bits set in each element of
      the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the number of bits set
      in the corresponding element of <emphasis
      role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vpopcntb</primary>
	<secondary>vec_popcnt</secondary>
      </indexterm>
      <indexterm>
	<primary>vpopcntw</primary>
	<secondary>vec_popcnt</secondary>
      </indexterm>
      <indexterm>
	<primary>vpopcntd</primary>
	<secondary>vec_popcnt</secondary>
      </indexterm>
      <indexterm>
	<primary>vpopcnth</primary>
	<secondary>vec_popcnt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_popcnt</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vpopcntb  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vpopcntb  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vpopcnth  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vpopcnth  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vpopcntw  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vpopcntw  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vpopcntd  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vpopcntd  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_re">
      <title>vec_re</title>
      <subtitle>Vector Reciprocal Estimate</subtitle>
      <programlisting>
      r = vec_re (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing estimates of the reciprocals of the
      corresponding elements of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains the estimated value of the
      reciprocal of the corresponding element of <emphasis
      role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
        For finite reciprocals, this intrinsic guarantees at least 14
	bits of accuracy.
      </para>
      
      <indexterm>
	<primary>xvredp</primary>
	<secondary>vec_re</secondary>
      </indexterm>
      <indexterm>
	<primary>xvresp</primary>
	<secondary>vec_re</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_re</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvresp  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvredp  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_recipdiv">
      <title>vec_recipdiv</title>
      <subtitle>Vector Reciprocal Divide</subtitle>
      <programlisting>
      r = vec_recipdiv (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing refined approximations of the
      division of the corresponding elements of <emphasis
      role="bold">a</emphasis> by the corresponding elements of
      <emphasis role="bold">b</emphasis>.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains a refined approximation of
      the division of the corresponding element of <emphasis
      role="bold">a</emphasis> by the corresponding element of <emphasis
      role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
        <itemizedlist spacing="compact">
	  <listitem>
	    <para>
	      The example implementation for vector double assumes
	      that a register <emphasis>z</emphasis> initially
	      contains the double-precision floating-point value 1.0
	      in each doubleword.
	    </para>
	  </listitem>
	  <listitem>
	    <para>
              For finite reciprocals, this intrinsic guarantees at
	      least 23 bits of accuracy for single-precision floating
	      point, and at least 52 bits of accuracy for
	      double-precision floating point.
	    </para>
	  </listitem>
	  <listitem>
	    <para>
	      This built-in function does not correspond to a single
	      IEEE operation and does not provide the overflow,
	      underflow, and NaN propagation characteristics specified
	      for IEEE division.
	    </para>
	  </listitem>
	</itemizedlist>
      </para>
      
      <indexterm>
	<primary>xvredp</primary>
	<secondary>vec_recipdiv</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnmsubadp</primary>
	<secondary>vec_recipdiv</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmaddmdp</primary>
	<secondary>vec_recipdiv</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmuldp</primary>
	<secondary>vec_recipdiv</secondary>
      </indexterm>
      <indexterm>
	<primary>xvresp</primary>
	<secondary>vec_recipdiv</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmulsp</primary>
	<secondary>vec_recipdiv</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnmsubasp</primary>
	<secondary>vec_recipdiv</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmaddmsp</primary>
	<secondary>vec_recipdiv</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_recipdiv</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvresp      t,b
  xvmulsp     u,a,t
  xvnmsubasp  r/a,b,u
  xvmaddmsp   r/a,t,u
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvredp      t,b
  xvnmsubadp  z,b,t
  xvmaddadp   u,z,t
  xvmuldp     v,a,u
  xvnmsubadp  r/a,b,v
  xvmaddmdp   r/a,u,v
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_revb">
      <title>vec_revb</title>
      <subtitle>Vector Reverse Bytes</subtitle>
      <programlisting>
      r = vec_revb (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Reverse the bytes of each vector element of a vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains the byte-reversed value of
      the corresponding element of <emphasis role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
      <itemizedlist spacing="compact">
	<listitem>
	  <para>
	    The examples shown are for ISA 3.0.  More complex sequences are
	    required for earlier ISA levels.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    Interfaces that make no change to the data are deprecated.
	  </para>
	</listitem>
      </itemizedlist>
      </para>
      
      <indexterm>
	<primary>xxbrw</primary>
	<secondary>vec_revb</secondary>
      </indexterm>
      <indexterm>
	<primary>xxbrq</primary>
	<secondary>vec_revb</secondary>
      </indexterm>
      <indexterm>
	<primary>xxbrd</primary>
	<secondary>vec_revb</secondary>
      </indexterm>
      <indexterm>
	<primary>xxbrh</primary>
	<secondary>vec_revb</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_revb</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example ISA 3.0 Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  [none]
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>Deprecated</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  [none]
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>Deprecated</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  [none]
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>Deprecated</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxbrh  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>Deprecated</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  xxbrh  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxbrh  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxbrw  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>Deprecated</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  xxbrw  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxbrw  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxbrd  r,a
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>Deprecated</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  xxbrd  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxbrd  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry>
                <programlisting>
  xxbrq  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry>
                <programlisting>
  xxbrq  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xxbrw  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xxbrd  r,a
		</programlisting>
              </entry>
              <entry>
                <para></para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_reve">
      <title>vec_reve</title>
      <subtitle>Vector Reverse Elements</subtitle>
      <programlisting>
      r = vec_reve (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Reverse the elements of a vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Returns a vector
      with the elements of the source vector in reversed order.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The vpermr instruction is most naturally used to implement this built-in
      function for a little-endian target, and the vperm instruction for a
      big-endian target.  This is not technically necessary, however, provided
      the correct permute control vector is used.  Note that use of vpermr
      requires ISA 3.0.
      </para>
      <para><emphasis role="bold">Notes:</emphasis> The example
      implementations assume that the permute control vector for the
      vperm or vpermr instruction is in a register identified by pcv.
      The value of pcv differs based on the element size, and is the
      same (in natural element order) for big- and little-endian,
      assuming the use of vperm for big-endian and vpermr for
      little-endian.
      </para>
      <informaltable>
	<tgroup cols="2">
          <colspec colname="c0" colwidth="10*" />
          <colspec colname="c1" colwidth="10*" />
	  <thead>
	    <row>
	      <entry align="center">
		<emphasis role="bold">Vector types</emphasis>
	      </entry>
	      <entry align="center">
		<emphasis role="bold">Permute control vector</emphasis>
	      </entry>
	    </row>
	  </thead>
	  <tbody>
	    <row>
	      <entry align="center">
		<para>
		  vector char
		</para>
	      </entry>
	      <entry align="center">
		<para>
		  { 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1,
		  0 }
		</para>
	      </entry>
	    </row>
	    <row>
	      <entry align="center">
		<para>
		  vector short
		</para>
	      </entry>
	      <entry align="center">
		<para>
		  { 14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0,
		  1 }
		</para>
	      </entry>
	    </row>
	    <row>
	      <entry align="center">
		<para>
		  vector int, vector float
		</para>
	      </entry>
	      <entry align="center">
		<para>
		  { 12, 13, 14, 15, 8, 9, 10, 11, 4, 5, 6, 7, 0, 1, 2,
		  3 }
		</para>
	      </entry>
	    </row>
	    <row>
	      <entry align="center">
		<para>
		  vector long long, vector double
		</para>
	      </entry>
	      <entry align="center">
		<para>
		  { 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6,
		  7 }
		</para>
	      </entry>
	    </row>
	  </tbody>
	</tgroup>
      </informaltable>
      
      <indexterm>
	<primary>vperm</primary>
	<secondary>vec_reve</secondary>
      </indexterm>
      <indexterm>
	<primary>vpermr</primary>
	<secondary>vec_reve</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_reve</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
	    </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  vperm[r]  r,a,a,pcv
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_rint">
      <title>vec_rint</title>
      <subtitle>Vector Round to Nearest Integer</subtitle>
      <programlisting>
      r = vec_rint (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the floating-point integral values nearest
      to the values of the corresponding elements of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains the nearest representable
      floating-point integral value to the value of the corresponding element
      of <emphasis role="bold">a</emphasis>. When an input element value is
      exactly between two integer values, the result value is selected based
      on the rounding mode specified by the Floating-Point Rounding Control
      field (RN) of the FPSCR register.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvrdpic</primary>
	<secondary>vec_rint</secondary>
      </indexterm>
      <indexterm>
	<primary>xvrspic</primary>
	<secondary>vec_rint</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_rint</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvrspic  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvrdpic  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_rl">
      <title>vec_rl</title>
      <subtitle>Vector Rotate Left</subtitle>
      <programlisting>
      r = vec_rl (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Rotates each element of a vector left by a given number of bits.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is obtained by rotating the
      corresponding element of <emphasis role="bold">a</emphasis> left by the
      number of bits specified by the corresponding element of
      <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vrlb</primary>
	<secondary>vec_rl</secondary>
      </indexterm>
      <indexterm>
	<primary>vrlw</primary>
	<secondary>vec_rl</secondary>
      </indexterm>
      <indexterm>
	<primary>vrld</primary>
	<secondary>vec_rl</secondary>
      </indexterm>
      <indexterm>
	<primary>vrlh</primary>
	<secondary>vec_rl</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_rl</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vrlb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vrlb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vrlh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vrlh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vrlw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vrlw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vrld  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vrld  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_rlmi">
      <title>vec_rlmi</title>
      <subtitle>Vector Rotate Left then Mask Insert</subtitle>
      <programlisting>
      r = vec_rlmi (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Rotates each element of a vector left and inserts each element under
      a mask.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is obtained by rotating the
      corresponding element of vector <emphasis role="bold">b</emphasis> left
      and inserting it under mask into the corresponding element of
      <emphasis role="bold">a</emphasis>. Bits 11:15 of the corresponding
      element of <emphasis role="bold">c</emphasis> contain the mask
      beginning, bits 19:23 contain the mask end, and bits 27:31 contain the
      shift count.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The referenced bit numbers within the elements of <emphasis
      role="bold">c</emphasis> are in left-to-right order.
      </para>
      
      <indexterm>
	<primary>vrlwmi</primary>
	<secondary>vec_rlmi</secondary>
      </indexterm>
      <indexterm>
	<primary>vrldmi</primary>
	<secondary>vec_rlmi</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_rlmi</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <colspec colname="c6" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vrlwmi r/a,b,c
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vrldmi r/a,b,c
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_rlnm">
      <title>vec_rlnm</title>
      <subtitle>Vector Rotate Left then AND with Mask</subtitle>
      <programlisting>
      r = vec_rlnm (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Rotates each element of a vector left, then logically ANDs it with a
      mask.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">a</emphasis> is rotated left, then logically ANDed
      with a mask specified by <emphasis role="bold">b</emphasis> and
      <emphasis role="bold">c</emphasis>.</para>
      <para><emphasis role="bold">b</emphasis> contains the shift count for
      each element in the low-order byte, with other bytes zero.
      <emphasis role="bold">c</emphasis> contains the mask begin and mask end
      for each element, with the mask end in the low-order byte, the mask
      begin in the next higher byte, and other bytes zero.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_rlnm</secondary>
      </indexterm>
      <indexterm>
	<primary>vslw</primary>
	<secondary>vec_rlnm</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlor</primary>
	<secondary>vec_rlnm</secondary>
      </indexterm>
      <indexterm>
	<primary>vrlwnm</primary>
	<secondary>vec_rlnm</secondary>
      </indexterm>
      <indexterm>
	<primary>xxspltib</primary>
	<secondary>vec_rlnm</secondary>
      </indexterm>
      <indexterm>
	<primary>vextsb2d</primary>
	<secondary>vec_rlnm</secondary>
      </indexterm>
      <indexterm>
	<primary>vsld</primary>
	<secondary>vec_rlnm</secondary>
      </indexterm>
      <indexterm>
	<primary>vrldnm</primary>
	<secondary>vec_rlnm</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_rlnm</title>
      <tgroup cols="6">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <colspec colname="c6" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
 vspltisw t,8
 vslw     u,b,t
 xxlor    v,u,c
 vrlwnm   r,a,v
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
 xxspltib t,8
 vextsb2d u,t
 vsld     v,b,u
 xxlor    w,v,c
 vrldnm   r,a,w
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_round">
      <title>vec_round</title>
      <subtitle>Vector Round</subtitle>
      <programlisting>
      r = vec_round (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the rounded values of the corresponding
      elements of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains the value of the
      corresponding element of <emphasis role="bold">a</emphasis>, rounded
      to the nearest representable floating-point integer, using IEEE
      round-to-nearest rounding.  The current floating-point rounding
      mode is ignored.</para>
      <para><emphasis role="bold">Notes:</emphasis> This function might not
      follow the strict operation definition of the resolution of a tie during
      a round if the -qstrict=nooperationprecision compiler option is
      specified to the XLC compiler.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvrdpi</primary>
	<secondary>vec_round</secondary>
      </indexterm>
      <indexterm>
	<primary>vrfin</primary>
	<secondary>vec_round</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_round</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  vrfin  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvrdpi  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_rsqrt">
      <title>vec_rsqrt</title>
      <subtitle>Vector Reciprocal Square Root</subtitle>
      <programlisting>
      r = vec_rsqrt (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing a refined approximation of the reciprocal
      square roots of the corresponding elements of the source vector. This
      function provides an implementation-dependent greater precision than
      <emphasis role="bold">vec_rsqrte</emphasis>.</para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains a refined approximation of
      the reciprocal square root of the corresponding element of
      <emphasis role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
        <itemizedlist spacing="compact">
	  <listitem>
	    <para>
	      The example implementations assume that a register
	      <emphasis role="bold">h</emphasis> initially contains
	      the floating-point value 0.5 in each element (single- or
	      double-precision as appropriate).
	    </para>
	  </listitem>
	  <listitem>
	    <para>
              For finite square roots, this intrinsic guarantees at
	      least 23 bits of accuracy for single-precision floating
	      point, and at least 52 bits of accuracy for
	      double-precision floating point.
	    </para>
	  </listitem>
	</itemizedlist>
      </para>
      
      <indexterm>
	<primary>xvrsqrtedp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmuldp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlor</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnmsubadp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmaddadp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnmsubmdp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvadddp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvrsqrtesp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmulsp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvnmsubmsp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvmaddmsp</primary>
	<secondary>vec_rsqrt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_rsqrt</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvrsqrtesp  t,a
  xvmulsp     u,t,a
  xvmulsp     v,t,h
  xvnmsubmsp  v,u,h
  xvmaddmsp   r/v,t,t
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvrsqrtedp  t,a
  xvmuldp     u,t,a
  xvmuldp     v,t,h
  xxlor       w,h,h
  xvnmsubadp  w,u,v
  xvmaddadp   v,v,w
  xvmaddadp   u,u,w
  xvnmsubmdp  u,v,h
  xvmaddadp   v,v,u
  xvadddp     r,v,v
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_rsqrte">
      <title>vec_rsqrte</title>
      <subtitle>Vector Reciprocal Square Root Estimate</subtitle>
      <programlisting>
      r = vec_rsqrte (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing estimates of the reciprocal square roots of
      the corresponding elements of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains the estimated value of the
      reciprocal square root of the corresponding element of <emphasis
      role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
        For finite square roots, this intrinsic guarantees at least 14
	bits of accuracy.
      </para>
      
      <indexterm>
	<primary>xvrsqrtedp</primary>
	<secondary>vec_rsqrte</secondary>
      </indexterm>
      <indexterm>
	<primary>xvrsqrtesp</primary>
	<secondary>vec_rsqrte</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_rsqrte</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvrsqrtesp  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvrsqrtedp  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sbox_be">
      <title>vec_sbox_be</title>
      <subtitle>Vector AES SubBytes Big-Endian</subtitle>
      <programlisting>
      r = vec_sbox_be (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs the SubBytes operation, as defined in Federal Information
      Processing Standards FIPS-197, on a state_array contained in
      <emphasis role="bold">a</emphasis>.
      </para>

      <para><emphasis role="bold">Result value: r</emphasis> contains the
      result of the SubBytes operation, as defined in Federal Information
      Processing Standard FIPS-197, on the state array represented by
      <emphasis role="bold">a</emphasis>.</para>
      
      <para><emphasis role="bold">Endian considerations:</emphasis>
      All element numberings of the SubBytes operation use
      big-endian (i.e., left-to-right) order, reflecting the underlying
      hardware insruction.  Unlike most of the vector intrinsics in this
      chapter, <code>vec_sbox_be</code> does not follow the bi-endian
      programming model.
      </para>

      <indexterm>
	<primary>vsbox</primary>
	<secondary>vec_sbox_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sbox_be</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsbox  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sel">
      <title>vec_sel</title>
      <subtitle>Vector Select</subtitle>
      <programlisting>
      r = vec_sel (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector selecting bits from two source vectors
      depending on the corresponding bit values of a third source
      vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each bit of
      <emphasis role="bold">r</emphasis> has the value of the corresponding
      bit of <emphasis role="bold">a</emphasis> if the corresponding bit of
      <emphasis role="bold">c</emphasis> is 0. Otherwise, the bit of
      <emphasis role="bold">r</emphasis> has the value of the corresponding
      bit of <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxsel</primary>
	<secondary>vec_sel</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sel</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
	    </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxsel  r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_shasigma_be">
      <title>vec_shasigma_be</title>
      <subtitle>Vector SHA Sigma Big-Endian</subtitle>
      <programlisting>
      r = vec_shasigma_be (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a Secure Hash computation in accordance with Federal
      Information Processing Standards FIPS-180-3.
      </para>
      
      <para><emphasis role="bold">Result value:</emphasis> Each element of
      <emphasis role="bold">r</emphasis> contains the SHA256 or SHA512 hash
      as follows.
      </para>

      <para>The result of the SHA-256 function (<emphasis
      role="bold">r</emphasis>[<emphasis>i</emphasis>] for
      <emphasis>i</emphasis> = 0 to 3) is:</para>
      <itemizedlist>
	<listitem>
	  <para>
	    &#x03c3;0(<emphasis
	    role="bold">a</emphasis>[<emphasis>i</emphasis>]), if <emphasis
	    role="bold">b</emphasis> is 0 and bit <emphasis>i</emphasis> of
	    the 4-bit <emphasis role="bold">c</emphasis> is 0.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    &#x03c3;1(<emphasis
	    role="bold">a</emphasis>[<emphasis>i</emphasis>]), if <emphasis
	    role="bold">b</emphasis> is 0 and bit <emphasis>i</emphasis> of
	    the 4-bit <emphasis role="bold">c</emphasis> is 1.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    &#x03a3;0(<emphasis
	    role="bold">a</emphasis>[<emphasis>i</emphasis>]), if <emphasis
	    role="bold">b</emphasis> is nonzero and bit <emphasis>i</emphasis>
	    of the 4-bit <emphasis role="bold">c</emphasis> is 0.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    &#x03a3;1(<emphasis
	    role="bold">a</emphasis>[<emphasis>i</emphasis>]), if <emphasis
	    role="bold">b</emphasis> is nonzero and bit <emphasis>i</emphasis>
	    of the 4-bit <emphasis role="bold">c</emphasis> is 1.
	  </para>
	</listitem>
      </itemizedlist>

      <para>The result of the SHA-512 function (<emphasis
      role="bold">r</emphasis>[<emphasis>i</emphasis>] for
      <emphasis>i</emphasis> = 0 to 1) is:</para>
      <itemizedlist>
	<listitem>
	  <para>
	    &#x03c3;0(<emphasis
	    role="bold">a</emphasis>[<emphasis>i</emphasis>]), if <emphasis
	    role="bold">b</emphasis> is 0 and bit 2 &#x00d7;
	    <emphasis>i</emphasis> of the 4-bit <emphasis
	    role="bold">c</emphasis> is 0.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    &#x03c3;1(<emphasis
	    role="bold">a</emphasis>[<emphasis>i</emphasis>]), if <emphasis
	    role="bold">b</emphasis> is 0 and bit 2 &#x00d7;
	    <emphasis>i</emphasis> of the 4-bit <emphasis
	    role="bold">c</emphasis> is 1.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    &#x03a3;0(<emphasis
	    role="bold">a</emphasis>[<emphasis>i</emphasis>]), if <emphasis
	    role="bold">b</emphasis> is nonzero and bit 2 &#x00d7;
	    <emphasis>i</emphasis> of the 4-bit <emphasis
	    role="bold">c</emphasis> is 0.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    &#x03a3;1(<emphasis
	    role="bold">a</emphasis>[<emphasis>i</emphasis>]), if <emphasis
	    role="bold">b</emphasis> is nonzero and bit 2 &#x00d7;
	    <emphasis>i</emphasis> of the 4-bit <emphasis
	    role="bold">c</emphasis> is 1.
	  </para>
	</listitem>
      </itemizedlist>

      <para><emphasis role="bold">Endian considerations:</emphasis>
      All element numberings in the above description denote big-endian
      (i.e., left-to-right) order, reflecting the underlying hardware
      insruction.  Unlike most of the vector intrinsics in this chapter,
      <code>vec_pmsum_be</code> does not follow the bi-endian
      programming model.
      </para>
      
      <indexterm>
	<primary>vshasigmaw</primary>
	<secondary>vec_shasigma_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_shasigma_be</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>const int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vshasigmaw  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>const int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vshasigmaw  r,a,b,d
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_signed">
      <title>vec_signed</title>
      <subtitle>Vector Convert Floating-Point to Signed Integer</subtitle>
      <programlisting>
      r = vec_signed (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts a vector of floating-point numbers to a vector of signed
      integers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each
      element of <emphasis role="bold">r</emphasis> is obtained by
      truncating the corresponding element of <emphasis
      role="bold">a</emphasis> to a signed integer.  The current
      floating-point rounding mode is ignored.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcvspsxws</primary>
	<secondary>vec_signed</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvdpsxds</primary>
	<secondary>vec_signed</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_signed</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcvspsxws  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcvdpsxds  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_signed2">
      <title>vec_signed2</title>
      <subtitle>Vector Convert Double-Precision to Signed Word</subtitle>
      <programlisting>
      r = vec_signed2 (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts two vectors of double-precision floating-point numbers to a
      vector of signed 32-bit integers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> be the concatenation of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.  Each
      element of <emphasis role="bold">r</emphasis> is obtained by truncating
      the corresponding element of <emphasis role="bold">v</emphasis> to a
      signed 32-bit integer.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_signed2</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvdpsxws</primary>
	<secondary>vec_signed2</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgow</primary>
	<secondary>vec_signed2</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgew</primary>
	<secondary>vec_signed2</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_signed2</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi   t,b,a,3
 xxpermdi   u,b,a,0
 xvcvdpsxws v,t
 xvcvdpsxws w,u
 vmrgow     r,w,v
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi   t,a,b,0
 xxpermdi   u,a,b,3
 xvcvdpsxws v,t
 xvcvdpsxws w,u
 vmrgew     r,v,w
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_signede">
      <title>vec_signede</title>
      <subtitle>Vector Convert Double-Precision to Signed Word Even</subtitle>
      <programlisting>
      r = vec_signede (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts elements of a source vector to signed integers and stores
      them in the even-numbered elements of the result vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Element 0 of
      <emphasis role="bold">r</emphasis> contains element 0 of <emphasis
      role="bold">a</emphasis>, truncated to a signed integer.  Element 2 of
      <emphasis role="bold">r</emphasis> contains element 1 of <emphasis
      role="bold">a</emphasis>, truncated to a signed integer.  Elements 1 and
      3 of <emphasis role="bold">r</emphasis> are undefined.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xvcvdpsxws</primary>
	<secondary>vec_signede</secondary>
      </indexterm>
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_signede</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_signede</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcvdpsxws  t,a
  vsldoi      r,t,t,12
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xvcvdpsxws  t,a

		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_signedo">
      <title>vec_signedo</title>
      <subtitle>Vector Convert Double-Precision to Signed Word Odd</subtitle>
      <programlisting>
      r = vec_signedo (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts elements of a source vector to signed integers and stores them
      in the odd-numbered elements of the result vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Element 1 of
      <emphasis role="bold">r</emphasis> contains element 0 of <emphasis
      role="bold">a</emphasis>, truncated to a signed integer.  Element 3 of
      <emphasis role="bold">r</emphasis> contains element 1 of <emphasis
      role="bold">a</emphasis>, truncated to a signed integer.  Elements 0 and
      2 of <emphasis role="bold">r</emphasis> are undefined.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xvcvdpsxws</primary>
	<secondary>vec_signedo</secondary>
      </indexterm>
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_signedo</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_signedo</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcvdpsxws  r,a

		</programlisting>
              </entry>
              <entry>
                <programlisting>
  xvcvdpsxws  t,a
  vsldoi      r,t,t,12
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sl">
      <title>vec_sl</title>
      <subtitle>Vector Shift Left</subtitle>
      <programlisting>
      r = vec_sl (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a left shift for each element of a vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is the result of left-shifting the
      corresponding element of <emphasis role="bold">a</emphasis> by the
      number of bits specified by the corresponding element of <emphasis
      role="bold">b</emphasis>, modulo the number of bits in the element.
      Zeros are shifted in from the right.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vslb</primary>
	<secondary>vec_sl</secondary>
      </indexterm>
      <indexterm>
	<primary>vslw</primary>
	<secondary>vec_sl</secondary>
      </indexterm>
      <indexterm>
	<primary>vsld</primary>
	<secondary>vec_sl</secondary>
      </indexterm>
      <indexterm>
	<primary>vslh</primary>
	<secondary>vec_sl</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sl</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vslh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vslh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vslw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vslw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vsld  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vsld  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sld">
      <title>vec_sld</title>
      <subtitle>Vector Shift Left Double</subtitle>
      <programlisting>
      r = vec_sld (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Left shifts a double vector (that is, two concatenated vectors) by a
      given number of bytes. For vec_sld being performed on the vector bool
      and floating-point types, the result is undefined when the specified
      shift count is not a multiple of the element size.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Vector <emphasis
      role="bold">r</emphasis> receives the most-significant 16 bytes obtained
      by concatenating <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis> and shifting left by the number of bytes
      specified by <emphasis role="bold">c</emphasis>, which must be in the
      range 0–15.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      This intrinsic is <emphasis>not</emphasis> endian-neutral, so uses of
      vec_sld in big-endian code must be rewritten for little-endian targets.
      Historically, vec_sld could be used to shift by amounts not a multiple
      of the element size for most types, in which case the purpose of the
      shift is difficult to determine and difficult to automatically rewrite
      efficiently for little endian.  So the concatenation of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> is
      done in big-endian fashion (left to right), and the shift is always
      to the left.  This will generally produce surprising results for
      little-endian targets.  See also <xref
      linkend="VIPR.biendian.sld" />.
      </para>
      
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_sld</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sld</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>4-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi  r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sldw">
      <title>vec_sldw</title>
      <subtitle>Vector Shift Left Double by Words</subtitle>
      <programlisting>
      r = vec_sldw (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector obtained by shifting left the concatenated source
      vectors by the number of specified words.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Vector <emphasis
      role="bold">r</emphasis> receives the most-significant 16 bytes obtained
      by concatenating <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis> and shifting left by the number of words
      specified by <emphasis role="bold">c</emphasis>, which must be in the
      range 0–3.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      This intrinsic is <emphasis>not</emphasis> endian-neutral, so uses of
      vec_sldw in big-endian code must be rewritten for little-endian targets.
      The concatenation of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis> is
      done in big-endian fashion (left to right), and the shift is always
      to the left.  This will generally produce surprising results for
      little-endian targets.
      </para>
      
      <indexterm>
	<primary>xxsldwi</primary>
	<secondary>vec_sldw</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sldw</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>2-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xxsldwi r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>2-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xxsldwi r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>2-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xxsldwi r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>2-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xxsldwi r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>2-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xxsldwi r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>2-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xxsldwi r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>2-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xxsldwi r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>2-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xxsldwi r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sll">
      <title>vec_sll</title>
      <subtitle>Vector Shift Left Long</subtitle>
      <programlisting>
      r = vec_sll (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Left shifts an entire vector by a given number of bits.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Vector
      <emphasis role="bold">r</emphasis> contains the contents of <emphasis
      role="bold">a</emphasis>, shifted left by the number of bits specified
      by the three least-significant bits of <emphasis
      role="bold">b</emphasis>. Zeros are supplied on the right. The shift
      count must have been replicated into all bytes of <emphasis
      role="bold">b</emphasis>; if not, the value of <emphasis
      role="bold">r</emphasis> is undefined.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      This intrinsic is <emphasis>not</emphasis> endian-neutral, so uses of
      vec_sll in big-endian code must be rewritten for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vsl</primary>
	<secondary>vec_sll</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sll</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsl  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_slo">
      <title>vec_slo</title>
      <subtitle>Vector Shift Left by Octets</subtitle>
      <programlisting>
      r = vec_slo (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Left shifts a vector by a given number of bytes (octets).
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Vector <emphasis
      role="bold">r</emphasis> receives the contents of <emphasis
      role="bold">a</emphasis>, shifted left by the number of bytes specified
      by bits 1:4 of the least-significant byte of <emphasis
      role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      This intrinsic is <emphasis>not</emphasis> endian-neutral, so uses of
      vec_slo in big-endian code must be rewritten for little-endian targets.
      The shift count is in element 15 of <emphasis role="bold">b</emphasis>
      for big-endian, but in element 0 of <emphasis role="bold">b</emphasis>
      for little-endian.
      </para>
      
      <indexterm>
	<primary>vslo</primary>
	<secondary>vec_slo</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_slo</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslo  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_slv">
      <title>vec_slv</title>
      <subtitle>Vector Shift Left Variable</subtitle>
      <programlisting>
      r = vec_slv (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Left-shifts a vector by a varying number of bits by element.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> be a 17-byte vector formed from <emphasis
      role="bold">a</emphasis> in bytes [0:15] and a zero byte in element 16.
      Then each byte element <emphasis>i</emphasis> of <emphasis
      role="bold">r</emphasis> is determined as follows.  The start bit
      <emphasis>sb</emphasis> is obtained from bits 5:7 of byte element
      <emphasis>i</emphasis> of <emphasis role="bold">b</emphasis>.  Then
      the contents of bits <emphasis>sb</emphasis>:<emphasis>sb+7</emphasis>
      of the halfword in byte elements
      <emphasis>i</emphasis>:<emphasis>i+1</emphasis> of <emphasis
      role="bold">v</emphasis> are placed into byte element
      <emphasis>i</emphasis> of <emphasis role="bold">r</emphasis>.</para>
      <para>An example follows:
      <informaltable frame="all">
      <tgroup cols="17">
          <colspec colname="c0" colwidth="10*" />
          <colspec colname="c1" colwidth="10*" />
          <colspec colname="c2" colwidth="10*" />
          <colspec colname="c3" colwidth="10*" />
          <colspec colname="c4" colwidth="10*" />
          <colspec colname="c5" colwidth="10*" />
          <colspec colname="c6" colwidth="10*" />
          <colspec colname="c7" colwidth="10*" />
          <colspec colname="c8" colwidth="10*" />
          <colspec colname="c9" colwidth="10*" />
          <colspec colname="c10" colwidth="10*" />
          <colspec colname="c11" colwidth="10*" />
          <colspec colname="c12" colwidth="10*" />
          <colspec colname="c13" colwidth="10*" />
          <colspec colname="c14" colwidth="10*" />
          <colspec colname="c15" colwidth="10*" />
          <colspec colname="c16" colwidth="10*" />
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para> <emphasis role="bold">a</emphasis> </para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para> <emphasis role="bold">b</emphasis> </para>
              </entry>
              <entry align="center" valign="middle">
                <para>00</para>
              </entry>
              <entry align="center" valign="middle">
                <para>01</para>
              </entry>
              <entry align="center" valign="middle">
                <para>02</para>
              </entry>
              <entry align="center" valign="middle">
                <para>03</para>
              </entry>
              <entry align="center" valign="middle">
                <para>04</para>
              </entry>
              <entry align="center" valign="middle">
                <para>05</para>
              </entry>
              <entry align="center" valign="middle">
                <para>06</para>
              </entry>
              <entry align="center" valign="middle">
                <para>07</para>
              </entry>
              <entry align="center" valign="middle">
                <para>08</para>
              </entry>
              <entry align="center" valign="middle">
                <para>09</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0A</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0B</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0C</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0D</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0E</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para> <emphasis role="bold">r</emphasis> </para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>1E</para>
              </entry>
              <entry align="center" valign="middle">
                <para>3C</para>
              </entry>
              <entry align="center" valign="middle">
                <para>78</para>
              </entry>
              <entry align="center" valign="middle">
                <para>F0</para>
              </entry>
              <entry align="center" valign="middle">
                <para>E1</para>
              </entry>
              <entry align="center" valign="middle">
                <para>C3</para>
              </entry>
              <entry align="center" valign="middle">
                <para>87</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>1E</para>
              </entry>
              <entry align="center" valign="middle">
                <para>3C</para>
              </entry>
              <entry align="center" valign="middle">
                <para>78</para>
              </entry>
              <entry align="center" valign="middle">
                <para>F0</para>
              </entry>
              <entry align="center" valign="middle">
                <para>E1</para>
              </entry>
              <entry align="center" valign="middle">
                <para>C3</para>
              </entry>
              <entry align="center" valign="middle">
                <para>80</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </informaltable>
      </para>

      <para><emphasis role="bold">Endian considerations:</emphasis>
      All bit and byte element numbers are specified in big-endian order.
      This intrinsic is <emphasis>not</emphasis> endian-neutral.
      </para>
      
      <indexterm>
	<primary>vslv</primary>
	<secondary>vec_slv</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_slv</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vslv  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_splat">
      <title>vec_splat</title>
      <subtitle>Vector Splat</subtitle>
      <programlisting>
      r = vec_splat (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector that has all of its elements set to a given value.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the value of the
      element of <emphasis role="bold">a</emphasis> specified by <emphasis
      role="bold">b</emphasis>, which must be an element number less than the
      number of elements supported for <emphasis role="bold">a</emphasis>'s
      type.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>

      <indexterm>
	<primary>vspltb</primary>
	<secondary>vec_splat</secondary>
      </indexterm>
      <indexterm>
	<primary>xxspltw</primary>
	<secondary>vec_splat</secondary>
      </indexterm>
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_splat</secondary>
      </indexterm>
      <indexterm>
	<primary>vsplth</primary>
	<secondary>vec_splat</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_splat</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="17*" />
          <colspec colname="c4" colwidth="26*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 vspltb r,a,15-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vspltb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 vspltb r,a,15-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vspltb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 vspltb r,a,15-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vspltb r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 vsplth r,a,7-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vsplth r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 vsplth r,a,7-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vsplth r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 vsplth r,a,7-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vsplth r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 vsplth r,a,7-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 vsplth r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 xxspltw r,a,3-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 xxspltw r,a,3-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 xxspltw r,a,3-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,a,(1-b)*3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,a,(1-b)*3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,a,(1-b)*3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 xxspltw r,a,3-b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxspltw r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> const int</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,a,(1-b)*3
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi r,a,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_splat_s8">
      <title>vec_splat_s8</title>
      <subtitle>Vector Splat to Signed Byte</subtitle>
      <programlisting>
      r = vec_splat_s8 (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector with all elements equal to the given value.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      Each element of <emphasis role="bold">r</emphasis> is given the
      sign-extended 5-bit value of <emphasis role="bold">a</emphasis>.
      The range of this value is [-16:15].</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisb</primary>
	<secondary>vec_splat_s8</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_splat_s8</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>5-bit signed literal</para>
              </entry>
              <entry>
                <programlisting>
  vspltisb  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_splat_s16">
      <title>vec_splat_s16</title>
      <subtitle>Vector Splat to Signed Halfword</subtitle>
      <programlisting>
      r = vec_splat_s16 (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector with all elements equal to the given value.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      Each element of <emphasis role="bold">r</emphasis> is given the
      sign-extended 5-bit value of <emphasis role="bold">a</emphasis>.
      The range of this value is [-16:15].</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltish</primary>
	<secondary>vec_splat_s16</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_splat_s16</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>5-bit signed literal</para>
              </entry>
              <entry>
                <programlisting>
  vspltish  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_splat_s32">
      <title>vec_splat_s32</title>
      <subtitle>Vector Splat to Signed Word</subtitle>
      <programlisting>
      r = vec_splat_s32 (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector with all elements equal to the given value.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      Each element of <emphasis role="bold">r</emphasis> is given the
      sign-extended 5-bit value of <emphasis role="bold">a</emphasis>.
      The range of this value is [-16:15].</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_splat_s32</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_splat_s32</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>5-bit signed literal</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_splat_u8">
      <title>vec_splat_u8</title>
      <subtitle>Vector Splat to Unsigned Byte</subtitle>
      <programlisting>
      r = vec_splat_u8 (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector with all elements equal to the given value.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      The 5-bit signed value of <emphasis role="bold">a</emphasis> is
      sign-extended to a byte and the resulting value is cast to an
      unsigned char.  This value is placed in each element of
      <emphasis role="bold">r</emphasis>.  The range of the original value is
      [-16:15].</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisb</primary>
	<secondary>vec_splat_u8</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_splat_u8</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>5-bit signed literal</para>
              </entry>
              <entry>
                <programlisting>
  vspltisb  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_splat_u16">
      <title>vec_splat_u16</title>
      <subtitle>Vector Splat to Unsigned Halfword</subtitle>
      <programlisting>
      r = vec_splat_u16 (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector with all elements equal to the given value.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      The 5-bit signed value of <emphasis role="bold">a</emphasis> is
      sign-extended to a halfword and the resulting value is cast to an
      unsigned short.  This value is placed in each element of
      <emphasis role="bold">r</emphasis>.  The range of the original value is
      [-16:15].</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltish</primary>
	<secondary>vec_splat_u16</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_splat_u16</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>5-bit signed literal</para>
              </entry>
              <entry>
                <programlisting>
  vspltish  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_splat_u32">
      <title>vec_splat_u32</title>
      <subtitle>Vector Splat to Unsigned Word</subtitle>
      <programlisting>
      r = vec_splat_u32 (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector with all elements equal to the given value.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      The 5-bit signed value of <emphasis role="bold">a</emphasis> is
      sign-extended to a word and the resulting value is cast to an
      unsigned int.  This value is placed in each element of
      <emphasis role="bold">r</emphasis>.  The range of the original value is
      [-16:15].</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_splat_u32</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_splat_u32</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>5-bit signed literal</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_splats">
      <title>vec_splats</title>
      <subtitle>Vector Splat Scalar</subtitle>
      <programlisting>
      r = vec_splats (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector with the value of each element set to the value of
      the scalar input parameter.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is set to the value of <emphasis
      role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>rlwinm</primary>
	<secondary>vec_splats</secondary>
      </indexterm>
      <indexterm>
	<primary>mtvsrd</primary>
	<secondary>vec_splats</secondary>
      </indexterm>
      <indexterm>
	<primary>vspltb</primary>
	<secondary>vec_splats</secondary>
      </indexterm>
      <indexterm>
	<primary>mtvsrwz</primary>
	<secondary>vec_splats</secondary>
      </indexterm>
      <indexterm>
	<primary>xxspltw</primary>
	<secondary>vec_splats</secondary>
      </indexterm>
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_splats</secondary>
      </indexterm>
      <indexterm>
	<primary>vsplth</primary>
	<secondary>vec_splats</secondary>
      </indexterm>
      <indexterm>
	<primary>xxscvdpspn</primary>
	<secondary>vec_splats</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_splats</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char</para>
              </entry>
              <entry>
                <programlisting>
  rlwinm  t,a,0,0xff
  mtvsrd  u,t
  vspltb  r,u,7
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  rlwinm  t,a,0,0xff
  mtvsrd  u,t
  vspltb  r,u,7
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed short</para>
              </entry>
              <entry>
                <programlisting>
  rlwinm  t,a,0,0xffff
  mtvsrd  u,t
  vsplth  r,u,3
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  rlwinm  t,a,0,0xffff
  mtvsrd  u,t
  vsplth  r,u,3
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed int</para>
              </entry>
              <entry>
                <programlisting>
  mtvsrd  t,a
  vspltb  r,t,7
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  mtvsrd  t,a
  vspltb  r,t,7
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry>
                <programlisting>
  mtvsrd    t,a
  xxpermdi  r,t,t,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  mtvsrd    t,a
  xxpermdi  r,t,t,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed __int128</para>
              </entry>
              <entry>
                <programlisting>
  mtvsrwz  t,a
  xxspltw  r,t,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned __int128</para>
              </entry>
              <entry>
                <programlisting>
  mtvsrwz  t,a
  xxspltw  r,t,1
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>float</para>
              </entry>
              <entry>
                <programlisting>
  xxscvdpspn  t,a
  xxspltw     r,t,0
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>double</para>
              </entry>
              <entry>
                <programlisting>
  xxpermdi  r,a,a,0
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sqrt">
      <title>vec_sqrt</title>
      <subtitle>Vector Square Root</subtitle>
      <programlisting>
      r = vec_sqrt (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the square root of each element in the
      source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is the square root of the
      corresponding element of <emphasis role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvsqrtdp</primary>
	<secondary>vec_sqrt</secondary>
      </indexterm>
      <indexterm>
	<primary>xvsqrtsp</primary>
	<secondary>vec_sqrt</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sqrt</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvsqrtsp  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvsqrtdp  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sr">
      <title>vec_sr</title>
      <subtitle>Vector Shift Right</subtitle>
      <programlisting>
      r = vec_sr (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a logical right shift for each element of a vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is the result of logically
      right-shifting the corresponding element of <emphasis
      role="bold">a</emphasis> by the number of bits specified by the
      corresponding element of <emphasis role="bold">b</emphasis>, modulo the
      number of bits in the element. Zeros are shifted in from the
      left.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vsrb</primary>
	<secondary>vec_sr</secondary>
      </indexterm>
      <indexterm>
	<primary>vsrw</primary>
	<secondary>vec_sr</secondary>
      </indexterm>
      <indexterm>
	<primary>vsrd</primary>
	<secondary>vec_sr</secondary>
      </indexterm>
      <indexterm>
	<primary>vsrh</primary>
	<secondary>vec_sr</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sr</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsrb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsrb  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vsrh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vsrh  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vsrw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vsrw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vsrd  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vsrd  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sra">
      <title>vec_sra</title>
      <subtitle>Vector Shift Right Algebraic</subtitle>
      <programlisting>
      r = vec_sra (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs an algebraic right shift for each element of a vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is the result of algebraically
      right-shifting the corresponding element of <emphasis
      role="bold">a</emphasis> by the number of bits specified by the
      corresponding element of <emphasis role="bold">b</emphasis>, modulo the
      number of bits in the element. Copies of the sign bit are shifted in
      from the left.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vsrab</primary>
	<secondary>vec_sra</secondary>
      </indexterm>
      <indexterm>
	<primary>vsraw</primary>
	<secondary>vec_sra</secondary>
      </indexterm>
      <indexterm>
	<primary>vsrad</primary>
	<secondary>vec_sra</secondary>
      </indexterm>
      <indexterm>
	<primary>vsrah</primary>
	<secondary>vec_sra</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sra</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsrab  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsrab  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vsrah  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vsrah  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vsraw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vsraw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vsrad  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vsrad  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_srl">
      <title>vec_srl</title>
      <subtitle>Vector Shift Right Long</subtitle>
      <programlisting>
      r = vec_srl (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Right shifts a vector by a given number of bits.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Vector <emphasis
      role="bold">r</emphasis> contains the contents of <emphasis
      role="bold">a</emphasis>, shifted right by the number of bits specified
      by the 3 least-significant bits of <emphasis role="bold">b</emphasis>.
      Zeros are supplied on the left. The shift count must have been
      replicated into all bytes of <emphasis role="bold">b</emphasis>; if not,
      the value of <emphasis role="bold">r</emphasis> is undefined.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      This intrinsic is <emphasis>not</emphasis> endian-neutral, so uses of
      vec_srl in big-endian code must be rewritten for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vsr</primary>
	<secondary>vec_srl</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_srl</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsr  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sro">
      <title>vec_sro</title>
      <subtitle>Vector Shift Right by Octets</subtitle>
      <programlisting>
      r = vec_sro (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Right shifts a vector by a given number of bytes (octets).
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Vector
      <emphasis role="bold">r</emphasis> receives the contents of
      <emphasis role="bold">a</emphasis>, shifted right by the number of bytes
      specified by bits 1–4 of the least-significant byte of
      <emphasis role="bold">b</emphasis>.
      Zeros are supplied from the left.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      This intrinsic is <emphasis>not</emphasis> endian-neutral, so uses of
      vec_sro in big-endian code must be rewritten for little-endian targets.
      The shift count is in element 15 of <emphasis role="bold">b</emphasis>
      for big-endian, but in element 0 of <emphasis role="bold">b</emphasis>
      for little-endian.  See also <xref linkend="VIPR.biendian.sld" />.
      </para>
      
      <indexterm>
	<primary>vsro</primary>
	<secondary>vec_sro</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sro</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsro  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_srv">
      <title>vec_srv</title>
      <subtitle>Vector Shift Right Variable</subtitle>
      <programlisting>
      r = vec_srv (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Right-shifts a vector by a varying number of bits by element.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> be a 17-byte vector formed from a zero byte
      in element 0 and the elements of <emphasis role="bold">a</emphasis>
      in bytes [1:16].  Then each byte element <emphasis>i</emphasis> of
      <emphasis role="bold">r</emphasis> is determined as follows.  The
      start bit <emphasis>sb</emphasis> is obtained from bits 5:7 of
      byte element <emphasis>i</emphasis> of <emphasis
      role="bold">b</emphasis>.  Then the contents of bits
      (8 &#8211; <emphasis>sb</emphasis>):(15 &#8211; <emphasis>sb</emphasis>) of the
      halfword in byte elements <emphasis>i</emphasis>:<emphasis>i</emphasis>+1
      of <emphasis role="bold">v</emphasis> are placed into byte element
      <emphasis>i</emphasis> of <emphasis role="bold">r</emphasis>.</para>
      <para>An example follows:
      <informaltable frame="all">
      <tgroup cols="17">
          <colspec colname="c0" colwidth="10*" />
          <colspec colname="c1" colwidth="10*" />
          <colspec colname="c2" colwidth="10*" />
          <colspec colname="c3" colwidth="10*" />
          <colspec colname="c4" colwidth="10*" />
          <colspec colname="c5" colwidth="10*" />
          <colspec colname="c6" colwidth="10*" />
          <colspec colname="c7" colwidth="10*" />
          <colspec colname="c8" colwidth="10*" />
          <colspec colname="c9" colwidth="10*" />
          <colspec colname="c10" colwidth="10*" />
          <colspec colname="c11" colwidth="10*" />
          <colspec colname="c12" colwidth="10*" />
          <colspec colname="c13" colwidth="10*" />
          <colspec colname="c14" colwidth="10*" />
          <colspec colname="c15" colwidth="10*" />
          <colspec colname="c16" colwidth="10*" />
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para> <emphasis role="bold">a</emphasis> </para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para> <emphasis role="bold">b</emphasis> </para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0E</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0D</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0C</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0B</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0A</para>
              </entry>
              <entry align="center" valign="middle">
                <para>09</para>
              </entry>
              <entry align="center" valign="middle">
                <para>08</para>
              </entry>
              <entry align="center" valign="middle">
                <para>07</para>
              </entry>
              <entry align="center" valign="middle">
                <para>06</para>
              </entry>
              <entry align="center" valign="middle">
                <para>05</para>
              </entry>
              <entry align="center" valign="middle">
                <para>04</para>
              </entry>
              <entry align="center" valign="middle">
                <para>03</para>
              </entry>
              <entry align="center" valign="middle">
                <para>02</para>
              </entry>
              <entry align="center" valign="middle">
                <para>01</para>
              </entry>
              <entry align="center" valign="middle">
                <para>00</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para> <emphasis role="bold">r</emphasis> </para>
              </entry>
              <entry align="center" valign="middle">
                <para>00</para>
              </entry>
              <entry align="center" valign="middle">
                <para>3C</para>
              </entry>
              <entry align="center" valign="middle">
                <para>78</para>
              </entry>
              <entry align="center" valign="middle">
                <para>F0</para>
              </entry>
              <entry align="center" valign="middle">
                <para>E1</para>
              </entry>
              <entry align="center" valign="middle">
                <para>C3</para>
              </entry>
              <entry align="center" valign="middle">
                <para>87</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
              <entry align="center" valign="middle">
                <para>1E</para>
              </entry>
              <entry align="center" valign="middle">
                <para>3C</para>
              </entry>
              <entry align="center" valign="middle">
                <para>78</para>
              </entry>
              <entry align="center" valign="middle">
                <para>F0</para>
              </entry>
              <entry align="center" valign="middle">
                <para>E1</para>
              </entry>
              <entry align="center" valign="middle">
                <para>C3</para>
              </entry>
              <entry align="center" valign="middle">
                <para>87</para>
              </entry>
              <entry align="center" valign="middle">
                <para>0F</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </informaltable>
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      All bit and byte element numbers are specified in big-endian order.
      This intrinsic is <emphasis>not</emphasis> endian-neutral.
      </para>
      
      <indexterm>
	<primary>vsrv</primary>
	<secondary>vec_srv</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_srv</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsrv  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_st">
      <title>vec_st</title>
      <subtitle>Vector Store Indexed</subtitle>
      <programlisting>
      vec_st (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Stores a 16-byte vector into memory at the address specified by a
      displacement and a pointer, ignoring the four low-order bits
      of the calculated address.
      </para>
      <para><emphasis role="bold">Operation: </emphasis>A memory address
      is obtained by adding <emphasis role="bold">b</emphasis> and <emphasis
      role="bold">c</emphasis>, and masking off the four low-order bits of the
      result.  The 16-byte vector in <emphasis role="bold">a</emphasis> is
      stored to the resultant memory address.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>stvx</primary>
	<secondary>vec_st</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_st</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example ISA 3.0
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double *</para>
              </entry>
              <entry>
                <programlisting>
  stvx  r,b,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_ste">
      <title>vec_ste</title>
      <subtitle>Vector Store Element Indexed</subtitle>
      <programlisting>
      vec_ste (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Stores a single element from a 16-byte vector into memory at the address
      specified by a displacement and a pointer, aligned to the element size.
      </para>
      <para><emphasis role="bold">Operation: </emphasis>The integer value
      <emphasis role="bold">b</emphasis> is added to the pointer value
      <emphasis role="bold">c</emphasis>.  The resulting address is rounded
      down to the nearest address that is a multiple of
      <emphasis>es</emphasis>, where <emphasis>es</emphasis> is 1 for char
      pointers, 2 for short pointers, and 4 for float or int pointers.
      An element offset <emphasis>eo</emphasis> is calculated by taking the
      resultant address modulo 16.  The vector element of <emphasis
      role="bold">a</emphasis> at offset <emphasis>eo</emphasis> is stored
      to the resultant address.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para>
	<emphasis role="bold">Notes:</emphasis>
	Be careful to note that the address (b+c) is aligned to an
	element boundary.  Do not attempt to store unaligned data with
	this intrinsic.
      </para>
      
      <indexterm>
	<primary>stvebx</primary>
	<secondary>vec_ste</secondary>
      </indexterm>
      <indexterm>
	<primary>stvewx</primary>
	<secondary>vec_ste</secondary>
      </indexterm>
      <indexterm>
	<primary>stvehx</primary>
	<secondary>vec_ste</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_ste</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example ISA 3.0
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stvebx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stvebx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stvebx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stvebx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stvehx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvehx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stvehx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvehx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvehx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stvewx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stvewx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stvewx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stvewx  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>float *</para>
              </entry>
              <entry>
                <programlisting>
  stvewx  r,b,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_stl">
      <title>vec_stl</title>
      <subtitle>Vector Store Indexed Least Recently Used</subtitle>
      <programlisting>
      vec_stl (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Stores a 16-byte vector into memory at the address specified by a
      displacement and a pointer, ignoring the four low-order bits
      of the calculated address, and marking the cache line containing
      the address as least frequently used.
      </para>
      <para><emphasis role="bold">Operation: </emphasis>A memory address
      is obtained by adding <emphasis role="bold">b</emphasis> and <emphasis
      role="bold">c</emphasis>, and masking off the four low-order bits of the
      result.  The 16-byte vector in <emphasis role="bold">a</emphasis> is
      stored to the resultant memory address, and the containing cache
      line is marked as least frequently used.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
        This intrinsic can be used to indicate the last	access to a
	portion of memory, as a hint to the data cache controller that
	the associated cache line can be replaced without performance
	loss.
      </para>
      
      <indexterm>
	<primary>stvxl</primary>
	<secondary>vec_stl</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_stl</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example ISA 3.0
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double *</para>
              </entry>
              <entry>
                <programlisting>
  stvxl  r,b,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sub">
      <title>vec_sub</title>
      <subtitle>Vector Subtract</subtitle>
      <programlisting>
      r = vec_sub (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the result of subtracting each element of
      one source vector from the corresponding element of another source
      vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the result of
      subtracting the value of the corresponding element of <emphasis
      role="bold">b</emphasis> from the value of the corresponding element of
      <emphasis role="bold">a</emphasis>. The arithmetic is modular for
      integer vectors.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vsububm</primary>
	<secondary>vec_sub</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuwm</primary>
	<secondary>vec_sub</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuqm</primary>
	<secondary>vec_sub</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubudm</primary>
	<secondary>vec_sub</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuhm</primary>
	<secondary>vec_sub</secondary>
      </indexterm>
      <indexterm>
	<primary>xvsubdp</primary>
	<secondary>vec_sub</secondary>
      </indexterm>
      <indexterm>
	<primary>xvsubsp</primary>
	<secondary>vec_sub</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sub</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsububm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsububm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vsubuhm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vsubuhm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vsubuwm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vsubuwm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  vsubudm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  vsubudm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed __int128</para>
              </entry>
              <entry>
                <programlisting>
  vsubuqm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned __int128</para>
              </entry>
              <entry>
                <programlisting>
  vsubuqm  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvsubsp  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvsubdp  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_subc">
      <title>vec_subc</title>
      <subtitle>Vector Subtract Carryout</subtitle>
      <programlisting>
      r = vec_subc (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector wherein each element contains the carry
      produced by subtracting the corresponding elements of the two
      source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the complement of the
      carry produced by subtracting the value of the corresponding element of
      <emphasis role="bold">b</emphasis> from the value of the corresponding
      element of <emphasis role="bold">a</emphasis>. The value is 0 if a
      borrow occurred, or 1 if no borrow occurred.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vsubcuw</primary>
	<secondary>vec_subc</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubcuq</primary>
	<secondary>vec_subc</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_subc</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vsubcuw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vsubcuw  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed __int128</para>
              </entry>
              <entry>
                <programlisting>
  vsubcuq  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned __int128</para>
              </entry>
              <entry>
                <programlisting>
  vsubcuq  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sube">
      <title>vec_sube</title>
      <subtitle>Vector Subtract Extended</subtitle>
      <programlisting>
      r = vec_sube (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the result of first elementwise subtracting
      one vector from another vector, and then elementwise adding a third
      carry vector. Elements of the carry vector have a value of 0 or 1.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">c'</emphasis> be a vector for which each element is 0 if
      the rightmost bit of the corresponding element of <emphasis
      role="bold">c</emphasis> is 0, and 1 otherwise. Then the value of each
      element of <emphasis role="bold">r</emphasis> is produced by subtracting
      the corresponding element of <emphasis role="bold">b</emphasis> from the
      corresponding element of <emphasis role="bold">a</emphasis>, and then
      adding the corresponding element of <emphasis role="bold">c'</emphasis>.
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
      Code generated for this intrinsic should ensure only the
      low-order bit of <emphasis role="bold">c</emphasis> participates
      in the sum.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_sube</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuwm</primary>
	<secondary>vec_sube</secondary>
      </indexterm>
      <indexterm>
	<primary>xxland</primary>
	<secondary>vec_sube</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubeuqm</primary>
	<secondary>vec_sube</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sube</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  t,1
  vsubuwm   u,a,b
  xxland    v,c,t
  vsubuwm   r,u,v
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  t,1
  vsubuwm   u,a,b
  xxland    v,c,t
  vsubuwm   r,u,v
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed __int128</para>
              </entry>
              <entry>
                <programlisting>
  vsubeuqm  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned __int128</para>
              </entry>
              <entry>
                <programlisting>
  vsubeuqm  r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_subec">
      <title>vec_subec</title>
      <subtitle>Vector Subtract Extended Carryout</subtitle>
      <programlisting>
      r = vec_subec (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the carries produced by subtracting one
      vector from another, then adding a third vector to the difference.  The
      third vector is a carry vector, with each element having a value of 0
      or 1.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the carry produced by
      subtracting the corresponding element of <emphasis
      role="bold">b</emphasis> from the corresponding element of <emphasis
      role="bold">a</emphasis>, and then adding the carry specified in the
      corresponding element of <emphasis role="bold">c</emphasis> (1 if there
      is a carry, 0 otherwise).</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis>
      Code generated for this intrinsic should ensure only the
      low-order bit of <emphasis role="bold">c</emphasis> participates
      in the sum.
      </para>
      
      <indexterm>
	<primary>vspltisw</primary>
	<secondary>vec_subec</secondary>
      </indexterm>
      <indexterm>
	<primary>xxland</primary>
	<secondary>vec_subec</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuwm</primary>
	<secondary>vec_subec</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubcuw</primary>
	<secondary>vec_subec</secondary>
      </indexterm>
      <indexterm>
	<primary>xxlor</primary>
	<secondary>vec_subec</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubecuq</primary>
	<secondary>vec_subec</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_subec</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  t,1
  xxland    u,c,t
  vsubuwm   v,a,b
  vsubcuw   w,a,b
  vsubcuw   x,v,u
  xxlor     r,w,x
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vspltisw  t,1
  xxland    u,c,t
  vsubuwm   v,a,b
  vsubcuw   w,a,b
  vsubcuw   x,v,u
  xxlor     r,w,x
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed __int128</para>
              </entry>
              <entry>
                <programlisting>
  vsubecuq  r,a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned __int128</para>
              </entry>
              <entry>
                <programlisting>
  vsubecuq  r,a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_subs">
      <title>vec_subs</title>
      <subtitle>Vector Subtract Saturated</subtitle>
      <programlisting>
      r = vec_subs (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the saturated differences of each set of
      corresponding elements of the source vectors.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of each
      element of <emphasis role="bold">r</emphasis> is the saturated result of
      subtracting the value of the corresponding element of <emphasis
      role="bold">b</emphasis> from the value of the corresponding element of
      <emphasis role="bold">a</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vsubsbs</primary>
	<secondary>vec_subs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsububs</primary>
	<secondary>vec_subs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubsws</primary>
	<secondary>vec_subs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuws</primary>
	<secondary>vec_subs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubshs</primary>
	<secondary>vec_subs</secondary>
      </indexterm>
      <indexterm>
	<primary>vsubuhs</primary>
	<secondary>vec_subs</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_subs</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vsubsbs  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  vsububs  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vsubshs  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  vsubuhs  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vsubsws  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vsubuws  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sum2s">
      <title>vec_sum2s</title>
      <subtitle>Vector Sum Across Half</subtitle>
      <programlisting>
      r = vec_sum2s (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a sum-across
      operation within each doubleword of the first source vector together with
      accumulated results in the second source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Elements 0 and 2
      of <emphasis role="bold">r</emphasis> are 0. Element 1 of <emphasis
      role="bold">r</emphasis> contains the saturated sum of elements 0 and 1
      of <emphasis role="bold">a</emphasis> and element 1 of <emphasis
      role="bold">b</emphasis>. Element 3 of <emphasis
      role="bold">r</emphasis> contains the saturated sum of elements 2 and 3
      of <emphasis role="bold">a</emphasis> and element 3 of <emphasis
      role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_sum2s</secondary>
      </indexterm>
      <indexterm>
	<primary>vsum2sws</primary>
	<secondary>vec_sum2s</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sum2s</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vsldoi    t,b,b,12
  vsum2sws  u,a,t
  vsldoi    r,u,u,4
		</programlisting>
              </entry>
              <entry>
                <programlisting>

  vsum2sws  r,a,b

		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sum4s">
      <title>vec_sum4s</title>
      <subtitle>Vector Sum Across Quarter</subtitle>
      <programlisting>
      r = vec_sum4s (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a sum-across
      operation within each word of the first source vector together with
      accumulated results in the second source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>
      There are two cases:
        <itemizedlist>
	  <listitem>
	    <para>
	      <emphasis role="bold">a</emphasis> is a vector of signed
	      or unsigned char.  For each element
	      <emphasis>n</emphasis> of the result vector, the value
	      is obtained by adding elements 4<emphasis>n</emphasis>
	      through 4<emphasis>n</emphasis> + 3 of <emphasis
	      role="bold">a</emphasis> and element
	      <emphasis>n</emphasis> of <emphasis
	      role="bold">b</emphasis> using saturated addition.
	    </para>
	  </listitem>
	  <listitem>
	    <para>
	      <emphasis role="bold">a</emphasis> is a vector of signed
	      short.  For each element <emphasis>n</emphasis> of the
	      result vector, the value is obtained by adding elements
	      2<emphasis>n</emphasis> and 2<emphasis>n</emphasis> + 1
	      of <emphasis role="bold">a</emphasis> and element
	      <emphasis>n</emphasis> of <emphasis
	      role="bold">b</emphasis> using saturated addition.
	    </para>
	  </listitem>
	</itemizedlist>
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>vsum4sbs</primary>
	<secondary>vec_sum4s</secondary>
      </indexterm>
      <indexterm>
	<primary>vsum4shs</primary>
	<secondary>vec_sum4s</secondary>
      </indexterm>
      <indexterm>
	<primary>vsum4ubs</primary>
	<secondary>vec_sum4s</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sum4s</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vsum4sbs  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  vsum4ubs  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vsum4shs  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_sums">
      <title>vec_sums</title>
      <subtitle>Vector Sum Across</subtitle>
      <programlisting>
      r = vec_sums (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the results of performing a sum-across
      operation on the first source vector together with accumulated results
      in the second source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Elements 0, 1, and 2
      of <emphasis role="bold">r</emphasis> are 0. Element 3 is the saturated
      sum of all the elements of <emphasis role="bold">a</emphasis> and
      element 3 of <emphasis role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>vspltw</primary>
	<secondary>vec_sums</secondary>
      </indexterm>
      <indexterm>
	<primary>vsumsws</primary>
	<secondary>vec_sums</secondary>
      </indexterm>
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_sums</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_sums</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vspltw   t,b,0
  vsumsws  u,a,t
  vsldoi   r,u,u,12
		</programlisting>
              </entry>
              <entry>
                <programlisting>

  vsumsws  r,a,b

		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_test_data_class">
      <title>vec_test_data_class</title>
      <subtitle>Vector Test Data Class</subtitle>
      <programlisting>
      r = vec_test_data_class (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Determines the data class for each floating-point element.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is set to all ones if the
      corresponding element of <emphasis role="bold">a</emphasis> matches one
      of the possible data types selected by <emphasis
      role="bold">b</emphasis>. If not, the element is set to all zeros.
      <emphasis role="bold">b</emphasis> can select one of the following data
      classes, or more than one of them by ORing the constants together.
      <programlisting>
  Not a number (NaN)       64
  Positive infinity        32
  Negative infinity        16
  Positive zero             8
  Negative zero             4
  Positive subnormal        2
  Negative subnormal        1
      </programlisting>
      </para>
      <para>
	For clarity of code, the following named constants are suggested.
	Preferably, compilers will provide these constants in a header
	file, but this is not required for compliance.
	<programlisting>
  #define __VEC_CLASS_FP_NAN          (1&lt;&lt;6)
  #define __VEC_CLASS_FP_INFINITY_P   (1&lt;&lt;5)
  #define __VEC_CLASS_FP_INFINITY_N   (1&lt;&lt;4)
  #define __VEC_CLASS_FP_ZERO_P       (1&lt;&lt;3)
  #define __VEC_CLASS_FP_ZERO_N       (1&lt;&lt;2)
  #define __VEC_CLASS_FP_SUBNORMAL_P  (1&lt;&lt;1)
  #define __VEC_CLASS_FP_SUBNORMAL_N  (1&lt;&lt;0)

  #define __VEC_CLASS_FP_INFINITY   (__VEC_CLASS_FP_INFINITY_P
                                     | __VEC_CLASS_FP_INFINITY_N)
  #define __VEC_CLASS_FP_ZERO       (__VEC_CLASS_FP_ZERO_P | __VEC_CLASS_FP_ZERO_N)
  #define __VEC_CLASS_FP_SUBNORMAL  (__VEC_CLASS_FP_SUBNORMAL_P
                                     | __VEC_CLASS_FP_SUBNORMAL_N)
  #define __VEC_CLASS_FP_NOT_NORMAL (__VEC_CLASS_FP_NAN | __VEC_CLASS_FP_SUBNORMAL
                                     | __VEC_CLASS_FP_ZERO | __VEC_CLASS_FP_INFINITY)
	</programlisting>
      </para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvtstdcsp</primary>
	<secondary>vec_test_data_class</secondary>
      </indexterm>
      <indexterm>
	<primary>xvtstdcdp</primary>
	<secondary>vec_test_data_class</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_test_data_class</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>7-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xvtstdcsp  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>7-bit unsigned literal</para>
              </entry>
              <entry>
                <programlisting>
  xvtstdcdp  r,a,b
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_trunc">
      <title>vec_trunc</title>
      <subtitle>Vector Truncate</subtitle>
      <programlisting>
      r = vec_trunc (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Returns a vector containing the truncated values of the corresponding
      elements of the source vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> contains the value of the
      corresponding element of <emphasis role="bold">a</emphasis>, truncated
      to an integral value.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvrdpiz</primary>
	<secondary>vec_trunc</secondary>
      </indexterm>
      <indexterm>
	<primary>xvrspiz</primary>
	<secondary>vec_trunc</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_trunc</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvrspiz  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvrdpiz  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_unpackh">
      <title>vec_unpackh</title>
      <subtitle>Vector Unpack High</subtitle>
      <programlisting>
      r = vec_unpackh (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Unpacks the most-significant (“high”) half of a vector into a vector
      with larger elements.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>If <emphasis
      role="bold">a</emphasis> is an integer vector, the value of each element
      of <emphasis role="bold">r</emphasis> is the value of the corresponding
      element of the most-significant half of <emphasis
      role="bold">a</emphasis>.</para>
      <para>If <emphasis role="bold">a</emphasis> is a floating-point vector,
      the value of each element of <emphasis role="bold">r</emphasis> is the
      value of the corresponding element of the most-significant half of
      <emphasis role="bold">a</emphasis>, widened to the result
      precision.</para>
      <para>If <emphasis role="bold">a</emphasis> is a pixel vector, the value
      of each element of <emphasis role="bold">r</emphasis> is taken from the
      corresponding element of the most-significant half of <emphasis
      role="bold">a</emphasis> as follows:</para>
      <itemizedlist spacing="compact">
        <listitem>
          <para>All bits in the first byte of the element of <emphasis
	  role="bold">r</emphasis> are set to the value of the first bit of
	  the element of <emphasis role="bold">a</emphasis>.</para>
        </listitem>
        <listitem>
          <para>The least-significant 5 bits of the second byte of the
          element of <emphasis role="bold">r</emphasis> are set to the value
	  of the next 5 bits in the element of <emphasis
	  role="bold">a</emphasis>.</para>
        </listitem>
        <listitem>
          <para>The least-significant 5 bits of the third byte of the
          element of <emphasis role="bold">r</emphasis> are set to the value
	  of the next 5 bits in the element of <emphasis
	  role="bold">a</emphasis>.</para>
        </listitem>
        <listitem>
          <para>The least-significant 5 bits of the fourth byte of the
          element of <emphasis role="bold">r</emphasis> are set to the value
	  of the next 5 bits in the element of <emphasis
	  role="bold">a</emphasis>.</para>
        </listitem>
      </itemizedlist>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The "high" half of a vector with <emphasis>n</emphasis> elements is the
      first <emphasis>n</emphasis>/2 elements of the vector.  For little
      endian, these elements are in the rightmost half of the vector.  For
      big endian, these elements are in the leftmost half of the vector.
      </para>
      
      <indexterm>
	<primary>vupklsh</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>vupkhsh</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>vupklpx</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>vupkhpx</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>vupklsw</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>vupkhsw</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>vupklsb</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>vupkhsb</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>xxsldwi</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvspdp</primary>
	<secondary>vec_unpackh</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_unpackh</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  vupklsb  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupkhsb  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vupklsb  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupkhsb  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  vupklsh  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupkhsh  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vupklsh  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupkhsh  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry>
                <programlisting>
  vupklpx  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupkhpx  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  vupklsw  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupkhsw  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vupklsw  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupkhsw  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
 xxsldwi  t,a,a,3
 xxsldwi  u,a,t,2
 xvcvspdp r,u
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxsldwi   t,a,a,1
 xxsldwi   u,t,a,3
 xvcvspdp  r,u
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_unpackl">
      <title>vec_unpackl</title>
      <subtitle>Vector Unpack Low</subtitle>
      <programlisting>
      r = vec_unpackl (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Unpacks the least-significant (“low”) half of a vector into a vector
      with larger elements.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>If <emphasis
      role="bold">a</emphasis> is an integer vector, the value of each element
      of <emphasis role="bold">r</emphasis> is the value of the corresponding
      element of the least-significant half of <emphasis
      role="bold">a</emphasis>.</para>
      <para>If <emphasis role="bold">a</emphasis> is a floating-point vector,
      the value of each element of <emphasis role="bold">r</emphasis> is the
      value of the corresponding element of the least-significant half of
      <emphasis role="bold">a</emphasis>, widened to the result
      precision.</para>
      <para>If <emphasis role="bold">a</emphasis> is a pixel vector, the value
      of each element of <emphasis role="bold">r</emphasis> is taken from the
      corresponding element of the least-significant half of <emphasis
      role="bold">a</emphasis> as follows:</para>
      <itemizedlist spacing="compact">
        <listitem>
          <para>All bits in the first byte of the element of <emphasis
	  role="bold">r</emphasis> are set to the value of the first bit of
	  the element of <emphasis role="bold">a</emphasis>.</para>
        </listitem>
        <listitem>
          <para>The least-significant 5 bits of the second byte of the
          element of <emphasis role="bold">r</emphasis> are set to the value
	  of the next 5 bits in the element of <emphasis
	  role="bold">a</emphasis>.</para>
        </listitem>
        <listitem>
          <para>The least-significant 5 bits of the third byte of the
          element of <emphasis role="bold">r</emphasis> are set to the value
	  of the next 5 bits in the element of <emphasis
	  role="bold">a</emphasis>.</para>
        </listitem>
        <listitem>
          <para>The least-significant 5 bits of the fourth byte of the
          element of <emphasis role="bold">r</emphasis> are set to the value
	  of the next 5 bits in the element of <emphasis
	  role="bold">a</emphasis>.</para>
        </listitem>
      </itemizedlist>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The "high" half of a vector with <emphasis>n</emphasis> elements is the
      first <emphasis>n</emphasis>/2 elements of the vector.  For little
      endian, these elements are in the rightmost half of the vector.  For
      big endian, these elements are in the leftmost half of the vector.
      </para>
      
      <indexterm>
	<primary>vupkhsh</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>vupklsh</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>vupkhpx</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>vupklpx</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>vupkhsw</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>vupklsw</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>vupkhsb</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>vupklsb</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>xxsldwi</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvspdp</primary>
	<secondary>vec_unpackl</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_unpackl</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">ARG1</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  vupkhsb  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupklsb  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  vupkhsb  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupklsb  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  vupkhsh  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupklsh  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  vupkhsh  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupklsh  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector pixel</para>
              </entry>
              <entry>
                <programlisting>
  vupkhpx  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupklpx  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  vupkhsw  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupklsw  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  vupkhsw  r,a
		</programlisting>
              </entry>
              <entry>
                <programlisting>
  vupklsw  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
 xxsldwi   t,a,a,1
 xxsldwi   u,t,a,3
 xvcvspdp  r,u
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxsldwi   t,a,a,3
 xxsldwi   u,a,t,2
 xvcvspdp  r,u
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_unsigned">
      <title>vec_unsigned</title>
      <subtitle>Vector Convert Floating-Point to Unsigned Integer</subtitle>
      <programlisting>
      r = vec_unsigned (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts a vector of floating-point numbers to a vector of unsigned
      integers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Each element of
      <emphasis role="bold">r</emphasis> is obtained by truncating the
      corresponding element of <emphasis role="bold">a</emphasis> to an
      unsigned integer.  The current floating-point rounding mode is
      ignored.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xvcvspsxws</primary>
	<secondary>vec_unsigned</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvdpsxds</primary>
	<secondary>vec_unsigned</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_unsigned</title>
      <tgroup cols="3">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <thead>
            <row>
              <entry align="center">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry>
                <programlisting>
  xvcvspsxws  r,a
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
  xvcvdpsxds  r,a
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_unsigned2">
      <title>vec_unsigned2</title>
      <subtitle>Vector Convert Double-Precision to Unsigned Word</subtitle>
      <programlisting>
      r = vec_unsigned2 (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts two vectors of double-precision floating-point numbers to a
      vector of unsigned 32-bit integers.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Let <emphasis
      role="bold">v</emphasis> be the concatenation of <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>.  Each
      element of <emphasis role="bold">r</emphasis> is obtained by truncating
      the corresponding element of <emphasis role="bold">v</emphasis> to an
      unsigned 32-bit integer.  The current floating-point rounding
      mode is ignored.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xxpermdi</primary>
	<secondary>vec_unsigned2</secondary>
      </indexterm>
      <indexterm>
	<primary>xvcvdpuxws</primary>
	<secondary>vec_unsigned2</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgow</primary>
	<secondary>vec_unsigned2</secondary>
      </indexterm>
      <indexterm>
	<primary>vmrgew</primary>
	<secondary>vec_unsigned2</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_unsigned2</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
 xxpermdi   t,b,a,3
 xxpermdi   u,b,a,0
 xvcvdpuxws v,t
 xvcvdpuxws w,u
 vmrgow     r,w,v
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xxpermdi   t,a,b,3
 xxpermdi   u,a,b,0
 xvcvdpuxws v,t
 xvcvdpuxws w,u
 vmrgew     r,v,w
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_unsignede">
      <title>vec_unsignede</title>
      <subtitle>Vector Convert Double-Precision to Unsigned Word
      Even</subtitle>
      <programlisting>
      r = vec_unsignede (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts elements of the source vector to unsigned integers and stores
      them in the even-numbered elements of the result vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Element 0 of
      <emphasis role="bold">r</emphasis> contains element 0 of <emphasis
      role="bold">a</emphasis>, truncated to an unsigned integer.  Element 2 of
      <emphasis role="bold">r</emphasis> contains element 1 of <emphasis
      role="bold">a</emphasis>, truncated to a signed integer.  Elements 1 and
      3 of <emphasis role="bold">r</emphasis> are undefined.  Truncation
      of a negative number to an unsigned integer results in a value of
      zero.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xvcvdpuxws</primary>
	<secondary>vec_unsignede</secondary>
      </indexterm>
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_unsignede</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_unsignede</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
 xvcvdpuxws t,a
 vsldoi     r,t,t,12
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xvcvdpuxws r,a

		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_unsignedo">
      <title>vec_unsignedo</title>
      <subtitle>Vector Convert Double-Precision to Unsigned Word Odd</subtitle>
      <programlisting>
      r = vec_unsignedo (a)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Converts elements of the source vector to unsigned integers and stores
      them in the odd-numbered elements of the result vector.
      </para>
      <para><emphasis role="bold">Result value: </emphasis> Element 1 of
      <emphasis role="bold">r</emphasis> contains element 0 of <emphasis
      role="bold">a</emphasis>, truncated to an unsigned integer.  Element 3 of
      <emphasis role="bold">r</emphasis> contains element 1 of <emphasis
      role="bold">a</emphasis>, truncated to an unsigned integer.  Elements 0
      and 2 of <emphasis role="bold">r</emphasis> are undefined.  Truncation
      of a negative number to an unsigned integer results in a value of
      zero.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      The element numbering within a register is left-to-right for big-endian
      targets, and right-to-left for little-endian targets.
      </para>
      
      <indexterm>
	<primary>xvcvdpuxws</primary>
	<secondary>vec_unsignedo</secondary>
      </indexterm>
      <indexterm>
	<primary>vsldoi</primary>
	<secondary>vec_unsignedo</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_unsignedo</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry>
                <programlisting>
 xvcvdpuxws r,a

		</programlisting>
              </entry>
              <entry>
                <programlisting>
 xvcvdpuxws t,a
 vsldoi     r,t,t,12
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xl">
      <title>vec_xl</title>
      <subtitle>VSX Unaligned Load</subtitle>
      <programlisting>
      r = vec_xl (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Loads a 16-byte vector from the memory address specified by the
      displacement and the pointer.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of
      <emphasis role="bold">r</emphasis> is obtained by adding <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>, then
      loading the 16-byte vector from the resultant memory address.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      For ISA 2.07, there is no bi-endian unaligned load instruction.
      For little-endian targets, it is necessary to use the lxvd2x instruction
      and swap the doublewords with an xxswapd instruction.  For big-endian
      targets, the lxvd2x instruction or lxvw4x instruction suffices.  The
      examples below assume ISA 3.0, where the bi-endian lxv instruction is
      available.
      </para>
      <para><emphasis role="bold">Notes:</emphasis></para>
      <itemizedlist>
	<listitem>
	  <para>
	    For languages that support built-in methods for pointer
	    dereferencing, such as the C/C++ * and [ ] operators, use
	    of the native operators is encouraged when the memory to
	    be accessed is aligned on a 32-bit boundary or aligned to
	    the type of <emphasis role="bold">b</emphasis>, whichever
	    is weaker.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    GCC provides a commonly used synonym for vec_xl called
	    vec_vsx_ld.  Although these have the same behavior, only
	    vec_xl is guaranteed to be portable across compliant
	    compilers.  Therefore vec_xl is preferred.
	  </para>
	</listitem>
      </itemizedlist>
      
      <indexterm>
	<primary>lxv</primary>
	<secondary>vec_xl</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xl</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center">
                <para><emphasis role="bold">Example ISA 3.0
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed __int128 *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned __int128 *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry>
                <programlisting>
  lxv  r,a(b)
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xl_be">
      <title>vec_xl_be</title>
      <subtitle>VSX Unaligned Load as Big Endian</subtitle>
      <programlisting>
      r = vec_xl_be (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Loads a vector from an address into a register in big-endian element
      order, regardless of the endianness of the target machine.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The value of
      <emphasis role="bold">r</emphasis> is obtained by adding <emphasis
      role="bold">a</emphasis> and <emphasis role="bold">b</emphasis>, then
      loading the vector elements from the resulting address in big-endian
      order.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      In big-endian mode, this acts just like the vec_xl intrinsic.
      In little-endian mode, the highest-numbered element of <emphasis
      role="bold">r</emphasis> is loaded from the lowest data address, and
      the lowest-numbered element of <emphasis role="bold">r</emphasis> from
      the highest data address.
      </para>
      
      <indexterm>
	<primary>lxvb16x</primary>
	<secondary>vec_xl_be</secondary>
      </indexterm>
      <indexterm>
	<primary>lxv</primary>
	<secondary>vec_xl_be</secondary>
      </indexterm>
      <indexterm>
	<primary>lxvw4x</primary>
	<secondary>vec_xl_be</secondary>
      </indexterm>
      <indexterm>
	<primary>lxvd2x</primary>
	<secondary>vec_xl_be</secondary>
      </indexterm>
      <indexterm>
	<primary>lxvh8x</primary>
	<secondary>vec_xl_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xl_be</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example ISA 3.0 LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example ISA 3.0 BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry>
                <programlisting>
 lxvb16x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
 lxvb16x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry>
                <programlisting>
 lxvh8x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
 lxvh8x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry>
                <programlisting>
 lxvw4x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
 lxvw4x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry>
                <programlisting>
 lxvd2x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
 lxvd2x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed __int128 *</para>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned __int128 *</para>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry>
                <programlisting>
 lxvw4x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry>
                <programlisting>
 lxvd2x r,a,b
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 lxv r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xl_len">
      <title>vec_xl_len</title>
      <subtitle>Vector Load with Length</subtitle>
      <programlisting>
      r = vec_xl_len (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Loads a vector of a specified byte length.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Loads the number of
      bytes specified by <emphasis role="bold">b</emphasis> from the address
      specified in <emphasis role="bold">a</emphasis>. Initializes elements in
      order from the byte stream (as defined by the endianness of the target).
      Any bytes of elements that cannot be initialized from the
      number of loaded bytes have a zero value.</para>
      <para>Between 0 and 16 bytes, inclusive, will be loaded. The length is
      specified by the least-significant byte of <emphasis
      role="bold">b</emphasis>, as <emphasis>min</emphasis> (<emphasis
      role="bold">b</emphasis> <emphasis>mod</emphasis> 256, 16). The behavior
      is undefined if the length argument is outside of
      the range 0–255, or if it is not a multiple of the vector element
      size.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis> vec_xl_len should
      not be used to load from cache-inhibited memory.</para>
      
      <indexterm>
	<primary>sldi</primary>
	<secondary>vec_xl_len</secondary>
      </indexterm>
      <indexterm>
	<primary>lxvl</primary>
	<secondary>vec_xl_len</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xl_len</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example
		Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed char *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed short *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned short *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed int *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned int *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed long long *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned long long *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>signed __int128 *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned __int128 *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>float *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>double *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lxvl  r,a,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xl_len_r">
      <title>vec_xl_len_r</title>
      <subtitle>Vector Load with Length Right-Justified</subtitle>
      <programlisting>
      r = vec_xl_len_r (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Loads a vector of a specified byte length, right-justified.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>Loads the number of
      bytes specified by <emphasis role="bold">b</emphasis> from the address
      specified in <emphasis role="bold">a</emphasis>, right justified in
      <emphasis role="bold">r</emphasis>. Initializes elements in order from
      the byte stream (as defined by the endianness of the target).
      Any bytes of elements that cannot be initialized from the
      number of loaded bytes have a zero value.</para>
      <para>Between 0 and 16 bytes, inclusive, will be loaded. The length
      is specified by the least-significant byte of <emphasis
      role="bold">b</emphasis>, as <emphasis>min</emphasis> (<emphasis
      role="bold">b</emphasis> <emphasis>mod</emphasis> 256, 16).  The
      behavior is undefined if the length argument is outside of the range
      0–255.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis> vec_xl_len_r should
      not be used to load from cache-inhibited memory.</para>
      
      <indexterm>
	<primary>sldi</primary>
	<secondary>vec_xl_len_r</secondary>
      </indexterm>
      <indexterm>
	<primary>lvsl</primary>
	<secondary>vec_xl_len_r</secondary>
      </indexterm>
      <indexterm>
	<primary>lxvll</primary>
	<secondary>vec_xl_len_r</secondary>
      </indexterm>
      <indexterm>
	<primary>vperm</primary>
	<secondary>vec_xl_len_r</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xl_len_r</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example
		Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>unsigned char *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi  t,b,56
  lvsl  u,0,b
  lxvll v,a,t
  vperm r,v,v,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xor">
      <title>vec_xor</title>
      <subtitle>Vector Exclusive OR</subtitle>
      <programlisting>
      r = vec_xor (a, b)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Performs a bitwise XOR of two vectors.
      </para>
      <para><emphasis role="bold">Result value: v</emphasis> is the bitwise
      exclusive OR of <emphasis role="bold">a</emphasis> and <emphasis
      role="bold">b</emphasis>.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      
      <indexterm>
	<primary>xxlxor</primary>
	<secondary>vec_xor</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xor</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">r</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool char</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed char</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned char</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool short</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed short</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned short</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool int</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed int</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned int</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector bool long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector bool long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector signed long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector unsigned long long</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector float</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> vector double</para>
              </entry>
              <entry>
                <programlisting>
  xxlxor  r,a,b
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xst">
      <title>vec_xst</title>
      <subtitle>VSX Unaligned Store</subtitle>
      <programlisting>
      vec_xst (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Stores a 16-byte value into memory at the address specified by the
      displacement and pointer.
      </para>
      <para><emphasis role="bold">Operation: </emphasis>The values of
      <emphasis role="bold">b</emphasis> and <emphasis
      role="bold">c</emphasis> are added, and the value of <emphasis
      role="bold">a</emphasis> is stored to the resultant address.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      For ISA 2.07, there is no bi-endian unaligned store instruction.  For
      little-endian targets, it is necessary to first swap the doublewords
      of the value to be stored using an xxswapd instruction, and then store
      the result using the stxvd2x instruction.  For big-endian targets, the
      stxvd2x or stxvw4x instruction suffices.  The examples below assume ISA
      3.0, where the bi-endian stxv instruction is available.
      </para>
      <para><emphasis role="bold">Notes:</emphasis></para>
      <itemizedlist>
	<listitem>
	  <para>
	    For languages that support built-in methods for pointer
	    dereferencing, such as the C/C++ * and [ ] operators, use
	    of the native operators is encouraged when the memory to
	    be accessed is aligned on a 32-bit boundary or aligned to
	    the type of <emphasis role="bold">b</emphasis>, whichever
	    is weaker.
	  </para>
	</listitem>
	<listitem>
	  <para>
	    GCC provides a commonly used synonym for vec_xst called
	    vec_vsx_st.  Although these have the same behavior, only
	    vec_xst is guaranteed to be portable across compliant
	    compilers.  Therefore vec_xst is preferred.
	  </para>
	</listitem>
      </itemizedlist>
      
      <indexterm>
	<primary>stxv</primary>
	<secondary>vec_xst</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xst</title>
      <tgroup cols="4">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example ISA 3.0
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed char *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed __int128 *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned __int128 *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry>
                <programlisting>
  stxv  a,b(c)
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xst_be">
      <title>vec_xst_be</title>
      <subtitle>VSX Unaligned Store as Big Endian</subtitle>
      <programlisting>
      vec_xst_be (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Stores a vector to an address using big-endian
      element order, regardless of the endianness of the target machine.
      </para>
      <para><emphasis role="bold">Result value: </emphasis>The values of
      <emphasis role="bold">b</emphasis> and <emphasis
      role="bold">c</emphasis> are added, and the value of <emphasis
      role="bold">a</emphasis> is stored to the resultant address using
      big-endian element order.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      In big-endian mode, this acts just like the vec_xst intrinsic.  In
      little-endian mode, the lowest data address receives the
      highest-numbered element of <emphasis role="bold">a</emphasis>, and
      the highest data address receives the lowest-numbered element of
      <emphasis role="bold">a</emphasis>.
      </para>
      
      <indexterm>
	<primary>stxvb16x</primary>
	<secondary>vec_xst_be</secondary>
      </indexterm>
      <indexterm>
	<primary>stxv</primary>
	<secondary>vec_xst_be</secondary>
      </indexterm>
      <indexterm>
	<primary>stxvw4x</primary>
	<secondary>vec_xst_be</secondary>
      </indexterm>
      <indexterm>
	<primary>stxvd2x</primary>
	<secondary>vec_xst_be</secondary>
      </indexterm>
      <indexterm>
	<primary>stxvh8x</primary>
	<secondary>vec_xst_be</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xst_be</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example ISA 3.0 LE
		Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example ISA 3.0 BE
		Implementation</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed char *</para>
              </entry>
              <entry>
                <programlisting>
 stxvb16x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry>
                <programlisting>
 stxvb16x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry>
                <programlisting>
 stxvh8x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry>
                <programlisting>
 stxvh8x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry>
                <programlisting>
 stxvw4x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry>
                <programlisting>
 stxvw4x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry>
                <programlisting>
 stxvd2x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry>
                <programlisting>
 stxvd2x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed __int128 *</para>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned __int128 *</para>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry>
                <programlisting>
 stxvw4x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry>
                <programlisting>
 stxvd2x a,b,c
		</programlisting>
              </entry>
              <entry>
                <programlisting>
 stxv a,b,c
		</programlisting>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xst_len">
      <title>vec_xst_len</title>
      <subtitle>Vector Store with Length</subtitle>
      <programlisting>
      vec_xst_len (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Stores a vector of a specified byte length.
      </para>
      <para><emphasis role="bold">Operation: </emphasis>Stores the number of
      bytes specified by <emphasis role="bold">c</emphasis> of the vector
      <emphasis role="bold">a</emphasis> to the address specified in
      <emphasis role="bold">b</emphasis>. The bytes are obtained starting from
      the lowest-numbered byte of the lowest-numbered element (as defined by
      the endianness of the target). All bytes of an element
      are accessed before proceeding to the next higher element.</para>
      <para>Between 0 and 16 bytes, inclusive, will be stored. The length
      is specified by the least-significant byte of <emphasis
      role="bold">c</emphasis>, as <emphasis>min</emphasis> (<emphasis
      role="bold">c</emphasis> <emphasis>mod</emphasis> 256, 16). The behavior
      is undefined if the length argument is outside of the range 0–255,
      or if it is not a multiple of the vector element size.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis> vec_xst_len should
      not be used to store to cache-inhibited memory.</para>
      
      <indexterm>
	<primary>sldi</primary>
	<secondary>vec_xst_len</secondary>
      </indexterm>
      <indexterm>
	<primary>stxvl</primary>
	<secondary>vec_xst_len</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xst_len</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed char *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed short *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned short</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned short *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed int *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned int</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned int *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed long long *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned long long</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned long long *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector signed __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> signed __int128 *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned __int128</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned __int128 *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector float</para>
              </entry>
              <entry align="center" valign="middle">
                <para> float *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
            <row>
              <entry align="center" valign="middle">
                <para>vector double</para>
              </entry>
              <entry align="center" valign="middle">
                <para> double *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  sldi   t,c,56
  stxvl  a,b,t
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>
    <?hard-pagebreak?>

    <simplesect xml:id="vec_xst_len_r">
      <title>vec_xst_len_r</title>
      <subtitle>Vector Store with Length Right-Justified</subtitle>
      <programlisting>
      vec_xst_len_r (a, b, c)
      </programlisting>

      <para><emphasis role="bold">Purpose:</emphasis>
      Stores a right-justified vector of a specified byte length.
      </para>
      <para><emphasis role="bold">Operation: </emphasis>Stores the number of
      bytes specified by <emphasis role="bold">c</emphasis> of the
      right-justified vector <emphasis role="bold">a</emphasis> to the address
      specified by <emphasis role="bold">b</emphasis>.</para>
      <para>Between 0 and 16 bytes, inclusive, will be stored. The length is
      specified by the least-significant byte of <emphasis
      role="bold">c</emphasis>, as <emphasis>min</emphasis> (<emphasis
      role="bold">b</emphasis> <emphasis>mod</emphasis> 256, 16). The
      behavior is undefined if the length argument is outside of the range
      0–255.</para>
      <para><emphasis role="bold">Endian considerations:</emphasis>
      None.
      </para>
      <para><emphasis role="bold">Notes:</emphasis> vec_xst_len_r should
      not be used to store to cache-inhibited memory.</para>
      
      <indexterm>
	<primary>lvsr</primary>
	<secondary>vec_xst_len_r</secondary>
      </indexterm>
      <indexterm>
	<primary>sldi</primary>
	<secondary>vec_xst_len_r</secondary>
      </indexterm>
      <indexterm>
	<primary>vperm</primary>
	<secondary>vec_xst_len_r</secondary>
      </indexterm>
      <indexterm>
	<primary>stxvll</primary>
	<secondary>vec_xst_len_r</secondary>
      </indexterm>

      <table frame="all">
      <title>Supported type signatures for vec_xst_len_r</title>
      <tgroup cols="5">
          <colspec colname="c1" colwidth="20*" />
          <colspec colname="c2" colwidth="20*" />
          <colspec colname="c3" colwidth="20*" />
          <colspec colname="c4" colwidth="20*" />
          <colspec colname="c5" colwidth="20*" />
          <thead>
            <row>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">a</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">b</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para>
                  <emphasis role="bold">c</emphasis>
                </para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Example Implementation</emphasis></para>
              </entry>
              <entry align="center" valign="middle">
                <para><emphasis role="bold">Restrictions</emphasis></para>
              </entry>
            </row>
          </thead>
          <tbody>
            <row>
              <entry align="center" valign="middle">
                <para>vector unsigned char</para>
              </entry>
              <entry align="center" valign="middle">
                <para> unsigned char *</para>
              </entry>
              <entry align="center" valign="middle">
                <para> size_t</para>
              </entry>
              <entry>
                <programlisting>
  lvsr   t,0,c
  sldi   u,c,56
  vperm  v,a,a,t
  stxvll v,b,u
		</programlisting>
              </entry>
              <entry align="center" valign="middle">
                <para>ISA 3.0 or later</para>
              </entry>
            </row>
          </tbody>
        </tgroup>
      </table>

    </simplesect>

  </section>

</chapter>