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@ -72,18 +72,61 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="section_intro">
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server family.
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</para>
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<para>
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Next talk about VSX introduced for P7. Changes in registers and
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types.
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IBM extended VMX by introducing the Vector-Scalar Extension
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(VSX) for the POWER7 family of processors. VSX adds 64 logical
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Vector Scalar Registers (VSRs); however, to optimize the amount
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of per-process register state, the registers overlap with the
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VRs and the scalar floating-point registers (FPRs) (see <xref
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linkend="VIPR.intro.unified" />). The VSRs can represent all
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the data types representable by the VRs, and can also be treated
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as containing two 64-bit integers or two 64-bit double-precision
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floating-point values.
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</para>
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<para>
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Both the VMX and VSX instruction sets have been expanded for the
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POWER8 and POWER9 processor families. Starting with POWER8,
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a VSR can now contain a single 128-bit integer; and starting
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with POWER9, a VSR can contain a single 128-bit floating-point
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value. The VMX and VSX instruction sets together may be
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referred to as the POWER SIMD (single-instruction,
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multiple-data) instructions.
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</para>
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<section>
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<title>Little-Endian Linux</title>
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<para>
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Yes, it caused a lot of problems. See chapter on this.
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The POWER architecture has supported operation in either
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big-endian (BE) or little-endian (LE) mode from the
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beginning. However, IBM's POWER servers were only shipped
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with big-endian operating systems (AIX, Linux, i5/OS) prior to
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the introduction of POWER8. With POWER8, IBM began
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supporting little-endian Linux distributions for the first
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time, and introduced a new application binary interface (the
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64-Bit ELFv2 ABI Specification <xref
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linkend="VIPR.intro.links" />) that can be used for either
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big- or little-endian support. In practice, the ELFv2 ABI is
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currently used only for little-endian Linux.
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</para>
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<para>
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Although POWER has always supported big- and little-endian
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memory accesses, the introduction of vector register support
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added a layer of complexity to programming for processors
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operating in different endian modes. Arrays of elements
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loaded into a VR or VSR will be indexed from left to right in
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the register in big-endian mode, but will be indexed from
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right to left in the register in little-endian mode. However,
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the VMX and VSX instructions originally assumed that elements
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will always be indexed from left to right in the register.
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This is an inconvenience that needs to be hidden from the
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application programmer wherever possible. To this end, IBM
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developed a bi-endian vector programming model (see <xref
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linkend="VIPR.biendian" />). The intrinsic functions provided
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for the bi-endian vector programming model are described in
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<xref linkend="VIPR.vec-ref" />.
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</para>
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</section>
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</section>
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<section>
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<section xml:id="VIPR.intro.unified">
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<title>The Unified Vector Register Set</title>
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<para>filler</para>
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</section>
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Bill Schmidt
5 years ago