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@ -18,32 +18,32 @@
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xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.biendian">
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<!-- Chapter Title goes here. -->
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<title>The POWER Bi-Endian Vector Programming Model</title>
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<title>The Power Bi-Endian Vector Programming Model</title>
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<para>
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To ensure portability of applications optimized to exploit the
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SIMD functions of POWER ISA processors, this reference defines a
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SIMD functions of Power ISA processors, this reference defines a
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set of functions and data types for SIMD programming. Compliant
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compilers will provide suitable support for these functions,
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preferably as built-in functions that translate to one or more
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POWER ISA instructions.
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Power ISA instructions.
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</para>
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<para>
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Compilers are encouraged, but not required, to provide built-in
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functions to access individual instructions in the IBM POWER®
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functions to access individual instructions in the IBM Power®
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instruction set architecture. In most cases, each such built-in
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function should provide direct access to the underlying
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instruction.
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</para>
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<para>
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However, to ease porting between little-endian (LE) and big-endian
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(BE) POWER systems, and between POWER and other platforms, it is
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(BE) Power systems, and between Power and other platforms, it is
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preferable that some built-in functions provide the same semantics
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on both LE and BE POWER systems, even if this means that the
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on both LE and BE Power systems, even if this means that the
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built-in functions are implemented with different instruction
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sequences for LE and BE. To achieve this, vector built-in
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functions provide a set of functions derived from the set of
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hardware functions provided by the POWER SIMD instructions. Unlike
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hardware functions provided by the Power SIMD instructions. Unlike
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traditional “hardware intrinsic” built-in functions, no fixed
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mapping exists between these built-in functions and the generated
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hardware instruction sequence. Rather, the compiler is free to
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@ -52,13 +52,13 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.biendian">
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built-in functions.
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</para>
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<para>
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As we've seen, the POWER SIMD instructions operate on groups of 1,
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As we've seen, the Power SIMD instructions operate on groups of 1,
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2, 4, 8, or 16 vector elements at a time in 128-bit registers. On
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a big-endian POWER platform, vector elements are loaded from
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a big-endian Power platform, vector elements are loaded from
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memory into a register so that the 0th element occupies the
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high-order bits of the register, and the (N – 1)th element
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occupies the low-order bits of the register. This is referred to
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as big-endian element order. On a little-endian POWER platform,
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as big-endian element order. On a little-endian Power platform,
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vector elements are loaded from memory such that the 0th element
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occupies the low-order bits of the register, and the (N –
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1)th element occupies the high-order bits. This is referred to as
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@ -68,7 +68,7 @@ xmlns:xlink="http://www.w3.org/1999/xlink" xml:id="VIPR.biendian">
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<note>
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<para>
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Much of the information in this chapter was formerly part of
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Chapter 6 of the 64-Bit ELF V2 ABI Specification for POWER.
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Chapter 6 of the 64-Bit ELF V2 ABI Specification for Power.
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</para>
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</note>
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@ -123,7 +123,7 @@ vector double g = (vector double) { 3.5, -24.6 };</programlisting>
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For the C and C++ programming languages (and related/derived
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languages), these data types may be accessed based on the type
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names listed in <xref linkend="VIPR.biendian.vectypes" /> when
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POWER SIMD language extensions are enabled using either the
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Power SIMD language extensions are enabled using either the
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<code>vector</code> or <code>__vector</code> keywords.
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</para>
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<para>
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@ -478,7 +478,7 @@ register vector double vd = vec_splats(*double_ptr);</programlisting>
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<title>Vector Operators</title>
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<para>
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In addition to the dereference and assignment operators, the
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POWER Bi-Endian Vector Programming Model provides the usual
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Power Bi-Endian Vector Programming Model provides the usual
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operators that are valid on pointers; these operators are also
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valid for pointers to vector types.
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</para>
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@ -589,7 +589,7 @@ register vector double vd = vec_splats(*double_ptr);</programlisting>
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<section>
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<title>Vector Built-In Functions</title>
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<para>
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Some of the POWER SIMD hardware instructions refer, implicitly
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Some of the Power SIMD hardware instructions refer, implicitly
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or explicitly, to vector element numbers. For example, the
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<code>vspltb</code> instruction has as one of its inputs an
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index into a vector. The element at that index position is to
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@ -650,7 +650,7 @@ register vector double vd = vec_splats(*double_ptr);</programlisting>
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</entry>
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<entry>
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<para>
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<emphasis role="bold">Corresponding POWER
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<emphasis role="bold">Corresponding Power
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Instructions</emphasis>
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</para>
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</entry>
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@ -761,7 +761,7 @@ register vector double vd = vec_splats(*double_ptr);</programlisting>
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(Deprecated)</title>
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<para>
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Versions 1.0 through 1.4 of the 64-Bit ELFv2 ABI Specification
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for POWER provided for optional compiler support for using
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for Power provided for optional compiler support for using
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big-endian element ordering in little-endian environments.
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This was initially deemed useful for porting certain libraries
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that assumed big-endian element ordering regardless of the
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Bill Schmidt
5 years ago
