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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2017 OpenPOWER Foundation
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<section xmlns="http://docbook.org/ns/docbook"
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xmlns:xi="http://www.w3.org/2001/XInclude"
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xmlns:xlink="http://www.w3.org/1999/xlink"
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version="5.0"
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xml:id="sec_more_examples">
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<title>Some more intrinsic examples</title>
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<para>The intrinsic
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<link xlink:href="https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtpd_ps&expand=1624">_mm_cvtpd_ps</link>
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converts a packed vector double into
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a packed vector single float. Since only 2 doubles fit into a 128-bit vector
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only 2 floats are returned and occupy only half (64-bits) of the XMM register.
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For this intrinsic the 64 bits are packed into the logical left half of the result
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register and the logical right half of the register is set to zero (as per the
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Intel <literal>cvtpd2ps</literal> instruction).</para>
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<para>The PowerISA provides the VSX Vector round and Convert
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Double-Precision to Single-Precision format (xvcvdpsp) instruction. In the ABI
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this is <literal>vec_floato</literal> (vector double).
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This instruction converts each double
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element, then transfers converted element 0 to float element 1, and converted
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element 1 to float element 3. Float elements 0 and 2 are undefined (the
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hardware can do whatever). This does not match the expected results for
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<literal>_mm_cvtpd_ps</literal>.
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<programlisting><![CDATA[vec_floato ({1.0, 2.0}) result = {<undefined>, 1.0, <undefined>, 2.0}
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_mm_cvtpd_ps ({1.0, 2.0}) result = {1.0, 2.0, 0.0, 0.0}]]></programlisting></para>
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<para>So we need to re-position the results to word elements 0 and 2, which
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allows a pack operation to deliver the correct format. Here the merge-odd
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splats element 1 to 0 and element 3 to 2. The Pack operation combines the low
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half of each doubleword from the vector result and vector of zeros to generate
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the require format.
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<programlisting><![CDATA[extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
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_mm_cvtpd_ps (__m128d __A)
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{
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__v4sf result;
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__v4si temp;
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const __v4si vzero = {0,0,0,0};
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__asm__(
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"xvcvdpsp %x0,%x1;\n"
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: "=wa" (temp)
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: "wa" (__A)
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: );
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temp = vec_mergeo (temp, temp);
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result = (__v4sf)vec_vpkudum ((vector long)temp, (vector long)vzero);
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return (result);
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}]]></programlisting></para>
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<para>This technique is also used to implement
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<link xlink:href="https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttpd_epi32&expand=1624,1859">_mm_cvttpd_epi32</link>
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which converts a packed vector double into a packed vector int. The PowerISA instruction
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<literal>xvcvdpsxws</literal> uses a similar layout for the result as
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<literal>xvcvdpsp</literal> and requires the same fix up.</para>
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</section>
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