Aux Vector section misstates the interpretation of cache geometries #110

In Section 4.1.2.3 (Auxiliary Vector), we have

The low-order sixteen bits contain the cache associativity as a value N, where N = 1 represents 
a direct-mapped cache, N = 0xffff represents a fully associative cache, and any other N represents 
an N-way set-associative cache. The next higher-order sixteen bits contain the size of the cache
line in bytes. Note that the cache line size is not necessarily the same as the cache block size.

In fact, the two fields described herein are swapped, as Linux uses

#define get_cache_geometry(level) \
        (ppc64_caches.level.assoc << 16 | ppc64_caches.level.line_size)

in https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/include/asm/elf.h#n136.

In Section 4.1.2.3 (Auxiliary Vector), we have ``` The low-order sixteen bits contain the cache associativity as a value N, where N = 1 represents a direct-mapped cache, N = 0xffff represents a fully associative cache, and any other N represents an N-way set-associative cache. The next higher-order sixteen bits contain the size of the cache line in bytes. Note that the cache line size is not necessarily the same as the cache block size. ``` In fact, the two fields described herein are swapped, as Linux uses ``` #define get_cache_geometry(level) \ (ppc64_caches.level.assoc << 16 | ppc64_caches.level.line_size) ``` in https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/include/asm/elf.h#n136.

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Aux Vector section misstates the interpretation of cache geometries #110